Semiconductor element and forming method thereof
By setting conductive contacts in semiconductor components, the GIDL leakage current and latch-up effect problems caused by reduced spacing are solved, achieving more efficient current conduction and greater internal space utilization, supporting further reduction of components.
Patent Information
- Application Number
- CN202410283292.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2025-09-19
AI Technical Summary
As semiconductor device sizes shrink, the spacing between internal components shrinks, leading to the possibility of band-to-band tunneling (BTBT) between sources connected to different external bias voltages. This phenomenon, known as gate-induced drain leakage (GIDL), limits the process of device size reduction. Existing improvement methods, such as preserving spacing or forming silicon-germanium epitaxial regions, also have process limitations.
Conductive contacts are set in semiconductor components. Conductive contacts are formed by filling grooves with conductive materials in the substrate to connect to the ground terminal, reduce substrate resistance, improve GIDL leakage current, release internal space, and avoid latch-up effect.
It effectively reduces substrate effects, improves current conduction efficiency, frees up internal space, avoids latch-up effects, and is not limited by existing process depth limitations, supporting further component miniaturization.
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Figure CN120676707A_ABST
Abstract
Description
Technical Field
[0001] Some embodiments of the present disclosure provide semiconductor devices and methods of forming the same. Background Art
[0002] As semiconductor device sizes shrink, the spacing between internal components also decreases. However, during this process of spacing reduction, gate-induced drain leakage (GIDL) may occur due to band-to-band tunneling (BTBT) between external sources with different bias voltages (for example, one connected to an external power line and the other to ground). To prevent the accumulation of GIDL leakage current and the resulting increase in device substrate voltage, appropriate spacing between internal components must be maintained, but this will limit the process of shrinking semiconductor device sizes.
[0003] Therefore, there is a need to provide a semiconductor device and a method for forming the same that can improve the body effect caused by the increase in substrate voltage and free up more internal available space. Summary of the Invention
[0004] Some embodiments of the present disclosure provide a semiconductor device comprising a substrate, a plurality of first conductivity type doped regions, a plurality of second conductivity type doped regions, and a conductive contact. The plurality of first conductivity type doped regions are disposed in the substrate. The plurality of second conductivity type doped regions are disposed in the substrate. The conductive contact is disposed in the substrate, wherein the first conductivity type doped regions are located between the conductive contact and the second conductivity type doped regions.
[0005] In some embodiments, the conductive contacts comprise a conductor material.
[0006] In some embodiments, the conductive contact further comprises silicon, silicon germanium, or a combination thereof.
[0007] In some embodiments, the semiconductor device further includes a first isolation member disposed in the substrate and located between the first conductive type doped region and the conductive contact.
[0008] In some embodiments, the depth to which the conductive contact is buried in the substrate is greater than the depth to which the first isolation member is buried in the substrate.
[0009] In some embodiments, the semiconductor device further includes a second isolation member disposed between the first conductivity type doping region and the second conductivity type doping region.
[0010] In some embodiments, the semiconductor device further includes a first gate and a second gate. The first gate is disposed on the substrate and contacts the first conductive type doped region. The second gate is disposed on the substrate and contacts the second conductive type doped region.
[0011] In some embodiments, one of the first conductivity type doped regions is electrically connected to the ground terminal, and one of the second conductivity type doped regions is electrically connected to a power line.
[0012] Some embodiments of the present disclosure provide a method for forming a semiconductor element, comprising: providing a substrate; forming a groove in the substrate; filling the groove with a contact material to form a conductive contact; doping the substrate with a first conductive type dopant to form a plurality of first conductive type doped regions; and doping the substrate with a second conductive type dopant to form a plurality of second conductive type doped regions, wherein the first conductive type doped region is located between the conductive contact and the second conductive type doped region.
[0013] In some embodiments, before the step of forming a groove in the substrate, a first isolation member is formed in the substrate; the step of forming a groove in the substrate includes forming the groove adjacent to the first isolation member; and the step of doping a first conductive type dopant into the substrate includes forming a first conductive type doping region adjacent to the first isolation member, so that the first isolation member is located between the first conductive type doping region and the conductive contact.
[0014] In some embodiments, the depth of the groove is greater than the depth of the first isolation member buried in the substrate.
[0015] In some embodiments, before the step of forming the groove in the substrate, a second isolation member is formed in the substrate and located between the first conductivity type doping region and the second conductivity type doping region.
[0016] In some embodiments, after the step of filling the groove with a contact material, the method includes forming a dummy gate structure on the substrate; and after the steps of doping the substrate with a first conductive type dopant and doping the substrate with a second conductive type dopant, the method includes removing the dummy gate structure.
[0017] In some embodiments, after the steps of doping a first conductive type dopant into the substrate and doping a second conductive type dopant into the substrate, the method includes: forming a first gate on the substrate and contacting the first conductive type doping region; and forming a second gate on the substrate and contacting the second conductive type doping region.
[0018] Some embodiments of the present disclosure provide a semiconductor device comprising: a substrate, a plurality of first-conductivity-type doped regions, a first spacer, and a conductive contact. The plurality of first-conductivity-type doped regions are disposed in the substrate. The first spacer is disposed in the substrate, adjacent to the first-conductivity-type doped regions. The conductive contact is disposed in the substrate, wherein the first spacer is located between the first-conductivity-type doped regions and the conductive contact.
[0019] In some embodiments, the depth to which the conductive contact is buried in the substrate is greater than the depth to which the first isolation member is buried in the substrate.
[0020] In some embodiments, the semiconductor device further includes: a first gate disposed on the substrate and contacting the first conductive type doped region.
[0021] In some embodiments, the semiconductor device further includes a plurality of second conductivity type doped regions disposed in the substrate, wherein the first conductivity type doped regions are located between the second conductivity type doped regions and the conductive contacts.
[0022] In some embodiments, the semiconductor device further includes a second isolation member disposed between the first conductivity type doping region and the second conductivity type doping region.
[0023] In some embodiments, the semiconductor device further includes: a second gate disposed on the substrate and contacting the second conductivity type doped region.
[0024] It is to be understood that both the foregoing general description and the following detailed description are examples, and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The present disclosure can be more fully understood by reading the following detailed description of embodiments with reference to the accompanying drawings.
[0026] Figures 1 to 3A ,as well as Figures 4 to 6 Schematic cross-sectional views of various intermediate stages in a method of forming a semiconductor device according to some embodiments of the present disclosure are exemplarily described.
[0027] Figure 3B A cross-sectional schematic diagram illustrating an intermediate stage in a method for forming a semiconductor device according to other embodiments of the present disclosure is exemplarily described. DETAILED DESCRIPTION
[0028] It will be appreciated that the different embodiments or examples provided below may implement different features of the subject matter of the present disclosure. The examples of specific components and arrangements are intended to simplify the present disclosure rather than to limit it. Of course, these are merely examples and are not intended to be limiting. For example, the description below of a first feature being formed on a second feature includes the two being in direct contact, or the two being separated by other additional features rather than in direct contact. In addition, the present disclosure may repeat reference numbers and / or symbols in multiple embodiments. Such repetition is for simplicity and clarity and does not represent a relationship between the various embodiments and / or configurations discussed.
[0029] The terms used in this specification generally have their ordinary meanings in the art and in the context in which they are used. The examples used in this specification, including examples of any term discussed herein, are illustrative only and do not limit the scope and meaning of the present disclosure or any exemplary term. Similarly, the present disclosure is not limited to the embodiments provided in this specification.
[0030] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the scope of this embodiment, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.
[0031] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0032] As used herein, the terms "include", "comprising", "having" and the like should be understood as open ended, that is, meaning including but not limited to.
[0033] Reference Figure 1 , providing a substrate 110 with an isolation member 120 embedded therein.
[0034] In some embodiments, the step of providing a substrate 110 having embedded isolation members 120 includes providing a substrate 110; forming a plurality of recessed portions in the substrate 110; and depositing an insulating material in the recessed portions to form a plurality of isolation members 120 (isolation members 121, 122, 123, 124, and 125) to divide the upper surface 112 of the substrate 110 into a plurality of electrically isolated portions. In some embodiments, the isolation members 120 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or thermal oxidation.
[0035] In some embodiments, the material of the substrate 110 includes silicon, silicon germanium, silicon carbide, or a combination thereof. In some embodiments, a portion of the substrate 110 is doped with a specific semiconductor type dopant. For example, a portion of the region is lightly doped with a first conductivity type (e.g., N-type dopants such as phosphorus, arsenic, and nitrogen), and another portion of the region is lightly doped with a second conductivity type (e.g., P-type dopants such as boron, gallium, and aluminum) to assist in the flow of electrons in conjunction with the source and drain formed after the subsequent doping process. In some embodiments, the insulating material used for the isolation member 120 includes silicon oxide, silicon oxynitride, silicon hydroxide, or a combination thereof.
[0036] Reference Figure 2 , a groove 130 is formed in the substrate 110 .
[0037] In some embodiments, the step of forming the groove 130 in the substrate 110 includes: forming a mask layer on the substrate 110 to expose a portion of the substrate 110 (not shown); etching the exposed portion of the substrate 110 to form the groove 130; and removing the mask layer (for example, by chemical-mechanical polishing (CMP)) (not shown).
[0038] In some embodiments, the recess 130 is adjacent to the isolation member 124 and is located between the isolation member 124 and the isolation member 125 (adjacent to the isolation member 124). In some embodiments, the depth D1 of the recess 130 is greater than or equal to the depth D2 of the isolation member 124 embedded in the substrate 110 (i.e., the distance from the upper surface 124a of the isolation member 124 to the lower surface 124b, wherein the upper surface 124a of the isolation member 124 is substantially flush with the upper surface 112 of the substrate 110). In some other embodiments, the depth D1 of the recess 130 is less than (but not equal to) the depth D2 of the isolation member 124 embedded in the substrate 110. By adjusting the depth D1 of the recess 130, the depth of the subsequently formed conductive contact can be controlled.
[0039] Reference Figure 2 as well as Figure 3A , filling the groove 130 with a contact material to form a conductive contact 140 .
[0040] In some embodiments, the contact material includes a conductive material (e.g., metal) to reduce the parasitic substrate resistance of the substrate 110. The subsequent connection to the ground terminal can also reduce the latch-up effect caused by a low-impedance conductive path driven by a rising substrate voltage between adjacent doped regions of different conductivity types. In some embodiments, the contact material further includes silicon, silicon germanium, or a combination thereof. This, in combination with the conductive material, can further enhance the heat resistance of the conductive contact 140 and improve its integration with the substrate 110.
[0041] In some embodiments, the conductive contact 140 can be formed through a deposition process. In some embodiments, the contact material completely fills the groove 130, so the depth D3 of the conductive contact 140 (extending inward from the upper surface 141 to the lower surface 142, wherein the upper surface 141 is approximately flush with the upper surface 112 of the substrate 110) is the same as the depth D1 of the groove 130. In some embodiments, the depth D3 of the conductive contact 140 is greater than the depth D2 of the isolation member 124 buried in the substrate 110. Generally speaking, the greater the depth D3, the better the conductive contact 140 can reduce leakage current, but if the depth D3 is too deep (for example, more than twice the depth of the first conductive type doping region 150, 151, 152, 153 or the second conductive type doping region 160, 161, 162, 163), the volume occupied by the conductive contact 140 is too large, which will excessively compress the installation space of other components. In some other embodiments, please refer to Figure 3B The depth D3 of the conductive contact 140 is less than (but not equal to) the depth D2 of the isolation member 124 embedded in the substrate 110 .
[0042] In some embodiments, after filling the groove 130 with the contact material, a dummy gate structure (not shown) is formed on the substrate 110. The dummy gate structure can block dopants during subsequent doping processes and expose the area to be doped in the substrate 110, thereby locating the doping position of subsequent dopants.
[0043] Reference Figure 4 , first conductive type dopants are doped into the substrate 110 to form a plurality of first conductive type doping regions 150 (first conductive type doping region 151, first conductive type doping region 152, and first conductive type doping region 153); and second conductive type dopants are doped into the substrate 110 to form a plurality of second conductive type doping regions 160 (second conductive type doping region 161 and second conductive type doping region 162).
[0044] In some embodiments, the first conductivity type doping region 151 and the first conductivity type doping region 152 are located between the conductive contact 140 and the second conductivity type doping region 160. That is, the conductive contact 140 is located on a side of the first conductivity type doping region 152 away from the second conductivity type doping region 160. In some embodiments, the conductive contact 140 is interposed between the isolation member 124 and the isolation member 125. The isolation member 124 and the isolation member 125 electrically isolate the conductive contact 140 from other conductivity type doping regions (e.g., the first conductivity type doping region 152). The isolation member 124 and the isolation member 125 can also prevent the conductive material of the conductive contact 140 from diffusing, thereby preventing electronic interference between the conductive contact 140 and the first conductivity type doping region 152.
[0045] In some embodiments, the first conductive type dopant and the second conductive type dopant are respectively an N-type dopant (such as phosphorus, arsenic, nitrogen, etc.) and a P-type dopant (such as boron, gallium, aluminum, etc.), or the first conductive type dopant and the second conductive type dopant are respectively a P-type dopant and an N-type dopant. Those skilled in the art can select appropriate dopants as needed to match the subsequent applied voltage.
[0046] In some embodiments, the step of doping the substrate 110 with the first conductive type doping material includes forming the first conductive type doping region 151 and the first conductive type doping region 152 adjacent to the isolation member 124, such that the isolation member 124 is located between the first conductive type doping region (151, 152) and the conductive contact 140, and there is no isolation member between the first conductive type doping region 151 and the first conductive type doping region 152. In some embodiments, the first conductive type doping region 151 and the first conductive type doping region 152 are located between the isolation member 124 and the isolation member 123, and are electrically isolated from other doped regions by the isolation members 123, 124.
[0047] In some embodiments, the step of doping the substrate 110 with the second conductivity type doping material includes forming the second conductivity type doping region 161 and the second conductivity type doping region 162 adjacent to the isolation member 124, such that the isolation member 122 is located between the first conductivity type doping region 151 and the second conductivity type doping region 162. In some embodiments, the second conductivity type doping region 161 and the second conductivity type doping region 162 are located between the isolation members 121 and 122, and are electrically isolated from other doped regions by the isolation members 121 and 122. Furthermore, there is no isolation member between the second conductivity type doping region 161 and the second conductivity type doping region 162, so that the region remains as a channel region after a bias is subsequently applied. For example, the second conductive type doping region 161 is electrically isolated from the first conductive type doping region 153 (located on the side of the second conductive type doping region 161 away from the first conductive type doping regions 151 and 152) by the isolation member 121, and the second conductive type doping region 162 is electrically isolated from the first conductive type doping region 151 by the isolation member 122.
[0048] In some embodiments, before performing the doping process, a dummy gate structure is first provided to locate the region to be doped, and after the steps of doping the first conductive type dopant into the substrate 110 and doping the second conductive type dopant into the substrate 110 , the dummy gate structure is removed.
[0049] Reference Figure 5A first gate G1 is formed on the substrate 110 and contacts the first conductive type doping region 151 and the first conductive type doping region 152 , and a second gate G2 is formed on the substrate 110 and contacts the second conductive type doping region 161 and the second conductive type doping region 162 , thereby obtaining the semiconductor device 100 .
[0050] In some embodiments, the first gate G1 includes a first gate dielectric layer on the substrate 110 and a first gate layer on the first gate dielectric layer (not shown). In some embodiments, the second gate G2 includes a second gate dielectric layer on the substrate 110 and a second gate layer on the second gate dielectric layer (not shown). Subsequently, by applying a specific bias voltage to the first gate G1 and the second gate G2, a first channel region and a second channel region can be formed under the first gate G1 and the second gate G2, respectively.
[0051] Reference Figure 6 , electrically connecting the ground terminal VSS to the first conductive type doping region 152 and the conductive contact 140 , and electrically connecting the power line VDD to the first conductive type doping region 153 and the second conductive type doping region 161 .
[0052] In some embodiments, the power line VDD provides a first bias voltage to the second conductivity-type doped region 161, causing the second conductivity-type doped region 161 to function as a source and the second conductivity-type doped region 162 to function as a drain. Simultaneously, the second gate G2 also receives a second bias voltage. The applied voltage difference causes electrons to flow between the second conductivity-type doped region 161 and the second conductivity-type doped region 162, forming a channel region in the substrate 110 adjacent to the second gate G2.
[0053] In some embodiments, a circuit structure is provided in the substrate 110 to electrically connect the second conductive type doping region 161 and the first conductive type doping region 152 , so that current can flow between the power line VDD and the ground terminal VSS.
[0054] It should be noted that due to the bias voltage difference between the second conductivity type doped region 161 connected to the power line VDD and the first conductivity type doped region 152 connected to the ground terminal VSS, if the spacing between the two is insufficient (for example, due to excessive device density or a small substrate), band-to-band tunneling (BTBT) can easily occur, resulting in gate-induced drain leakage (GIDL). In this case, electrons can tunnel directly from the second conductivity type doped region 161 (connected to the power line VDD) to the first conductivity type doped region 152 (connected to the ground terminal VSS) without passing through the circuit structure electrically connected between the two. This creates a low-impedance conduction path at the bottom of the substrate, causing latch-up, resulting in current loss and reduced current conduction efficiency.
[0055] To prevent the aforementioned latch-up effect, conventional semiconductor device manufacturing processes may attempt to improve the latch-up effect by, for example, maintaining an appropriate spacing between adjacent doped regions. Alternatively, when forming the doped regions, a SiGe epitaxial region may be formed in an adjacent area. Both the doped regions and the SiGe epitaxial region are then connected to the ground terminal VSS to facilitate current flow through the SiGe epitaxial region.
[0056] However, maintaining the spacing will limit the size and density of components to a specific size, preventing continued device shrinkage. The preparation of the SiGe epitaxial region places high demands on the lattice structure (lattice defects will cause the risk of leakage), and therefore requires high process technology. In addition, the SiGe epitaxial region is limited by the depth limit of the epitaxial process (usually the depth can only be approximately equivalent to the doped region), and the limited depth it can extend into the substrate also limits the effect of reducing leakage current.
[0057] In contrast, the present disclosure sets the conductive contact 140 on the side of the first conductive type doped region 152 connected to the external ground terminal VSS, and uses the low resistance of the conductive material to reduce the parasitic substrate resistance, thereby improving the substrate effect (body effect) caused by the GIDL leakage current and improving the current conduction efficiency. In addition, since the conductive contact 140 is formed by filling the groove with conductive material (for example, see Figure 2 Therefore, the conductive contact 140 of appropriate depth can be prepared according to design requirements, and the flexibility of the preparation depth area is improved; in addition, compared with setting a silicon germanium epitaxial region, the conductive contact 140 is not limited by the upper limit of the depth of the epitaxial method, and the buried depth can be further increased, which can further improve the substrate effect.
[0058] It is also worth mentioning that the provision of the conductive contacts 140 can improve the latch-up effect. There is no need to deliberately maintain a specific spacing between the sources of the semiconductor device 100 to avoid the latch-up effect. Therefore, the internal space of the semiconductor device 100 can be released, thereby improving the utilization rate of the internal space.
[0059] Although the present disclosure has been described in detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0060]
Explanation of symbols
[0061] 100:Semiconductor components
[0062] 110:Substrate
[0063] 112: Upper surface
[0064] 120, 121, 122, 123, 124, 125: Isolators
[0065] 124a, 141: upper surface
[0066] 124b, 142: lower surface
[0067] 130: Groove
[0068] 140: conductive contacts
[0069] 150, 151, 152, 153: first conductivity type doping regions
[0070] 160, 161, 162: second conductivity type doping regions
[0071] D1, D2, D3: Depth
[0072] G1: first gate
[0073] G2: Second gate
[0074] VDD: power line
[0075] VSS: Ground terminal.
Claims
1. A semiconductor device, characterized in that: Include: substrate; a plurality of first conductivity type doped regions, disposed in the substrate; a plurality of second conductivity type doped regions disposed in the substrate; and A conductive contact is disposed in the substrate, wherein the plurality of first conductive type doping regions are located between the conductive contact and the plurality of second conductive type doping regions. The semiconductor device according to claim 1 , wherein the conductive contact comprises a conductive material. 3 . The semiconductor device according to claim 2 , wherein the conductive contact further comprises silicon, silicon germanium, or a combination thereof.
4. The semiconductor element according to any one of claims 1 to 3, wherein The device further comprises a first isolation member which is arranged in the substrate and located between the plurality of first conductive type doping regions and the conductive contacts. 5 . The semiconductor device according to claim 4 , wherein a depth of the conductive contact buried in the substrate is greater than a depth of the first spacer buried in the substrate. 6 . The semiconductor device according to claim 1 , wherein one of the plurality of first conductivity type doped regions is electrically connected to a ground terminal, and one of the plurality of second conductivity type doped regions is electrically connected to a power line.
7. A method for forming a semiconductor device, characterized in that: Include: providing a substrate; forming a groove in the substrate; Filling the groove with a contact material to form a conductive contact; doping the substrate with a first conductive type dopant to form a plurality of first conductive type doping regions; as well as Doping the substrate with a second conductive type dopant to form a plurality of second conductive type doping regions, wherein the plurality of first conductive type doping regions are located between the conductive contacts and the plurality of second conductive type doping regions.
8. The method according to claim 7, wherein: Before the step of forming the groove in the substrate, the method includes forming a first isolation member in the substrate; The step of forming the groove in the substrate includes forming the groove adjacent to the first isolation member; as well as The step of doping the first conductive type dopant into the substrate includes forming the plurality of first conductive type doping regions adjacent to the first isolation member, so that the first isolation member is located between the plurality of first conductive type doping regions and the conductive contact. 9 . The method according to claim 7 , wherein before the step of forming the groove in the substrate, the method further comprises forming a second isolation member in the substrate and located between the plurality of first conductivity type doping regions and the plurality of second conductivity type doping regions.
10. The method according to claim 7, wherein: After the step of filling the groove with the contact material, the method includes forming a dummy gate structure on the substrate; as well as After the steps of doping the first conductive type dopant into the substrate and doping the second conductive type dopant into the substrate, the method includes removing the dummy gate structure.