Driving substrate, manufacturing method thereof, display panel and display device

Abstract

The invention provides a driving substrate and a manufacturing method thereof, a display panel and a display device. The driving substrate comprises a substrate and a transistor. The transistor comprises a drain electrode, a source electrode, a grid electrode, an insulating layer, a semiconductor layer, a first doped layer and a second doped layer, the insulating layer covers the grid electrode to the substrate, and the semiconductor layer is arranged on the insulating layer. The semiconductor layer comprises a first semiconductor, a second semiconductor and a third semiconductor, the third semiconductor is connected between the first semiconductor and the second semiconductor, the thickness of the third semiconductor is smaller than that of the first semiconductor, and the thickness of the third semiconductor is smaller than that of the second semiconductor. Therefore, the thickness of the third semiconductor is smaller than that of the first semiconductor, and the thickness of the third semiconductor is smaller than that of the second semiconductor, so that the leakage current of the grid electrode under the high negative bias voltage condition is reduced, the on / off current ratio of the transistor is improved, and the display effect of the display device is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving substrate, a method for manufacturing a driving substrate, a display panel, and a display device. Background Art

[0002] In a display device, by increasing the on / off current ratio of the transistor, the brightness difference between the display device in the on and off states can be made more significant, which is beneficial to improving the contrast. The brightness control of each pixel is more precise, making the image clearer and the colors more vivid. In addition, the leakage current in the off state will also be smaller, reducing unnecessary power consumption.

[0003] Therefore, how to further improve the on / off current ratio of the transistor to enhance the overall display performance of the display device is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a driving substrate, a method for manufacturing a driving substrate, a display panel and a display device, which aim to further improve the on / off current ratio of the transistor to improve the contrast, resolution and power consumption of the display panel and the display device, thereby comprehensively improving the display performance of the display panel and the display device.

[0005] In a first aspect, an embodiment of the present application provides a driving substrate, comprising a substrate and a transistor disposed on the substrate. The transistor comprises a drain, a source, a gate, an insulating layer, a semiconductor layer, a first doping layer, and a second doping layer. The insulating layer covers the gate on the substrate, and the semiconductor layer is disposed on the surface of the insulating layer opposite to the gate. The semiconductor layer comprises a first semiconductor, a second semiconductor, and a third semiconductor. The first semiconductor and the second semiconductor are spaced apart, the third semiconductor is connected between the first semiconductor and the second semiconductor, the thickness of the third semiconductor is less than the thickness of the first semiconductor, and the thickness of the third semiconductor is less than the thickness of the second semiconductor. The first doping layer is disposed on the surface of the first semiconductor opposite to the insulating layer, the second doping layer is disposed on the surface of the second semiconductor opposite to the insulating layer, the drain is disposed on the surface of the first doping layer opposite to the first semiconductor, and the source is disposed on the surface of the second doping layer opposite to the second semiconductor.

[0006] Therefore, the present application reduces the leakage current of the transistor under high negative bias conditions by making the thickness of the third semiconductor smaller than the thickness of the first semiconductor and the thickness of the third semiconductor smaller than the thickness of the second semiconductor, thereby improving the on / off current ratio of the transistor and improving the display effect of the display panel.

[0007] In an exemplary embodiment, the height of the first semiconductor is higher than that of the second semiconductor, and the third semiconductor is inclined.

[0008] In an exemplary embodiment, the insulating layer includes a first boss, a second boss, and an insulating layer body. The insulating layer body covers the gate electrode on the substrate, and the first and second bosses are disposed on the surface of the insulating layer body facing away from the gate electrode. The first boss includes a first surface, which is the surface of the first boss facing away from the insulating layer body. The second boss includes a second surface, which is the surface of the second boss facing away from the insulating layer body. The first surface is higher than the second surface. The first semiconductor is disposed on the first surface, and the second semiconductor is disposed on the second surface.

[0009] In an exemplary embodiment, the first boss further includes an inclined surface, the inclined surface is connected to the first surface and the second surface respectively, the inclined surface forms an angle with the first surface and the second surface respectively, and the third semiconductor is disposed on the inclined surface.

[0010] In an exemplary embodiment, the driving substrate further includes a passivation layer and an electrode, the passivation layer covers the drain, the source, and the surface of the insulating layer facing away from the substrate, the passivation layer is provided with a via, the via passes through the passivation layer, and the drain is exposed from the via; the electrode is arranged on a portion of the surface of the passivation layer facing away from the insulating layer and extends into the via, and the electrode is connected to the drain to achieve electrical connection between the electrode and the drain.

[0011] In a second aspect, an embodiment of the present application further provides a method for manufacturing a drive substrate, which is used to form the above-mentioned drive substrate, and the method for manufacturing the drive substrate comprises: providing a substrate, sequentially forming a gate and an insulating layer on the substrate, wherein the insulating layer covers the gate to the substrate. A semiconductor layer, a first doping layer, and a second doping layer are sequentially formed on the surface of the insulating layer facing away from the gate. The semiconductor layer comprises a first semiconductor, a second semiconductor, and a third semiconductor, wherein the first semiconductor is spaced apart from the second semiconductor, and the third semiconductor is connected between the first semiconductor and the second semiconductor. The thickness of the third semiconductor is less than the thickness of the first semiconductor, and the thickness of the third semiconductor is less than the thickness of the second semiconductor. The first doping layer is located on the surface of the first semiconductor facing away from the insulating layer, and the second doping layer is located on the surface of the second semiconductor facing away from the insulating layer. A drain is formed on the first doping layer, and a source is formed on the second doping layer.

[0012] Therefore, the present application reduces the leakage current of the transistor under high negative bias conditions by making the thickness of the third semiconductor smaller than the thickness of the first semiconductor and the thickness of the third semiconductor smaller than the thickness of the second semiconductor, thereby improving the on / off current ratio of the transistor and improving the display effect of the display panel.

[0013] In an exemplary embodiment, the sequentially forming a gate and an insulating layer on the substrate includes: forming a gate on the substrate; forming an insulating layer on a surface of the gate facing away from the substrate, wherein the insulating layer covers the gate to the substrate.

[0014] In an exemplary embodiment, forming an insulating layer on a surface of the gate facing away from the substrate includes: forming an insulating structure on the substrate, the insulating structure covering the gate; forming a photoresist on a surface of the insulating structure facing away from the gate, the photoresist comprising a first sub-photoresist and a second sub-photoresist, the first sub-photoresist and the second sub-photoresist being connected, and the second sub-photoresist being higher than the first sub-photoresist; etching a portion of the insulating structure not blocked by the photoresist toward the substrate; removing the first sub-photoresist and retaining the second sub-photoresist; and etching a portion of the insulating structure not blocked by the second sub-photoresist toward the substrate to form a first protrusion and a second protrusion.

[0015] In an exemplary embodiment, sequentially forming a semiconductor layer, a first doped layer, and a second doped layer on a surface of the insulating layer opposite to the gate electrode includes: forming a semiconductor structure on the insulating layer, forming a doped structure on a surface of the semiconductor structure opposite to the insulating layer, and forming a photoresist structure on a surface of the doped structure opposite to the semiconductor structure. Removing portions of the semiconductor structure not blocked by the photoresist structure to form the semiconductor layer, and removing portions of the doped structure not blocked by the photoresist structure to form a doped transition structure. Removing the doped transition structure at locations of the semiconductor layer corresponding to the third semiconductor to form the first doped layer and the second doped layer.

[0016] In a third aspect, an embodiment of the present application further provides a display panel, which includes a driving circuit and the above-mentioned driving substrate, or includes a driving substrate formed by the above-mentioned manufacturing method, and the driving circuit is electrically connected to the transistors of the driving substrate.

[0017] In a fourth aspect, an embodiment of the present application further provides a display device, which includes a power supply board and the above-mentioned display panel, wherein the power supply board is electrically connected to the display panel, and the power supply board is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of the layer structure of a display device disclosed in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the layer structure of a display panel disclosed in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of the layer structure of the driving substrate disclosed in an embodiment of the present application;

[0022] Figure 4 Schematic diagram of transistor voltage setting and channel partitioning;

[0023] Figure 5 A schematic structural diagram of a third semiconductor disclosed in an embodiment of the present application;

[0024] Figure 6 A schematic flow chart of a method for manufacturing a drive substrate disclosed in an embodiment of the present application;

[0025] Figure 7 Schematic diagram of the process of step S100 in the method for manufacturing a driving substrate disclosed in an embodiment of the present application;

[0026] Figure 8 Schematic diagram of sub-steps of step S110;

[0027] Figure 9 for Figure 7 A schematic diagram of the corresponding layer structure formed in step S110 is shown;

[0028] Figure 10 for Figure 7 The schematic diagram of the top view structure formed corresponding to step S110 shown;

[0029] Figure 11 Schematic diagram of the process of step S120 in the method for manufacturing a driving substrate disclosed in an embodiment of the present application;

[0030] Figure 12 for Figure 11 A schematic diagram of the corresponding layer structure formed in step S121 is shown;

[0031] Figure 13 for Figure 11 A schematic diagram of the corresponding layer structure formed in step S122 is shown;

[0032] Figure 14 for Figure 11 A schematic diagram of the corresponding layer structure formed in step S123 is shown;

[0033] Figure 15 for Figure 11 A schematic diagram of the corresponding layer structure formed in step S124 is shown;

[0034] Figure 16 for Figure 11 The schematic diagram of the top view structure formed corresponding to step S124 is shown;

[0035] Figure 17 Schematic diagram of the process of step S200 in the method for manufacturing a driving substrate disclosed in an embodiment of the present application;

[0036] Figure 18 for Figure 17 A schematic diagram of the corresponding layer structure formed in step S210 is shown;

[0037] Figure 19 for Figure 17 A schematic diagram of the corresponding layer structure formed in step S220 is shown;

[0038] Figure 20 for Figure 17 A schematic diagram of the corresponding layer structure formed in step S230 is shown;

[0039] Figure 21 for Figure 17 The schematic diagram of the top view structure formed corresponding to step S230 shown;

[0040] Figure 22 for Figure 6 The schematic diagram of the corresponding layer structure formed in step S300 is shown;

[0041] Figure 23 for Figure 6 The schematic diagram of the top view structure formed corresponding to step S300 is shown;

[0042] Figure 24 for Figure 6 The schematic diagram of the corresponding layer structure formed in step S400 is shown;

[0043] Figure 25 for Figure 6 The schematic diagram of the top view structure formed corresponding to step S400 is shown;

[0044] Figure 26 for Figure 6 A schematic diagram of the corresponding layer structure formed in step S500 is shown;

[0045] Figure 27 for Figure 6 The schematic diagram of the top view structure formed corresponding to step S500 is shown.

[0046] Description of reference numerals:

[0047] 1-display device; 10-display panel; 11-drive substrate; 12-liquid crystal layer; 13-color filter substrate; 30-backlight module; 110-substrate; 120-transistor; 121-drain; 122-source; 123-gate; 124-insulating layer; 125-semiconductor layer; 126-first doping layer; 127-second doping layer; 130-passivation layer; 130a-via; 140-electrode; 210-metal layer; 220-photoresist layer; 230-first light shielding plate; 240-insulating structure; 250-photoresist; 251-first sub-photoresist; 252-second sub-photoresist; 260-second light shielding plate; 261-first light shielding portion; 262-second light shielding portion; 270-semiconductor structure; 280-doping structure; 290-doped transition structure; 310-photoresist structure; 330-third light shielding plate; 331-third light shielding portion; 332-fourth light shielding portion; 333-fifth light shielding portion; 1241-first boss; 1241a-first surface; 1241b-inclined surface; 1242-second boss; 1242a-second surface; 1243-insulating layer body; 1251-first semiconductor; 1252-second semiconductor; 1253-third semiconductor; step S100-step S500-steps of the method for manufacturing a driving substrate; step S110-step S120-steps of step S100; step S121-step S124-steps of step S120; step S210-step S230-steps of step S200. DETAILED DESCRIPTION

[0048] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0049] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers of the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application include direct and indirect connections (couplings) unless otherwise specified. The directional terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0050] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal connections between two components. A person of ordinary skill in the art will understand the specific meanings of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," and so on, in the specification, claims, and accompanying drawings of this application are used to distinguish between different objects, not to describe a specific order. Furthermore, the terms "include," "may include," "comprise," or "may include" as used in this application indicate the presence of the corresponding functions, operations, components, etc. disclosed, and do not limit the presence or absence of one or more additional functions, operations, components, etc. Furthermore, the terms "include" or "comprising" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. It should also be understood that "at least one" described herein means one or more, such as one, two or three, etc., and "plurality" means at least two, such as two or three, etc., unless otherwise clearly defined.

[0051] Terms such as "parallel" and "perpendicular" are defined based on current technological advancements and are not strictly mathematical definitions. A small amount of deviation is permitted, and terms such as approximately parallel or approximately perpendicular are acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 5 degrees. For another example, "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 85 and 95 degrees.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0053] See also Figure 1 , Figure 1 This is a schematic diagram of the layer structure of the display device disclosed in the embodiments of this application. The display device 1 provided in the embodiments of this application can be used in electronic devices including, but not limited to, televisions, smartphones, tablet computers, laptop computers, desktop computers, mobile phones, and in-vehicle displays. According to the embodiments of this application, the specific type of the display device 1 is not particularly limited. Those skilled in the art can design it accordingly based on the specific application requirements of the display device 1, and no further details are given here.

[0054] The display device 1 includes a stacked display panel 10 and a backlight module 30 . The display panel 10 is disposed on the light-emitting side of the backlight module 30 . The backlight module 30 is used to provide backlight. The display panel 10 is used to display images under the backlight provided by the backlight module 30 .

[0055] In the embodiment of this application, Figure 1 The backlight module 30 shown can be an edge-lit backlight module, or a direct-lit backlight module. The display panel 10 can be a twisted nematic (TN) display panel, a vertical alignment (VA) display panel, an in-plane switching (IPS) display panel, or a fringe field switching (FFS) display panel, and this application does not impose any specific restrictions on this.

[0056] In an exemplary embodiment, the display device 1 may further include other necessary components and elements, such as a driver board, a power board, a high-voltage board, and a key control board. The power board is electrically connected to the display panel 10 and is used to supply power to the display panel 10. Those skilled in the art may make additional modifications based on the specific type and actual function of the display device 1, and detailed description is omitted here.

[0057] In some embodiments, the display device 1 may further include a processor and a memory, wherein the processor is electrically connected to the display panel 10 and is used to control the display panel 10 to display. The memory is electrically connected to the processor and is used to store program codes required for the processor to run and control the display content of the display panel 10.

[0058] In an exemplary embodiment, the memory may include volatile memory, such as random access memory (RAM); the memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory (FM), hard disk drive (HDD), or solid-state drive (SSD). The memory may also include a combination of the above types of memory.

[0059] In an exemplary embodiment, the processor includes one or more general-purpose processors, wherein a general-purpose processor can be any type of device capable of processing electronic instructions, including a central processing unit (CPU), a microprocessor, a microcontroller, a main processor, a controller, etc. The processor is used to execute various types of digital storage instructions, such as software or firmware programs stored in memory, which enables the computing device to provide a wide variety of services.

[0060] See also Figure 2 , Figure 2 This is a schematic diagram of the layer structure of the display panel disclosed in an embodiment of the present application. The display panel 10 includes a drive substrate 11, a liquid crystal layer 12, and a color filter substrate 13. The drive substrate 11 and the color filter substrate 13 are arranged opposite and spaced apart. The liquid crystal layer 12 is arranged between the drive substrate 11 and the color filter substrate 13. The drive substrate 11 is used to form a preset electric field, which is used to drive the liquid crystal molecules in the liquid crystal layer 12 to deflect, thereby changing the transmittance of the liquid crystal layer 12. The drive substrate 11 is also the array substrate of the liquid crystal display panel, that is, the drive substrate 11 is applied to the liquid crystal display panel.

[0061] It should be noted that the driving substrate 11 of the present application can also be applied to organic light-emitting diode (OLED) display panels, sub-millimeter light-emitting diode (Mini LED) display panels and micron light-emitting diode (Micro LED) display panels, and the present application does not impose any specific restrictions on this.

[0062] See also Figure 3 , Figure 3Schematic diagram of the layer structure of the drive substrate disclosed in the embodiment of the present application. For ease of description, in the embodiment of the present application, the width direction or length direction of the display panel 10 is defined as the X-axis direction, and the thickness direction of the display panel 10 is defined as the Y-axis direction, wherein the X-axis direction and the Y-axis direction are perpendicular to each other.

[0063] In the embodiment of the present application, the driving substrate 11 includes a substrate 110, a transistor 120, a passivation layer 130, and an electrode 140. The transistor 120 is disposed on the substrate 110, and the passivation layer 130 covers the surface of the transistor 120 facing away from the substrate 110. The electrode 140 is disposed on a portion of the surface of the passivation layer 130 facing away from the transistor 120. The passivation layer 130 is used to isolate external media (such as oxygen, moisture, and other impurities) from entering the transistor 120. The transistor 120 may be a MOS transistor, and the electrode 140 may be a pixel electrode or an anode.

[0064] In an exemplary embodiment, the driving substrate 11 further includes a driving circuit, which is electrically connected to the transistors of the driving substrate. The driving circuit is configured to provide the transistors with electrical signals for displaying the display panel.

[0065] In an exemplary embodiment, the transistor 120 includes a drain electrode 121, a source electrode 122, a gate electrode 123, an insulating layer 124, a semiconductor layer 125, a first doped layer 126, and a second doped layer 127. The gate electrode 123 is disposed on a surface of the substrate 110 facing the Y-axis direction, that is, the gate electrode 123 is disposed on a surface of the substrate 110 facing the passivation layer 130. The insulating layer 124 covers a surface of the gate electrode 123 facing away from the substrate 110 and is connected to the surface of the substrate 110 facing the Y-axis direction, that is, the insulating layer 124 covers the gate electrode 123 to the surface of the substrate 110 facing the passivation layer 130. The semiconductor layer 125 is disposed on the portion of the surface of the insulating layer 124 facing away from the gate 123, and the orthographic projection of the semiconductor layer 125 in the Y-axis direction is within the range of the orthographic projection of the gate 123 in the Y-axis direction. That is, the orthographic projection of the semiconductor layer 125 on the substrate 110 is within the range of the orthographic projection of the gate 123 on the substrate 110. The first doped layer 126 and the second doped layer 127 are spaced apart, and both the first doped layer 126 and the second doped layer 127 are disposed on the surface of the semiconductor layer 125 facing away from the insulating layer 124. The drain electrode 121 is spaced apart from the source electrode 122. The drain electrode 121 is disposed on the surface of the first doped layer 126 facing away from the semiconductor layer 125 and covers the portion of the surface of the insulating layer 124 facing away from the substrate 110. The source electrode 122 is disposed on the surface of the second doped layer 127 facing away from the semiconductor layer 125 and covers the portion of the surface of the insulating layer 124 facing away from the substrate 110.

[0066] In the exemplary embodiment of the present application, the orthographic projection of the semiconductor layer 125 on the substrate 110 is located within the range of the orthographic projection of the gate 123 on the substrate 110, which means that: the boundary of the orthographic projection of the semiconductor layer 125 on the substrate 110 falls within the boundary of the orthographic projection of the gate 123 on the substrate 110, or the boundary of the orthographic projection of the gate 123 on the substrate 110 overlaps with the boundary of the orthographic projection of the semiconductor layer 125 on the substrate 110. In other words, the orthographic projection of the gate 123 on the substrate 110 includes the orthographic projection position of the semiconductor layer 125 on the substrate 110.

[0067] The passivation layer 130 covers the drain electrode 121, the source electrode 122, and the surface of the insulating layer 124 facing away from the substrate 110. The passivation layer 130 defines a via 130a, which penetrates the passivation layer 130 along the Y-axis, with the drain electrode 121 exposed through the via 130a. The electrode 140 is disposed on a portion of the surface of the passivation layer 130 facing away from the insulating layer 124 and extends into the via 130a. The electrode 140 is connected to the drain electrode 121 to achieve electrical connection between the electrode 140 and the drain electrode 121.

[0068] In an exemplary embodiment, the insulating layer 124 includes a first boss 1241 , a second boss 1242 and an insulating layer body 1243 . Figure 3 The first and second bosses 1241, 1242, and the insulating layer body 1243 are demarcated by dashed lines. The insulating layer body 1243 covers the surface of the gate 123 facing away from the substrate 110 and is connected to the surface of the substrate 110 facing the Y-axis. In other words, the insulating layer body 1243 covers the gate 123 to the surface of the substrate 110 facing the passivation layer 130. The first and second bosses 1241, 1242 are arranged along the X-axis and are connected to the second bosses 1242. The first and second bosses 1241, 1242 are arranged on the surface of the insulating layer body 1243 facing away from the gate 123. The orthographic projection of the first boss 1241 in the Y-axis direction is within the range of the orthographic projection of the gate 123 in the Y-axis direction, and the orthographic projection of the second boss 1242 in the Y-axis direction is within the range of the orthographic projection of the gate 123 in the Y-axis direction.

[0069] The first boss 1241 includes a first surface 1241a and a sloped surface 1241b. The first surface 1241a is the surface of the first boss 1241 facing away from the insulating layer body 1243, while the sloped surface 1241b is the surface of the first boss 1241 facing toward the second boss 1242. The second boss 1242 includes a second surface 1242a, which is the surface of the second boss 1242 facing away from the insulating layer body 1243. The sloped surface 1241b is connected to the first surface 1241a and the second surface 1242a, respectively. The height of the first surface 1241a in the Y-axis direction is higher than the height of the second surface 1242a in the Y-axis direction, that is, the first surface 1241a is higher than the second surface 1242a. The sloped surface 1241b forms an angle with the Y-axis direction, that is, the sloped surface 1241b forms an angle with the first surface 1241a and the second surface 1242a, respectively.

[0070] The semiconductor layer 125 includes a first semiconductor 1251, a second semiconductor 1252, and a third semiconductor 1253. The first semiconductor 1251 and the second semiconductor 1252 are spaced apart, and the third semiconductor 1253 is disposed between the first semiconductor 1251 and the second semiconductor 1252, and the third semiconductor 1253 is connected to the first semiconductor 1251 and the second semiconductor 1252, respectively.

[0071] The thickness of the third semiconductor 1253 is smaller than that of the first semiconductor 1251 , and the thickness of the third semiconductor 1253 is smaller than that of the second semiconductor 1252 .

[0072] The first semiconductor 1251 is disposed on the first surface 1241a, the second semiconductor 1252 is disposed on the second surface 1242a, and the third semiconductor 1253 is disposed on the inclined surface 1241b. Because the third semiconductor 1253 is disposed on the inclined surface 1241b, it can be tilted relative to the first semiconductor 1251 and tilted relative to the second semiconductor 1252. That is, the first semiconductor 1251 is parallel to the X-axis, and the thickness of the first semiconductor 1251 is parallel to the Y-axis. The second semiconductor 1252 is parallel to the X-axis, and the thickness of the second semiconductor 1252 is parallel to the Y-axis. The third semiconductor 1253 forms an angle with both the X-axis and the Y-axis.

[0073] In an exemplary embodiment, the first doping layer 126 is arranged on the surface of the first semiconductor 1251 facing away from the insulating layer 124, the second doping layer 127 is arranged on the surface of the second semiconductor 1252 facing away from the insulating layer 124, the drain 121 is arranged on the surface of the first doping layer 126 facing away from the first semiconductor 1251, and the source 122 is arranged on the surface of the second doping layer 127 facing away from the second semiconductor 1252.

[0074] It can be understood that the present application reduces the leakage current of the transistor 120 under high negative bias conditions of the gate 123 by making the thickness of the third semiconductor 1253 smaller than the thickness of the first semiconductor 1251 and the thickness of the third semiconductor 1253 smaller than the thickness of the second semiconductor 1252, thereby improving the on / off current ratio of the transistor 120 and improving the display effect of the display panel 10.

[0075] It can also be understood that the height of the first semiconductor 1251 is higher than the height of the second semiconductor 1252, the first doping layer 126 is arranged on the first semiconductor 1251, and the drain 121 is arranged on the first doping layer 126, that is, the distance between the drain 121 and the gate 123 is increased, and the leakage current of the transistor 120 under high negative bias conditions of the gate 123 is further reduced.

[0076] The principle of increasing the distance between the drain 121 and the gate 123 to reduce the leakage current of the transistor 120 is that under the action of an external voltage, the energy band structure of the transistor 120 changes, thereby forming an on-state with low channel resistance and an off-state with high channel resistance. Figure 4 , Figure 4 Figure 1 shows the voltage setting and channel partitioning of a transistor. Assuming the source voltage Vs = 0V and the drain voltage Vd > 0V, the drain-source voltage difference Vds > 0V. When the gate voltage Vg < 0V (i.e., Vgs < 0V), electrons in the front channel near the insulating layer are expelled by the negative electric field, causing the transistor to be in the off state. At this point, the front channel region of the amorphous silicon (a-Si) near the insulating layer has a high hole density and a low electron density, resulting in a significant difference in carrier distribution compared to the interior of the amorphous silicon. As the negative gate bias continues to increase, and under the combined effects of a large negative Vgs and positive Vds, hot ions are generated between the gate and drain, emitting holes. These holes, acting as carriers, accumulate at the interface between the amorphous silicon and the insulating layer, further increasing the hole density. Eventually, when these holes accumulate to a certain level, they migrate to the drain, generating hole current and causing leakage. Therefore, if the distance between the drain and gate can be appropriately increased, the negative electric field effect will be weakened, and the generation of leakage current can be effectively reduced. The present application effectively increases the distance between the drain and gate through a stepped design. Compared with existing transistors, the occurrence of hole leakage can be better reduced, that is, the leakage current of transistor 120 is reduced.

[0077] See also Figure 5 , Figure 5 This is a schematic diagram of the structure of the third semiconductor disclosed in the embodiment of this application. Figure 5 As shown, the thickness of the first semiconductor 1251 is L1, that is, the thickness of the first semiconductor 1251 along the Y-axis is L1. The thickness of the third semiconductor 1253 along the Y-axis is L2, where L2 is equal to L1. The thickness of the third semiconductor 1253 is L3, where L3 is equal to L2 × cosθ. θ is the angle between the inclined surface 1241b and the X-axis, and L3 is inversely proportional to the angle θ, that is, L3 decreases as θ increases.

[0078] Since the actual thickness of the third semiconductor 1253 is L3, and L3 is smaller than L2, which is smaller than L1, the third semiconductor 1253 is tilted to reduce its thickness, thereby achieving a thinner channel.

[0079] Existing technologies use deep / extreme ultraviolet (EUV) or electron beam lithography to reduce channel thickness, but these techniques are not suitable for large-scale mass production. For mass-produced display panels, current processes primarily rely on coating and etching to achieve the target channel thickness. Reducing the coating thickness to achieve thinner channels compromises surface uniformity, negatively impacting electrical performance. Prolonging the etching time to achieve thinner channels can lead to over-etching and channel breakage, resulting in lower display panel yields.

[0080] As can be understood, the technical solution of the present application tilts the third semiconductor 1253 to reduce the thickness of the third semiconductor 1253. The thinner third semiconductor 1253 can achieve a smaller subthreshold swing, allowing the transistor 120 to switch between on and off more quickly, reducing the operating voltage and, in turn, the power consumption of the transistor 120. Furthermore, the surface of the third semiconductor 1253 of the present application is relatively uniform and there is no risk of scratching.

[0081] In an exemplary embodiment, the semiconductor layer 125 may be single crystal silicon or amorphous silicon, and the first doping layer 126 and the second doping layer 127 may be doping layers for doping free electrons.

[0082] In summary, the display device 1 provided in the embodiments of the present application includes a display panel 10, which includes a drive substrate 11. The drive substrate 11 includes a substrate 110 and a transistor 120. The transistor 120 includes a drain electrode 121, a source electrode 122, a gate electrode 123, an insulating layer 124, a semiconductor layer 125, a first doping layer 126, and a second doping layer 127. The gate electrode 123 is disposed on the surface of the substrate 110 facing the Y-axis, and the insulating layer 124 covers the surface of the gate electrode 123 facing away from the substrate 110. The semiconductor layer 125 is disposed on the surface of the insulating layer 124 facing away from the gate electrode 123. The first doping layer 126 and the second doping layer 127 are both disposed on the surface of the semiconductor layer 125 facing away from the insulating layer 124, with the first doping layer 126 and the second doping layer 127 spaced apart. The drain electrode 121 is spaced apart from the source electrode 122, and the drain electrode 121 is disposed on the surface of the first doping layer 126 facing away from the semiconductor layer 125. The source electrode 122 is disposed on the surface of the second doped layer 127 facing away from the semiconductor layer 125. The semiconductor layer 125 includes a first semiconductor 1251, a second semiconductor 1252, and a third semiconductor 1253. The first semiconductor 1251 and the second semiconductor 1252 are spaced apart, and the third semiconductor 1253 is disposed between the first semiconductor 1251 and the second semiconductor 1252, and is connected to the first semiconductor 1251 and the second semiconductor 1252, respectively. The thickness of the third semiconductor 1253 is thinner than that of the first semiconductor 1251, and the thickness of the third semiconductor 1253 is thinner than that of the second semiconductor 1252. Therefore, by making the thickness of the third semiconductor 1253 thinner than that of the first semiconductor 1251 and the thickness of the third semiconductor 1253 thinner than that of the second semiconductor 1252, the present application reduces the leakage current of the transistor 120 under high negative bias conditions of the gate 123, thereby improving the on / off current ratio of the transistor 120 and enhancing the display quality of the display panel 10.

[0083] See also Figure 6 , Figure 6 This is a flow chart of the manufacturing method of the drive substrate disclosed in the embodiment of this application. The manufacturing method of the drive substrate is used to form the above-mentioned drive substrate 11. For the description of the similarities between the structure involved in the manufacturing method of the drive substrate and the structure of the drive substrate 11, please refer to the relevant description of the drive substrate 11 in the above embodiment, which will not be repeated here. Figure 6 and Figure 3 The manufacturing method of the driving substrate 11 specifically includes the following steps.

[0084] Step S100 : providing a substrate 110 , sequentially forming a gate 123 and an insulating layer 124 on the substrate 110 , wherein the insulating layer 124 covers the gate 123 to the substrate 110 .

[0085] Step S200: A semiconductor layer 125, a first doping layer 126, and a second doping layer 127 are sequentially formed on the surface of the insulating layer 124 facing away from the gate 123, wherein the semiconductor layer 125 includes a first semiconductor 1251, a second semiconductor 1252, and a third semiconductor 1253. The first semiconductor 1251 and the second semiconductor 1252 are spaced apart, the third semiconductor 1253 is disposed between the first semiconductor 1251 and the second semiconductor 1252, and the third semiconductor 1253 is connected to the first semiconductor 1251 and the second semiconductor 1252, respectively. The thickness of the third semiconductor 1253 is less than the thickness of the first semiconductor 1251, and the thickness of the third semiconductor 1253 is less than the thickness of the second semiconductor 1252. The first doping layer 126 and the second doping layer 127 are spaced apart, the first doping layer 126 is located on the surface of the first semiconductor 1251 facing away from the insulating layer 124, and the second doping layer 127 is located on the surface of the second semiconductor 1252 facing away from the insulating layer 124.

[0086] Step S300 , forming a drain 121 on the first doping layer 126 and a source 122 on the second doping layer 127 , wherein the drain 121 also covers a portion of the surface of the insulating layer 124 , and the source 122 also covers a portion of the surface of the insulating layer 124 .

[0087] In step S400 , a passivation layer 130 is formed on the drain electrode 121 and the source electrode 122 , and a via hole 130 a is opened in the passivation layer 130 , so that the drain electrode 121 is exposed through the via hole 130 a .

[0088] In step S500 , an electrode 140 is formed in the via hole 130 a and on a portion of the surface of the passivation layer 130 facing away from the insulating layer 124 , and the electrode 140 is electrically connected to the drain electrode 121 .

[0089] See also Figure 7 , Figure 7 Schematic diagram of the process of step S100 in the method for manufacturing a driving substrate disclosed in an embodiment of the present application. Step S100 includes the following sub-steps.

[0090] Step S110 , providing a substrate 110 , and forming a gate 123 on the substrate 110 .

[0091] Specifically, see Figure 8 , Figure 8Schematic diagram of the sub-steps of step S110. A metal layer 210 is deposited on the substrate 110 by a physical vapor deposition process (PVD). Then a layer of photoresist is coated on the surface of the metal layer 210 facing away from the substrate 110 to form a photoresist layer 220. After vacuum drying and pre-baking, the metal layer 210 is exposed using the first light shielding plate 230 as a mask, and then the metal layer 210 is developed and cured. The prepared etching solution (for example, Cu acid) is used to etch the metal layer 210 by immersion or spraying to form a gate 123. After etching is completed, the remaining photoresist is removed using a photoresist remover, and then the substrate 110 is cleaned again to thoroughly clean the photoresist remover, etching solution and residues on the surface of the substrate 110 to complete the preparation of the gate 123. The gate 123 formed is as shown in FIG. Figure 9 and Figure 10 As shown, Figure 9 for Figure 7 The schematic diagram of the corresponding layer structure formed in step S110 is shown. Figure 10 for Figure 7 The schematic diagram of the top view of the structure formed in step S110 is shown, wherein the metal layer 210 may be copper.

[0092] Step S120 : forming an insulating layer 124 on the surface of the gate 123 facing away from the substrate 110 , wherein the insulating layer 124 covers the gate 123 on the substrate 110 .

[0093] See also Figure 11 , Figure 11 Schematic diagram of the process of step S120 in the method for manufacturing a driving substrate disclosed in an embodiment of the present application.

[0094] Step S121: forming an insulating structure 240 on the substrate 110, wherein the insulating structure 240 covers the gate 123, and forming a photoresist 250 on a surface of the insulating structure 240 facing away from the gate 123, wherein the photoresist 250 includes a first sub-photoresist 251 and a second sub-photoresist 252, wherein the first sub-photoresist 251 is connected to the second sub-photoresist 252, and the height of the second sub-photoresist 252 is higher than the height of the first sub-photoresist 251.

[0095] Specifically, see Figure 12 , Figure 12 for Figure 11Schematic diagram of the corresponding layer structure formed in step S121. An insulating structure 240 is formed on the substrate 110 by chemical vapor deposition (CVD), wherein the insulating structure 240 is composed of a mixture of silicon nitride (SiNx) and silicon oxide (SiOx), and the ratio of SiNx to SiOx can be adjusted as needed. Then, a layer of photoresist material is coated on the insulating structure 240 to form a photoresist 250. After vacuum drying and pre-baking, a second light shielding plate 260 is set above the photoresist 250, and the photoresist 250 is exposed using the second light shielding plate 260 as a mask. Then, the photoresist 250 is developed, cured and etched to form a stepped photoresist 250, that is, the height of the second sub-photoresist 252 is higher than the height of the first sub-photoresist 251.

[0096] It should be noted that the second light shielding plate 260 includes a first light shielding portion 261 and a second light shielding portion 262 . The first light shielding portion 261 is semi-transparent, and the second light shielding portion 262 is opaque, so that the formed light block 250 is stepped.

[0097] In an exemplary embodiment, the orthographic projection of the photoresist 250 in the Y-axis direction is within the range of the orthographic projection of the gate 123 in the Y-axis direction, that is, the orthographic projection of the photoresist 250 on the substrate 110 is within the range of the orthographic projection of the gate 123 on the substrate 110.

[0098] Step S122 , etching the portion of the insulating structure 240 that is not blocked by the photoresist 250 toward the substrate 110 .

[0099] Specifically, see Figure 13 , Figure 13 for Figure 11 Schematic diagram of the corresponding layer structure formed in step S122. The portion of the insulating structure 240 not blocked by the photoresist 250 is first etched using plasma gas (e.g., a mixture of CF and oxygen, a mixture of CHF and oxygen, or a mixture of SF and oxygen). The portion of the insulating structure 240 not blocked by the photoresist 250 is etched away toward the substrate 110, thereby reducing the thickness of the portion of the insulating structure 240 not blocked by the photoresist 250.

[0100] Step S123 , removing the first sub-photoresist 251 and retaining the second sub-photoresist 252 .

[0101] Specifically, see Figure 14 , Figure 14 for Figure 11The schematic diagram of the corresponding layer structure formed in step S123 is shown. The photoresist 250 is cleaned. Since the thickness of the first sub-photoresist 251 and the second sub-photoresist 252 are inconsistent, the thinner first sub-photoresist 251 is removed and the thicker second sub-photoresist 252 is retained.

[0102] Step S124 , etching the portion of the insulating structure 240 that is not blocked by the second sub-photoresist 252 toward the substrate 110 to form a first boss 1241 and a second boss 1242 .

[0103] Specifically, see Figure 15 , Figure 15 for Figure 11 The schematic diagram of the corresponding layer structure formed in step S124 is shown, Figure 16 for Figure 11 The schematic diagram of the top view of the structure formed in step S124 is shown. The insulating structure 240 is etched a second time using a plasma gas (e.g., a mixture of CF and oxygen, a mixture of CHF and oxygen, or a mixture of SF and oxygen) to form the first and second protrusions 1241 and 1242 of the insulating layer 124. After etching, the second sub-photoresist 252 is removed using a photoresist stripping solution, and the resulting structure is then cleaned to remove the photoresist, etching solution, and residues.

[0104] In an exemplary embodiment, the insulating layer 124 includes a first boss 1241, a second boss 1242, and an insulating layer body 1243. The insulating layer body 1243 covers the gate 123 and the substrate 110. The first boss 1241 and the second boss 1242 are disposed on the surface of the insulating layer body 1243 facing away from the gate 123. The first boss 1241 includes a first surface 1241a and an inclined surface 1241b, and the second boss 1242 includes a second surface 1242a. The inclined surface 1241b is located between the first surface 1241a and the second surface 1242a, respectively connected to the first surface 1241a and the second surface 1242a. The height of the first surface 1241a in the Y-axis direction is higher than the height of the second surface 1242a in the Y-axis direction, that is, the first surface 1241a is higher than the second surface 1242a.

[0105] See also Figure 17 , Figure 17 Schematic diagram of the process of step S200 in the method for manufacturing a driving substrate disclosed in an embodiment of the present application. Step S200 includes the following steps.

[0106] Step S210 , forming a semiconductor structure 270 on the insulating layer 124 , forming a doping structure 280 on a surface of the semiconductor structure 270 facing away from the insulating layer 124 , and forming a photoresist structure 310 on a surface of the doping structure 280 facing away from the semiconductor structure 270 .

[0107] Specifically, see Figure 18 , Figure 18 for Figure 17 Schematic diagram of the corresponding layer structure formed in step S210. A semiconductor structure 270 is formed on the insulating layer 124 through a deposition process. The semiconductor structure 270 covers the first surface 1241a, the inclined surface 1241b, and the second surface 1242a. A doped structure 280 is formed on the surface of the semiconductor structure 270 facing away from the insulating layer 124 through a deposition process. A photoresist material is applied to the surface of the doped structure 280 facing away from the insulating layer 124. After vacuum drying and pre-baking to shape the material, a photoresist structure 310 is formed through exposure, development, curing, and etching processes.

[0108] In an exemplary embodiment, the orthographic projection of the first surface 1241a in the Y-axis direction is located within the orthographic projection of the light-blocking structure 310 in the Y-axis direction, the orthographic projection of the inclined surface 1241b in the Y-axis direction is located within the orthographic projection of the light-blocking structure 310 in the Y-axis direction, and the orthographic projection of the second surface 1242a in the Y-axis direction is located within the orthographic projection of the light-blocking structure 310 in the Y-axis direction. In other words, the orthographic projections of the first surface 1241a, the inclined surface 1241b, and the second surface 1242a in the Y-axis direction are all located within the orthographic projection of the light-blocking structure 310 in the Y-axis direction.

[0109] Step S220 , removing the portion of the semiconductor structure 270 not blocked by the photoblocking structure 310 to form the semiconductor layer 125 , and removing the portion of the doping structure 280 not blocked by the photoblocking structure 310 to form the doping transition structure 290 .

[0110] Specifically, see Figure 19 , Figure 19 for Figure 17Schematic diagram of the corresponding layer structure formed in step S220. A third light shielding plate 330 is disposed directly above the first surface 1241a, the inclined surface 1241b, and the second surface 1242a. The orthographic projection of the third light shielding plate 330 in the Y-axis direction coincides with the orthographic projection of the photoresist structure 310 in the Y-axis direction. The semiconductor structure 270 is exposed using the third light shielding plate 330 as a mask. The semiconductor structure 270 and the doping structure 280 are then developed, cured, and etched. The portion of the semiconductor structure 270 not blocked by the photoresist structure 310 is removed to form the semiconductor layer 125. The portion of the doping structure 280 not blocked by the photoresist structure 310 is removed to form the doping transition structure 290.

[0111] In an exemplary embodiment, the semiconductor layer 125 covers the first surface 1241 a , the inclined surface 1241 b , and the second surface 1242 a . The doped transition structure 290 is located on the surface of the semiconductor layer 125 facing away from the insulating layer 124 .

[0112] In the prior art, deep / extreme ultraviolet or electron beam lithography technology is used to reduce the thickness of the channel, but it is not suitable for large-scale mass production. For display panels produced on a large scale, the current process mainly uses coating and etching to achieve channel preparation of target thickness. If a thinner channel is achieved by reducing the coating thickness, the uniformity of the channel surface cannot be guaranteed, which will have a negative impact on the electrical performance. If a thinner channel is achieved by extending the etching time, over-engraving may occur, resulting in channel breakage, resulting in a low yield of the display panel. However, the present application forms a third semiconductor 1253 on the bevel 1241b, so that the thickness of the third semiconductor 1253 is less than the thickness of the first semiconductor 1251 and the thickness of the third semiconductor 1253 is less than the thickness of the second semiconductor 1252. Moreover, the surface of the third semiconductor 1253 is relatively uniform and there is no risk of breakage.

[0113] In step S230 , the doping transition structure 290 at a position corresponding to the third semiconductor 1253 of the semiconductor layer 125 is removed to form a first doping layer 126 and a second doping layer 127 .

[0114] Specifically, see Figure 20 and Figure 21 , Figure 20 for Figure 17 The schematic diagram of the corresponding layer structure formed in step S230 is shown. Figure 21 for Figure 17 The schematic diagram of the top view structure formed corresponding to step S230 is shown.

[0115] Specifically, the third light shielding plate 330 includes a third light shielding portion 331, a fourth light shielding portion 332, and a fifth light shielding portion 333. The third light shielding portion 331 and the fourth light shielding portion 332 are opaque, and the fifth light shielding portion 333 is semi-transparent. The doped structure 280 is exposed using the third light shielding plate 330 as a mask, and then the doped transition structure 290 is developed, cured, and etched to remove the portion of the doped transition structure 290 that is not blocked by the third light shielding portion 331 and the fourth light shielding portion 332. That is, the doped transition structure 290 at the corresponding position below the fifth light shielding portion 333 is also removed to form the first doped layer 126 and the second doped layer 127. After the first doped layer 126 and the second doped layer 127 are formed, the photoresist structure 310 is removed. The photoresist structure 310 is used to protect the first doped layer 126 and the second doped layer 127 from being removed.

[0116] In a possible implementation, the third semiconductor 1253 is etched by using the third light shielding portion 331 and the fourth light shielding portion 332 as masks, thereby further reducing the thickness of the third semiconductor 1253 .

[0117] See also Figure 22 and Figure 23 , Figure 22 for Figure 6 The schematic diagram of the corresponding layer structure formed in step S300 is shown. Figure 23 for Figure 6 The schematic diagram of the top view structure formed corresponding to step S300 is shown.

[0118] Specifically, after forming a semiconductor layer 125, a first doped layer 126, and a second doped layer 127 in sequence on the surface of the insulating layer 124 facing away from the gate 123, a physical vapor deposition (PVD) process, followed by exposure, development, curing, and etching, is used to form the drain electrode 121 on the first doped layer 126 and the source electrode 122 on the second doped layer 127. After forming the drain electrode 121 and the source electrode 122, a photoresist stripping solution is used to remove the photoresist on the structure, and then the photoresist, etching solution, and residue on the structure are cleaned.

[0119] See also Figure 24 and Figure 25 , Figure 24 for Figure 6 The schematic diagram of the corresponding layer structure formed in step S400 is shown, Figure 25 for Figure 6 The schematic diagram of the top view structure formed corresponding to step S400 is shown.

[0120] Specifically, a drain electrode 121 is formed on the first doped layer 126, and a source electrode 122 is formed on the second doped layer 127. A passivation layer 130 is then formed on the drain electrode 121 and the source electrode 122 through a chemical vapor deposition process, followed by exposure, development, curing, and etching. The passivation layer 130 also covers the insulating layer 124. A via 130a is formed in the passivation layer 130, and the drain electrode 121 is exposed through the via 130a.

[0121] See also Figure 26 and Figure 27 , Figure 26 for Figure 6 The schematic diagram of the corresponding layer structure formed in step S500 is shown. Figure 27 for Figure 6 The schematic diagram of the top view structure formed corresponding to step S500 is shown.

[0122] Specifically, a passivation layer 130 is formed on the drain electrode 121 and the source electrode 122, and after a via hole 130a is opened in the passivation layer 130, an electrode 140 is formed in the via hole 130a and on the surface of the passivation layer 130 facing away from the insulating layer 124 through plating, photoresist coating, exposure, etching, and photoresist stripping processes. Since the drain electrode 121 is exposed through the via hole 130a, the electrode 140 is electrically connected to the drain electrode 121.

[0123] In summary, the manufacturing method of the driving substrate provided in the embodiment of the present application includes: providing a substrate 110 , sequentially forming a gate 123 and an insulating layer 124 on the substrate 110 , and the insulating layer 124 covers the gate 123 to the substrate 110 . A semiconductor layer 125, a first doping layer 126, and a second doping layer 127 are sequentially formed on the surface of the insulating layer 124 facing away from the gate 123. The semiconductor layer 125 includes a first semiconductor 1251, a second semiconductor 1252, and a third semiconductor 1253. The first semiconductor 1251 and the second semiconductor 1252 are spaced apart, the third semiconductor 1253 is disposed between the first semiconductor 1251 and the second semiconductor 1252, and the third semiconductor 1253 is connected to the first semiconductor 1251 and the second semiconductor 1252, respectively. The thickness of the third semiconductor 1253 is less than that of the first semiconductor 1251, and the thickness of the third semiconductor 1253 is less than that of the second semiconductor 1252. The first doping layer 126 and the second doping layer 127 are spaced apart. The first doping layer 126 is located on the surface of the first semiconductor 1251 facing away from the insulating layer 124, and the second doping layer 127 is located on the surface of the second semiconductor 1252 facing away from the insulating layer 124. A drain electrode 121 is formed on the first doped layer 126, and a source electrode 122 is formed on the second doped layer 127. The drain electrode 121 also covers a portion of the surface of the insulating layer 124, and the source electrode 122 also covers a portion of the surface of the insulating layer 124. Therefore, in the present application, by making the thickness of the third semiconductor 1253 smaller than the thickness of the first semiconductor 1251, and the thickness of the third semiconductor 1253 smaller than the thickness of the second semiconductor 1252, the leakage current of the transistor 120 under high negative bias conditions is reduced, thereby improving the on / off current ratio of the transistor 120 and enhancing the display effect of the display panel 10.

[0124] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0125] It should be understood that the application of this application is not limited to the above examples. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the scope of protection of the claims appended to this application. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments and making equivalent changes in accordance with the claims of this application still fall within the scope of this application.

Claims

1. A driving substrate comprising a substrate and a transistor disposed on the substrate, characterized in that: The transistor includes a drain, a source, a gate, an insulating layer, a semiconductor layer, a first doping layer and a second doping layer, wherein the insulating layer covers the gate on the substrate, and the semiconductor layer is arranged on a surface of the insulating layer facing away from the gate; The semiconductor layer includes a first semiconductor, a second semiconductor, and a third semiconductor, wherein the first semiconductor and the second semiconductor are spaced apart, the third semiconductor is connected between the first semiconductor and the second semiconductor, and the thickness of the third semiconductor is smaller than that of the first semiconductor, and the thickness of the third semiconductor is smaller than that of the second semiconductor; The first doped layer is arranged on the surface of the first semiconductor facing away from the insulating layer, the second doped layer is arranged on the surface of the second semiconductor facing away from the insulating layer, the drain is arranged on the surface of the first doped layer facing away from the first semiconductor, and the source is arranged on the surface of the second doped layer facing away from the second semiconductor.

2. The driving substrate according to claim 1, wherein: The first semiconductor is higher than the second semiconductor, and the third semiconductor is inclined.

3. The driving substrate according to claim 2, wherein: The insulating layer includes a first boss, a second boss, and an insulating layer body, the insulating layer body covers the gate on the substrate, the first boss and the second boss are arranged on the surface of the insulating layer body facing away from the gate, the first boss includes a first surface, which is the surface of the first boss facing away from the insulating layer body, the second boss includes a second surface, which is the surface of the second boss facing away from the insulating layer body, and the height of the first surface is higher than the height of the second surface; The first semiconductor is disposed on the first surface, and the second semiconductor is disposed on the second surface.

4. The driving substrate according to claim 3, wherein: The first boss further includes an inclined surface, the inclined surface is connected to the first surface and the second surface respectively, and forms an angle with the first surface and the second surface respectively. The third semiconductor is disposed on the inclined surface.

5. The driving substrate according to any one of claims 1 to 4, wherein: The driving substrate further includes a passivation layer and an electrode, wherein the passivation layer covers the drain electrode, the source electrode, and a surface of the insulating layer facing away from the substrate, the passivation layer is provided with a via hole, the via hole penetrates the passivation layer, and the drain electrode is exposed through the via hole; The electrode is disposed on a portion of the surface of the passivation layer facing away from the insulating layer and extends into the via hole. The electrode is connected to the drain electrode to achieve electrical connection between the electrode and the drain electrode.

6. A method for manufacturing a driving substrate, characterized in that: Used to form the driving substrate according to any one of claims 1 to 5, the manufacturing method of the driving substrate comprising: Providing a substrate, and sequentially forming a gate and an insulating layer on the substrate, wherein the insulating layer covers the gate to the substrate; A semiconductor layer, a first doped layer, and a second doped layer are sequentially formed on a surface of the insulating layer facing away from the gate, wherein the semiconductor layer includes a first semiconductor, a second semiconductor, and a third semiconductor, wherein the first semiconductor is spaced apart from the second semiconductor, and the third semiconductor is connected between the first semiconductor and the second semiconductor, wherein the thickness of the third semiconductor is less than that of the first semiconductor, and the thickness of the third semiconductor is less than that of the second semiconductor, wherein the first doped layer is located on a surface of the first semiconductor facing away from the insulating layer, and wherein the second doped layer is located on a surface of the second semiconductor facing away from the insulating layer; A drain electrode is formed on the first doping layer and a source electrode is formed on the second doping layer.

7. The method for manufacturing a driving substrate according to claim 6, wherein: The step of sequentially forming a gate and an insulating layer on the substrate comprises: forming a gate on the substrate; forming an insulating structure on the substrate, the insulating structure covering the gate, and forming a photoresist on a surface of the insulating structure opposite to the gate, the photoresist comprising a first sub-photoresist and a second sub-photoresist, the first sub-photoresist being connected to the second sub-photoresist, and the second sub-photoresist having a height higher than that of the first sub-photoresist; Etching the portion of the insulating structure not blocked by the photoresist in a direction close to the substrate; removing the first sub-photoresist and retaining the second sub-photoresist; The portion of the insulating structure not blocked by the second sub-photoresist is etched toward the substrate to form a first boss and a second boss.

8. The method for manufacturing a driving substrate according to claim 6, wherein: The step of sequentially forming a semiconductor layer, a first doping layer, and a second doping layer on a surface of the insulating layer facing away from the gate comprises: forming a semiconductor structure on the insulating layer, forming a doping structure on a surface of the semiconductor structure facing away from the insulating layer, and forming a photoresist structure on a surface of the doping structure facing away from the semiconductor structure; removing the portion of the semiconductor structure not blocked by the photoresist structure to form a semiconductor layer, and removing the portion of the doping structure not blocked by the photoresist structure to form a doping transition structure; The doping transition structure at a position of the semiconductor layer corresponding to the third semiconductor is removed to form a first doping layer and a second doping layer.

9. A display panel, characterized in that: The invention comprises a driving circuit and the driving substrate according to any one of claims 1 to 5, or comprises a driving substrate formed by the manufacturing method of the driving substrate according to any one of claims 6 to 8, wherein the driving circuit is electrically connected to the transistor of the driving substrate.

10. A display device, characterized in that: The display device comprises a power supply board and the display panel as claimed in claim 9, wherein the power supply board is electrically connected to the display panel and is used to supply power to the display panel.

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