Scalable qubit bias device based on multiplexed charge storage

Abstract

Embodiments of a semiconductor device circuit (100) including a gate for biasing a qubit device and a method for operating the device are disclosed. Embodiments may include a multiplexed array (102, 104, 106, 108) of capacitor cells, where each capacitor cell includes transistor-controlled capacitors (C1, C2, C3, C4), where each capacitor is connected between a drain of a respective transistor (T1, T2, T3, T4) and ground, where each source of all transistors of all capacitor cells is connected to a common control point (111), where the common control point (111) is connected to the common control point (111). And wherein each gate of the transistors of the capacitor cell is individually voltage controllable (Vg1, Vg2, Vgn). The embodiment may include a charging unit (110) connected to the common control point, and a discharging unit (112) connected to the common control point, where the charging unit and the discharging unit are alternately activatable.

Description

Background Art

[0001] The present application generally relates to a semiconductor device circuit, and more particularly to a semiconductor device circuit for biasing a gate of a qubit device. The present application also relates to a method for operating a semiconductor device circuit for biasing a gate of a qubit device.

[0002] Quantum computing remains one of the hottest topics in physics, industry, and research. Classical digital computers and / or processors are slowly reaching their physical limitations, leading researchers to seek new approaches to solving mathematical and other problems that cannot be solved by classical von Neumann machines due to physical limitations in terms of size, power consumption, and ultimately processing speed. Furthermore, commercial enterprises are interested in new computing options.

[0003] Quantum computing is therefore one of the promising fields for achieving quantum supremacy—a true advantage in solving very complex calculations or tasks in a reasonable amount of time. As is well known, conventional computers encode process information in bits (i.e., "1s" and "0s"). Quantum computers, on the other hand, are based on so-called qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition describes a situation in which each qubit can represent a 1 or 0 between possible outcomes of an event, inferring both. Entanglement means that qubits in a superposition can be related to each other in a nonclassical way. That is, the state of one qubit—whether it is 1, 0, or both—can depend on the state of another qubit, and when entangled, the qubits contain more information than a single qubit. Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor device circuit for biasing a gate of a qubit device may be provided. The semiconductor device circuit may include a multiplexed array of capacitor cells. Thus, the following may apply to the capacitor cell array: each capacitor cell may include a transistor-controlled capacitor, each capacitor may be connected between the drain of a corresponding transistor and ground, each source of all transistors of all capacitor cells may be connected to a common control point, and each gate of the transistors of the capacitor cells may be individually voltage-controllable.

[0005] Furthermore, the semiconductor device circuit may include a charging unit connected to the common control point, and a discharging unit connected to the common control point, wherein the charging unit and the discharging unit are alternately activatable.

[0006] According to another aspect of the present invention, a method for operating a semiconductor device circuit for biasing a gate of a qubit device may be provided. The method may include providing a semiconductor device circuit comprising a multiplexed array of capacitor cells. For the multiplexed array of capacitor cells, the following may apply: each capacitor cell may comprise a transistor-controlled capacitor, each capacitor may be connected between the drain of a corresponding transistor and ground, each source of all transistors of all capacitor cells may be connected to a common control point, and each gate of the transistors of the capacitor cells may be individually voltage-controllable. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] It should be noted that embodiments of the present invention are described with reference to different subject matters. In particular, some embodiments are described with reference to method-type claims, while other embodiments are described with reference to apparatus-type claims. However, unless otherwise indicated, a person skilled in the art will appreciate from the above and following description that, in addition to any combination of features belonging to one type of subject matter, any combination of features relating to different subject matters, in particular any combination of features of method-type claims with features of apparatus-type claims, is also considered to be disclosed in this document.

[0008] The aspects defined below are apparent from the examples of embodiment to be described hereinafter and are explained with reference to the examples of embodiment, to which the invention is not limited.

[0009] Preferred embodiments of the present invention will be described, by way of example only, with reference to the following drawings:

[0010] Figure 1 A block diagram illustrating an embodiment of a semiconductor device circuit of the present invention for biasing a gate of a qubit device;

[0011] Figure 2 is shown in the context of a current driven bias circuit including Figure 1 Figure 1. Block diagram of the ;

[0012] Figure 3a 、 Figure 3b shows different gate voltages V where different capacitor units are activated G1 、V G2 and V G3 and the corresponding output voltage graph;

[0013] Figure 4 shows the activation voltage V for a certain amount of time G1 , that is, at t write period;

[0014] Figure 5 Another diagram with different writing time periods is shown;

[0015] Figure 6 shows a signal flow diagram for an illustrative control algorithm for a two output exemplary embodiment;

[0016] Figure 7 A more complete example of voltage-driven biasing is shown;

[0017] Figure 8 Another voltage driven bias circuit using a DAC is shown;

[0018] Figure 9 Another current driven bias circuit using a DAC is shown; and

[0019] Figure 10 A flow chart describing a process of operating a semiconductor device circuit for biasing a gate of a qubit device in accordance with at least one embodiment is shown. DETAILED DESCRIPTION

[0020] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Details of well-known features and techniques may be omitted from the description to avoid unnecessarily obscuring the presented embodiments.

[0021] In the context of this specification, the following technical conventions, terms and / or expressions may be used:

[0022] The term "bias gate" may refer to a component of a qubit device that is used to define the constraints of the state of an active particle.

[0023] The term "qubit device" may refer to physical devices that currently operate typically in a temperature range below or well below 4 K in order to manipulate the physical states of elementary particles to achieve quantum computing.

[0024] The term "capacitor unit" can refer to a component of the concepts presented herein that includes a transistor and a capacitor, where the drain of the transistor is connected to the capacitor. The source of the transistor can be the input of the capacitor unit, and the common point between the drain of the transistor and the capacitor can be the output of the capacitor unit. The capacitor unit can be controlled via the gate of the transistor. Therefore, the capacitor unit can include a capacitor controlled by a transistor.

[0025] The term "array of capacitor cells" may denote a plurality of capacitor cells that may be activated in a multiplexed manner. Additionally, all capacitor cells of the array may be connected to a common control point, ie via the sources of the transistors of the capacitor cells.

[0026] The term “common control point” may refer to an electrical contact point to which all inputs of all capacitor units and outputs of the charging and discharging units may be connected.

[0027] The term “individually voltage controllable” may mean that each output of the plurality of capacitor units may have a different voltage level (or current).

[0028] The term “charging unit” may refer to a single unit using a transistor in the proposed semiconductor device circuit, which is used to control a supply voltage input of each of the capacitor units.

[0029] The term “discharging unit” may refer to a circuit using another transistor that may be activated at a time when the charging unit may be deactivated in order to discharge one of the capacitors of one of the capacitor units.

[0030] The term “alternately activatable” may mean that only one of both the charging unit and the discharging unit may be activated at the same time.

[0031] The term “first control voltage” may refer to a control signal for controlling a gate of a transistor of a charging unit.

[0032] The term "second control voltage" may refer to a control signal for controlling the gate of a transistor of a discharge cell and thus determining whether current flows through a source / drain channel of the corresponding transistor. The second control voltage may be used in a voltage driving mode.

[0033] The term "third control voltage" may refer to a control signal for controlling the gate of a transistor of a discharge unit and thus determining whether current flows from the source to the drain of the corresponding transistor. The third control voltage may be used in a current drive mode in which current to ground may be measured.

[0034] The term “quasi-constant” may mean that the voltage, in particular the output of the capacitor unit, may be maintained within a predetermined tolerance range between an upper voltage level and a lower voltage level.

[0035] The term “time-based activation” may mean that an activation signal may be periodically provided to a unit to be controlled.

[0036] The term "control gate of a qubit device" may refer to a component of a qubit device that is required for confinement of the active components of the qubit device. Typically, a qubit device may include two or four control gates.

[0037] As mentioned earlier, quantum computing remains one of the hottest topics in physics, industry, and research. Classical digital computers and / or processors are slowly reaching their physical limitations, leading researchers to seek new approaches to solving mathematical and other problems that cannot be solved by classical von Neumann machines due to physical limitations in terms of size, power consumption, and ultimately processing speed. Furthermore, commercial enterprises are interested in new computing options.

[0038] However, achieving quantum supremacy—that is, the ability to essentially solve quantum computing problems that are intractable using classical computing systems—requires a relatively large number of error-free elementary quantum devices (potentially along with error correction mechanisms). Furthermore, quantum devices operate at cryostats and very low temperatures. Typically, three temperature regions are used: (i) room temperature, approximately 300 Kelvin (3 K to 4 Kelvin), and (iii) the temperature level at which quantum devices / quantum chips actually operate, approximately 10 mK. Furthermore, nearly all control electronics operate at room temperature. On the other hand, quantum devices—especially the larger numbers mentioned above—require control signals, signal detection lines, and input lines. Therefore, with n qubits, one can expect at least 2n coaxial cables extending from room temperature down to the 10 mK region where the n qubit devices are operated: one cable for signal control, one cable for bias signals, and one or fewer cables for readout. For newer qubit devices, the total number of signal lines can even exceed this number. This presents a real challenge and bottleneck, as typical coaxial cables require a certain diameter, making it a real physical limitation.

[0039] Therefore, a 1000-qubit machine will require a new level of control and another level of signal management. Therefore, integrated electronics implemented on advanced CMOS nodes that can operate in the 3K to 4K temperature region hold the promise of achieving higher density, improved scalability, low power consumption, and relatively low cost.

[0040] However, current approaches have their limitations. Although DACs (digital-to-analog converters) can operate at 3K, they lack more comprehensive closed-loop control and feedback circuitry or SRAM to store DAC modes. In other cases, a reference clock signal must be provided externally, from a room-temperature waveform generator. In still other cases, if the qubit device is driven to room temperature without any digitization, noise from the CMOS chip used could interfere with the qubit device's quantum state or readout signal.

[0041] In some designs, such as quantum dot qubit devices, even more control wires may be needed to constrain the qubits' degrees of freedom to force them into specific states. This may require even more control and / or signal wires from room temperature to the qubit chip.

[0042] As an example, reference should be made to US 2019 / 0 164 959 A1. This document describes a quantum integrated circuit assembly comprising a quantum circuit component comprising a plurality of qubits and control logic coupled to the quantum circuit component and configured to control the operation of that component, wherein the quantum circuit component and the control logic are provided on a single die. The document also describes a method for manufacturing such an assembly.

[0043] In addition, a publication from TU Delft should be mentioned: “Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing”, authored by Luc Enthofen et al., DOI: https: / / doi.org / 10.1109 / VLSITechnologyandCir46769.2022.9830309, published in 2022 and also included in the proceedings of the 2022 IEEE VLSI Technology and Circuits Conference. . In this paper, a 15b cryogenic CMOS DAC based on a 22nm FinFET process is proposed for multiplexing spin qubit bias. The integrated DAC architecture and robust digitally assisted high-voltage output stage achieve low power consumption (157μW) and small area (0.08mm) independent of the number of biased qubits. 2 ), and the 3V output range far exceeds the nominal supply.

[0044] However, the problem remains that too many control signals and cables may be routed from room temperature to the operating temperature of a quantum chip, so a simple and cost-effective yet robust device for controlling the gate bias of qubit devices is needed.

[0045] Therefore, there is a significant need for a semiconductor device for biasing the gate of a qubit device. The presently described embodiments of a semiconductor device circuit for biasing the gate of a qubit device may include a multiplexed array of capacitor cells. Thus, the following may apply to the array of capacitor cells: each capacitor cell may include a transistor-controlled capacitor, each capacitor may be connected between the drain of a corresponding transistor and ground, each source of all transistors of all capacitor cells may be connected to a common control point, and each gate of the transistors of a capacitor cell may be individually voltage-controllable.

[0046] Furthermore, the semiconductor device circuit may include a charging unit connected to the common control point, and a discharging unit connected to the common control point, wherein the charging unit and the discharging unit are alternately activatable.

[0047] According to another aspect of the present invention, a method for operating a semiconductor device circuit for biasing a gate of a qubit device may be provided. The method may include providing a semiconductor device circuit comprising a multiplexed array of capacitor cells. For the multiplexed array of capacitor cells, the following may apply: each capacitor cell may comprise a transistor-controlled capacitor, each capacitor may be connected between the drain of a corresponding transistor and ground, each source of all transistors of all capacitor cells may be connected to a common control point, and each gate of the transistors of the capacitor cells may be individually voltage-controllable.

[0048] Additionally, embodiments of the presently described semiconductor device circuit may include a charge unit connected to a common control point, and a discharge unit connected to the common control point, wherein the charge unit and the discharge unit may be alternately activatable.

[0049] Furthermore, the presently described methods for utilizing illustrative embodiments of a circuit including a semiconductor device may include selectively and time-based activating one of the capacitor cells of the array of capacitor cells.

[0050] The proposed semiconductor device circuit for biasing the gate of a qubit device may provide several advantages, technical effects, contributions and / or improvements:

[0051] The proposed semiconductor device circuits could address the problem that the external electronics of quantum computers do not scale well. The proposed solution could also achieve significantly better form factors and cost reductions—for example, for racks of AWGs (quantum arbitrary waveform generators)—reduced thermal load on cooling equipment, and overall reduced power consumption. This could be achieved through significantly better scaling of DC current and voltage signals, particularly for electrostatic control of spin qubit devices, and by controlling current in a multiplexed manner (e.g., flux control) for superconducting qubits. Furthermore, it could simplify the implementation of new qubit device variants, which may require more control lines than today's qubit devices.

[0052] The proposed circuit can take digital signals and DC voltages as inputs and generate a range of different voltages or currents as outputs in a multiplexed manner. Therefore, the circuit could be suitable for generating the DC control signals required for spin and superconducting qubits in a scalable manner, meaning a significantly lower number of input signals and cables might be required to control the functionality of the qubits. In particular, the circuit could be well-suited to controlling many bias gates of a qubit device, as the multiplexing occurs in the 3K to 4K temperature range rather than at room temperature.

[0053] Quasi-constant voltage or current multiplexing can be achieved by refreshing the capacitor cells of the circuit. Thus, different voltage levels for each addressed bias gate can be possible. Since the discharge time of the capacitor is very long compared to the required charging time, the on / off ratio can be in the range of 10 4 to 10 6 As a result, hundreds or even thousands of gates can be controlled by a single circuit. This can reduce the amount of equipment required (for example, wiring from room temperature to the temperature level of the qubit device) and operational complexity.

[0054] The combination of local charge storage (i.e., the capacitors of the capacitor cells) and multiplexed charge refresh operations enables these benefits: the ability to generate a large number of quasi-static DC signals for controlling the gates of qubit designs. By controlling three charge refresh time constants (explained in more detail below), DC signal level control can be achieved using only a single digital control signal. This signal generation is well-suited for tight integration with qubit devices to provide the required DC control signals. Consequently, the proposed concept can be more energy-efficient and compact than other approaches, such as using DACs (digital-to-analog converters), to generate a large number of quasi-DC levels.

[0055] Furthermore, quasi-constant voltage or current levels can be achieved in two ways: (i) by varying the duty cycle of the control signal to the capacitor cell's transistor while keeping the frequency constant, or (ii) by varying the frequency of the control signal itself while keeping the duty cycle constant. This can also contribute to the flexibility of the proposed concept. Controlling the frequency is particularly attractive because it can be accomplished with relatively simple circuitry (i.e., a voltage-controlled oscillator). In this sense, a single voltage-controlled oscillator, together with control logic and the proposed invention, can control the generation of bias levels for a large number of DC qubits. This is a significantly more efficient solution in terms of power and complexity compared to today's standard approaches.

[0056] Hereinafter, additional embodiments of the inventive concept, largely applicable to semiconductor device circuits and methods, will be described.

[0057] According to an embodiment of the presently described semiconductor device circuit, the charging unit may include a transistor, the drain of which may be connected to the common control point, and the source of which may be connected to a supply voltage, such as V dd , and the gate of the transistor can be connected to a first control voltage for activating the charging unit. Thus, the transistor can operate in a typical switching mode, where the switching mode can be determined by the first control voltage. That is, the source / drain line can be opened or closed by the gate voltage.

[0058] According to another described embodiment of the presently described semiconductor device circuit, a discharge unit—particularly in voltage-driven mode—may include a transistor whose drain can be connected to a common control point, whose source can be connected to ground via a resistor, and whose gate can be connected to a second control voltage for activating the discharge unit. This can allow the amount of charge that may have been stored, i.e., as a voltage in the capacitor of a selected one of the capacitor cells, to be measured. This operating mode can be denoted as voltage-driven mode.

[0059] According to yet another embodiment of the presently described semiconductor device circuit, the discharge unit—particularly in current drive mode—may include a transistor whose drain can be connected to a common control point, whose source can be connected to ground via a current measurement unit, and whose gate can be connected to a second control voltage for activating the discharge unit. Measurements can be performed using a voltage drop across a resistor (i.e., the current measurement unit). This operating mode may be denoted as current drive mode.

[0060] According to another embodiment of the presently described semiconductor device circuit, the voltage level at the drain of a capacitor cell's transistor can be maintained quasi-constant by time-based activation (i.e., continuous reactivation with a constant frequency) of the gate of the corresponding capacitor cell's transistor. Thus, the drain of the transistor can be coupled to one connector of the capacitor (while the other contact of the capacitor is connected to ground, for example) and to the qubit gate. Since only leakage current can flow, "quasi-constant" can be equated to a loss in the capacitor from one of the time-based activation cycles in the range of less than 5%, less than 3%, less than 2%, and less than 1% being achievable.

[0061] In other embodiments, the circuitry may be adapted to be operable in a 3 K environment. Approximately 3 K / 4 K represents a temperature range in which a typical control unit and control logic may operate to control the operation of a qubit device and / or qubit chip that may operate within a 10 mK temperature range.

[0062] According to another embodiment of the semiconductor device circuit, the signal level at the drain of the transistor of the capacitor unit can represent the bias voltage level for the control gate of the qubit device. Therefore, the drain contact of the transistor of the capacitor unit can be in electrical contact with the control gate of the qubit device. No additional electrical components may be required. Thus, this is a very straightforward and technically clean solution for controlling multiple bias gates of a qubit device without requiring coaxial cables to reach room temperature.

[0063] According to another embodiment of the presently described semiconductor device circuit, the discharge time of the capacitor of the capacitor unit can be at least 1000 times greater than the charging time. This may depend on the load and leakage current. However, experiments have shown that factors of up to 1,000,000 should be possible.

[0064] According to another embodiment of the presently described semiconductor device circuit, each transistor in the circuit is of n-type enhancement type. This type of transistor is relatively easy to manufacture and can operate within the 3K / 4K temperature range.

[0065] According to another possible embodiment, the presently described semiconductor device circuit, in particular the capacitor unit, may further include a resistor connected in parallel with the capacitor of the capacitor unit. This may allow for the generation of a controlled discharge current, for example, flux control, which may be used to cause a change in the properties of a superconducting qubit due to the magnetic field that may be generated by the flow of current.

[0066] For the illustrative proposed method, the following additional embodiments may contribute to the advantages of the proposed concept:

[0067] According to one embodiment, the method may further include activating the charging unit by connecting the gate of a transistor of the charging unit to a first control voltage. The source of the transistor of the charging unit may be connected to a supply voltage, and the drain of the transistor of the charging unit may be connected to a common control point. In an embodiment, the method may further include deactivating the discharge unit by connecting the gate of the transistor of the discharge unit to ground. Thus, a controlled electric field at the bias gate of one or more qubit gates or a chip can be achieved by selecting the corresponding capacitor unit and activating the charging unit.

[0068] According to another embodiment, the method may further include periodically (i.e., using a fixed frequency) activating one of the capacitor cells of the array of capacitor cells by applying a recharge voltage to the gate of the transistor of the corresponding capacitor cell, thereby achieving a quasi-constant voltage level at the drain of the transistor of the one capacitor cell. In this way, multiplexing of multiple capacitor cells and, therefore, multiplexing of multiple bias gates of the qubit device may be achieved.

[0069] According to another embodiment, the method may further include periodically (i.e., again using a fixed frequency) activating another capacitor cell in the array of capacitor cells other than one of the capacitor cells, thereby achieving, for example, another quasi-constant voltage level at the drain of the transistor of the other capacitor cell. In conjunction with the subject matter described in the preceding paragraphs, different capacitor cells may be activated, for example, in a cyclic manner. Furthermore, if more capacitor cells are available, they may be activated in a more general multiplexed manner.

[0070] According to yet another embodiment, the method may further comprise controlling—in particular, varying, increasing / decreasing—the frequency of activation of one of the capacitor cells, while maintaining a constant duration of activation, in particular within the activation time period. Thus, the quasi-constant voltage level (possibly another level) may also be influenced at the drain of the transistor of the other capacitor cell. Thus, the quasi-constant voltage level at the output of a capacitor cell may be influenced by the activation time (i.e., the activation voltage at the gate of the transistor of the capacitor cell) or the activation frequency.

[0071] According to another embodiment, the method may further include activating the discharge unit by connecting the gate of the transistor of the discharge unit to a second control voltage. Alternatively, the drain of the transistor of the discharge unit may be connected to a common control point. Furthermore, the charge unit may be simultaneously deactivated, for example, by connecting the gate of the transistor of the charge unit to ground. The discharge effect may be achieved by connecting the source of the transistor of the charge unit to ground via a discharge unit resistor and connecting the drain of the transistor of the charge unit to the common control point. It will be appreciated that either the charge unit or the discharge unit may be activated so as not to create a shortcut.

[0072] According to another embodiment, the method may further comprise measuring the voltage across the discharge unit resistor. Thus, the voltage level of the capacitor of the capacitor unit may be measured. This may allow the amount of charge accumulated at the capacitor to be determined.

[0073] According to an alternative embodiment, the method may further include connecting an output-side resistor in parallel to the capacitors of the capacitor cell and periodically activating one of the capacitor cells of the array of capacitor cells. Thus, a periodic current (which may again be quasi-constant) may be applied through the output-side resistor. This type of operating circuit may be denoted as a current-driven bias mode. It may be used, for example, for flux control of qubits, where the current means a magnetic field that can influence the superconducting qubit device. It may also be noted that the method embodiments above in this paragraph may describe voltage-driven biasing or voltage-driven biasing circuits.

[0074] Below, a detailed description of the accompanying drawings will be given. All illustrations in the figures are schematic. First, a block diagram of an embodiment of a semiconductor device circuit of the present invention for biasing the gate of a qubit device is given. Subsequently, further embodiments and embodiments of a method for operating a semiconductor device circuit for biasing the gate of a qubit device will be described.

[0075] Figure 1 A block diagram of a preferred embodiment of a semiconductor device circuit 100 for biasing the gate of a qubit device is shown. Figure 1 An illustrative voltage driven bias circuit is shown. The semiconductor device circuit 100 includes a multiplexed or multiplexable array of capacitor cells 102, ... 108. Thus, each capacitor cell 102, ... 108 includes a transistor controlled capacitor C1, ... C n , which are connected to the corresponding transistors T1, ...T n The common point between the transistor and the capacitor of the capacitor unit can also be the contact point for the bias gate of the qubit device.

[0076] Furthermore, all transistors T1, ..., T2 of all capacitor units 102, ..., 108 n Each source of is connected to the common control point 111, and the transistors T1, ..., T n Each gate of is individually voltage controllable. By selectively activating the charging unit 110 and having a cyclically activated gate voltage V Gi , the corresponding transistor of the capacitor unit i=1,…n, the output terminal V Oi , i=1, . . . n can be selectively activated with a predetermined amount of charge to generate a predetermined quasi-constant voltage level across the capacitors of the capacitor units. To this end, the charging unit 110 is important since it is connected to the common control point 111 .

[0077] In an embodiment, in order to operate the semiconductor device circuit in another mode, if the charging unit 110 is disabled, that is, if no control voltage is connected to the transistor T CH The gate of transistor T is then connected to the common control point 111, and the discharge unit 112 can be activated. DIS The gate of the discharge unit is activated. DIS The source is connected via the measuring resistor R m The common control point 111 is connected to the ground. Using a voltage measuring unit (e.g., a voltmeter), the voltage across the capacitor C1 and its time characteristic, i.e., its time characteristic across the corresponding capacitor C i behavior during discharge. To achieve this, the gate of the capacitor cell should also be activated by a control voltage.

[0078] To achieve these two operation modes, the charging unit and the discharging unit may be activated alternately; ie, only the charging unit or (exclusively) the discharging unit may be activated.

[0079] Figure 1 An illustrative embodiment comprising a voltage driven bias circuit is depicted, wherein V O1 ,…V On are activated sequentially, ie one at a time, ie in multiplexed mode.

[0080] Figure 2 Shows the inclusion of Figure 1 Schematic diagram 200 of the same three building blocks discussed in the context of FIG, namely a plurality of capacitor units 102, ... 108, a charging unit 110 and a (slightly modified) discharging unit 202. However, in this embodiment, a current driven bias circuit with a modified discharging unit 202 is implemented. Compared to the discharging unit 112 (compare Figure 1 ) is compared to a current measuring unit (e.g., an ammeter) connected across the transistor T DIS (discharge transistor) to realize the current drive bias circuit.

[0081] In addition, the corresponding resistor R i , i=1, ... n is connected in parallel to the capacitor C of each capacitor unit 102, ... 108 i , the corresponding current I OI , I=1, ...n flows through the capacitor units 102, ...108. In this operation mode (ie, current drive mode), the voltage controller controls in parallel (compare Figure 7 、 Figure 8 , reference numeral 704) multiple V1, ...V n (rather than sequentially controlled as in voltage drive mode) in order to activate multiple (or all) capacitor units.

[0082] Figure 3a A schematic diagram 300 is shown in which different gate voltages V G1 、V G2 and V G3 is activated for different time periods t1, t2 and t3. Thus, the Y-axis corresponds to the voltage level of the gate control signal and the X-axis represents time.

[0083] Accordingly, Figure 3b A schematic diagram 302 is shown with the corresponding output signal, in particular on the Y axis of the capacitor unit, wherein the X axis again represents time. It can be seen that for the first time period T1, the voltage level V of the corresponding output signal O1 (measured at) higher than the shorter time periods T2 and T3: V O1 >VO2 >V O3 In particular, Figure 3b It should be considered as the basis for understanding the subsequent drawings.

[0084] Figure 4 shows a specific time period (here denoted as t write ) activation voltage V G1 Schematic diagram 400. As long as the gate signal V G1 Active at the gate of the transistor of the corresponding capacitor unit, the output signal V O1 Then, at time t rest During this period, the output signal V O1 Mainly due to leakage current decreases until time t refrech The refresh signal during the period becomes valid again at the gate of the transistor of the corresponding capacitor unit. As a result, the output signal is at a lower voltage value V l (l=low) and higher voltage value V u It should be clear that the output signal has a certain tolerance V tol .

[0085] For the controlled parameters, the following applies:

[0086] t write : During this period, the target voltage V O Initialize the capacitor unit, and

[0087] Q w = C V DD ( 1 – e -(t_write / RC) ) and V O = Q W / C

[0088] t rest Used to create quasi-static V O signal. This is needed because the charging bias

[0089] VDD ≠ V O , and V u,d = V o,u e -(t_rest / RC) ) and Qrest = C V o,u e -(t_rest / RC) .

[0090] t refresh Bring the output signal back to V O Target:

[0091] Q refesh =Q rest +C V DD (1- e -(t_refresh / RC)

[0092] It should also be understood that the discharge of the capacitors of the capacitor unit occurs due to leakage. This is especially the case at the output of the capacitor unit (ie V O ) is connected to the gate of the spin qubit, since such a gate also has some leakage. Practical examples have shown that the discharge time is in the range of seconds, meaning that t rest >>t refresh Therefore, the DC levels at the potentially connected gates of a qubit are fairly static, and a high multiplexing ratio can be supported between different ones of the capacitor cells (i.e., different ones of the connected qubit gates).

[0093] In contrast, for a current driven bias circuit, the capacitor needs to be continuously charged and then discharged through the resistor, as already shown above.

[0094] Figure 5 The following table shows different writing time periods (ie, t write1 , t write2 ) is another schematic diagram 500. In this figure, t rest and t refresh The relationship between is shown as not being compressed in the x-direction as in the previous figure. However, the ratio is also represented realistically here. Assuming again that the discharge of the capacitors of the capacitor cell is due to leakage, the RC time constant is given by the gate voltage of the transistor at each capacitor (i.e., R ON ) control. In the on state, R ON Very small, so the RC drive time constant is close to the RC time constant of the external parasitic, that is, charging is fast.

[0095] In the off-state, the channel resistance is R OFF , which is about 1 MOhm to 1 GOhm, which means that the discharge is relatively slow. And 10 4 to 10 6 (or even larger) on / off ratio. This factor can be exploited towards higher multiplexing and flatter DC levels (i.e., V Oi level).

[0096] Therefore, the voltage stability factor with the multiplexing factor M is given as:

[0097] VS = (R ON / R OFF) (M-1).

[0098] exist Figure 5 In the lower part, some examples are shown, showing that a very high voltage stability, i.e. quasi-constant, can be expected.

[0099] Figure 6 A signal flow diagram 600 of an illustrative control algorithm that may be used with an exemplary embodiment for Figure 5 The upper part of the diagram shows two examples of stable outputs - i.e., 2 capacitor cells. Figure 5 The lower part of shows a visual representation of a dual-output example. The abbreviations are as follows:

[0100] t wn : Output the writing time of n;

[0101] t rn : Output the rest time of n;

[0102] t fn : Output n refresh time;

[0103] V n : controller signal;

[0104] V Gn : driving gate signal; and

[0105] V DCn : Output signal.

[0106] In another embodiment, the voltage controller can output multiple parallel control signals; in this case, the algorithm is always the same as the single output example. To this end, the following table can be exemplary:

[0107] step Duration Voltage Controller Voltage drive <![CDATA[V O1 ]]> <![CDATA[t1]]> <![CDATA[t w1 ]]> <![CDATA[V1]]> <![CDATA[V G1 ]]> <![CDATA[V DC1 ]]> <![CDATA[t2]]> <![CDATA[t r1 ]]> 0 0 <![CDATA[V DC1 ]]> <![CDATA[t3]]> <![CDATA[t f1 ]]> <![CDATA[V1]]> <![CDATA[V G1 ]]> <![CDATA[V DC1 ]]> <![CDATA[t4]]> <![CDATA[t r1 ]]> 0 0 <![CDATA[V DC1 ]]> <![CDATA[t5]]> <![CDATA[t f1 ]]> <![CDATA[V1]]> <![CDATA[V G1 ]]> <![CDATA[V DC1 ]]>

[0108] Figure 7 A more complete voltage driven biasing example is shown 700. At the bottom, signals for qubit bias 708 are shown (symbolically), e.g., connected to one or more gates of one or more qubit devices (e.g., spin qubit devices and / or superconducting qubit devices).

[0109] To control the exemplary qubit device according to the presently described embodiments, a programmable logic 702, e.g., a "program" for the quantum computing system, may be provided. Selected supply signals are passed from the programmable logic 702 to a voltage controller circuit 704. Here, the digital signals V1, ..., V n is generated and provided to the gate of the voltage drive bias circuit 706, for example, as in Figure 1The voltage drive bias circuit 706 ultimately provides a voltage output signal V O1 ,…V On can be used as a qubit device bias signal, i.e. connected to the qubit device gate. Therefore, the following signal characteristics can be used:

[0110] Select: Digital signal,

[0111] V1,…,V n : digital signal,

[0112] V DD : Supply bias,

[0113] V G1 ,…,V Gn : digital signal, and

[0114] V O1 ,…,V On :analog signal.

[0115] Figure 8 shows a very similar Figure 7 A block diagram of an illustrative voltage-driven bias circuit is shown. Identical control blocks are denoted by the same reference numerals. The visible difference is that the digital-to-analog converter (DAC) 802 converts the digital control signal into an analog supply voltage, allowing the target output signal level to be controlled by the DAC on the supply side of the voltage controller circuit. In this case, the charging voltage / current is controlled by generating the correct supply voltage level at the DAC and fully charging the capacitor, rather than controlling the capacitor circuit charging time to a constant value. This solution has the benefit of reducing operational multiplexing complexity, but this comes at the expense of increased DC power requirements and slightly reduced scalability.

[0116] Figure 9 The current drive bias circuit is also very similar to Figure 7 The main difference here is the voltage drive bias circuit (compare Figure 8 ) has been replaced by current driven bias circuit 902, as discussed in the context of some of the above figures.

[0117] at last, Figure 10A block diagram of an exemplary method 1000 for operating an illustrative semiconductor device circuit for biasing a gate of a qubit device, according to at least one embodiment, is shown. The method includes providing, at 1002, a semiconductor device circuit comprising a multiplexed array of capacitor cells having the following characteristics: each capacitor cell comprises a transistor-controlled capacitor; each capacitor is connected between the drain of a corresponding transistor and ground; each source of all transistors of all capacitor cells is connected to a common control point; each gate of the transistors of a capacitor cell is individually voltage controllable; a charging unit is connected to the common control point; and a discharging unit is connected to the common control point, wherein the charging unit and the discharging unit are alternately activatable.

[0118] The method 1000 also includes selectively and time-based activating one of the capacitor cells of the array of capacitor cells at 1004. The activation of the capacitor cells is performed in a multiplexed manner.

[0119] As an optional and exemplary additional step, method 1000 may further include periodically activating one of the capacitor cells in the array of capacitor cells at 1006. As can be seen from the "Summary" section of this document, many other optional method steps are possible.

[0120] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present invention.As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0121] The description of various embodiments of the present invention has been provided for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0122] All means or steps in the appended claims plus corresponding structures, materials, acts, and equivalents of functional elements are intended to include any structure, material, or act for performing the function in combination with other claimed elements, as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and practical application, and to enable those of ordinary skill in the art to understand various embodiments of the invention with various modifications, as are suitable for the particular use contemplated.

Claims

1. A semiconductor device circuit for biasing a gate of a qubit device, comprising: a multiplexed array of capacitor cells, wherein each of the capacitor units comprises a transistor-controlled capacitor; wherein each of the transistor-controlled capacitors is connected between a drain of a corresponding transistor and ground; wherein each source of each of said corresponding transistors of each of said capacitor units is connected to a common control point; wherein each gate of each of the transistor-controlled capacitors of each of the capacitor units is individually voltage controllable; a charging unit connected to the common control point; and discharge unit, connected to the common control point, The charging unit and the discharging unit may be activated alternately.

2. The semiconductor device circuit according to claim 1, wherein the charging unit further comprises: A transistor includes a drain connected to a common control point and further includes a source connected to a supply voltage and a gate connectable to a first control voltage for activation of the charging unit.

3. The semiconductor device circuit according to any one of the preceding claims, wherein the discharge unit further comprises: A transistor includes a drain connected to the common control point, a source connected to ground via a resistor, and a gate connectable to a second control voltage for activation of the discharge unit.

4. The semiconductor device circuit according to any one of the preceding claims, wherein the discharge unit further comprises: A transistor includes a drain connected to the common control point, a source connected to the ground via the current measuring unit, and a gate connectable to a third control voltage for activation of the discharge unit. 5 . The semiconductor device circuit according to claim 1 , wherein the voltage level at the drain of the transistor of the capacitor cell is kept quasi-constant by time-dependent activation of the gate of the transistor of the respective capacitor cell.

6. The semiconductor device circuit of any preceding claim, wherein the semiconductor device circuit is adapted to be operable in a 3K environment.

7. The semiconductor device circuit of any one of the preceding claims, wherein the signal level at the drain of the transistor of the capacitor unit represents a bias voltage level for a control gate of a qubit device. 8 . The semiconductor device circuit according to claim 1 , wherein a discharge time of the capacitor of the capacitor unit is at least 1000 times longer than a charge time.

9. The semiconductor device circuit according to any one of the preceding claims, wherein each transistor in the semiconductor device circuit is of n-type enhancement type.

10. The semiconductor device circuit according to any one of the preceding claims, further comprising a resistor connected in parallel with the transistor-controlled capacitor of the capacitor unit.

11. A method for operating a semiconductor device circuit for biasing a gate of a qubit device, the method comprising: Provide semiconductor device circuits, including: a multiplexed array of capacitor cells, wherein each of the capacitor cells comprises a transistor-controlled capacitor, wherein each of the capacitors is connected between a drain of a transistor and ground, wherein each source of the transistors of each of the capacitor cells is connected to a common control point, and wherein each gate of the transistors of the capacitor cells is individually voltage controllable; a charging unit connected to the common control point; and a discharge unit connected to the common control point, wherein the charge unit and the discharge unit are alternately activated; and One of the capacitor cells of the multiplexed array of capacitor cells is selectively and time-based activated.

12. The method according to the preceding claim, further comprising: activating the charging unit by connecting a gate of a transistor of the charging unit to a first control voltage, wherein a source of the transistor of the charging unit is connected to a supply voltage and a drain of the transistor of the charging unit is connected to the common control point; and The discharge unit is deactivated by connecting the gate of the transistor of the discharge unit to ground, wherein the source of the transistor of the discharge unit is connected to a supply voltage and the drain of the transistor of the charge unit is connected to the common control point.

13. The method according to the preceding claim, further comprising: One of the capacitor cells of the array of capacitor cells is periodically activated by applying a recharging voltage to the gate of the transistor of the respective capacitor cell, thereby achieving a quasi-constant voltage level at the drain of the transistor of the respective capacitor cell.

14. The method according to the preceding claim, further comprising: Another capacitor cell in the array of capacitor cells other than the one of the capacitor cells is periodically activated to achieve a quasi-constant voltage level at the drain of the transistor of the other capacitor cell.

15. The method according to any one of the two preceding claims, further comprising: The activation frequency of the one of the capacitor cells is controlled while the duration of the activation is made constant to maintain the quasi-constant voltage level at the drain of the transistor of the other capacitor cell.

16. The method according to any one of the five preceding claims, further comprising: activating the discharge cell by connecting a gate of a transistor of the discharge cell to a second control voltage, wherein a source of the transistor of the discharge cell is connected to a supply voltage and a drain of the transistor of the discharge cell is connected to the common control point; and The charging unit is deactivated by connecting a gate of a transistor of the charging unit to ground, wherein a source of the transistor of the charging unit is connected to ground via a discharge unit resistor and a drain of the transistor of the charging unit is connected to the common control point.

17. The method according to the preceding claim, further comprising: The voltage across the discharge unit resistor is measured.

18. The method according to any one of the two preceding claims, further comprising: Connecting an output side resistor in parallel to the capacitor of the capacitor unit; and Respective capacitor cells of the array of capacitor cells are activated periodically, thereby implying a periodic current flow through the output-side resistor.

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