Phase lock detector
By using latches and logic gates in a phase-locked loop to evaluate the state change of the clock signal, the problem of complex and inefficient phase-locked loop lock detection in the prior art is solved, and fast and reliable phase-locked detection is achieved.
Patent Information
- Application Number
- CN202380094399.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-12-22
- Filing Date
- 2023-12-19
- Publication Date
- 2025-09-19
AI Technical Summary
The lock detection method of the phase-locked loop in the prior art is complex and requires a large number of clock cycles to determine whether the signals are in phase, resulting in low detection efficiency.
By using latches to record the state changes of clock signals and evaluating the proximity of signal edges in the time domain, it is possible to quickly determine whether two clock signals are in phase, and lock detection is performed using a detection system composed of latches and logic gates.
It achieves fast and reliable phase-locked detection, reduces dependence on complex circuits, is suitable for high-speed operation, and can determine the locking state of the phase-locked loop in a relatively short time.
Smart Images
Figure CN120677640A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to systems and methods for detecting lock in a phase locked loop (PLL) control system. Background Art
[0002] Lock detection in a phase-locked loop typically relies on comparing the output of the PLL's phase detector or loop filter with a reference input signal. Because the output of the phase detector or loop filter encodes the phase error in the control loop, comparison with the reference signal can reveal whether the output signal meets a required condition, such as whether its variation within a reference clock period is below a threshold. If the output signal's variation relative to the input is sufficiently low, it can be inferred that the PLL is in lock.
[0003] The present invention seeks to provide an improved system for detecting lock in a phase locked loop. Summary of the Invention
[0004] According to a first aspect, the present invention provides a system for determining whether a first clock signal and a second clock signal are in phase; the system comprising:
[0005] a first latch arranged to receive a first clock signal;
[0006] a second latch arranged to receive a second clock signal;
[0007] a first detector; and
[0008] a second detector arranged to receive the first clock signal and the second clock signal;
[0009] wherein the first latch is arranged to latch when the first clock signal transitions from a first state to a second state;
[0010] wherein the second latch is arranged to latch when the second clock signal transitions from the first state to the second state;
[0011] wherein the first detector is configured to output a first detector output signal when the first latch and the second latch are latched; and
[0012] Therein, the second detector is arranged to generate a second detector output signal upon receiving the first detector output signal, the second detector output signal indicating whether both the first clock signal and the second clock signal are in the second state.
[0013] According to a second aspect, the present invention provides a method for determining whether a first clock signal and a second clock signal are in phase; the method comprising:
[0014] detecting a change in state of a first of the first clock signal and the second clock signal at a first time,
[0015] detecting a change in state of a second of the first clock signal and the second clock signal at a second time,
[0016] in response to detecting a change in state of a second of the first and second clock signals at a second time, comparing the states of the first and second clock signals at a second time; and
[0017] Based on the first clock signal and the second clock signal being in the same state at the second time, it is determined that the first clock signal and the second clock signal are in phase.
[0018] Thus, it can be seen that according to the present disclosure, a system and method for determining whether two clock signals are in phase are provided, wherein the proximity of edges of a first clock signal (e.g., a reference clock) and a second clock signal (e.g., a generated clock signal) in the time domain is evaluated to determine whether the two signals are in phase. This is achieved by first determining that the first clock signal and the second clock signal have entered the same state (e.g., a logic high or logic low), and secondly, determining that both the first clock signal and the second clock signal remain in the same state while the second clock signal enters the same state as the first clock signal. Essentially, this arrangement determines whether the two clock signals are sufficiently close in phase based on the overlap between them. If the two clock signals are out of phase, they will drift until one clock changes state twice while the other clock has not caught up. This results in the detection of non-overlap, which can then be used to determine the degree of lock. This is a particularly efficient design with a low component count, can run quickly, and can therefore operate reliably on very high-speed clocks.
[0019] In some embodiments, the first detector output signal can be received by the first latch and the second latch, thereby resetting the first latch and the second latch. The first latch and the second latch can have a reset input arranged to receive the first detector output signal. This allows the first latch and the second latch to be quickly reset after both latches are latched, so that they return to their initial (e.g., non-latched or reset) state, ready to play a role in the next state change of their respective clock signals. This makes it possible to quickly and continuously detect multiple state changes of the first clock signal and the second clock signal. Once a conversion is detected on both clock signals, the overlap situation will be checked, and the latches can be reset for the next inspection.
[0020] In some embodiments, the first latch and the second latch can be bistable, that is, they have two stable states. For example, they can be latched or non-latched, or they can be in a set state or a reset state. In such an embodiment, resetting the first latch and the second latch may cause the first latch and the second latch to become non-latched or enter a reset state. In the non-latched or reset state, the first latch and the second latch can be effectively reset so that they can receive further inputs from the first clock and the second clock, respectively.
[0021] In this document, the term "latch" is used in a broad sense to cover any bistable circuit with a set (latched) state and a reset (non-latched) state, that is, both edge-triggered and level-triggered latches. It is also used to cover simple (sometimes called transparent or asynchronous) latches and flip-flops (sometimes called synchronous or clocked latches).
[0022] In some embodiments, the first latch may include a first resettable D flip-flop (sometimes referred to as a delay or data flip-flop), the second latch may include a second resettable D flip-flop, and the first resettable D flip-flop and the second resettable D flip-flop each include a corresponding clock input and reset input. A first clock signal may be received at the clock input of the first latch, and a second clock signal may be received at the clock input of the second latch. In this way, the latch timing of the first resettable D flip-flop and the second resettable D flip-flop is controlled by the first clock signal and the second clock signal, respectively. It should be understood that the clock inputs of the first latch and the second latch may be arranged to trigger latching when a rising edge is received at the clock input or to trigger latching when a falling edge is received at the clock input. Each of the first latch and the second latch may be arranged to latch (i.e., enter a latched state or a set state) when an appropriate signal (e.g., a rising edge or a falling edge) is received at the clock input. Once latched, each latch will remain in the latched (or set) state until reset by an appropriate signal at its reset input. The reset inputs of the first latch and the second latch may be arranged to receive the first detector output signal. Thus, each latch is arranged to be driven into a latched (or set) state upon receipt of its corresponding clock signal, and to be driven into an unlatched (or reset) state upon receipt of a reset signal (the reset signal indicating that both latches are in the latched (or set) state).
[0023] In some embodiments, a first clock signal can be provided to a clock input of a first resettable D flip-flop, and a second clock signal can be provided to a clock input of a second resettable D flip-flop. In some embodiments, the reset input of the first resettable D flip-flop and the reset input of the second resettable D flip-flop can be configured to receive the first detector output signal. The first D flip-flop and the second D flip-flop can also have a third "data" input. The data input can be configured to receive a stable (e.g., fixed) predetermined input, such as a fixed high level signal. The data input is used to drive the latch to a latched or set state when an appropriate input is received at the clock input.
[0024] In some embodiments, the first latch can be configured to detect a change in the state of the first clock signal based on the first clock signal transitioning from the first state to the second state. Similarly, in some embodiments, the second latch can be configured to detect a change in the state of the second clock based on the second clock signal transitioning from the first state to the second state. This enables the first latch and the second latch to detect a change in the state of the first clock signal and the second clock signal, respectively. Based on the change in the state of the first clock signal and / or the second clock signal, one or more outputs of the first latch and / or the second latch may change. For example, the first latch can provide an output signal indicating the current state of the first latch (whether latched or non-latched, or in other words, set or reset). When the first latch is in a non-latched state and when the state of the first clock signal transitions from the first state to the second state, the first latch will transition from the non-latched state to the latched state, and the output of the first latch will change, indicating that a change in the state of the first clock signal has been detected. For example, the first latch output can be switched from a high level to a low level, and vice versa. Similarly, the second latch can provide an output signal indicating the current state of the second latch (whether latched or non-latched, or in other words, set or reset). When the second latch is in the non-latched state and when the state of the second clock signal transitions from the first state to the second state, the second latch will transition from the non-latched state to the latched state, and the output of the second latch will change, indicating that a change in the state of the second clock signal has been detected. For example, the second latch output can switch from a high level to a low level, and vice versa.
[0025] It should be understood that some latches may have multiple outputs. For example, each latch may also output an inverted version of the output signal for ease of use.
[0026] In some embodiments, the first clock signal and / or the second clock signal can be a square wave signal. A square wave signal can have two states, for example, high (such as digital 1) and low (such as digital 0). In some embodiments, the first state of the first clock signal and / or the second clock signal can correspond to the high state of the square wave, and the second state of the first clock signal and / or the second clock signal can correspond to the low state of the square wave. However, it should be understood that in some embodiments, the first state of the first clock signal and / or the second clock signal can correspond to the low state of the square wave, and the second state of the first clock signal and / or the second clock signal can correspond to the high state of the square wave. The transition between the low state and the high state can be used to define the rising edge of the first clock signal and / or the second clock signal, and the transition between the high state and the low state can be used to define the falling edge of the first clock signal and / or the second clock signal.
[0027] In some embodiments, the first detector may include a first logic gate. For example, the first detector may be a first AND gate. Using an AND gate as the first detector provides a way to generate a first detector output signal (at the output of the AND gate) that indicates whether the first latch and the second latch are both latched at the same time (i.e., both in a latched or set state). This signal can be provided to the second detector to enable it to determine whether the first clock signal and the second clock signal are both in the second state (e.g., whether they are in phase), and it can be provided to the reset input of the latch at the same time.
[0028] In some embodiments, the second detector may be arranged to receive the first clock signal and the second clock signal and determine whether the first clock signal and the second clock signal are in the same state. In some embodiments, the second detector may include a second logic gate and a third latch. In some such embodiments, the second logic gate may be a second AND gate configured to receive the first clock signal and the second clock signal as inputs.
[0029] In such an embodiment, the second AND gate can be configured to output overlapping signals indicating whether both the first clock signal and the second clock signal are in the second state. For example, if the inputs received at the second AND gate (the first clock signal and the second clock signal) are both high (i.e., in an embodiment where the second state is high), the second AND gate will provide a high output, indicating that the first clock signal and the second clock signal are in the same high state. However, if only one of the first clock signal and the second clock signal is high and the other is low (or if both are low), the second AND gate will provide a low output. The second AND gate can provide its output to the third latch.
[0030] It should be understood that in other embodiments, different logic gates may be used. For example, in an embodiment where the second state is a low level, a NOR gate (or gate) may be used to output a high level signal when both the first clock and the second clock are in a low state, and to output a low level signal in all other cases. For such an embodiment, if D flip-flops are used as latches, these flip-flops will need to have falling edge sensitivity, rather than the rising edge sensitivity used when the second logic gate is an AND gate. It should be understood that a combination of logic gates may be used to implement similar logic. However, it is particularly convenient that only a single logic gate is required here to detect the overlap of the first clock signal and the second clock signal in the second state. Using a single logic gate allows for fast operation, a simple detection circuit, and is suitable for high-speed operation.
[0031] In some embodiments, the third latch can be a D flip-flop including a clock input and a data input. The first detector output signal can be provided to the clock input of the third latch, and the output signal of the second logic gate (e.g., a second AND gate) can be provided to the data input of the third latch.
[0032] In some embodiments, the system may include a leading signal detector configured to determine the latching order of the first latch and the second latch (i.e., the order in which the first latch and the second latch are switched to a set state). In some such embodiments, the leading signal detector may be configured to output a "sequential" signal having a first state and a second state. The first state of the sequential signal may indicate that the first clock signal leads the second signal (i.e., the first clock signal is received before the second clock signal), and wherein the second state of the sequential signal may indicate that the second clock signal leads the first clock signal (i.e., the second clock signal is received before the first clock signal). Using the leading signal detector can advantageously allow the leading / lagging state of the first clock signal and the second clock signal to be determined, for example, providing an indication of their relative phase. This information can be used by other circuits (e.g., control circuits) to correct for phase differences and maintain lock.
[0033] According to a third aspect, a phase-locked loop (PLL) is provided, comprising a system for determining whether a first clock signal and a second clock signal are in phase, as discussed above. In some embodiments, the PLL may include a counter element configured to receive a second detector output signal. The counter element may be configured to determine whether the PLL is in a locked state based on the second detector output signal. For example, if the second detector output signal remains stable for a predetermined time (e.g., a predetermined number of clock cycles), the counter may determine that the PLL is in a locked state. Thus, a system for determining whether a first clock signal and a second clock signal are in phase may be used to help determine phase lock in a PLL. In some embodiments, if the second detector output signal received by the counter element remains constant for a predetermined number of clock cycles, the PLL may be determined to be in a locked state. For example, the counter may be configured to add a count to its total count upon receiving a clock signal if the second detector output signal is high. The counter may be periodically reset to restart counting and obtain a new measure of phase lock. Alternatively, the counter may be configured to maintain a rolling count over a predetermined number of clock cycles. The PLL may be considered to be in a locked state when the counter value exceeds a certain threshold. This allows occasional glitches to be ignored while still catching significant and persistent deviations from the locked state when the clock signals fall out of overlap. In some embodiments, the threshold can be set so that only the maximum count is considered to indicate a locked state (i.e., a single non-overlapping clock signal can be considered to indicate a loss of phase lock).
[0034] The features of any aspect or embodiment described herein may, where appropriate, be applied to any other aspect or embodiment described herein. When different embodiments or sets of embodiments are mentioned, it should be understood that these embodiments are not necessarily mutually exclusive and may overlap. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Certain preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
[0036] Figure 1 is a schematic representation of a digital phase-locked loop according to the prior art;
[0037] Figure 2 is a schematic representation of a digital phase lock detection mechanism according to an embodiment of the present invention;
[0038] Figure 3 is a schematic diagram of signals generated by main components of a digital phase lock detection mechanism according to an embodiment of the present invention; and
[0039] Figure 4 is a schematic representation of a digital phase locked loop including a phase lock detection mechanism according to the present invention. DETAILED DESCRIPTION
[0040] Figure 1 A digital phase locked loop (PLL) 100 according to the prior art is shown. The digital PLL 100 is intended to synchronize a generated clock signal GEN with an input reference clock signal REF such that both signals are aligned in phase. Figure 1 The illustrated prior art digital PLL 100 is intended to use a reference clock signal REF of a first frequency (eg, generated by a digital oscillator) to generate a clock signal GEN of a second frequency (eg, a higher multiple of the reference signal REF frequency) while ensuring that the generated signal GEN has the same phase.
[0041] Figure 1 The illustrated digital PLL 100 includes a reference clock source 101 that provides a reference clock signal REF to a first frequency divider 103. The first frequency divider 103 outputs a lower frequency signal (REF / M) to a phase frequency detector (PFD) 105, which will be described below. The PFD 105 outputs a phase error value to an infinite impulse response (IIR) filter 107, which outputs a filtered signal to a digital controlled oscillator (DCO) 109. The DCO 109 outputs a generated clock signal GEN based on the output of the PFD 105. The generated clock signal GEN is provided to a second frequency divider 113 and to an output 111 of the digital PLL 100.
[0042] The second frequency divider 113 outputs a lower frequency signal (GEN / N) to the phase frequency detector 105, where it is compared with the output signal of the first frequency divider 103 (i.e., the divided reference signal REF / M) to determine a phase error value to be provided to the IIR filter 107. The phase error value determined by the PFD 105 depends on the phase difference between GEN / N and REF / M, which should be zero when the two signals are in phase.
[0043] If the frequency of REF / M is higher than GEN / N, the PFD 105 outputs a "high" signal, which, when supplied to the digitally controlled oscillator 109, increases the frequency of the generated signal GEN output by the DCO 109. If the frequency of REF / M is lower than GEN / N, the PFD 105 outputs a "low" signal, which, when supplied to the digitally controlled oscillator 109, decreases the frequency of the generated signal GEN. By adjusting the frequency of the generated signal GEN generated by the DCO 109, the generated signal GEN can be phase-aligned with the reference signal REF over time.
[0044] To determine whether the generated signal GEN and the reference signal REF are phase-aligned, that is, whether digital PLL 100 is in a stable, locked state, GEN divider 113 also provides the GEN / N output to counter logic 114. Counter logic 114 counts clock cycles of the GEN / N signal over a defined period of time to obtain a measure of its frequency. Counter logic 114 can thereby determine whether the GEN / N signal is at the expected frequency and / or whether the GEN / N frequency is stable. A stable count with little variation indicates a good lock, while a varying count indicates a need for phase correction. If counter logic 114 determines that the GEN and REF signals are sufficiently locked, counter logic 114 outputs a LOCK signal at output 115.
[0045] so, Figure 1 The illustrated digital PLL 100 can be used to generate a clock signal GEN having a frequency set by the ratio M / N, with the generated signal GEN being related to a reference clock signal REF such that GEN / N is in phase with REF / M. The digital PLL 100 can also provide an indication of whether phase lock has been achieved in the form of a LOCK signal at output 115. The lock criteria and properties of the generated signal (e.g., its frequency relative to the frequency of the reference signal REF) can be set via a configuration input 117, which provides inputs to the first frequency divider 103 and the second frequency divider 113.
[0046] However, Figure 1 The arrangement shown requires complex circuitry, and the frequency-based approach requires a large number of clock cycles to determine that the generated and reference signals are in phase (ie, that the output frequency is in phase and stable relative to the input frequency).
[0047] According to at least preferred embodiments of the present invention, without such complex circuitry, phase lock can be advantageously determined by evaluating the proximity of the edges of the reference clock signal to the generated signal in the time domain rather than the frequency domain, thereby determining a lock condition by implementing a novel lock detection mechanism.
[0048] As will be explained below, the system of the present invention determines whether the rising edge (or falling edge) of the reference clock signal and the generated clock signal occurs within a time window by using a "latch" to record whether the two signals have transitioned to the same state (e.g., record when each clock signal becomes a logic high level). Once it is determined that the two signals have transitioned to such a state, the signals are compared to determine whether the two signals remained in the same state when the second signal entered the state, that is, whether there was an overlap in the time period when the two signals were in the same state.
[0049] Figure 2There is shown a lock detection mechanism 200 according to an embodiment of the invention. The lock detection mechanism 200 is arranged to be implemented in a digital phase locked loop to provide an output indicating whether the generated signal and the reference signal are in phase.
[0050] The lock detection mechanism 200 includes a reference clock source 201 that outputs a reference clock signal REF / M 221 and a generated clock source 203 that outputs a generated clock signal GEN / N 223. As described above with respect to the prior art phase-locked loop 100, the generated clock signal GEN / N 223 can be a high-frequency signal having a frequency that is a multiple of the reference clock signal REF / M 221. For example, the reference clock signal REF / M 221 can be a 1.05 GHz signal, while the frequency of the generated clock signal GEN / N 223 can be five times that frequency, i.e., 5.25 GHz. In the embodiment described herein, the reference clock signal REF / M 221 and the generated clock signal GEN / N 223 are square wave signals having two states: a logic high state and a logic low state. The transition between the logic low state and the logic high state occurs on the rising edge of the clock signal, and the transition between the logic high state and the logic low state occurs on the falling edge of the clock signal.
[0051] like Figure 2 The illustrated lock detection mechanism 200 is intended to determine whether the generated clock signal GEN / N 223 and the reference clock signal REF / M 221 are synchronized and to provide two output signals indicating their properties—a first output signal (PHASE) indicating whether the two signals are in phase, and a second output signal (STATUS) indicating which signal leads (or equivalently lags) the other.
[0052] In the lock detection mechanism 200, a reference signal REF / M 221 generated by a reference clock source 201 is provided to the "clock" input of a first AND gate 202 and a first latch (implemented in the form of a first resettable data flip-flop 205, referred to herein as a D flip-flop), the "data" input of which is initially set to a logic high level. The first D flip-flop 205 acts as an electronic storage component whose output remains constant until triggered by an appropriate clock input, at which point its output is set to the value of the "data" input. D flip-flops are typically edge triggered, so that the output is set when an appropriate edge is received at the clock input. The D flip-flop can be arranged to be triggered on either a rising or falling edge. The first resettable D flip-flop 205 has a constant logic "1" at its data input, so that an appropriate trigger at its clock input will cause its output to become "1". Once the output of the first D flip-flop 205 is set in this way, it remains in that state until the first D flip-flop 205 is reset. Although in Figure 2In the embodiment shown, the rising edge of the clock signal is detected, but it should be understood that the falling edge of the clock signal may also be used (with appropriate changes to other logics, such as using a NOR gate instead of the AND gate 202).
[0053] The output signal GEN / N 223 generated by the clock source 203 is also provided to the first AND gate 202 and the “Clock” input of the second D flip-flop 206 , the “Data” input of which is also initially set to a logic high level.
[0054] Based on inputs from the reference clock source 201 and the generated clock source 203, the first AND gate 202 outputs an “overlap” signal OL to the “data” input of the third D flip-flop 207, which is used to generate an output indicating the status of the lock detection mechanism 200 (i.e., whether the reference signal REF / M 221 and the generated signal GEN / N 223 at least partially overlap at a given time), as will be described below.
[0055] In the lock detection mechanism 200 , the outputs of the first D flip-flop 205 and the second D flip-flop 206 are provided to the inputs of the second AND gate 209 and the leading signal detector 211 .
[0056] The leading signal detector 211 provides an output signal PHASE, which outputs a logic high level or a logic low level, respectively, depending on whether the generated signal GEN / N 223 leads the reference signal REF / M 221, or vice versa. The PHASE signal can then be provided to the IIR filter and the digitally controlled oscillator to adjust the frequency of the generated signal GEN / N 223 so that its phase is more closely aligned with the phase of the reference signal REF / M 221, as described above with respect to Figure 1 The PLL 100 is described.
[0057] Based on the signals received from the first D flip-flop 205 and the second D flip-flop 206, the second AND gate 209 is configured to provide a reset signal RST to the reset inputs of the first D flip-flop 205 and the second D flip-flop 206 and to the "clock" input (which does not need to be resettable) of the third D flip-flop 207, which is used to generate an output indicating the state of the lock detection mechanism 200.
[0058] Therefore, the signal from the second AND gate 209 is first used to reset the first flip-flop 205 and the second D flip-flop 206 to output a logic low level so that the rising edge of the subsequent clock signal can be detected, and secondly used to trigger the sampling of the overlap signal OL from the first AND gate 202 to determine whether the signal GEN / N 223 and the signal REF / M 221 are in the same state (for example, Figure 2are all logic high levels in the embodiments).
[0059] In use, the generated signal GEN / N 223 and the reference signal REF / M 221 are provided to the first AND gate 202, and the "clock" inputs of the first D flip-flop 205 and the second D flip-flop 206. Based on the input of the first AND gate 202, the first AND gate 202 outputs a logic low or logic high signal to the "data" input of the third D flip-flop 207. When an edge of the first clock signal (e.g., a rising edge of the leading signal) is detected by its corresponding D flip-flop, the D flip-flop outputs a logic high signal to the second AND gate 209 and the leading signal detector 211.
[0060] At this stage, the second AND gate 209 does not output a logic high signal because only one of its terminals receives a logic high signal. However, when the edge of the second clock signal (e.g., the rising edge of the hysteresis signal) is detected by its corresponding D flip-flop, the D flip-flop outputs a "high" signal to the AND gate 209 and the leading signal detector 211. Subsequently, both inputs of the second AND gate 209 are logic high, and the second AND gate 209 outputs a reset signal RST. Therefore, the reset signal depends on the signal GEN / N 223 and the signal REF / M 221 so that it tracks the hysteresis edge. In other words, the reset signal is always generated when the hysteresis edge is received, regardless of which signal lags behind the other signal. This means that the reset signal is adaptive in the time domain.
[0061] The output of the reset signal RST has two effects. First, the outputs of the first D flip-flop 205 and the second D flip-flop 206 are set to zero, and second, the rising edge of the signal of the second AND gate 209 is received at the clock input of the third D flip-flop 207. When the third D flip-flop 207 detects this transition, its output is a set value based on the value of its "data" input, that is, based on the output of the first AND gate 202. This value depends on the state of the generated signal GEN / N 223 and the reference signal REF / M 221 when the reset signal RST is output. Thus, since the first D flip-flop 205 and the second D flip-flop 206 both output logic high signals to the second AND gate 209, the lock detection mechanism 200 can determine that the signal GEN / N 223 and the signal REF / M 221 are in the same state (for example, Figure 2 The third D flip-flop 207 can determine whether the two signals overlap at least partially in time (based on the output of the high overlap signal OL by the first AND gate 202). If both conditions are met, the third D flip-flop 207 provides a logic high signal to the STATUS output 217. If not, a logic low signal is provided to the status output 217.
[0062] Status output 217 may be provided to a counter element (similar to Figure 1 The digital PLL implementing the lock detection mechanism 200 is determined to be in a locked condition once the predetermined number of clock cycles during which the generated clock signal GEN / N 223 and the reference clock signal REF / M 221 are in the same state is reached. Of course, other logic may be used to determine the locked condition.
[0063] Thus, the digital lock detection mechanism 200 can be used to determine whether the first clock signal and the second clock signal are in phase without requiring computationally intensive components such as a phase-frequency detector. The digital lock detection mechanism 200 also allows for easy adjustment of the sensitivity of the lock condition by varying the duty cycle of the reference clock signal REF / M 221 and / or the generated clock signal GEN / N 223. Thus, the sensitivity can be set by the duty cycle. A lower duty cycle results in a lower chance of signal overlap, and thus a higher sensitivity of the lock condition. In contrast, if a high duty cycle is used, the chance of overlap between the reference signal REF / M 221 and the generated signal GEN / N 223 is higher, thereby reducing the sensitivity of the lock condition. The simplicity of the structure described herein is particularly advantageous for enabling convenient control of the lock sensitivity.
[0064] Figure 3 Examples of signals output by components of the lock detection mechanism 200 during operation are shown in FIG.
[0065] Figure 3 Shown Figure 2 The main components of the lock detection mechanism 200 output a time sequence of signals from a first time period 301 to a last time period 310 during a process of performing lock detection between the reference signal REF / M 221 received at the reference clock input 201 and the generated signal GEN / N 223 output by the generated clock source 203. Figure 3 The frequencies of signals GEN / N 223 and REF / M 221 in the first time period 301-307 are close (but not identical). In the first time period 301-307, the generated clock signal GEN / N 223 and the reference clock signal REF / M 221 operate at different frequencies. In the second time period 308-310, the generated clock signal GEN / N 223 and the reference clock signal REF / M 221 operate at the same frequency and are synchronized.
[0066] Initially, in a first time period 301 , it can be seen that the generated clock signal GEN / N 223 leads the reference clock signal REF / M 221 , ie, the leading (left) edge of a pulse in the generated signal precedes the corresponding edge of the reference signal.
[0067] The pulse in the generate signal GEN / N 223 causes the corresponding output of the second D flip-flop 206 (in Figure 3 ) becomes a logic high level, matching the output of the generated clock signal.
[0068] Since the reference clock signal REF / M 221 is at a logic low level during this period, its corresponding flip-flop (the first D flip-flop 205, Figure 3 The output of the first AND gate 202 (shown as "DOWN") is also at a logic low level. Since the generated clock signal GEN / N 223 and the reference clock signal REF / M 221 are in different states, the first AND gate 202 and the second AND gate 209 (having outputs OL and RST, respectively) are also at a logic low level. It can be seen that the output PHASE of the leading signal detector 211 is at a logic high level, indicating that the generated signal GEN / N 223 leads the reference signal REF / M 221. It can be seen that the output STATUS of the third D flip-flop 207 (indicating the state of the lock detection mechanism 200) is at a logic low level, indicating that the two signals are out of phase.
[0069] However, when the leading edge of the reference clock signal REF / M 221 is detected by the first D flip-flop 205 (e.g., upon the first flip-flop 205 outputting a "DOWN" pulse in time period 301), both inputs of the second AND gate 209 become logic high, causing the second AND gate 209 to output a reset signal RST. Receiving the reset signal RST from the first and second D flip-flops 205 and 206 causes their respective output signals DOWN and UP to become logic low for the remainder of the first time period 301. When the reset signal RST is received by the third D flip-flop 207, the state of the first AND gate 202 is read into the third D flip-flop 207, which then provides the output signal STATUS to the status output 217. During time period 301, when the reset signal RST is received by the third D flip-flop, both GEN / N 223 and REF / M 221 are logic high, causing the output OL of the first AND gate 202 to also be logic high, indicating an overlap between the two signals. This causes the output signal STATUS of the third D flip-flop 207 to transition to a logic high state when the reset signal RST is transmitted.
[0070] During the second time period 302, the generated clock signal GEN / N 223 continues to lead the reference signal REF / M 221, and the process described above repeats. The leading edge of the pulse in the generated clock signal GEN / N 223 causes the output of the second D flip-flop 206 to transition to a logic high state, where it remains until the leading edge of the pulse in the reference signal REF / M 221 causes the output of the first D flip-flop 205 to transition to a logic high state. At this point, the reset signal RST is sent to the first D flip-flop 205, the second D flip-flop 206, and the third D flip-flop 207. This causes the first and second flip-flops 205 and 206 to transition to a logic low state, causing the state of the first AND gate 202 to be read by the third D flip-flop 207 and output as the STATUS signal, which is provided to the status output 217. When the reset pulse RST is sent during the time period 302, both GEN / N 223 and REF / M 221 are at a logic high level, and therefore the STATUS output remains at a logic high level. When the generated clock signal GEN / N 223 continues to lead the reference clock signal REF / N 221 in the time period 302 , the PHASE output 213 also maintains a logic high level.
[0071] However, during time period 303, reference clock signal REF / M 221 "passes" generated clock signal GEN / N 223, becoming the leading signal of the two. Therefore, unlike time periods 301 and 302, the leading edge of the pulse in the reference clock signal causes the output of first D flip-flop 205 to transition to a logic high state before the output of second D flip-flop 206. Shortly thereafter, the leading edge of the pulse in generated clock signal GEN / N 223 causes the output of second D flip-flop 206 to transition to a logic high state, thereby causing second AND gate 209 to output a reset signal. This causes both first and second D flip-flops 205, 206 to transition to a logic low state, and causes the state of first AND gate 202 to be read and output at STATUS output 217. As with time periods 301 and 302, when the reset pulse is sent during time period 303, both GEN / N 223 and REF / M 221 are at a logic high level, and therefore the STATUS output remains at a logic high level during time period 303.
[0072] However, since generated signal GEN / N 223 no longer leads reference signal REF / M 221 during time period 303, PHASE output 213 transitions to a logic low state. This process repeats during time periods 304 and 305, during which reference signal REF / M 221 continues to lead generated signal GEN / N 223, and the two signals remain phase aligned.
[0073] However, in Figure 3In the example shown, it can be seen that the STATUS output changes from a logic high level to a logic low level during time period 306. This is because, when the reset signal RST is activated at the beginning of time period 306, the generated clock signal GEN / N 223 is at a logic high level, while the reference clock signal REF / M 221 is at a logic low level, i.e., they do not overlap. Therefore, when the reset signal RST is received at the third D flip-flop 207, the signal OL output by the first AND gate 202 is at a logic low level, causing the STATUS output to transition to a logic low level during time period 306 and remain at a logic low level during time period 307.
[0074] During time periods 308-310, it can be seen that generated signal GEN / N 223 and reference signal REF / N 221 operate at the same frequency and are synchronized. During this time period, first D flip-flop 205 and second D flip-flop 206 switch states almost simultaneously, and when reset signal RST is sent from second AND gate 209, the output of first AND gate 202 remains at a logic high level. Therefore, when reference clock signal REF / N 221 and generated clock signal GEN / N 223 are in phase, the STATUS output remains high.
[0075] The process outlined above can be incorporated as part of a phase-locked loop, such as Figure 4 shown. Figure 4 A phase locked loop 400 is shown, which includes Figure 1 The phase-locked loop 100 shown in FIG. 1 is equivalent to the phase-locked loop 100 shown in FIG. 1 , but the phase frequency detector 107 is replaced by the lock detection mechanism 200 of the present disclosure. Figure 4 In the phase-locked loop 400 shown, Figure 1 Identical components of the phase-locked loop 100 are given corresponding reference numerals.
[0076] Figure 4 The lock detection mechanism 200 shown provides two outputs as described above - the first output is provided to the counter logic 414 in the form of a STATUS signal, and the second output is provided to the IIR filter 407 and the DCO 409 in the form of a PHASE signal for bringing the generated clock signal GEN closer in phase to the reference clock signal REF. Figure 4 As can be seen, the implementation shown here uses REF divider 403 and GEN divider 413 to provide the same frequency inputs to lock detection mechanism 200. When lock detection mechanism 200 is implemented in phase locked loop 400, counter logic 414 uses the STATUS output to determine whether phase locked loop 400 is in a locked condition.
[0077] Counter logic 414 is used to determine whether the STATUS signal remains at a logic high level for a threshold time interval (e.g., a predetermined number of counts or clock cycles). If this condition is met, it can be determined that the reference signal REF and the generated signal GEN are in phase lock. As described above, by adjusting the duty cycle of the divided reference signal REF / M 221 and the divided generated signal GEN / N 223, the strictness of the lock condition can be dynamically adjusted to be more or less stringent. In some embodiments, this duty cycle adjustment can be performed by the clock dividers 403, 413 and can therefore be adjusted by, for example, an appropriate configuration signal 417 from a controller (not shown).
[0078] Those skilled in the art will appreciate that the present invention has been described by way of description of one or more specific embodiments thereof, but is not limited to these embodiments; many variations and modifications are possible within the scope of the appended claims.
Claims
1. A system for determining whether a first clock signal and a second clock signal are in phase, the system comprising: a first latch arranged to receive a first clock signal; a second latch arranged to receive a second clock signal; a first detector; as well as a second detector arranged to receive the first clock signal and the second clock signal; wherein the first latch is arranged to latch when the first clock signal transitions from a first state to a second state; wherein the second latch is arranged to latch when the second clock signal transitions from the first state to the second state; wherein the first detector is configured to output a first detector output signal when the first latch and the second latch are latched; and Therein, the second detector is arranged to generate a second detector output signal upon receiving the first detector output signal, the second detector output signal indicating whether both the first clock signal and the second clock signal are in the second state.
2. The system of claim 1, wherein the first detector output signal is received by the first latch and the second latch, causing the first latch and the second latch to be reset.
3. The system of claim 2, wherein the first latch and the second latch are bi-stable such that they can be latched or non-latched, and wherein resetting the first latch and the second latch causes the first latch and the second latch to become non-latched.
4. The system of any one of the preceding claims, wherein the first latch comprises a first resettable D flip-flop, wherein the second latch comprises a second resettable D flip-flop, and wherein the first resettable D flip-flop and the second resettable D flip-flop each comprise a respective clock input and a reset input. 5 . The system of claim 4 , wherein the first clock signal is provided to a clock input of the first resettable D flip-flop, and wherein the second clock signal is provided to a clock input of the second resettable D flip-flop. 6 . The system of claim 4 , wherein the reset input of the first resettable D flip-flop and the reset input of the second resettable D flip-flop are configured to receive the first detector output signal.
7. A system according to any of the preceding claims, wherein the first latch is configured to detect a change in state of the first clock signal based on the first clock signal transitioning from a first state to a second state, and wherein the second latch is configured to detect a change in state of the second clock signal based on the second clock signal transitioning from a first state to a second state.
8. A system according to any preceding claim, wherein the first clock signal and the second clock signal are square waves.
9. The system according to any of the preceding claims, wherein the first detector is a first logic gate, wherein optionally the logic gate is a first AND gate.
10. A system according to any preceding claim, wherein the second detector is arranged to receive the first clock signal and the second clock signal and to determine whether the first clock signal and the second clock signal are in the same state.
11. A system according to any preceding claim, wherein the second detector comprises a second logic gate and a third latch.
12. The system of claim 11 , wherein the second logic gate is a second AND gate configured to receive the first clock signal and the second clock signal as inputs and output an overlap signal to the third latch indicating whether the first clock signal and the second clock signal are in the same state.
13. The system of claim 12, wherein the third latch is a D flip-flop comprising a clock input and a data input.
14. The system of claim 13, wherein the first detector output signal is provided to a clock input of the third latch, and wherein the output signal of the second AND gate is provided to a data input of the third latch.
15. The system according to any preceding claim, further comprising a leading signal detector configured to determine a latching order of the first latch and the second latch.
16. The system of claim 15 , wherein the leading signal detector is configured to output a sequential signal having a first state and a second state; wherein the first state of the sequential signal indicates that the first clock signal leads the second signal, and wherein the second sequential state indicates that the second clock signal leads the first clock signal.
17. A phase locked loop comprising a system according to any preceding claim.
18. The phase locked loop of claim 17, comprising a counter element configured to receive the second detector output signal.
19. The phase-locked loop of claim 18, wherein the counter element is configured to determine whether the phase-locked loop is in a locked state based on the second detector output signal.
20. The phase-locked loop according to claim 19, wherein: If the second detector output signal received by the counter element remains constant for a predetermined number of clock cycles, it is determined that the phase locked loop is in a locked state.
21. A method for determining whether a first clock signal and a second clock signal are in phase, the method comprising: detecting a change in state of a first of the first clock signal and the second clock signal at a first time, detecting a change in state of a second of the first clock signal and the second clock signal at a second time, in response to detecting a change in the state of a second of the first clock signal and the second clock signal at a second time, comparing the states of the first clock signal and the second clock signal at a second time; as well as Based on the first clock signal and the second clock signal being in the same state at the second time, it is determined that the first clock signal and the second clock signal are in phase.