Power semiconductor devices and methods for manufacturing power semiconductor devices

Abstract

A power semiconductor device (1) is specified, comprising: a first electrode (2), a first semiconductor layer (3) of a first conductivity type, a drift layer (4) of a first conductivity type, a second semiconductor layer (5) of a second conductivity type different from the first conductivity type, and a second electrode (6), wherein at least one of the first semiconductor layer (3) and the second semiconductor layer (5) comprises an oxide layer (24) extending in an active region (9) of the power semiconductor device (1) surrounded by a termination region (8) of the power semiconductor device (1), and at least one of the first semiconductor layer (3) and the second semiconductor layer (5) has a beveled structure (19). Furthermore, a method for manufacturing the power semiconductor device (1) is specified.

Description

Technical Field

[0001] This disclosure relates to a power semiconductor device and a method for manufacturing the power semiconductor device. Summary of the Invention

[0002] Embodiments of this disclosure relate to a power semiconductor device with improved performance. Further embodiments of this disclosure relate to a method for manufacturing such a power semiconductor device.

[0003] This is achieved through the subject matter of the independent claims. Further embodiments will be apparent in the dependent claims described below.

[0004] A power semiconductor device is described. Herein and hereinafter, the term "power" refers, for example, to a power semiconductor module, power semiconductor device, and / or power semiconductor chip suitable for handling voltages and currents exceeding 100 V and / or exceeding 10 A (exemplary, voltages reaching 10 kV and currents reaching 10 kA).

[0005] According to an embodiment, the power semiconductor device includes a first electrode. The first electrode extends laterally, for example. For instance, the first electrode is configured to make conductive contact with an external environment. Exemplarily, the first electrode comprises or is made of metal.

[0006] The first electrode may comprise a first layer and a second layer stacked one on top of the other in a vertical direction perpendicular to the lateral direction. For example, the metal included in the first layer may differ from the metal included in the second layer. The first layer exemplarily includes molybdenum, while the second layer exemplarily includes aluminum and / or other metals (e.g., copper, titanium, and / or nickel). Specifically, the first layer is configured to make conductive contact with the outside, while the second layer is a metallization layer. For example, the metallization layer may be applied in a method using a sputtering or evaporation process.

[0007] According to an embodiment, the power semiconductor device includes a first semiconductor layer of a first conductivity type. The first semiconductor layer extends laterally, for example. For example, the first semiconductor layer includes or is composed of a semiconductor material. For example, the semiconductor material is based on silicon. The first semiconductor layer includes, for example, a first dopant of a first conductivity type.

[0008] According to an embodiment, the power semiconductor device includes a drift layer of a first conductivity type. The drift layer extends, exemplarily, in a lateral direction. For example, the drift layer comprises or is composed of a semiconductor material. Exemplarily, the semiconductor material comprises or is composed of the same material as the first semiconductor layer. The drift layer includes, for example, another first dopant of the first conductivity type. The other first dopant of the drift layer is, for example, the same dopant as the dopant in the first semiconductor layer.

[0009] For example, the maximum doping concentration of the drift layer is lower than the maximum doping concentration of the first semiconductor layer. The maximum doping concentration of the drift layer is, for example, at least an order of magnitude lower than the maximum doping concentration of the first semiconductor layer.

[0010] According to an embodiment, the power semiconductor device includes a second semiconductor layer of a second conductivity type different from the first conductivity type. The second semiconductor layer extends, exemplarily, in the lateral direction. For example, the second semiconductor layer comprises or is composed of a semiconductor material. Exemplarily, the semiconductor material comprises or is composed of the same material as the first semiconductor layer. The first semiconductor layer includes, for example, a second dopant of a second conductivity type.

[0011] For example, the first conductivity type is n-type, while the second conductivity type is p-type, and vice versa. For instance, the first dopant is an n-type dopant, while the second dopant is a p-type dopant, and vice versa.

[0012] According to an embodiment, the power semiconductor device includes a second electrode. The second electrode extends, exemplarily, in a lateral direction. For example, the second electrode is configured to make conductive contact with an external environment. For example, the second electrode comprises or is made of metal.

[0013] The second electrode may include a third and a fourth layer stacked vertically on top of each other. For example, the metal included in the third layer may be different from the metal included in the fourth layer. The third layer exemplarily includes aluminum and / or other metals (e.g., copper, titanium, nickel, tungsten, platinum, and / or gold), while the fourth layer exemplarily includes molybdenum. In particular, the third layer is a metallization layer, and the additional layers are configured to make conductive contact with the outside.

[0014] For example, the first electrode is the cathode electrode of a power semiconductor device, while the second electrode is the anode electrode of a power semiconductor device, and vice versa.

[0015] For example, the first and fourth layers are not present in a power semiconductor device. For example, the first and fourth layers are provided for processing a power semiconductor device, wherein the first electrode includes only the second layer, and the second electrode includes only the third layer.

[0016] According to an embodiment of a power semiconductor device, an oxide layer is disposed on at least one of a first semiconductor layer and a second semiconductor layer, the oxide layer extending within an active region of the power semiconductor device surrounded by a termination region. The termination region is a peripheral region of the power semiconductor device, and the active region is a central region of the power semiconductor device. The peripheral region completely surrounds the active region in the lateral direction.

[0017] The active region is located at the centroid of the power semiconductor device and extends laterally toward at least one edge of the power semiconductor device. The terminating region extends laterally along the edge region defining the active region of the power semiconductor device.

[0018] For example, the oxide layer may be disposed only on the first semiconductor layer or only on the second semiconductor layer. Alternatively, the oxide layer may be disposed on both the first and second semiconductor layers.

[0019] The oxide layer extends within the active region, particularly from the terminating region towards the centroid. Exemplarily, the oxide layer in a plan view is circular, elliptical, or polygonal (e.g., quadrilateral). Specifically, the shape of the oxide layer in a plan view corresponds to the outline of a power semiconductor device (especially a drift layer) in a plan view.

[0020] If an oxide layer is disposed on the first semiconductor layer, the oxide layer faces the first electrode. The oxide layer comprises a semiconductor material of the first semiconductor layer that has been specifically oxidized.

[0021] Exemplarily, the oxide layer is fabricated by locally applying a plasma-enhanced chemical vapor deposition (PECVD) process to the bottom surface of the first semiconductor layer. Specifically, the oxide layer material is applied to, and particularly completely to, the bottom surface of the first semiconductor layer. Subsequently, photoresist is exemplarily applied to, and particularly completely to, the bottom surface of the oxide layer material. For example, the photoresist is specifically constructed using a mask to fabricate the oxide layer.

[0022] For example, the oxide layer protrudes beyond the first semiconductor layer in the vertical direction toward the first electrode.

[0023] If an oxide layer is disposed on the second semiconductor layer, the oxide layer faces the second electrode. The oxide layer comprises a semiconductor material of the second semiconductor layer that has been specifically oxidized.

[0024] Exemplarily, the oxide layer is fabricated by locally applying it to the top surface of the first semiconductor layer using a plasma-enhanced chemical vapor deposition (PECVD) process. Specifically, the material of the oxide layer is applied, particularly completely, to the top surface of the second semiconductor layer. Subsequently, photoresist is exemplarily applied, particularly completely, to the top surface of the oxide layer material. For example, the photoresist is specifically constructed using a mask to fabricate the oxide layer.

[0025] For example, the oxide layer protrudes beyond the second semiconductor layer in the vertical direction toward the second electrode.

[0026] The oxide layer has a height of up to 1 µm in the vertical direction.

[0027] For example, the power semiconductor described herein is a fast recovery diode, particularly a free-floating discrete fast recovery diode. Furthermore, the power semiconductor described herein can be a reverse-conducting integrated gate-commutated thyristor (RC-IGCT). The RC-IGCT comprises a diode portion and a GCT portion, wherein a separation region is arranged between the diode portion and the GCT portion. The diode includes all the elements of the active region described herein, and the separation region is formed by all the elements of the termination region.

[0028] In summary, such power semiconductor devices having a combination of a first semiconductor layer and / or a second semiconductor layer with an oxide layer offer the following advantages in particular.

[0029] Advantageously, the oxide layer reduces the emitter injection efficiency in the termination region. Due to the presence of the oxide region, the termination region of the power semiconductor device is effectively and electrically disconnected from operation in the ON state by significantly reducing the emitter injection efficiency in the termination region. Advantageously, less heat is generated in the termination region with lower cooling capacity. Therefore, thermal stability is improved during frequency operation or in surge current events, enabling the power semiconductor device to operate at higher temperatures.

[0030] The presence of an oxide layer in the active region (and especially the active region adjacent to the termination region) can advantageously reduce and precisely predetermine the emitter injection efficiency.

[0031] According to another embodiment of a power semiconductor device, a first electrode, a first semiconductor layer, a drift layer, a second semiconductor layer, and a second electrode are stacked vertically on top of each other along a stacking direction. Directly adjacent elements are in direct contact with each other, for example. Exemplarily, the first layer of the first electrode faces away from the first semiconductor layer, while the second layer of the first electrode faces the first semiconductor layer. Exemplarily, the third layer of the second electrode faces the second semiconductor layer, while the fourth layer of the second electrode faces away from the second semiconductor layer.

[0032] According to another embodiment of the power semiconductor device, the first semiconductor layer includes a first sub-layer facing a first electrode and a second sub-layer facing a drift layer. For example, the maximum doping concentration of the first sub-layer is higher than the maximum doping concentration of the second sub-layer. The maximum doping concentration of the first sub-layer is, for example, at least one order of magnitude higher than the maximum doping concentration of the second sub-layer.

[0033] According to another embodiment of the power semiconductor device, the second semiconductor layer includes a third sublayer facing the drift layer and a fourth sublayer facing the second electrode. For example, the maximum doping concentration of the fourth sublayer is higher than the maximum doping concentration of the third sublayer. The maximum doping concentration of the fourth sublayer is, for example, at least an order of magnitude higher than the maximum doping concentration of the third sublayer.

[0034] According to another embodiment of the power semiconductor device, one of the first electrode and the second electrode extends over the active region and the termination region. Specifically, only one of the first electrode and the second electrode extends over the active region and the termination region.

[0035] For example, the first electrode extends laterally and completely covers the first semiconductor layer. Specifically, the second layer of the first electrode completely (particularly in the active and terminating regions) covers the bottom surface of the first sublayer of the first semiconductor layer. Exemplarily, the first layer of the first electrode covers the second layer of the first electrode only in the active region. That is to say, the first layer of the first electrode extends laterally only in the active region.

[0036] Alternatively, the second electrode extends laterally and completely covers the second semiconductor layer. Specifically, the third layer of the second electrode completely (particularly in the active and termination regions) covers the top surface of the fourth sublayer of the second semiconductor layer. Exemplarily, the fourth layer of the second electrode covers the third layer of the second electrode only in the active region. That is, the fourth layer of the second electrode extends laterally only in the active region.

[0037] According to another embodiment of the power semiconductor device, the other of the first electrode and the second electrode extends only over the active region.

[0038] If the first electrode extends in the lateral direction and completely covers the first semiconductor layer, i.e., covers both the active and terminating regions, then the second electrode extends only over the active region. Specifically, the third and fourth layers of the second electrode have the same extent in the lateral direction.

[0039] If the second electrode extends laterally and completely covers the second semiconductor layer, i.e., covers both the active and terminating regions, then the first electrode extends only over the active region. Specifically, the first and second layers of the first electrode have the same extent in the lateral direction.

[0040] According to another embodiment of the power semiconductor device, a fourth sublayer extends laterally over the active region and the termination region. For example, the fourth sublayer overlaps with the active region and at least partially overlaps with the termination region in a plan view. If the second semiconductor layer has a beveled structure, the fourth sublayer overlaps with the termination region by at least 20% or at least 50% in a plan view.

[0041] According to another embodiment of the power semiconductor device, the fourth sublayer extends only over the active region. Specifically, the fourth sublayer overlaps only with the active region in a plan view, and not with the terminating region.

[0042] This advantageously further reduces the emitter efficiency in the termination region.

[0043] According to an embodiment of a power semiconductor device, at least one of the first semiconductor layer and the second semiconductor layer has a sloped structure. Exemplarily, each of the first and second semiconductor layers has a bottom surface and a top surface, both extending in a lateral direction, wherein the top and bottom surfaces are connected to at least one side surface. The side surface of at least one of the first and second semiconductor layers is inclined relative to the vertical direction in a termination region.

[0044] For example, the inclined structure is arranged in the termination region. In particular, the inclined structure is arranged only in the termination region. That is to say, the inclined structure defines the extent of the termination region in the lateral direction.

[0045] According to another embodiment of the power semiconductor device, the second semiconductor layer gradually narrows towards the second electrode in the termination region. A beveled structure is arranged in the second semiconductor layer such that the side surface of the second semiconductor layer forms an angle of less than 90° with the top surface of the drift layer.

[0046] Depending on the angle, that is, depending on the steepness of the slope structure, the junction depth can be predetermined. In other words, depending on the angle, the emitter efficiency in the termination region can be preset in a precise manner.

[0047] According to another embodiment of the power semiconductor device, the first semiconductor layer gradually narrows towards the first electrode in the termination region. A beveled structure is arranged in the first semiconductor layer such that the side surface of the first semiconductor layer forms an angle of less than 90° with the bottom surface of the drift layer.

[0048] Advantageously, depending on the angle, the emitter efficiency in the termination region can be preset with particular precision.

[0049] According to another embodiment of a power semiconductor device, an oxide layer is located on a first sublayer, within the active region and the termination region. Exemplarily, the bottom surface of the first sublayer and the bottom surface of the oxide layer are not in a common plane.

[0050] For example, the oxide layer extends to partially cover the active region but completely cover the termination region. If the beveled structure is arranged in the second semiconductor layer, the oxide layer completely covers the first electrode in the termination region.

[0051] Alternatively, if the beveled structure is arranged in the first semiconductor layer, the oxide layer completely covers the second electrode in the termination region.

[0052] According to another embodiment of a power semiconductor device, an oxide layer is located between a first sublayer and a first electrode. Exemplarily, the bottom surface of the first sublayer and the bottom surface of the oxide layer are in direct contact with the first electrode, particularly the second layer.

[0053] According to another embodiment of the power semiconductor device, the oxide layer extends laterally from the termination region into the active region up to a specified distance. Specifically, the oxide layer extends laterally from the interface between the termination region and the active region to a specified distance within the active region.

[0054] According to another embodiment of the power semiconductor device, the extension distance is at least 1 and at most 7 times the height of the drift layer in the vertical direction. In particular, the extension distance is at least 3 and at most 5 times the height of the drift layer.

[0055] This extended distance advantageously reduces the emitter efficiency at the interface between the termination regions in the active region.

[0056] According to another embodiment of the power semiconductor device, another oxide layer is located on a fourth sublayer within the active region. Exemplarily, the top surface of the fourth sublayer and the top surface of the other oxide layer are not in a common plane.

[0057] If the beveled structure is arranged in the second semiconductor layer, then another oxide layer only partially covers the second electrode in the active region. The termination region, for example, has no additional oxide layer.

[0058] Alternatively, if the beveled structure is arranged in the first semiconductor layer, another oxide layer only partially covers the first electrode in the active region. The termination region, for example, has no additional oxide layer.

[0059] According to another embodiment of the power semiconductor device, another oxide layer is located between the fourth sublayer and the second electrode. Exemplarily, the top surface of the fourth sublayer and the top surface of the oxide layer are in direct contact with the second electrode, particularly the third layer.

[0060] According to another embodiment of the power semiconductor device, another oxide layer extends laterally from the termination region into the active region for another extension distance. Specifically, the other oxide layer extends laterally from the interface between the termination region and the active region into the active region for another extension distance in the lateral direction.

[0061] According to another embodiment of the power semiconductor device, the additional extension distance is at least 1 and at most 7 times the height of the drift layer in the vertical direction. In particular, the additional extension distance is at least 3 and at most 5 times the height of the drift layer.

[0062] The other extension distance may be equal to the stated extension distance. Alternatively, the other extension distance may be different from the stated extension distance.

[0063] According to another embodiment, the power semiconductor device includes a passivation layer. For example, the passivation layer encapsulates layers of the power semiconductor device. Specifically, portions of the first electrode and portions of the second electrode do not have passivation layers. Exemplarily, the first layer of the first electrode and the fourth layer of the second electrode do not have passivation layers.

[0064] Passivation layers comprise electrically insulating materials, such as dielectric materials. For example, passivation layer materials may include semi-insulating materials on the silicon surface. Besides insulating the semiconductor surface from its surroundings, this material serves to discharge leakage current to one of the electrodes, especially at elevated temperatures.

[0065] According to another embodiment of the power semiconductor device, the first electrode, the first semiconductor layer, the drift layer, the second semiconductor layer, and the second electrode are surrounded by a passivation layer in the termination region. For example, the side surfaces of these layers and the electrodes are completely covered by the passivation layer.

[0066] For example, the beveled structure is completely embedded in the passivation layer. That is to say, the side surface forming the beveled structure is completely covered by the passivation layer.

[0067] Advantageously, the presence of the passivation layer protects power semiconductor devices from environmental influences.

[0068] According to another embodiment of the power semiconductor device, the first semiconductor layer is constructed from a plurality of doped regions of a second conductivity type in the termination region.

[0069] These doped regions extend within the termination region. Exemplarily, each doped region is circular, elliptical, or polygonal (e.g., quadrilateral) in a plan view. In particular, the shape of the doped region in a plan view corresponds to the shape of a power semiconductor device (especially a drift layer) in a plan view.

[0070] For example, a doped region is disposed in a semiconductor layer, and an oxide layer is not disposed on that semiconductor layer. If the first semiconductor layer includes a doped region, then an oxide layer is disposed on the second semiconductor layer. If the second semiconductor layer includes a doped region, then an oxide layer is disposed on the first semiconductor layer.

[0071] For example, the first sublayer includes a doped region, and / or the fourth sublayer includes a doped region.

[0072] According to another embodiment of the power semiconductor device, the first sublayer is divided into segments by doped regions in the lateral direction. Exemplarily, the segments are separated by doped regions in the lateral direction. That is to say, directly adjacent segments are specifically not in physical contact with each other.

[0073] By utilizing doped regions, especially combinations of oxide layers and doped regions, emitter efficiency can be precisely predetermined and reduced.

[0074] Furthermore, this document describes a method for manufacturing power semiconductor devices, which can be used to manufacture or produce power semiconductor devices as described above herein. Therefore, features related to power semiconductor devices are also disclosed in conjunction with this method, and vice versa.

[0075] According to an embodiment of the method, a semiconductor material having a drift layer is provided. Exemplarily, the semiconductor material is based on silicon. The semiconductor material is particularly provided as a wafer.

[0076] For example, the drift layer of the first conductivity type is manufactured during silicon ingot pulling. In other words, it exists in the starting silicon wafer before manufacturing.

[0077] According to an embodiment of the method, a first semiconductor layer of a first conductivity type is fabricated on a first side of the drift layer. Exemplarily, a first dopant is incorporated into the wafer (e.g., the first side of the drift layer) by at least one of an ion implantation or deposition process, followed by a diffusion process.

[0078] According to an embodiment of the method, a second semiconductor layer of a second conductivity type, different from the first conductivity type, is fabricated on the second side of the drift layer opposite to the first side. Exemplarily, a second dopant is incorporated into the wafer (e.g., the second side of the drift layer) via at least one of an ion implantation or deposition process, followed by a diffusion process.

[0079] According to an embodiment of the method, a bevel structure is fabricated in at least one of a first semiconductor layer and a second semiconductor layer in the termination region of the active region surrounding a power semiconductor device.

[0080] According to an embodiment of the method, an oxide layer is fabricated on at least one of a first semiconductor layer or a second semiconductor layer.

[0081] According to another embodiment of the method, the inclined structure is manufactured by a grinding process. Attached Figure Description

[0082] The accompanying drawings are included to provide further understanding. In the drawings, elements with the same structure and / or function may be designated by the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative and not necessarily drawn to scale.

[0083] Figures 1 to 3 These are cross-sectional views of a power semiconductor device according to an exemplary embodiment.

[0084] Figure 4This is a planar schematic diagram of a power semiconductor device according to an exemplary embodiment, and

[0085] Figure 5 This is an exemplary diagram of the hole density of a power semiconductor device under different exemplary embodiments. Detailed Implementation

[0086] according to Figure 1 An exemplary embodiment of the power semiconductor device 1 includes a first electrode 2 and a second electrode 6. The first electrode includes a first layer 14 and a second layer 15, and the second electrode includes a third layer 16 and a fourth layer 17. The power semiconductor device 1 further includes a first semiconductor layer 3 of a first conductivity type and a second semiconductor layer 5 of a second conductivity type. The first semiconductor layer includes a first sublayer 10 and a second sublayer 11, and the second semiconductor layer includes a third sublayer 12 and a fourth sublayer 13. Further, the power semiconductor device 1 includes a drift layer 4.

[0087] The first electrode 2 (particularly the first layer 14 and the second layer 15), the first semiconductor layer 3 (particularly the first sublayer 10 and the second sublayer 11), the drift layer 4, the second semiconductor layer 5 (particularly the third sublayer 12 and the fourth sublayer 13), and the second electrode 6 (particularly the third layer 16 and the fourth layer 17) are stacked one on top of the other in a stacking direction corresponding to the vertical direction. Each of these layers extends in a transverse direction perpendicular to the vertical direction. Furthermore, each of these layers is in direct contact with the other. The bottom surfaces of these layers face the first electrode 2, and the top surfaces of these layers face the second electrode 6.

[0088] The second layer 15 of the first electrode 2 completely covers the bottom surface of the first sublayer 10 of the first semiconductor layer 3. The first layer 14 of the first electrode 2 completely covers the bottom surface of the second layer 15 only in the active region 9 of the power semiconductor device 1. That is to say, the first layer 14 completely overlaps with the active region 9 in the lateral direction in a plan view, and in particular, overlaps completely and uniformly.

[0089] Specifically, the plan view is a view of the top surface of each element of the power semiconductor device 1 in the vertical direction.

[0090] The active region 9 is located at the centroid of the power semiconductor device 1 and extends around the centroid in the lateral direction. Figure 1 Only half of power semiconductor device 1 is shown. For example, Figure 1 The left edge of the symbol includes the centroid.

[0091] Termination region 8 extends in the lateral direction along the edge region defining the active region 9 of the power semiconductor device 1. Termination region 8 does not have the first layer 14 of the first electrode 2. That is to say, the first layer 14 does not overlap with termination region 8 in the lateral direction in a plan view.

[0092] The third layer 16 of the second electrode 6 completely covers the top surface of the fourth sub-layer 13 of the second semiconductor layer 5 only in the active region 9. The fourth layer 17 of the second electrode 6 completely covers the top surface of the third layer 16. That is to say, the third layer 16 and the fourth layer 17 completely overlap with the active region 9 in the plan view and in the lateral direction, and in particular, overlap completely and uniformly.

[0093] Termination region 8 does not have the third layer 16 and the fourth layer 17 of the second electrode 6. That is to say, the third layer 16 and the fourth layer 17 do not overlap with termination region 8 in the plan view or in the lateral direction.

[0094] The second semiconductor layer 5 has a sloped structure 19 in the termination region 8. The side surface of the second semiconductor layer 5 (which connects the top and bottom surfaces of the second semiconductor layer 5) is inclined relative to the vertical direction. The side surface of the second semiconductor layer 5 is inclined only in the termination region 8. The angle between the side surface of the second semiconductor layer 5 and the bottom surface of the second semiconductor layer 5 is less than 90°, and in particular less than 45°. That is to say, the third sublayer 12 and the fourth sublayer 13 gradually narrow towards the second electrode 6 in the termination region 8.

[0095] An oxide layer 24 extending in the active region 9 and the termination region 8 is disposed on the first sublayer 10 of the first semiconductor layer 3. The oxide layer 24 faces the first electrode 2. The oxide layer 24 comprises the semiconductor material of the first semiconductor layer 3.

[0096] The bottom surface of oxide layer 24 protrudes vertically beyond the bottom surface of first sublayer 10, reaching first electrode 2. First electrode 2 completely covers the bottom surface of first sublayer 10 and bottom surface of oxide layer 24.

[0097] The oxide layer 24 extends to partially cover the active region 9 but completely cover the termination region 8. That is, the oxide layer 24 completely overlaps the termination region 8 in a plan view. The oxide layer 24 extends laterally from the interface between the active region 9 and the termination region 8 into the active region 9 up to an extension distance 23. The extension distance 23 is at least one and at most seven times the height of the drift layer 4 in the vertical direction.

[0098] The power semiconductor device 1 further includes a passivation layer 18. The passivation layer 18 encapsulates the power semiconductor device 1, wherein, in particular, a portion of the first electrode 2 and a portion of the second electrode 6 do not have the passivation layer 18.

[0099] and Figure 1 Compared to the exemplary embodiments, according to Figure 2The fourth sublayer 13 of the second semiconductor layer 5 in an exemplary embodiment includes an oxide layer 24. The oxide layer 24 extends only in the active region 9. That is to say, the oxide layer 24 completely overlaps with the active region 9 in a plan view within an extension distance 23, and further, the oxide layer 24 does not overlap with the terminating region 8 in a plan view.

[0100] The oxide layer 24 faces the second electrode 6. The oxide layer 24 includes the semiconductor material of the second semiconductor layer 5.

[0101] The top surface of oxide layer 24 protrudes vertically beyond the top surface of fourth sublayer 13, reaching the second electrode 6. The second electrode 6 completely covers the top surface of fourth sublayer 13 and the top surface of oxide layer 24.

[0102] like Figure 1 In the middle, the oxide layer 24 extends in the lateral direction from the interface between the active region 9 and the termination region 8 into the active region 9 up to an extension distance of 23.

[0103] according to Figure 4 An exemplary embodiment of the power semiconductor device 1 has an oxide layer 24 and another oxide layer 25. The oxide layer 24 on the first sublayer 10 corresponds to Figure 1 The oxide layer 24 in the middle, while another oxide layer 25 on the fourth sublayer 13 corresponds to Figure 2 Oxide layer 24 in the middle.

[0104] according to Figure 4 The power semiconductor device 1 of the exemplary embodiment is based on Figures 1 to 3 A plan view of one of the power semiconductor devices 1. In the plan view, the top surfaces of the fourth layer 17 and the passivation layer 18 are freely accessible. The power semiconductor device 1 has a circular shape.

[0105] The doped regions are not visible in this view, so they are indicated by dashed lines. The doped regions extend within the terminating region 8, wherein each of the doped regions completely surrounds the active region 9 in the lateral direction. In particular, each of the doped regions has a circular shape in the plan view, which corresponds to the shape of the power semiconductor device 1 in the plan view.

[0106] According to Figure 5 In the graph, the y-axis represents the hole density ρ, with units of cm. -3 The x-axis represents the distance x of the power semiconductor device 1 in the drift layer 4 from the center to the edge region in the lateral direction, in µm.

[0107] Curve C1 corresponds to a typical power semiconductor device 1 that does not include a first semiconductor layer 3 having an oxide layer 24. Curve C2 corresponds to... Figure 1For power semiconductor device 1, curve C3 corresponds to... Figure 2 The power semiconductor device 1, and curve C4 corresponds to the ... Figure 3 1. Power semiconductor devices.

[0108] Figure Labels

[0109] 1 Power Semiconductor Devices

[0110] 2 First electrode

[0111] 3 First semiconductor layer

[0112] 4 drift layers

[0113] 5 Second semiconductor layer

[0114] 6 Second electrode

[0115] 7-doped region

[0116] 8 Termination Zone

[0117] 9 active areas

[0118] 10 First Sub-layer

[0119] 11 Second Sub-layer

[0120] 12 Third Sub-layer

[0121] 13 Fourth Sub-layer

[0122] 14 First Floor

[0123] 15 Second Layer

[0124] 16 Third Floor

[0125] 17 Fourth Floor

[0126] 18 passivation layers

[0127] 19 Sloping Structure

[0128] 20 sections

[0129] 21 Another doped region

[0130] 23 Extended Distance

[0131] 24 oxide layer

[0132] 25 Another oxide layer

Claims

1. A power semiconductor device (1), comprising: - First electrode (2). - First semiconductor layer of first conductivity type (3). - The first type of conductive drift layer (4). - A second semiconductor layer (5) of a second conductivity type different from the first conductivity type, and - Second electrode (6), wherein, - The first semiconductor layer (3) includes a first sub-layer (10) facing the first electrode (2) and a second sub-layer (11) facing the drift layer (4). - The second semiconductor layer (5) includes a third sublayer (12) facing the drift layer (4) and a fourth sublayer (13) facing the second electrode (6). - The maximum doping concentration of the first sublayer (10) is higher than the maximum doping concentration of the second sublayer (11). - The maximum doping concentration of the fourth sublayer (13) is higher than the maximum doping concentration of the third sublayer (12). - An oxide layer (24) extends in the active region (9) of the power semiconductor device (1) surrounded by the termination region (8) of the power semiconductor device (1), the oxide layer being located between the first sublayer (10) and the first electrode (2) in the active region (9) and the termination region (8). - Another oxide layer (25) is located in the active region (9) between the fourth sublayer (13) and the second electrode (6). - The other oxide layer (25) extends in the lateral direction from the termination region (8) into the active region (9) to another extension distance (23). - The second semiconductor layer (5) has a beveled structure (19) in the termination region (8), such that the second semiconductor layer (5) gradually narrows towards the second electrode (6) in the termination region (8). - The first electrode (2) extends in a lateral direction covering the active region (9) and the termination region (8) to completely cover the first semiconductor layer (3), while the second electrode (6) extends only on the active region (9). - The other oxide layer (25) extends only in the active region (9), and - The first electrode (2), the first semiconductor layer (3), the drift layer (4), the second semiconductor layer (5) and the second electrode (6) are stacked vertically on top of each other along the stacking direction.

2. The power semiconductor device (1) according to claim 1, wherein, - The fourth sublayer (13) extends in the lateral region over the active region (9) and the termination region (8), or - The fourth sublayer (13) extends only on the active region (9).

3. The power semiconductor device (1) according to any one of claims 1 to 2, wherein, - The oxide layer (24) extends laterally from the termination region (8) into the active region (9) up to an extension distance (23), and - The extension distance (23) is at least 1 and at most 7 times the height of the drift layer (4) in the vertical direction.

4. The power semiconductor device (1) according to any one of claims 1 to 2, wherein, - The other extension distance (23) is at least 1 and at most 7 times the height of the drift layer (4) in the vertical direction.

5. The power semiconductor device (1) according to any one of claims 1 to 2, wherein, - The first semiconductor layer (3) is constructed from a plurality of doped regions (7) of the second conductivity type in the termination region (8).

6. The power semiconductor device (1) according to claim 5, wherein, - The first sublayer (10) is divided into multiple segments (20) in the lateral direction by the doped region (7).

7. The power semiconductor device (1) according to any one of claims 1 to 2, further comprising: - Passivation layer (18), wherein, - The first electrode (2), the first semiconductor layer (3), the drift layer (4), the second semiconductor layer (5) and the second electrode (6) are surrounded by the passivation layer (18).

8. A method for manufacturing a power semiconductor device, the power semiconductor device comprising a first electrode (2) and a second electrode (6), the method comprising: - Provide a semiconductor material having a drift layer (4) of a first conductivity type, - A first semiconductor layer (3) of the first conductivity type is fabricated on the first side of the drift layer (4). - A second semiconductor layer (5) of a second conductivity type different from the first conductivity type is fabricated on the second side opposite to the first side of the drift layer (4). - A beveled structure (19) is fabricated in the second semiconductor layer (5) in the termination region (8) surrounding the active region (9) of the power semiconductor device (1), such that the second semiconductor layer (5) gradually narrows towards the second electrode (6) in the termination region (8), and - An oxide layer (24) is fabricated on the first semiconductor layer (3), wherein, - The first semiconductor layer (3) includes a first sub-layer (10) facing the first electrode (2) and a second sub-layer (11) facing the drift layer (4). - The second semiconductor layer (5) includes a third sublayer (12) facing the drift layer (4) and a fourth sublayer (13) facing the second electrode (6). - The maximum doping concentration of the first sublayer (10) is higher than the maximum doping concentration of the second sublayer (11). - The maximum doping concentration of the fourth sublayer (13) is higher than the maximum doping concentration of the third sublayer (12). - The oxide layer (24) is located between the first sublayer (10) and the first electrode (2) in the active region (9) and the termination region (8). - Another oxide layer (25) is located in the active region (9) between the fourth sublayer (13) and the second electrode (6). - The other oxide layer (25) extends in the lateral direction from the termination region (8) into the active region (9) to another extension distance (23). - The first electrode (2) extends in a lateral direction covering the active region (9) and the termination region (8) to completely cover the first semiconductor layer (3), while the second electrode (6) extends only on the active region (9). - The other oxide layer (25) extends only in the active region (9), and - The first electrode (2), the first semiconductor layer (3), the drift layer (4), the second semiconductor layer (5) and the second electrode (6) are stacked vertically on top of each other along the stacking direction.

9. The method according to claim 8, wherein, At least one - The inclined structure (19) is manufactured by a grinding process.

Images