Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic apparatus

Abstract

The present disclosure pertains to a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an electronic apparatus, whereby the degree of freedom in wiring design can be further improved. The solid-state imaging device includes: a first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which a signal charge generated in the photoelectric conversion portion is stored; and a second semiconductor layer on which a plurality of transistors including pixel transistors for reading out signal charges of the charge storage portion are formed, the second semiconductor layer being laminated on the first semiconductor layer. At least one specific transistor of the plurality of transistors is configured such that at least one wiring connected to the well region, the source electrode, or the drain electrode is connected from a layer opposite to the gate electrode side of the second semiconductor layer, and a bottom surface of the well region, the source electrode, or the drain electrode connected to the wiring is in contact with the insulating film. This disclosure can be applied, for example, to a solid-state imaging device or the like.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device, and particularly to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device configured to further increase the degree of freedom in wiring design. Background Art

[0002] The applicant of the present disclosure proposed a solid-state imaging device in Patent Document 1, which comprises a stack of: a first substrate on which a photodiode is formed for each pixel; a second substrate having a circuit for reading out pixel signals based on the charge generated by the photodiodes; and a third substrate having a logic circuit for processing the pixel signals. In the solid-state imaging device proposed in Patent Document 1, a transfer transistor and a floating diffusion for transferring charge from the photodiodes are formed on the first substrate, while an amplifier transistor, a reset transistor, a select transistor, and the like are formed on the second substrate. [Citation List] [Patent Document]

[0003] [Patent Document 1]: International Publication No. WO 2020 / 262643 Summary of the Invention [Technical Issues]

[0004] In such a solid-state imaging device, it is desired to further improve the degree of freedom in wiring design.

[0005] The present disclosure has been made in view of such circumstances, and provides a solid-state imaging device capable of further improving the degree of freedom in wiring design. [Technical means to solve technical problems]

[0006] A solid-state imaging device according to a first aspect of the present disclosure includes: a first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which signal charges generated in the photoelectric conversion portion are stored; and a second semiconductor layer on which a plurality of transistors including a pixel transistor for reading out the signal charge of the charge storage portion are formed, the second semiconductor layer being stacked on the first semiconductor layer; In which, at least one specific transistor among the multiple transistors is constructed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is constructed to be in contact with the insulating film.

[0007] A method for manufacturing a solid-state imaging device according to a second aspect of the present disclosure includes: a first semiconductor layer and a second semiconductor layer stacked, the first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which signal charges generated in the photoelectric conversion portion are stored, and a plurality of transistors including a pixel transistor for reading out the signal charges of the charge storage portion being formed on the second semiconductor layer; and At least one specific transistor among the multiple transistors is formed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is in contact with the insulating film.

[0008] An electronic device according to a third aspect of the present disclosure includes a solid-state imaging device, the solid-state imaging device including: a first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which signal charges generated in the photoelectric conversion portion are stored; and a second semiconductor layer on which a plurality of transistors including a pixel transistor for reading out the signal charge of the charge storage portion are formed, the second semiconductor layer being stacked on the first semiconductor layer; In which, at least one specific transistor among the multiple transistors is constructed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is constructed to be in contact with the insulating film.

[0009] In the first to third aspects of the present disclosure, a first semiconductor layer and a second semiconductor layer are stacked, the first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which signal charge generated in the photoelectric conversion portion is stored, and a plurality of transistors including a pixel transistor for reading out the signal charge from the charge storage portion are formed on the second semiconductor layer. At least one specific transistor among the plurality of transistors is configured such that at least one wiring connected to a well region, a source electrode, or a drain electrode is connected from a layer opposite to a gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode, or the drain electrode connected to the wiring is formed in contact with an insulating film.

[0010] The solid-state imaging device and the electronic device may be independent devices, or may be modules integrated into other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1is a block diagram illustrating an example of a functional configuration of a solid-state imaging device according to an embodiment of the present disclosure. Figure 2 is a plan view showing a schematic configuration example of a solid-state imaging device. Figure 3 is an equivalent circuit diagram showing a configuration example of a pixel sharing unit. Figure 4 1 is a cross-sectional view showing a configuration example of a pixel sharing unit portion of a first substrate and a second substrate. Figure 5 is shown with Figure 4 A cross-sectional view showing an example of the configuration of the first substrate and the second substrate in portions where those portions are different. Figure 6 Is used to illustrate Figure 5 The effect of the transistor is shown in the diagram. Figure 7 Is used to illustrate Figure 5 A diagram illustrating a method for manufacturing a transistor. Figure 8 Is used to illustrate Figure 5 A diagram illustrating a method for manufacturing a transistor. Figure 9 It shows Figure 5 A cross-sectional view of a first variation of the transistor shown. Figure 10 It shows Figure 5 A cross-sectional view of a second variation of the transistor shown. Figure 11 It is a cross-sectional view showing a configuration example of stacking three substrates in a pixel sharing unit portion. Figure 12 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the technology according to the present disclosure is applied. Figure 13 A diagram for explaining an example of use of an image sensor. Figure 14 is a block diagram showing an example of a schematic configuration of a vehicle control system. Figure 15 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging portion. DETAILED DESCRIPTION

[0012] Hereinafter, a mode for implementing the technology disclosed herein (hereinafter referred to as an "embodiment") will be described with reference to the accompanying drawings. The description will be given in the following order. 1. Functional Block Diagram of a Solid-State Imaging Device 2. Schematic Structure of a Solid-State Imaging Device 3. Equivalent circuit diagram of pixel sharing unit 4. Example of pixel sharing unit configuration 5. DTMOS Configuration Example 6. DTMOS Manufacturing Method 7. Modifications 8. Example of a Three-Layer Stacked Structure of a Solid-State Imaging Device 9. Application examples of electronic devices 10. Application Examples of Mobile Objects

[0013] In the drawings referred to in the following description, identical or similar parts will be denoted by identical or similar reference numerals, and duplicate description will be omitted accordingly. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, and the like may differ from actual dimensions. The drawings may also include parts having different dimensional relationships and ratios than those in other drawings.

[0014] In addition, it should be understood that the definitions of directions such as up and down in the following description are provided for simplicity only and are not intended to limit the technical spirit of the present disclosure. For example, when an object is rotated 90 degrees, the up and down sides of the object are observed to become the left and right sides of the object, and when the object is rotated 180 degrees, the up and down sides of the object are reversed.

[0015] <1. Functional Block Diagram of Solid-State Imaging Device> Figure 1 is a block diagram illustrating an example of a functional configuration of a solid-state imaging device according to an embodiment of the present disclosure.

[0016] For example, Figure 1 The solid-state imaging device 1 shown includes an input section 21A, a row drive section 22 , a timing control section 23 , a pixel array section 24 , a column signal processing section 25 , an image signal processing section 26 , and an output section 21B.

[0017] In the pixel array section 24, pixels 31 are repeatedly arranged in an array. More specifically, pixel sharing units 32 each including a plurality of pixels 31 are repeatedly arranged in an array in the row direction and the column direction as a repeating unit. Figure 1In the example shown, one pixel sharing unit 32 is composed of four pixels 31, and when these four pixels 31 are distinguished, they are respectively referred to as pixels 31A, 31B, 31C and 31D. The pixel sharing unit 32 composed of pixels 31A, 31B, 31C and 31D is arranged in a manner of, for example, 2 rows and 2 columns. In this specification, for convenience, the row direction may be referred to as the H direction, and the column direction orthogonal to the row direction may be referred to as the V direction. The pixel array section 24 is provided with a plurality of pixels 31, a plurality of row drive signal lines 33 and a plurality of vertical signal lines (column readout lines) 34. The row drive signal lines 33 drive the individual pixels 31 arranged side by side in the row direction in the pixel array section 24. As will be referred to below Figure 3 As described in detail, the pixel sharing unit 32 is provided with a plurality of transistors. To drive these transistors, one pixel sharing unit 32 is connected to a plurality of row drive signal lines 33. The pixel sharing unit 32 is connected to vertical signal lines 34. Image signals are read from the respective pixels 31A, 31B, 31C, and 31D included in the pixel sharing unit 32 via the vertical signal lines 34.

[0018] For example, the row drive section 22 includes a row address control section that determines the position of a row for driving pixels, that is, a row decoder section, and a row drive circuit section that generates signals for driving the pixels 31 .

[0019] The timing control section 23 supplies signals to the row driver section 22 and the column signal processing section 25 to control timing based on the reference clock signal and timing control signal input to the device. Hereinafter, in this disclosure, all or part of the row driver section 22, the column signal processing section 25, and the timing control section 23 may be referred to simply as a pixel peripheral circuit section, a peripheral circuit section, or a control circuit section.

[0020] For example, the column signal processing section 25 includes a load circuit section that is connected to the vertical signal line 34 and forms a source follower circuit together with the pixel 31. The column signal processing section 25 may also include an amplifier circuit section that amplifies the signal read out from the pixel 31 through the vertical signal line 34. In addition, the column signal processing section 25 may also include a noise processing section that removes a system noise level from the signal read out from the pixel 31 as a result of photoelectric conversion.

[0021] The column signal processing unit 25 includes an analog-to-digital converter (ADC) for converting signals read from the pixels 31 or analog signals that have undergone noise processing into digital signals. The ADC includes a comparator for comparing the analog signal to be converted with a reference scanning signal to be compared, and a counter for measuring the time required to invert the comparison result obtained by the comparator. The column signal processing unit 25 may also include a horizontal scanning circuit for controlling the scanning of the columns to be read.

[0022] The image signal processing section 26 is a circuit that performs various types of signal processing on data obtained as a result of photoelectric conversion, that is, data obtained as a result of the imaging operation of the solid-state imaging device 1. For example, the image signal processing section 26 includes an image signal processing circuit section and a data holding section. The image signal processing section 26 may also include a processor section.

[0023] An example of signal processing performed in the image signal processing section 26 is tone curve correction processing, in which the AD-converted captured data is given a wider tonal range when the captured data has a dark subject, and the AD-converted captured data is given a narrower tonal range when the captured data has a bright subject. In this case, it is desirable to pre-store characteristic data regarding the tone curve in the data holding section of the image signal processing section 26 in order to determine which tone curve should be used to correct the tone of the captured data.

[0024] The input section 21A is a circuit that inputs, for example, a reference clock signal, timing control signals such as a vertical synchronization signal and a horizontal synchronization signal, and characteristic data to be stored in the data holding section of the image signal processing section 26 from outside the device to the solid-state imaging device 1. For example, the input section 21A includes an input terminal 41, an input circuit section 42, an input amplitude changing section 43, an input data conversion circuit section 44, and a power supply section (not shown).

[0025] The input terminal 41 is an external terminal for inputting data into the solid-state imaging device 1. The input circuit section 42 introduces the signal input to the input terminal 41 into the solid-state imaging device 1. The input amplitude changing section 43 changes the amplitude of the signal introduced via the input circuit section 42 to an amplitude that can be easily used within the solid-state imaging device 1. The input data conversion circuit section 44 changes the order of the data sequence of the input data. For example, the input data conversion circuit section 44 is a serial-to-parallel conversion circuit that receives a serial signal as input data and converts it into a parallel signal. The input amplitude changing section 43 and the input data conversion circuit section 44 may be omitted. Based on the power supply externally supplied to the solid-state imaging device 1, the power supply section supplies power at various voltage levels required within the solid-state imaging device 1.

[0026] When the solid-state imaging apparatus 1 is connected to an external storage device such as a flash memory, an SRAM, and a DRAM, the input section 21A may further include a memory interface circuit for receiving data from these external storage devices.

[0027] The output section 21B is a circuit that outputs image data captured by the solid-state imaging device 1 or image data that has undergone signal processing by the image signal processing section 26 from the solid-state imaging device 1 to the outside of the device. For example, the output section 21B includes an output data conversion circuit section 45, an output amplitude changing section 46, an output circuit section 47, and an output terminal 48.

[0028] The output data conversion circuit section 45 changes the order of the data sequence of the output data. For example, the output data conversion circuit section 45 is a parallel-to-serial conversion circuit that converts parallel signals used within the solid-state imaging device 1 into serial signals. The output amplitude changing section 46 changes the amplitude of the signal used within the solid-state imaging device 1 to an amplitude that can be easily used by external equipment connected to the solid-state imaging device 1. The output circuit section 47 is a circuit that drives external wiring connected to the output terminal 48 outside the solid-state imaging device 1. The output terminal 48 is an external terminal for outputting data from the solid-state imaging device 1 to the outside of the device. The output data conversion circuit section 45 and the output amplitude changing section 46 may be omitted.

[0029] When the solid-state imaging apparatus 1 is connected to an external storage device such as a flash memory, an SRAM, and a DRAM, the output section 21B may further include a memory interface circuit for outputting data to these external storage devices.

[0030] <2. Schematic Configuration of Solid-State Imaging Device> Figure 2 2 is a plan view showing a schematic configuration example of the solid-state imaging device 1 .

[0031] The solid-state imaging device 1 has a three-dimensional structure in which a first substrate 100, a second substrate 200, and a third substrate 300 are bonded together. The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order with the second substrate 200 arranged therebetween. Figure 2 The planar structures of the first substrate 100 , the second substrate 200 and the third substrate 300 are schematically shown.

[0032] The pixel array section 24 and the pixel sharing unit 32 included in the pixel array section 24 are constructed using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 31A, 31B, 31C, and 31D of the pixel sharing unit 32. Each of these pixels 31 has a photodiode PD ( Figure 3 ) and the transfer transistor TR ( Figure 3 The second substrate 200 is provided with a pixel circuit 210 of the pixel sharing unit 32 ( Figure 3 ). The pixel circuit 210 reads pixel signals transmitted from the photodiodes PD of the respective pixels 31A, 31B, 31C, and 31D through the transfer transistors TR, or resets the photodiodes PD. In addition to the pixel circuits, the second substrate 200 also includes a plurality of row drive signal lines 33 extending in the row direction and a plurality of vertical signal lines 34 extending in the column direction. The second substrate 200 also includes power supply lines 35 extending in the row direction.

[0033] For example, the third substrate 300 includes an input section 21A, a row drive section 22, a timing control section 23, a column signal processing section 25, an image signal processing section 26, and an output section 21B. The row drive section 22 is provided in a region that partially overlaps with the pixel array section 24 in the stacking direction (hereinafter referred to as the "stacking direction") of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row drive section 22 is provided in a region that overlaps with the edge of the pixel array section 24 in the H direction in the stacking direction. For example, the column signal processing section 25 is provided in a region that partially overlaps with the pixel array section 24 in the stacking direction. More specifically, the column signal processing section 25 is provided in a region that overlaps with the edge of the pixel array section 24 in the V direction in the stacking direction. Although not shown, the input section 21A, the row drive section 22, the timing control section 23, the column signal processing section 25, the image signal processing section 26, and the output section 21B may be arranged at a position other than the third substrate 300, or, for example, may be arranged on the second substrate 200. The input section 21A and the output section 21B may be provided on the back side (light incident side) of the first substrate 100. The pixel circuit 210 provided on the second substrate 200 may also be referred to as a pixel transistor circuit, a pixel transistor group, a pixel readout circuit, or a readout circuit in some cases. In this specification, the term "pixel circuit" is used.

[0034] For example, the first substrate 100 and the second substrate 200 are electrically connected to each other via through-electrodes (not shown). For example, the second substrate 200 and the third substrate 300 are electrically connected to each other via contact portions 201, 202, 301, and 302. Contact portions 201 and 202 are provided on the second substrate 200, and contact portions 301 and 302 are provided on the third substrate 300. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R provided with a plurality of contact portions 201 and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 has a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array section 24 and the row driver section 22 in the stacking direction. In other words, for example, the contact regions 201R and 301R are provided in a region where the row driver section 22 (third substrate 300) and the pixel array section 24 (second substrate 200) overlap in the stacking direction, or in a region near such a region. For example, the contact regions 201R and 301R are provided at the edge of such a region in the H direction. For example, on the third substrate 300, the contact region 301R is provided at a position overlapping with a portion of the row driver section 22, or specifically, at the edge of the row driver section 22 in the H direction. For example, the contact sections 201 and 301 connect the row driver section 22 provided on the third substrate 300 to the row driver signal line 33 provided on the second substrate 200. For example, the contact sections 201 and 301 can connect the input section 21A provided on the third substrate 300 to the power supply line 35 and the reference potential line (reference potential line VSS described below). The contact regions 202R and 302R are provided between the pixel array section 24 and the column signal processing section 25 in the stacking direction. In other words, for example, the contact regions 202R and 302R are provided in a region where the column signal processing section 25 (third substrate 300) and the pixel array section 24 (second substrate 200) overlap in the stacking direction, or in a region near such a region. For example, the contact regions 202R and 302R are arranged at the edge of such a region in the V direction. For example, on the third substrate 300, the contact region 302R is provided at a position overlapping with a portion of the column signal processing section 25, or specifically, at the edge of the column signal processing section 25 in the V direction. For example, the contact portions 202 and 302 connect the pixel signal (a signal corresponding to the amount of charge generated as a result of photoelectric conversion in a photodiode) output from each of the plurality of pixel shared cells 32 included in the pixel array section 24 to the column signal processing section 25 provided on the third substrate 300.The pixel signal is configured to be transferred from the second substrate 200 to the third substrate 300 .

[0035] For example, the first substrate 100 and the second substrate 200 are provided with connection hole portions H1 and H2. The connection hole portions H1 and H2 pass through the first substrate 100 and the second substrate 200 and are open. The connection hole portions H1 and H2 are provided outside the pixel array portion 24 (or a portion overlapping with the pixel array portion 24). For example, the connection hole portion H1 is arranged outside the pixel array portion 24 in the H direction, and the connection hole portion H2 is arranged outside the pixel array portion 24 in the V direction. For example, the connection hole portion H1 reaches the input portion 21A provided in the third substrate 300, and the connection hole portion H2 reaches the output portion 21B provided in the third substrate 300. The connection hole portions H1 and H2 may be hollow, or may at least partially contain a conductive material. For example, there may be a structure including electrodes formed as the input portion 21A and / or the output portion 21B and bonding wires connected to these electrodes. Alternatively, a configuration is provided in which the electrodes formed as the input portion 21A and / or the output portion 21B are connected to the conductive material provided in the connection holes H1 and H2. The conductive material provided in the connection holes H1 and H2 may be embedded in a part or all of the connection holes H1 and H2, or the conductive material may be formed on the side walls of the connection holes H1 and H2.

[0036] <3. Equivalent Circuit Diagram of Pixel Sharing Unit> Figure 3 : is an equivalent circuit diagram showing a configuration example of the pixel sharing unit 32 .

[0037] The pixel sharing unit 32 includes four pixels 31, namely, pixels 31A, 31B, 31C, and 31D, and one pixel circuit 210 connected to these four pixels 31. The pixels 31A, 31B, 31C, and 31D are formed on the first substrate 100, and the pixel circuit 210 is formed on the second substrate 200. For example, the pixel circuit 210 includes four pixel transistors, or specifically, an amplifier transistor AMP, a select transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. The pixel sharing unit 32 operates the one pixel circuit 210 in a time-division manner, thereby sequentially outputting pixel signals of the corresponding four pixels 31A, 31B, 31C, and 31D included in the pixel sharing unit 32 to the vertical signal line 34. A mode in which one pixel circuit 210 is connected to a plurality of pixels 31 and the pixel signals of the plurality of pixels 31 are output by the one pixel circuit 210 in a time-division manner is referred to as "a plurality of pixels 31 sharing one pixel circuit 210."

[0038] Pixels 31A, 31B, 31C, and 31D have common constituent elements. Hereinafter, in order to distinguish the constituent elements of pixels 31A, 31B, 31C, and 31D from one another, "a" is given as a suffix to the reference numerals of the constituent elements of pixel 31A, "b" is given as a suffix to the reference numerals of the constituent elements of pixel 31B, "c" is given as a suffix to the reference numerals of the constituent elements of pixel 31C, and "d" is given as a suffix to the reference numerals of the constituent elements of pixel 31D. If it is not necessary to distinguish the constituent elements of pixels 31A, 31B, 31C, and 31D from one another, the identification symbols "a," "b," "c," and "d" that are suffixes to the reference numerals of the constituent elements of pixels 31A, 31B, 31C, and 31D will be omitted.

[0039] For example, the pixel 31 has a photodiode PD as a photoelectric conversion unit, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion unit FD electrically connected to the transfer transistor TR. In the photodiode PD (PDa, PDb, PDc, PDd), the cathode is electrically connected to the source of the transfer transistor TR (TRa, TRb, TRc, TRd), and the anode is electrically connected to a reference potential line (for example, ground). The photodiode PD performs photoelectric conversion on the incident light and generates a signal charge corresponding to the amount of light received. For example, the transfer transistor TR is an N-type CMOS (complementary metal oxide semiconductor) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion unit FD (FDa, FDb, FDc, FDd), and the gate is electrically connected to a drive signal line. The drive signal line is a plurality of row drive signal lines 33 ( Figure 1 ). The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion FD. For example, the floating diffusion FD is formed using an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD serves as a charge retention unit that temporarily holds the signal charge transferred from the photodiode PD and also as a charge-to-voltage conversion unit that generates a voltage corresponding to the amount of charge.

[0040] The four floating diffusions FDa, FDb, FDc, and FDd included in a single pixel sharing unit 32 are electrically connected to one another and to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of the multiple row drive signal lines 33 connected to a single pixel sharing unit 32. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is part of the multiple row drive signal lines 33 connected to a single pixel sharing unit 32. The gate of the amplifier transistor AMP is connected to the floating diffusions FDa, FDb, FDc, and FDd, the drain of the amplifier transistor AMP is connected to the power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to the vertical signal line 34, and the gate of the select transistor SEL is connected to the drive signal line. The driving signal line is a part of a plurality of row driving signal lines 33 connected to one pixel sharing unit 32 .

[0041] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifier transistor AMP generates a signal having a voltage corresponding to the level of the charge held in the floating diffusion FD as a pixel signal. The amplifier transistor AMP is connected to the vertical signal line 34 via the selection transistor SEL. The amplifier transistor AMP is connected to the load circuit portion ( Figure 1 ) together form a source follower. When the selection transistor SEL is turned on, the amplifier transistor AMP outputs the voltage of the floating diffusion portion FD to the column signal processing unit 25 via the vertical signal line 34. For example, the reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are N-type MOS transistors.

[0042] The FD conversion gain switching transistor FDG is used to change the gain of the charge-to-voltage conversion of the floating diffusion FD. Typically, images captured in the dark have a smaller pixel signal. For charge-to-voltage conversion based on Q = CV, if the capacitance of the floating diffusion FD (FD capacitance C) is large, V, the voltage converted from the charge by the amplifier transistor AMP, is smaller. On the other hand, in bright conditions, the pixel signal is larger, so unless the FD capacitance C is large, the floating diffusion FD cannot receive all the charge from the photodiode PD. Furthermore, the FD capacitance C needs to be large to prevent V, the voltage converted from the charge by the amplifier transistor AMP, from being too large (i.e., too small). Based on this fact, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, thereby increasing the overall FD capacitance C. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be made variable, thereby adjusting the conversion efficiency. For example, the FD conversion gain switching transistor FDG is an N-type MOS transistor.

[0043] It is also possible to provide a configuration in which the FD conversion gain switching transistor FDG is not provided. In this case, for example, the pixel circuit 210 is configured by three transistors: the amplifier transistor AMP, the selection transistor SEL, and the reset transistor RST.

[0044] The selection transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 33 ( Figure 1 ). The source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 34, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST.

[0045] Although not shown, the number of pixels 31 that share one pixel circuit 210 may not be four. For example, two or eight pixels 31 may share one pixel circuit 210. Alternatively, a pixel circuit 210 may be provided for each pixel rather than being shared by a plurality of pixels 31.

[0046] <4. Example of Pixel Sharing Unit Configuration> Figure 4 1 is a cross-sectional view schematically showing a configuration example of the pixel sharing unit 32 of the first substrate 100 and the second substrate 200. More specifically, Figure 4It is a cross-sectional view corresponding to two pixels in the V direction or the H direction among the pixels 31A, 31B, 31C, and 31D included in the pixel sharing unit 32 .

[0047] exist Figure 4 , a first substrate 100 and a second substrate 200 are stacked in this order. The first substrate 100 includes a semiconductor layer 100S as a first semiconductor layer and a wiring layer 100T as a first wiring layer. The second substrate 200 includes a semiconductor layer 200S as a second semiconductor layer and a wiring layer 200T as a second wiring layer. A light receiving lens 401 is formed on the back side (light incident side) of the first substrate 100. A color filter layer (not shown) can be provided between the light receiving lens 401 and the first substrate 100. A light receiving lens 401 is provided for each pixel 31.

[0048] In this specification, for the sake of convenience, in the following cross-sectional views, the light incident side of the solid-state imaging device 1 may be referred to as "lower," "lower side," "below," or "lower layer," and the side opposite to the light incident side may be referred to as "upper," "upper side," "above," and "upper layer." Furthermore, in this specification, for the sake of convenience, with respect to a substrate including a semiconductor layer and a wiring layer, the wiring layer side may be referred to as a front surface, and the semiconductor layer side may be referred to as a back surface.

[0049] The first substrate 100 includes, in order from the light-receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. For example, the semiconductor layer 100S is formed of a silicon substrate. For example, the semiconductor layer 100S includes a p-well layer 115 in a portion of the front surface on the wiring layer 100T side and in its vicinity, and an n-type semiconductor region 114 in a region deeper than the p-well layer 115. For example, the p-well layer 115 is a p-type semiconductor region, and the n-type semiconductor region 114 and the p-well layer 115 constitute a pn-junction photodiode PD. The light-receiving lens 401 is formed so as to oppose the semiconductor layer 100S, with, for example, the fixed charge film 112 and the insulating film 111 positioned between the light-receiving lens 401 and the semiconductor layer 100S. For example, the light-receiving lens 401 is positioned facing the photodiode PD of the pixel 31. The solid-state imaging device 1 is a back-illuminated solid-state imaging device, in which light enters from the back side of the first substrate 100 having the photodiode PD, for example.

[0050] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in this order from the first substrate 100 side. For example, the semiconductor layer 200S is formed of a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided in the thickness direction. For example, the well region 211 is a p-type semiconductor region. The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S and an element separation region 213 provided in a portion of the semiconductor layer 200S in the thickness direction. For example, the insulating region 212 is made of silicon oxide. The wiring layer 200T includes an interlayer insulating film 222 and a plurality of metal wirings W stacked therebetween. Figure 4 , only the first metal wiring W1 is shown among the plurality of metal wirings W stacked on the interlayer insulating film 222. The interlayer insulating film 222 is made of silicon oxide, for example.

[0051] The second substrate 200 is provided with an amplifier transistor AMP and a selection transistor SEL as part of the pixel circuit 210 configured for each pixel sharing unit 32. For example, the amplifier transistor AMP and the selection transistor SEL are provided on the front surface side (wiring layer 200T side) of the semiconductor layer 200S. In the solid-state imaging device 1, the second substrate 200 is bonded to the first substrate 100 in such a manner that the back side (semiconductor layer 200S side) of the second substrate 200 faces the front surface side (wiring layer 100T side) of the first substrate 100. In other words, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0052] A floating diffusion FD and a VSS contact region 118 are provided near the front surface of the semiconductor layer 100S. The floating diffusion FD is formed of an n-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (FDa, FDb, FDc, FDd) of the respective pixels 31A, 31B, 31C, and 31D are provided close to one another in the center of the pixel sharing unit 32. The four floating diffusions FD (FDa, FDb, FDc, FDd) included in the pixel sharing unit 32 are electrically connected to one another via a pad portion 120 in the first substrate 100 (more specifically, in the wiring layer 100T). Furthermore, the floating diffusion FD is connected from the wiring layer 100T of the first substrate 100 to the wiring layer 200T of the second substrate 200 via a through electrode 120E. Within the wiring layer 200T of the second substrate 200, the floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG (not shown) via the through electrode 120E. The VSS contact region 118 is electrically connected to the reference potential line VSS and is spaced apart from the floating diffusion FD. For example, the floating diffusion FD is located at one edge of each pixel 31 in the V direction, and the VSS contact region 118 is located at the other edge. For example, the VSS contact region 118 is formed from a p-type semiconductor region. The VSS contact region 118 is connected to, for example, ground potential or a fixed potential. This allows a reference potential to be supplied to the semiconductor layer 100S.

[0053] The first substrate 100 is provided with a photodiode PD, a floating diffusion portion FD, a VSS contact region 118, and a transfer transistor TR. The photodiode PD, the floating diffusion portion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 31A, 31B, 31C, and 31D. The transfer transistor TR is provided on the front surface side of the semiconductor layer 100S (the side opposite to the light incident surface side, the second substrate 200 side). The transfer transistor TR has a transfer gate TG. Figure 4 In the example shown, the transfer transistor TR is composed of a planar transistor in which a transfer gate TG is formed on the front surface of the semiconductor layer 100S, but it can also be composed of a vertical transistor in which a portion of the transfer gate TG is buried in the semiconductor layer 100S. The side surfaces of the transfer gate TG are covered by sidewalls SW. For example, the sidewalls SW include silicon nitride (SiN). A gate insulating film (not shown) is provided between the semiconductor layer 100S and the transfer gate TG. For example, a transfer gate TG is provided for each of the pixels 31A, 31B, 31C, and 31D so as to surround the floating diffusion portion FD in a plan view.

[0054] In the semiconductor layer 100S, a pixel separation portion 117 is provided to separate the pixels 31A, 31B, 31C, and 31D from each other. The pixel separation portion 117 is formed to extend in the normal direction of the semiconductor layer 100S (the direction perpendicular to the front surface of the semiconductor layer 100S). The pixel separation portion 117 is provided to separate the pixels 31A, 31B, 31C, and 31D from each other, and has, for example, a grid-like planar shape. For example, the pixel separation portion 117 electrically and optically separates the pixels 31A, 31B, 31C, and 31D from each other. For example, the pixel separation portion 117 includes a light shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light shielding film 117A. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. For example, the insulating film 117B is made of silicon oxide (SiO). For example, the pixel separation unit 117 has an FTI (full trench isolation) structure that penetrates the semiconductor layer 100S. The pixel separation unit 117 is not limited to the FTI structure. For example, a DTI (deep trench isolation) structure that does not penetrate the semiconductor layer 100S can be used. The pixel separation unit 117 is formed in a portion of the semiconductor layer 100S so as to extend in the normal direction of the semiconductor layer 100S.

[0055] For example, the semiconductor layer 100S is provided with a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S and is arranged between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on the side of the pixel separator 117, specifically between the pixel separator 117 and the n-type semiconductor region 114. For example, the first pinning region 113 and the second pinning region 116 are formed of p-type semiconductor regions.

[0056] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. The electric field generated by the fixed charge film 112 forms a first pinning region 113 at the interface on the light-receiving surface (back side) of the semiconductor layer 100S. This first pinning region 113 serves as a hole accumulation layer. This suppresses the generation of dark current caused by the interface energy level on the light-receiving surface of the semiconductor layer 100S. For example, the fixed charge film 112 is formed from an insulating film having a negative fixed charge. Examples of materials for such insulating films having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. On the side closer to the light-receiving lens 401 than to the fixed charge film 112, a light shielding film 117A is formed to be wider than the width inside the semiconductor layer 100S, and the light shielding film 117A is provided to cover a portion of the fixed charge film 112. The insulating film 111 is provided to cover the light shielding film 117A and the fixed charge film 112. For example, the insulating film 111 is made of silicon oxide.

[0057] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 includes an interlayer insulating film 123, pad portions 120 and 121, and a transfer gate TG. The interlayer insulating film 123 is provided on the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. For example, the interlayer insulating film 123 is made of a silicon oxide film. The composition of the wiring layer 100T is not limited to the above-mentioned composition, but can be any composition having metal wiring and an insulating film. The pad portions 120 and 121 are provided in a selected area on the semiconductor layer 100S. The pad portion 120 connects the floating diffusion portions FD (FDa, FDb, FDc, FDd) of each pixel 31A, 31B, 31C, and 31D to each other. For example, for each pixel sharing unit 32, the pad portion 120 is arranged in the center of the pixel sharing unit 32 in a plan view. The pad portion 120 is provided across the pixel separator 117 and is configured to overlap at least a portion of each of the floating diffusions FDa, FDb, FDc, and FDd. Specifically, the pad portion 120 is formed in a region that overlaps at least a portion of each of the plurality of floating diffusions FD (FDa, FDb, FDc, FDd) of the shared pixel circuit 210, and at least a portion of the pixel separator 117 formed between the plurality of photodiodes PD (PDa, PDb, PDc, PDd) of the shared pixel circuit 210, in a direction perpendicular to the front surface of the semiconductor layer 100S. The pad portion 121 connects the plurality of VSS contact regions 118 to one another. For example, the VSS contact regions 118 provided in pixels 31B and 31D adjacent to each other in the V direction of the pixel sharing unit 32 are electrically connected to the VSS contact regions 118 provided in pixels 31A and 31C adjacent to each other in the V direction of the adjacent pixel sharing unit 32 via the pad portion 121. For example, pad portion 121 is provided so as to straddle pixel separator 117 and overlap at least a portion of each of the four VSS contact regions 118. Specifically, pad portion 121 is formed in a region that overlaps at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of pixel separator 117 formed between the plurality of VSS contact regions 118, in a direction perpendicular to the front surface of semiconductor layer 100S. Providing pad portion 120 reduces the number of wiring lines connecting each floating diffusion FD to pixel circuit 210 (e.g., the gate electrode of amplifier transistor AMP) throughout the chip. Similarly, providing pad portion 121 reduces the number of wiring lines supplying potential to each VSS contact region 118 throughout the chip. This allows for a reduction in the overall chip area, suppresses electrical interference between wiring lines in miniaturized pixels, and / or reduces costs by reducing the number of components. Pad portions 120 and 121 can be provided at desired locations on first substrate 100 or second substrate 200.Specifically, the pad portions 120 and 121 can be provided in the insulating region 212 of the wiring layer 100T or the semiconductor layer 200S. In particular, when the pad portions 120 and 121 are provided on the wiring layer 100T, the number of wiring lines connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S can be reduced. Therefore, in the second substrate 200 on which the pixel circuit 210 is formed, the area of ​​the insulating region 212 used to form the through wiring lines connecting the floating diffusion FD to the pixel circuit 210 can be reduced. Consequently, a larger area of ​​the second substrate 200 for forming the pixel circuit 210 can be secured. By securing the area of ​​the pixel circuit 210, larger pixel transistors can be formed, thereby contributing to improved image quality by, for example, reducing noise. In particular, when the pixel separation unit 117 uses an FTI structure, since it is preferred to provide a floating diffusion unit FD and / or a VSS contact region 118 for each pixel 31, the number of wiring lines connecting the first substrate 100 and the second substrate 200 can be significantly reduced by using the configuration of the pad units 120 and 121. For example, the pad units 120 and 121 are made of polysilicon (Poly Si), or more specifically, doped polysilicon with impurities added. The pad units 120 and 121 can be made of a high melting point metal material such as tungsten (W), titanium (Ti), molybdenum (Mo), or tantalum (Ta). By forming the pad units 120 and 121 from a highly heat-resistant conductive material such as polysilicon, tungsten (W), titanium (Ti), or titanium nitride (TiN), the pixel circuit 210 can be formed after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. The reason for this will be explained below. Note that in the following description, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100 is referred to as the first manufacturing method. On the other hand, the method of bonding the second substrate 200 to the first substrate 100 after forming the pixel circuit 210 on the second substrate 200 is referred to as the second manufacturing method.

[0058] In the second manufacturing method, electrodes for electrical connection are preformed on the respective bonding surfaces of the first and second substrates 100, 200. When the first and second substrates 100, 200 are bonded together, the electrodes for electrical connection formed on the first and second substrates 100, 200, are simultaneously brought into contact with each other. This establishes electrical connection between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by using the second manufacturing method to construct the solid-state imaging device 1, appropriate manufacturing processes can be employed, depending on, for example, the respective configurations of the first and second substrates 100, 200, resulting in a high-quality, high-performance imaging device. In this second manufacturing method, alignment errors may occur when the first and second substrates 100, 200 are bonded together due to the bonding equipment used. For example, the diameters of the first and second substrates 100, 200 are approximately tens of centimeters. When the first and second substrates 100, 200 are bonded together, expansion and contraction of the substrates may occur within microscopic regions of each of the first and second substrates 100, 200. This expansion and contraction is caused by slight variations in the time the substrates are in contact with each other. Due to such expansion and contraction of the first substrate 100 and the second substrate 200, errors may occur in the positions of the electrodes for electrical connection formed on the first substrate 100 and the second substrate 200, respectively. In the second manufacturing method, it is preferred to handle such errors so that even if such errors occur, the electrodes of the first substrate 100 and the second substrate 200 can contact each other. Specifically, in view of the above-mentioned errors, the size of at least one of the electrodes of the first substrate 100 and the second substrate 200 is larger, and preferably the sizes of both electrodes are larger. Therefore, for example, when the second manufacturing method is used, the size of the electrode formed on the first substrate 100 or the second substrate 200 (the size in the substrate plane direction) becomes larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 200 in the thickness direction to the surface.

[0059] On the other hand, the first manufacturing method described above can be used by constructing the pad portions 120 and 121 from a heat-resistant conductive material. In the first manufacturing method, a first substrate 100 including the photodiode PD, transfer transistor TR, and the like is formed. Thereafter, the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together. At this point, the second substrate 200 is in a state where the patterns of the active elements and wiring layers that constitute the pixel circuit 210 have not yet been formed. Because the second substrate 200 is in a state before the patterning, even if errors occur in the bonding position of the first and second substrates 100, 200 when they are bonded, errors do not occur in the alignment between the patterns on the first and second substrates 100, 200. This is because the patterns on the second substrate 200 are formed after the first and second substrates 100, 200 are bonded together. When forming the pattern on the second substrate 200, for example, the pattern formed on the first substrate is used as an alignment target in an exposure device used for pattern formation. For the reasons described above, in the first manufacturing method, an error in the bonding position between the first substrate 100 and the second substrate 200 does not cause any problem in the manufacture of the solid-state imaging device 1. For the same reasons, an error caused by expansion and contraction of the substrates generated in the second manufacturing method does not cause any problem in the manufacture of the solid-state imaging device 1 in the first manufacturing method.

[0060] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (their semiconductor layers 200S) are bonded together in this manner, active elements are formed on the second substrate 200. Subsequently, through-electrodes 120E, 121E, and the like are formed. When forming through-electrodes 120E and 121E, for example, reduced projection exposure is used by an exposure device to form the through-electrode pattern from above the second substrate 200. Because reduced projection exposure is used, even if there is an alignment error between the second substrate 200 and the exposure device, the magnitude of the error in the second substrate 200 is only a fraction of the error in the second manufacturing method (the inverse of the reduced projection exposure magnification). Therefore, by constructing the solid-state imaging device 1 using the first manufacturing method, alignment of elements formed on each of the first substrate 100 and the second substrate 200 is facilitated, enabling the manufacture of a high-quality, high-performance imaging device.

[0061] The solid-state imaging device 1 manufactured using this first manufacturing method has different characteristics from the solid-state imaging device 1 manufactured using the second manufacturing method. Specifically, in the solid-state imaging device 1 manufactured using the first manufacturing method, for example, the through-electrodes 120E and 121E are configured to extend from the second substrate 200 to the first substrate 100, and their thickness (dimension in the substrate plane direction) is approximately constant. Alternatively, when the through-electrodes 120E and 121E have a tapered shape, the through-electrodes 120E and 121E have a tapered shape with a constant slope. In a solid-state imaging device 1 having such through-electrodes 120E and 121E, it is easy to miniaturize the pixels 31.

[0062] Here, when manufacturing the solid-state imaging device 1 using the first manufacturing method, after bonding the first substrate 100 and the second substrate 200 (its semiconductor layer 200S), active elements are formed on the second substrate 200. This means that the heat treatment required during the formation of the active elements also affects the first substrate 100. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided on the first substrate 100. For example, it is preferable to use a material with a higher melting point than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200 (i.e., a material with higher heat resistance). For example, a conductive material with high heat resistance, such as doped polysilicon, tungsten, titanium, or titanium nitride, is used for the pad portions 120 and 121. Therefore, using the first manufacturing method described above, the solid-state imaging device 1 can be manufactured. The pad portions 120 and 121 can be made of a metal material such as tantalum nitride (TaN), aluminum (Al), or copper (Cu).

[0063] <5. DTMOS Configuration Example> Figure 5 is schematically shown with Figure 4 The diagram shows a cross-sectional view of a configuration example of the first substrate 100 and the second substrate 200 in portions where the portions are different.

[0064] Figure 5 The figure shows a portion of the first substrate 100 in the stacking direction of the second substrate 200, and particularly shows a cross-sectional structure near the transistor TRX formed on the second substrate 200. For example, the transistor TRX is a special transistor (specific transistor) provided in any one or more circuits of the input section 21A, the row driver 22, the timing control section 23, the column signal processing section 25, the image signal processing section 26, and the output section 21B. The transistor TRX is configured as a DTMOS (dynamic threshold voltage MOS) in which the gate electrode and the well region are electrically short-circuited.

[0065] The transistor TRX includes a gate electrode TGX formed on the front surface of the semiconductor layer 200S, a well region 211 formed in the semiconductor layer 200S, a source electrode 251, and a drain electrode 252. The side of the gate electrode TGX is covered by the sidewall SWX. The source electrode 251 and the drain electrode 252 are formed in the entire thickness direction of the semiconductor layer 200S, and the bottom surfaces of the source electrode 251 and the drain electrode 252 are in contact with the interlayer insulating film 123 of the wiring layer 100T. The area outside the source electrode 251 and the drain electrode 252 is separated by the insulating region 212. For example, the gate electrode TGX is made of polysilicon (Poly Si), or more specifically, made of doped polysilicon with added impurities. The source electrode 251 and the drain electrode 252 are composed of n-type semiconductor regions. For example, the sidewall SWX contains silicon nitride (SiN).

[0066] The wiring layer 200T of the second substrate 200 has contact wirings 261, 262, and 263 and a through electrode 142. The contact wiring 261 is connected to the gate electrode TGX and supplies a predetermined voltage Vg (gate voltage Vg) to the gate electrode TGX. The contact wiring 262 is connected to the source electrode 251, and the contact wiring 263 is connected to the drain electrode 252. Barrier metals 271, 272, 273, and 144 are formed between the contact wirings 261, 262, 263, the through electrode 142, and the interlayer insulating film 222. The contact wirings 261, 262, 263 and the through electrode 142 are made of a metal material such as tungsten (W), aluminum (Al), or copper (Cu). For example, the barrier metals 271, 272, 273, and 144 are made of Ti, TiN, Ta, TaN, etc.

[0067] A plurality of active regions 171 (171A, 171B) are provided in the semiconductor layer 100S of the first substrate 100, and each active region 171 is separated by an element isolation region 172. For example, the active regions 171 are p-type semiconductor regions. For example, the element isolation regions 172 are made of silicon oxide. A contact region 173 is provided in the active region 171A near the front surface of the semiconductor layer 100S. For example, the contact region 173 is composed of a p-type semiconductor region having a higher concentration than that of the active region 171. For example, the contact region 173 is connected to a ground potential or a fixed potential. This allows a reference potential to be supplied to the semiconductor layer 100S.

[0068] The wiring layer 100T includes wiring 151, contact wiring 141, and through-electrode 142. The wiring 151 is formed on the front surface of the semiconductor layer 100S from, for example, polysilicon, or more specifically, doped polysilicon to which impurities are added. The wiring 151 can be formed from a high-melting-point metal material. For example, tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), etc. can be used as the high-melting-point metal material. The wiring 151 is connected to the well region 211, which is the body of the transistor TRX, via the contact wiring 141, and supplies a body potential to the well region 211 of the transistor TRX. Silicide 152 is formed at the connection portion between the well region 211 and the contact wiring 141. The body potential supplied from the wiring 151 to the well region 211 via the contact wiring 141 is the same as the potential supplied to the gate electrode TGX via the contact wiring 261. In other words, the well region 211 is electrically short-circuited to the gate electrode TGX.

[0069] Barrier metals 143 and 144 are formed between the contact wiring 141 and the through electrode 142 of the wiring layer 100T and the interlayer insulating film 123, respectively. The contact wiring 141 and the through electrode 142 are made of a metal material such as tungsten (W), aluminum (Al), or copper (Cu). For example, the barrier metals 143 and 144 are made of Ti, TiN, Ta, TaN, etc.

[0070] As described above, transistor TRX has an SOI (silicon on insulator) structure, in which the bottom surfaces of the well region 211, the source electrode 251, and the drain electrode 252 are in contact with the insulating film (interlayer insulating film 123). Transistor TRX is a DTMOS, in which the well region 211 is completely separated from other transistors by an insulating region (interlayer insulating film 123 and insulating region 212), and the same potential as the potential (gate voltage Vg) supplied to the gate electrode TGX is supplied to the well region 211 as the main body potential. When the DTMOS is turned off (Vg = 0 V), no substrate bias is applied, and the threshold voltage Vth is high. On the other hand, since the substrate bias effect occurs when the DTMOS is turned on, the threshold voltage Vth is reduced and a higher on-current can be obtained. Therefore, by operating the transistor TRX as a DTMOS, the increase in off-state leakage can be suppressed while increasing the on-current. The electrical characteristics of the transistor TRX can be improved.

[0071] Since the bottom surface of the source electrode 251 of the transistor TRX is in contact with the insulating film (interlayer insulating film 123 ), the contact area between the body and the source electrode can be minimized, and the current associated with the forward bias can be minimized.

[0072] In the transistor TRX, the contact wiring 141 is connected to the bottom surface of the well region 211, and the main body potential is supplied from the wiring 151 in the wiring layer 100T formed below the semiconductor layer 200S. Here, in the case of a configuration in which the main body potential is supplied from the wiring layer 200T on the front surface side of the semiconductor layer 200S to the well region 211, an area for connecting the contact wiring in the wiring layer 200T formed on the front surface side of the semiconductor layer 200S to the well region 211 is required. Therefore, it is necessary to increase the plane area so that Figure 6 The well region 211 shown protrudes in the planar direction, thereby increasing the area occupied by the transistor. In the transistor TRX, by connecting to the well region 211 from the wiring layer 100T on the back side of the semiconductor layer 200S, rather than connecting to the well region 211 from the wiring layer 200T on the front surface side of the semiconductor layer 200S, the area occupied by the transistor can be reduced and area loss can be suppressed. By connecting to the bottom surface of the well region 211, the design freedom of the contact wiring 141 is increased, and the inter-wiring capacitance can be reduced.

[0073] In the solid-state imaging device 1, the transistor TRX having a DTMOS structure can be used in any one or more circuits of the input section 21A, row driver section 22, timing control section 23, column signal processing section 25, image signal processing section 26, and output section 21B formed on the second substrate 200. A transistor having a DTMOS structure or a conventional transistor can be used based on the magnitude relationship between the source-drain current and the source-well current, or the maximum voltage applied to the gate electrode (and the main body). For example, in the case of an N-type MOS transistor, if the maximum voltage applied to the gate electrode is approximately 0.8 V, the forward current between the source and the main body is less affected. Therefore, when the maximum voltage applied to the gate electrode is 0.8 V or less, a transistor TRX having a DTMOS structure can be used. By using a transistor TRX having a DTMOS structure, transistor characteristics can be improved. In the case of a structure in which the bottom surface of the source electrode contacts the insulating film, the forward current is reduced, which is more advantageous.

[0074] The transistor TRX has been described as a transistor provided in any one circuit or multiple circuits of the input section 21A, the row drive section 22, the timing control section 23, the column signal processing section 25, the image signal processing section 26, and the output section 21B, but the transistor TRX may also be a transistor provided in the pixel array section 24. For example, at least one of the pixel transistors constituting the pixel circuit 210 shared by a plurality of pixels 31 or the pixel circuit 210 provided for each pixel may be used as a transistor TRX having a DTMOS structure. In the case where there is a transistor provided separately from the pixel circuit 210 for each pixel, the transistor may be used as the transistor TRX having a DTMOS structure.

[0075] <6. DTMOS Manufacturing Method> Now, next, refer to Figure 7 and Figure 8 right Figure 5 A method for manufacturing the transistor TRX shown will be described.

[0076] First, if Figure 7 As shown in FIG. 1A , an active region 171 (171A, 171B) and an element isolation region 172 are formed in a semiconductor layer 100S, which serves as the first substrate 100. For example, the active region 171 is a p-type semiconductor region. For example, the element isolation region 172 is made of silicon oxide. A contact region 173 is formed near the front surface of the active region 171A of the semiconductor layer 100S. For example, the contact region 173 is made of a p-type semiconductor region having a higher concentration than that of the active region 171. Elements such as MOS transistors (MOSFETs) are formed in the active region 171 (not shown).

[0077] Next, if Figure 7 As shown in FIG. B, a wiring 151 is formed in a predetermined region on the front surface of the semiconductor layer 100S. For example, the wiring 151 is made of a conductive material having high heat resistance such as polysilicon or tungsten.

[0078] Next, if Figure 7 As shown in FIG. 3 , an interlayer insulating film 123 of the wiring layer 100T is formed on the upper surface of the semiconductor layer 100S on which the wiring 151 is formed, for example, by using a CVD method (Chemical Vapor Deposition). Thereafter, the upper surface of the interlayer insulating film 123 is flattened by, for example, a CMP method (Chemical Mechanical Polishing). For example, the interlayer insulating film 123 can be made of SiO2, SiN, ION, SiCN, or the like. The first substrate 100 is composed of the semiconductor layer 100S and the wiring layer 100T.

[0079] Next, if Figure 7 As shown in FIG. 2 , a portion of the interlayer insulating film 123 in the region where the wiring 151 is formed is opened by etching to form a barrier metal 143 , and thereafter, a metal material such as tungsten is embedded and planarized to form the contact wiring 141 .

[0080] Next, if Figure 7 As shown in FIG. E, a portion of the metal material embedded as the contact wiring 141 is removed by etching back, and then the semiconductor layer 200S ( Figure 8 ) and planarize the metal material 152' of silicon and silicide. For example, the metal material 152' is made of titanium.

[0081] Next, if Figure 8 As shown in FIG. 1A , the semiconductor layer 200S to be the second substrate 200 is bonded to the interlayer insulating film 123 of the wiring layer 100T of the first substrate 100 by, for example, plasma bonding or the like. The semiconductor layer 200S is made of, for example, a silicon substrate.

[0082] Next, if Figure 8 As shown in FIG. 1B , a well region 211 serving as an active region and an insulating region 212 serving as an element isolation region are formed in the semiconductor layer 200S. For example, the well region 211 is configured as a p-type semiconductor region. For example, the insulating region 212 is composed of silicon oxide.

[0083] Next, if Figure 8 As shown in FIG. 3 , a gate electrode TGX and a sidewall SWX of the transistor TRX are formed on the well region 211, and a source electrode 251 and a drain electrode 252 are formed in the well region 211. Thus, the transistor TRX is completed. The source electrode 251 and the drain electrode 252 are n-type semiconductor regions, and are formed by ion implantation of n-type impurities such as phosphorus and arsenic and by performing an activation annealing process. In the source electrode 251 and the drain electrode 252, the n-type semiconductor region below the sidewall SWX can be an LDD (Lightly Doped Drain) region formed with a low impurity concentration. In view of Figure 8 In the heating process in step C shown, the well region 211 connected to the metal material 152 ′ of the contact wiring 141 is converted into silicide, thereby forming the silicide 152 .

[0084] Next, if Figure 8As shown in FIG. 2 , an interlayer insulating film 222 of the wiring layer 200T is formed on the upper surface of the semiconductor layer 200S on which the transistor TRX is formed, for example, by CVD. Thereafter, the upper surface of the interlayer insulating film 222 is planarized by, for example, CMP. For example, the interlayer insulating film 222 can be made of SiO2, SiN, ION, SiCN, or the like. The second substrate 200 is composed of the semiconductor layer 200S and the wiring layer 200T.

[0085] Next, if Figure 8 As shown in E, a contact wiring 261 connected to the gate electrode TGX, a contact wiring 262 connected to the source electrode 251, a contact wiring 263 connected to the drain electrode 252, and a through electrode 142 connected to the contact area 173 of the first substrate 100 are formed. More specifically, first, a through hole is formed and opened in the interlayer insulating film 222 that penetrates the wiring layer 200T in the area connected to the gate electrode TGX, the source electrode 251 and the drain electrode 252 of the second substrate 200 and the contact area 173 of the first substrate 100. A through hole that reaches the contact area 173 is formed in the area corresponding to the through electrode 142. After forming barrier metals 271, 272, 273 and 144 on the inner peripheral surface (side wall) of the through hole, a metal material such as tungsten is embedded, thereby forming the contact wirings 261, 262, 263 and the through electrode 142. Through the above process, the Figure 5 The structure around the transistor TRX is shown.

[0086] As described above, the transistor TRX may be formed on the first substrate 100 and the second substrate 200 .

[0087] <7. Modifications> Figure 9 and Figure 10 is a cross-sectional view showing a modified example of the transistor TRX. Figure 9 and Figure 10 In, with Figure 5 The corresponding parts to those in are denoted by the same reference numerals and logos, and the description of these parts is omitted as appropriate.

[0088] Figure 9 A first modification example of the transistor TRX is shown.

[0089] Figure 5 The transistor TRX shown has a DTMOS structure in which the same potential as the potential (gate voltage Vg) supplied to the gate electrode TGX is supplied to the well region 211 (body). Figure 5 In the transistor TRX shown, the potential of the well region 211 (body) is controlled to be the same as the potential of the gate electrode TGX.

[0090] On the other hand, the transistor TRX according to the first modification has a structure in which a fixed potential is applied to the well region 211 (body) regardless of the voltage control of the gate electrode TGX. Figure 5 In the transistor TRX, the wiring 151 formed on the front surface of the semiconductor layer 100S is omitted, and Figure 9 In the first modified example, a contact region 174 is formed in the active region 171C of the semiconductor layer 100S. Contact region 174 is composed of a p-type semiconductor region or an n-type semiconductor region. Active regions 171A and 171C are separated by element isolation region 172. Contact wiring 141, which is connected to the well region 211 (main body), is connected to contact region 174. A reference potential, such as a ground potential or a fixed potential, is supplied from contact region 174 to the well region 211 via contact wiring 141.

[0091] Notice, Figure 5 The transistor TRX shown may have a configuration in which a reference potential such as a ground potential or a fixed potential is supplied to the well region 211 (body) from a wiring 151 formed on the front surface of the semiconductor layer 100S, instead of the same potential as the gate voltage Vg.

[0092] Figure 10 A second modification example of the transistor TRX is shown.

[0093] In the second modification, active regions 171A and 171D are provided in the semiconductor layer 100S of the first substrate 100 and are separated by the element isolation region 172. Figure 5 In the transistor TRX shown, the wiring 151 for supplying the same potential as the gate voltage Vg to the well region 211 (body), the contact wiring 141, and the barrier metal 143 are omitted.

[0094] Furthermore, in the second modified example, the contact wiring 262 connected to the source electrode 251 of the transistor TRX and the barrier metal 272 on the periphery of the contact wiring 262 are not formed on the wiring layer 200T of the second substrate 200, but are formed on the wiring layer 100T of the first substrate 100. In other words, the contact wiring 262 connected to the source electrode 251 is configured so as to be connected from the bottom side of the source electrode 251 rather than from the upper side of the source electrode 251. Silicide 153 is formed at the connection portion between the source electrode 251 and the contact wiring 262. The contact wiring 262 connects the source electrode 251 and the contact region 175 of the active region 171D.

[0095] Figure 10The second modification example has a configuration in which the contact wiring 262 connected to the source electrode 251 is not connected from the upper side of the source electrode 251 but is connected from the lower side of the source electrode 251. Similarly, the contact wiring 263 connected to the drain electrode 252 may be connected not from the upper side of the drain electrode 252 but from the lower side of the drain electrode 252. Alternatively, both the contact wiring 262 connected to the source electrode 251 and the contact wiring 263 connected to the drain electrode 252 may be connected not from the upper side but from the lower side. In addition, a combination of Figure 9 The first variant and Figure 10 The structure of the second modification example.

[0096] As described above, in the solid-state imaging device 1, the transistor TRX formed on the second substrate 200 has a configuration in which at least one wiring (contact wiring 141, 262, 263) connected to the well region 211, source electrode 251, or drain electrode 252 is connected not from the upper side of the semiconductor layer 200S where the well region 211, source electrode 251, and drain electrode 252 are formed, but from the lower side of the semiconductor layer 200S where the well region 211, source electrode 251, and drain electrode 252 are formed, that is, from the wiring layer 100T on the side opposite to the gate electrode side of the semiconductor layer 200S. Furthermore, a configuration can be adopted in which the bottom surface of the well region 211, source electrode 251, or drain electrode 252 connected from the lower side is connected to the insulating film 123. Therefore, the degree of freedom in the layout of the contact wiring increases, thereby increasing the degree of freedom in wiring design, and the inter-wiring capacitance can be reduced. Furthermore, the area occupied by the transistor can be reduced, and area loss can be suppressed.

[0097] <8. Example of Three-Layer Stacked Structure of Solid-State Imaging Device> Figure 11 It shows Figure 4 The cross-sectional view is a configuration example of stacking three substrates in the pixel sharing unit 32 shown.

[0098] exist Figure 11 In the embodiment, due to the composition of the semiconductor layer 200S of the first substrate 100 and the second substrate 200, Figure 4 The structure shown is basically the same, so Figure 4 The different parts in the section are explained.

[0099] The wiring layer 200T of the second substrate 200 has second and third metal wirings W2 and W3 above the first metal wirings W1. The wiring layer 200T also has a plurality of bonding electrodes 241 on the surface that bonds with the wiring layer 300T of the third substrate 300. The bonding electrodes 241 are made of a metal such as Cu (copper) or Al (aluminum). Each bonding electrode 241 serves to electrically connect the second substrate 200 and the third substrate 300 and to bond the two substrates together.

[0100] The third substrate 300 has a semiconductor layer 300S as a third semiconductor layer and a wiring layer 300T as a third wiring layer, and is bonded to the second substrate 200 in such a manner that the front surface of the semiconductor layer 300S faces the front surface side of the second substrate 200. That is, the third substrate 300 is bonded to the second substrate 200 in a face-to-face manner. For example, a transistor 311 as a part of the image signal processing unit 26 is formed in the semiconductor layer 300S. For example, the wiring layer 300T includes an interlayer insulating film 321 and a plurality of metal wirings W stacked therebetween. Figure 4 In the embodiment, a double-layer metal wiring W having a first metal wiring W11 and a second metal wiring W12 is formed, but the number of stacked metal wirings W is not limited. For example, the metal wiring W is made of tungsten (W), aluminum (Al), copper (Cu), etc. For example, the interlayer insulating film 321 is made of silicon oxide. The wiring layer 300T also has a plurality of bonding electrodes 341 on the bonding surface of the wiring layer 200T with the second substrate 200. The bonding electrodes 341 are made of a metal such as Cu (copper) or Al (aluminum). Each bonding electrode 341 is used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding between the second substrate 200 and the third substrate 300.

[0101] By stacking three substrates as described above, the solid-state imaging device 1 can be formed with the same chip size as before, even if the number of pixels or pixel circuits increases. Alternatively, a solid-state imaging device 1 with a reduced chip size can be provided while the number of pixels or pixel circuits remains the same.

[0102] <9. Application examples of electronic devices> The technology disclosed herein is not limited to solid-state imaging devices. In other words, the technology disclosed herein can be generally applied to electronic devices that use solid-state imaging devices in image capture units (photoelectric conversion units), such as imaging devices (e.g., digital cameras or video cameras), mobile terminal devices with imaging functions, and copy machines that use solid-state imaging devices in image readout units. A solid-state imaging device can be in the form of a single chip, or it can be in the form of a module with imaging functions, in which the imaging unit and signal processing unit or optical system are packaged together.

[0103] Figure 12 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the technology according to the present disclosure is applied.

[0104] Figure 12 The imaging device 600 shown includes: an optical part 601 composed of a lens group, etc.; Figure 1 The solid-state imaging device 1 shown in FIG. 1 includes a solid-state imaging device (imaging device) 602 and a DSP (digital signal processor) circuit 603 as a camera signal processing circuit. The imaging device 600 further includes a frame memory 604, a display unit 605, a recording unit 606, an operation unit 607, and a power supply unit 608. The DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via a bus 609.

[0105] The optical section 601 captures incident light (image light) from the subject and forms an image on the imaging surface of the solid-state imaging device 602. The solid-state imaging device 602 converts the amount of incident light formed on the imaging surface by the optical section 601 into an electrical signal in units of pixels and outputs the electrical signal as a pixel signal. As the solid-state imaging device 602, it is possible to use Figure 1 The solid-state imaging device 1 shown is a solid-state imaging device that is a stack of at least two substrates, a first substrate 100 and a second substrate 200, and includes a transistor TRX to which a wiring connected to a well region 211 (main body) of a semiconductor layer 200S of the second substrate 200, a source electrode 251, or a drain electrode 252 is connected from the lower side of the semiconductor layer 200S.

[0106] The display section 605 is composed of, for example, a thin display such as a liquid crystal display (LCD) or an organic electroluminescence (EL) display, and displays a moving image or a still image captured by the solid-state imaging device 602. The recording section 606 records the moving image or the still image captured by the solid-state imaging device 602 in a recording medium such as a hard disk or a semiconductor memory.

[0107] The operation section 607 issues operation instructions for various functions of the imaging device 600 based on user operations. The power supply section 608 appropriately supplies various types of power used as operating power sources for the DSP circuit 603, frame memory 604, display section 605, recording section 606, and operation section 607 to these supply targets.

[0108] As described above, by using the solid-state imaging device 1 having the transistor TRX described above as the solid-state imaging device 602, it is possible to enhance the performance of the transistor having key characteristics. Furthermore, the increased freedom of wiring reduces inter-wiring capacitance, allows for finer pixel size, and achieves high image quality. Consequently, the imaging device 600 used in camera modules for video cameras, digital cameras, and mobile devices including mobile phones can be miniaturized and achieve higher quality captured images.

[0109] <Use Examples of Image Sensors> Figure 13 is a diagram showing an example of how an image sensor including the solid-state imaging device 1 is used.

[0110] For example, as an image sensor, the above-described solid-state imaging device 1 can be used in various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays as described below.

[0111] • Devices used to capture images for viewing, such as digital cameras and portable devices with camera functions • Traffic devices, such as on-board sensors that capture images of the front, rear, surroundings, and interior of a car for the purpose of safe driving, including automatic parking, or identifying the driver's status; surveillance cameras that monitor moving vehicles or roads; and distance sensors that measure the distance between vehicles. • Devices for home appliances, such as televisions, refrigerators, and air conditioners, to capture images of user gestures and perform appliance operations based on the gestures • Medical devices, such as endoscopes and devices for angiography by receiving infrared light • Security devices, such as surveillance cameras for crime prevention and cameras for personal identification • Devices for beauty care, such as dermatometers that take pictures of the skin and microscopes that take pictures of the scalp • Sports devices, such as action cameras and wearable cameras for sports applications • Agricultural devices, such as cameras used to monitor the condition of fields or crops.

[0112] <10. Application Examples for Mobile Objects> The technology disclosed herein (the present technology) can be applied to a variety of products. For example, the technology disclosed herein can be implemented as a device installed in any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0113] Figure 141 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0114] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 14 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0115] Drive system control unit 12010 controls the operation of devices related to the vehicle drive system according to various programs. For example, drive system control unit 12010 functions as a control device for devices such as a drive force generating device such as an internal combustion engine or a drive motor for generating drive force for the vehicle; a drive force transmission mechanism for transmitting drive force to wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating braking force for the vehicle.

[0116] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a portable device that replaces the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input of radio waves or signals and controls the vehicle's door locks, power windows, lights, and other devices.

[0117] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle in which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The imaging unit 12031 captures an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection or distance detection processing on people, vehicles, obstacles, signs, road surface symbols, and the like.

[0118] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal based on the amount of light received. The imaging unit 12031 can also output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0119] The in-vehicle information detection unit 12040 detects information about the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0120] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on information outside or inside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, vehicle-to-vehicle distance-based following, vehicle speed maintenance, vehicle collision warning, and vehicle lane departure warning.

[0121] Furthermore, by controlling the driving force generation device, steering mechanism, braking device, and the like based on information about the vehicle's surroundings acquired by vehicle exterior information detection unit 12030 or vehicle interior information detection unit 12040, microcomputer 12051 is capable of executing cooperative control, such as automatic driving, designed to enable autonomous driving without relying on driver input.

[0122] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights based on the position of the preceding vehicle or oncoming vehicle detected by the exterior information detection unit 12030 to perform cooperative control aimed at preventing glare, such as switching the high beam to the low beam.

[0123] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or auditorily notify the vehicle's passengers or the outside of the vehicle of information. Figure 14In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0124] Figure 15 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0125] exist Figure 15 In the figure, vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as imaging unit 12031.

[0126] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are provided at locations such as the front nose, side mirrors, rear bumper, rear door, and the upper portion of the windshield inside the vehicle 12100. Imaging unit 12101 provided on the front nose and imaging unit 12105 provided on the upper portion of the windshield inside the vehicle primarily capture images of the front of the vehicle 12100. Imaging units 12102 and 12103 provided on the side mirrors primarily capture images of the sides of the vehicle 12100. Imaging unit 12104 provided on the rear bumper or rear door primarily captures images of the rear of the vehicle 12100. The front images captured by imaging units 12101 and 12105 are primarily used to detect vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0127] Figure 15 The figure shows examples of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 represents the imaging range of imaging unit 12101 installed on the front nose, imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed on the side mirrors, respectively, and imaging range 12114 represents the imaging range of imaging unit 12104 installed on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 as viewed from above can be obtained.

[0128] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0129] For example, based on the distance information obtained from imaging units 12101 to 12104, by obtaining the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100), microcomputer 12051 can extract the closest three-dimensional object, particularly one located on the driving route of vehicle 12100 and traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h), as the preceding vehicle. Furthermore, microcomputer 12051 can set a predefined inter-vehicle distance to be maintained ahead of the preceding vehicle and execute automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control). Consequently, coordinated control, such as automated driving, can be executed, intended for autonomous driving without relying on driver input.

[0130] For example, based on the distance information obtained by the imaging units 12101 to 12104, the microcomputer 12051 can classify three-dimensional object data regarding three-dimensional objects into other three-dimensional objects such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, and utility poles, extract the three-dimensional object data, and use the three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 can identify obstacles around the vehicle 12100 as those observable by the driver of the vehicle 12100 and those that are difficult for the driver of the vehicle 12100 to observe. Furthermore, the microcomputer 12051 can determine a collision risk, indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and a collision is possible, a warning is output to the driver via the audio speaker 12061 or display unit 12062, or forced deceleration or evasive steering is executed by the drive system control unit 12010, thereby providing driving support for collision avoidance.

[0131] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from images captured by the imaging units 12101 to 12104, which function as infrared cameras, and performing pattern matching on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. The audio / video output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0132] Thus far, examples of vehicle control systems to which the technology of the present disclosure can be applied have been described. The technology of the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the solid-state imaging device 1 described above can be used as the imaging unit 12031. By applying the technology of the present disclosure to the imaging unit 12031, miniaturization and higher-quality captured images can be achieved. Furthermore, the use of the captured images obtained can reduce driver fatigue and improve driver and vehicle safety.

[0133] While the above examples illustrate a solid-state imaging device in which the first conductivity type is p-type, the second conductivity type is n-type, and electrons are used as signal charges, the present disclosure can also be applied to solid-state imaging devices in which holes are used as signal charges. That is, by configuring the first conductivity type to be n-type and the second conductivity type to be p-type, each of the above-mentioned semiconductor regions can be configured as a semiconductor region of opposite conductivity types.

[0134] In addition, the present disclosure can be applied not only to solid-state imaging devices that detect the distribution of the amount of incident light of visible light and capture the distribution as an image, but can also generally be applied to solid-state imaging devices that capture the distribution of the amount of incident light of infrared rays, X-rays, particles, etc. as an image. In a broad sense, it can also be applied to solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure or electrostatic capacitance and capture the distribution as an image.

[0135] Furthermore, the technology of the present disclosure can be applied not only to solid-state imaging devices but also generally to semiconductor devices having other semiconductor integrated circuits.

[0136] The embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the technology according to the present disclosure. For example, all or part of the above-described embodiments can be appropriately combined.

[0137] It should be noted that the beneficial effects described in this specification are merely exemplary and non-limiting, and beneficial effects other than those described in this specification may be produced.

[0138] The technology of the present disclosure can be configured as follows. (1) A solid-state imaging device comprising: a first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which signal charges generated in the photoelectric conversion portion are stored; and a second semiconductor layer on which a plurality of transistors including a pixel transistor for reading out the signal charge of the charge storage portion are formed, the second semiconductor layer being stacked on the first semiconductor layer; In which, at least one specific transistor among the multiple transistors is constructed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is constructed to be in contact with the insulating film. (2) The solid-state imaging device according to (1) above, wherein a first substrate and a second substrate are stacked, the first substrate including the first semiconductor layer and the first wiring layer, and The second substrate includes the second semiconductor layer and a second wiring layer, and The specific transistor is configured such that at least one wiring connected to the well region, the source electrode, or the drain electrode is connected from the first wiring layer arranged between the first semiconductor layer and the second semiconductor layer. (3) The solid-state imaging device according to (1) or (2) above, wherein the specific transistor is configured so that the at least one wiring connected to the well region, the source electrode, or the drain electrode is connected from a wiring formed on the upper surface of the first semiconductor layer. (4) The solid-state imaging device according to (3) above, wherein the specific transistor is configured to be connected to the well region from a wiring formed on an upper surface of the first semiconductor layer. (5) The solid-state imaging device according to (4) above, wherein the well region of the specific transistor is configured to be supplied with the same potential as that supplied to the gate electrode. (6) The solid-state imaging device according to (4) or (5) above, wherein the wiring formed on the upper surface of the first semiconductor layer is made of polysilicon or a high melting point metal material. (7) The solid-state imaging device according to (1) or (2) above, wherein the specific transistor is configured so that the at least one wiring connected to the well region, the source electrode, or the drain electrode is connected from a semiconductor region formed in the first semiconductor layer. (8) The solid-state imaging device according to (7) above, wherein the specific transistor is configured to be connected from the semiconductor region formed in the first semiconductor layer to the well region. (9) The solid-state imaging device according to (8) above, wherein the well region of the specific transistor is configured to be supplied with a reference potential. (10) The solid-state imaging device according to (7) above, wherein the specific transistor is configured to be connected from the semiconductor region formed in the first semiconductor layer to the source electrode or the drain electrode. (11) The solid-state imaging device according to any one of (1) to (10) above, wherein the specific transistor is configured to be separated from other elements in an element separation region. (12) The solid-state imaging device according to any one of (1) to (11) above, comprising: a first substrate including the first semiconductor layer and a first wiring layer; a second substrate including the second semiconductor layer and a second wiring layer; and a third substrate including a third semiconductor layer and a third wiring layer, Wherein, the second substrate is arranged between the first substrate and the third substrate. (13) A method for manufacturing a solid-state imaging device, comprising: a first semiconductor layer and a second semiconductor layer stacked, the first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which signal charges generated in the photoelectric conversion portion are stored, and a plurality of transistors including a pixel transistor for reading out the signal charges of the charge storage portion being formed on the second semiconductor layer; and At least one specific transistor among the multiple transistors is formed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is in contact with the insulating film. (14) An electronic device including a solid-state imaging device, the solid-state imaging device comprising: a first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which signal charges generated in the photoelectric conversion portion are stored; and a second semiconductor layer on which a plurality of transistors including a pixel transistor for reading out the signal charge of the charge storage portion are formed, the second semiconductor layer being stacked on the first semiconductor layer; In which, at least one specific transistor among the multiple transistors is constructed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is constructed to be in contact with the insulating film. [Reference Signs List]

[0139] 1Solid-state imaging device 24-pixel array unit 31 pixels 32-pixel shared unit PD photodiode TR transfer transistor TG transmission gate FD floating diffusion FDGFD conversion gain switching transistor AMP amplifier transistor RST reset transistor SEL select transistor W Metal Wiring SW sidewall TRX transistor TGX gate electrode SWX sidewall 100 first substrate 100S semiconductor layer 100T wiring layer 111 insulating film 117 pixel separation unit 117A light-shielding film 117B insulation film 120 pads 120E through-electrode 121 pad part 121E through-electrode 123 interlayer insulating film 141 contact wiring 142 through-electrode 143 barrier metal 151 wiring 152 Silicide 153 Silicide 171 active area 172 component separation area 173 contact area 174 contact area 175 contact area 200 second substrate 200S semiconductor layer 200T wiring layer 210 pixel circuit 211 well area 212 insulation area 213 component separation area 222 interlayer insulating film 251 source electrode 252 drain electrode 261 contact wiring 262 contact wiring 263 contact wiring 300 third substrate 300S semiconductor layer 300T wiring layer 401 light receiving lens 600 imaging device 602 solid-state imaging device.

Claims

1. A solid-state imaging device comprising: a first semiconductor layer including a photoelectric conversion portion and a charge storage portion, wherein the charge storage portion stores signal charges generated in the photoelectric conversion portion; and a second semiconductor layer on which a plurality of transistors including a pixel transistor for reading out the signal charge of the charge storage portion are formed, the second semiconductor layer being stacked on the first semiconductor layer; In which, at least one specific transistor among the multiple transistors is constructed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is constructed to be in contact with the insulating film.

2. The solid-state imaging device according to claim 1, in, A first substrate and a second substrate are stacked, the first substrate including the first semiconductor layer and the first wiring layer, The second substrate includes the second semiconductor layer and a second wiring layer, and The specific transistor is configured such that the at least one wiring connected to the well region, the source electrode, or the drain electrode is connected from the first wiring layer arranged between the first semiconductor layer and the second semiconductor layer.

3. The solid-state imaging device according to claim 1, wherein The specific transistor is configured so that the at least one wiring connected to the well region, the source electrode, or the drain electrode is connected from a wiring formed on an upper surface of the first semiconductor layer.

4. The solid-state imaging device according to claim 3, wherein The specific transistor is configured to be connected to the well region from a wiring formed on the upper surface of the first semiconductor layer.

5. The solid-state imaging device according to claim 4, wherein The well region of the specific transistor is configured to be supplied with the same potential as that supplied to the gate electrode.

6. The solid-state imaging device according to claim 4, wherein The wiring formed on the upper surface of the first semiconductor layer is made of polysilicon or a high melting point metal material.

7. The solid-state imaging device according to claim 1, wherein The specific transistor is configured such that at least one wiring connected to the well region, the source electrode, or the drain electrode is connected from a semiconductor region formed in the first semiconductor layer.

8. The solid-state imaging device according to claim 7, wherein The specific transistor is configured to be connected from a semiconductor region formed in the first semiconductor layer to the well region.

9. The solid-state imaging device according to claim 8, wherein The well region of the specific transistor is configured to be supplied with a reference potential.

10. The solid-state imaging device according to claim 7, wherein The specific transistor is configured to be connected to the source electrode or the drain electrode from a semiconductor region formed in the first semiconductor layer.

11. The solid-state imaging device according to claim 1, wherein The specific transistor is configured to be separated from other elements in an element isolation region.

12. The solid-state imaging device according to claim 1, comprising: a first substrate including the first semiconductor layer and a first wiring layer; a second substrate including the second semiconductor layer and a second wiring layer; as well as a third substrate including a third semiconductor layer and a third wiring layer, Wherein, the second substrate is arranged between the first substrate and the third substrate.

13. A method for manufacturing a solid-state imaging device, comprising: A first semiconductor layer and a second semiconductor layer are stacked, the first semiconductor layer including a photoelectric conversion portion and a charge storage portion in which signal charges generated in the photoelectric conversion portion are stored, and a plurality of transistors including a pixel transistor for reading out the signal charges from the charge storage portion are formed on the second semiconductor layer; and At least one specific transistor among the multiple transistors is formed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer on the side opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is in contact with the insulating film.

14. An electronic device comprising a solid-state imaging device, the solid-state imaging device comprising: a first semiconductor layer including a photoelectric conversion portion and a charge storage portion, wherein the charge storage portion stores signal charges generated in the photoelectric conversion portion; and a second semiconductor layer on which a plurality of transistors including a pixel transistor for reading out the signal charge of the charge storage portion are formed, the second semiconductor layer being stacked on the first semiconductor layer; In which, at least one specific transistor among the multiple transistors is constructed so that at least one wiring connected to the well region, the source electrode or the drain electrode is connected from the layer opposite to the gate electrode side of the second semiconductor layer, and the bottom surface of the well region, the source electrode or the drain electrode connected to the wiring is constructed to be in contact with the insulating film.

Images