AI computing power card BGA flatness testing method

Abstract

The invention relates to a BGA flatness testing method for an AI computing power card. The BGA flatness testing method comprises the following steps: S1, preprocessing: baking a BGA to eliminate internal stress; s2, temperature cycle testing, wherein the actual welding and working environment of the BGA is simulated through staged heating and cooling, and the highest temperature is larger than or equal to 250 DEG C; s3, optical interference detection: performing non-contact image acquisition on the surface of the BGA by adopting a Shadow Moire method in a temperature cycle process, and calculating the flatness of the BGA through the offset of moire fringes; and S4, judging: carrying out qualification judgment on the basis of the flatness maximum value in the high-temperature stage (greater than or equal to 200 DEG C). The invention provides a high-temperature dynamic flatness testing method for a large-size BGA (Ball Grid Array). Accurate flatness detection of the large-size BGA under a high-temperature condition is realized for the first time; by quantifying a test standard, assembly faults of clients caused by outflow of abnormal plates are avoided; the test process is high in repeatability, and the result reliability is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit packaging and testing technology, and in particular to a high-temperature flatness detection method for large-size BGA (ball grid array) packages for AI computing power cards. Background Art

[0002] In the manufacturing of high-performance computing hardware such as AI computing power cards, large-size BGA (ball grid array) packaging is widely used due to its high-density interconnection characteristics. However, existing BGA flatness detection technology has significant defects and cannot meet the requirements of high-reliability packaging:

[0003] Contact measurement causes structural damage: Traditional probe contact methods (such as CMMs) require physical contact with the solder ball surface. For high-density BGAs with solder ball pitches less than 0.5mm, probe positioning errors can easily cause micron-level scratches or collapse. This damage increases the risk of solder joint failure during the subsequent reflow process. Especially for large BGAs (over 70mm x 90mm), the mechanical stress of the probe can cause local deformation errors of up to 15 to 30μm.

[0004] Mismatch between the test environment and the actual working conditions: Conventional testing is carried out at a room temperature of 25°C, while the actual BGA soldering needs to experience a high temperature of more than 250°C (for example, the melting range of lead-free solder SnAgCu is 217-220°C). Due to the difference in thermal expansion coefficients between the epoxy resin substrate (CTE 14-18ppm / °C) and the silicon chip (CTE 2.6ppm / °C), the BGA will produce non-uniform thermal deformation at high temperatures (the warping can reach 100-200μm). Although existing optical detection solutions (such as CN112504209A using laser triangulation) achieve non-contact measurement, they do not integrate a temperature cycling module and cannot capture dynamic thermal deformation data.

[0005] The judgment criteria lack a quantitative basis: The current industry generally relies on manual visual inspection or single-point sampling (such as the four-corner measurement method), resulting in a high degree of dispersion in test results (±25μm). More seriously, a quantitative correlation model between high-temperature deformation and assembly failures has not been established. Abnormal boards (such as those with local warpage >100μm) flowing into the SMT placement process can cause defects such as solder bridging and head-in-pillow effects due to insufficient coplanarity. This type of failure is a key factor in the early failure of AI computing power cards. Summary of the Invention

[0006] In view of this, the present invention provides a high-temperature dynamic flatness test method for large-size BGAs, which realizes the accurate flatness detection of large-size BGAs under high temperature conditions for the first time; through quantitative test standards, it avoids abnormal board outflow and causes customer assembly failures; the test process has strong repeatability and improved result reliability.

[0007] The purpose of the present invention is achieved through the following technical solutions:

[0008] A method for testing the flatness of a BGA of an AI computing power card includes the following steps:

[0009] S1. Pretreatment: Bake the BGA to eliminate internal stress;

[0010] S2. Temperature Cycle Test: Simulates the actual BGA soldering and working environment by heating and cooling in stages, with the maximum temperature ≥ 250°C;

[0011] S3. Optical interferometry: During the temperature cycling process, the Shadow Moire method is used to acquire non-contact images of the BGA surface, and the BGA flatness is calculated based on the Moire fringe offset.

[0012] S4. Judgment: Qualification is determined based on the maximum flatness value at the high temperature stage (≥200°C).

[0013] The pretreatment step eliminates the internal stress of the BGA through baking, avoids test data deviation caused by residual stress, and improves the reliability of the test results; the dynamic temperature cycle simulates the real welding and working environment (such as reflow soldering peak temperature and long-term high-temperature operation scenarios), and ensures data reproducibility through two repeated cycle tests, solving the technical defect that traditional room temperature testing cannot reflect high-temperature deformation; non-contact optical detection avoids contact probe damage to the solder balls, and realizes the accurate detection of 70mm×90mm large-size BGA under high temperature conditions for the first time, which is especially suitable for high-density and large-size BGA to ensure test safety; the high-temperature stage judgment focuses on the deformation data of the cooling stage after welding (such as 240~250℃), sets a 100μm flatness threshold as the quantitative standard, directly links to the actual assembly failure risk, effectively intercepts the outflow of abnormal boards, and improves the actual guidance value of the test results.

[0014] Preferably, the baking temperature in S1 is 120-150° C., and the baking time is 6-15 hours.

[0015] The 120-150°C baking temperature balances the thermal stability of the material and the stress release efficiency, which can not only fully eliminate the internal stress of the epoxy resin substrate, but also avoid solder oxidation or substrate delamination caused by high temperature; the 6-15 hour baking time is adapted to substrates of different thicknesses (such as 0.8-1.6mm), ensuring uniform stress release and avoiding local stress residue caused by too short a time or increased energy consumption due to too long a time; this parameter range is compatible with mainstream packaging production line baking equipment (such as tunnel ovens and vacuum ovens) and can be integrated into existing production processes without additional modifications.

[0016] Preferably, the temperature rising section in S2 includes at least three stages, the temperature rising rates of each stage are 0.5-1.0°C / s, 0.3-0.5°C / s, 0.4-0.6°C / s, and the temperature difference between adjacent stages is ≥50°C.

[0017] By matching the thermal response characteristics of materials in different temperature ranges with differentiated heating rates (such as rapid heating in low-temperature zones to reduce test time and slowing down in high-temperature zones to avoid thermal shock), test efficiency and safety are improved. Simulating the actual soldering temperature curve (such as preheating → infiltration → reflow) ensures that the test data is highly consistent with the actual working conditions. By decreasing the rate (such as 1.0°C / s → 0.3°C / s), microcracks are prevented in the solder balls due to sudden heating in the high-temperature zone, ensuring a non-destructive test process.

[0018] Preferably, the Shadow Moire method in S3 adopts a Ronchi grating with a line density of 40 to 60 lines / mm and a light source incident angle of 30° to 60°.

[0019] A line density of 40 to 60 lines / mm generates clear moiré fringes on the BGA surface, balancing resolution and noise immunity, and avoiding fringe blurring caused by solder ball reflection interference in high-density gratings (>80 lines / mm). A light source angle of 30° to 60° enhances the sensitivity of surface undulations to fringe distortion, making it particularly suitable for detecting micron-level warpage (e.g., 50 to 100 μm) while avoiding signal loss caused by specular reflection at vertical incidence (0°). This parameter combination enables stable imaging even in high-temperature environments (e.g., 260°C), overcoming the interference of thermal radiation on the optical system.

[0020] Preferably, the judgment threshold in S4 is ≤100 μm, and at least two cycle tests are required to verify consistency.

[0021] The 100μm threshold is set based on the assembly tolerance of the AI ​​computing power card (such as a solder ball diameter of 0.6mm and a spacing of 0.8mm) to ensure that the risk of solder ball bridging is close to zero; two tests eliminate accidental errors in a single test (such as equipment fluctuations or transient thermal noise), improving the credibility and stability of the results; and deformation trends are recorded through multiple rounds of tests (such as comparison of data in the heating and cooling stages) to assist in analyzing the reliability of BGA thermal cycles.

[0022] Preferably, the temperature rising section specifically includes three stages: the first stage: room temperature to 150°C, at a rate of 0.7°C / s±0.1°C / s; the second stage: 150°C to 200°C, at a rate of 0.35°C / s±0.07°C / s; the third stage: 200°C to 260°C, at a rate of 0.5°C / s±0.07°C / s.

[0023] Quickly pass through the area below the glass transition temperature (Tg) to reduce the total test time; reduce the speed when approaching the solder melting point (such as 183°C for SnAgCu alloy) to prevent thermal stress concentration and cold solder joints; increase the speed in the stable soldering range (above 200°C) to simulate the efficiency of the real reflow soldering process; ensure rate stability through precise temperature control modules (such as PID algorithm) to avoid data drift caused by rate fluctuations.

[0024] Preferably, in said S3, the conversion relationship between the moiré fringe offset and the flatness is determined by a calibration plate, and the calculation formula is H=Δd×K, where K is a calibration coefficient.

[0025] A linear relationship between pixel offset (Δd) and true height (H) is established using a standard flat calibration plate (such as a zero-warp ceramic plate), eliminating inherent device errors (such as lens distortion). The calibration coefficient K can be dynamically adjusted based on different grating parameters (such as line density and incident angle) to accommodate the inspection needs of multiple BGA models. The formula H = Δd × K simplifies the data processing process, avoids the consumption of computing resources of complex models (such as neural networks), and is suitable for real-time online detection.

[0026] Preferably, the cooling rate in S2 is faster than the heating rate, and the maximum cooling rate is 0.8°C / s±0.1°C / s.

[0027] Rapid cooling simulates the forced cooling process after soldering, capturing transient deformation caused by thermal contraction and revealing potential assembly failures (such as solder joint cracking). It prevents brittle fracture of the substrate caused by overcooling, balancing inspection efficiency and equipment safety. Through the asymmetric design of heating and cooling rates, it accurately reproduces the actual thermal cycle load of the BGA and evaluates long-term reliability.

[0028] Preferably, the determination node in S4 is the flatness value when the temperature drops to 240-250°C.

[0029] 240-250℃ is close to the solidification temperature of solder (such as 183-217℃). At this time, the BGA deformation tends to be stable and has not yet completely cooled, and the data is most valuable for process guidance. It avoids the measurement noise (such as thermal radiation interference) that may be caused by the instantaneous high temperature of 260℃, and improves the data signal-to-noise ratio. The data at this temperature point directly reflects the final deformation of the solder joint after solidification, and predicts the probability of bridging or cold solder joints.

[0030] Preferably, the cooling method after baking in S1 is natural cooling or forced air cooling; wherein, during natural cooling, the sample is placed in the oven after baking and taken out after cooling to 50-60°C; during forced air cooling, clean air convection cooling with a wind speed of 1.5-3.0m / s is adopted, and the cooling end temperature is 50-60°C.

[0031] By limiting the post-baking cooling method (natural cooling / forced air cooling) and the end point temperature (50-60°C), the following effects can be achieved:

[0032] Stress release optimization: natural cooling avoids substrate micro-cracks caused by sudden cooling, forced air cooling improves production efficiency, and the end point temperature of 50-60℃ ensures that the substrate reaches a stable state;

[0033] Test consistency assurance: Eliminate uneven stress distribution inside the BGA caused by differences in cooling rates, and improve the repeatability of subsequent flatness test data;

[0034] Process compatibility: The wind speed range of 1.5 to 3.0 m / s is suitable for mainstream industrial air cooling equipment (such as SMT production line cooling modules) without additional modification.

[0035] The beneficial effects of the present invention compared to the prior art are:

[0036] A technological breakthrough in high-temperature dynamic testing: This technology enables the first non-contact dynamic flatness testing of large-size BGA packages in high-temperature soldering environments, overcoming the technical limitations of traditional testing methods in such high-temperature scenarios. Through the synergy of optical interferometry and multi-stage temperature control, high-precision deformation capture is achieved at temperatures close to the actual peak soldering temperature, significantly improving the consistency of test results with actual working conditions.

[0037] Defect Interception and Reliability Improvement: A quantitative determination system based on thermal deformation characteristics is established. Through multiple rounds of verification of dynamic data during the high-temperature phase, potential assembly failure risks are effectively identified. Compared to traditional single-shot normal-temperature testing solutions, this method significantly reduces the false positive rate through a cyclic testing mechanism, ensuring accurate interception of abnormal panels.

[0038] Full-process process optimization: Gradient temperature baking is used in the pretreatment stage to fully release the stress within the substrate and eliminate the interference of residual stress on the detection data; non-contact detection technology avoids physical damage to the high-density solder ball structure and ensures the integrity of the package; the node is determined to match the critical temperature range of the solder phase change, so that the detection data and the welding process form a direct feedback closed loop.

[0039] Industrial adaptability upgrade: The test process design is compatible with the rhythm requirements of mainstream production lines. The baking and cooling module and optical inspection system can be seamlessly integrated into existing packaging production lines to meet the needs of diverse production scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 This is a structural diagram of the AI ​​computing power card BGA according to one embodiment of the present invention.

[0042] Figure 2 Schematic diagram of BGA flatness monitoring and actual BGA flatness values ​​at different temperatures according to an embodiment of the present invention.

[0043] Figure 3 This is a schematic diagram showing that the BGA of an AI computing power card rises to 260 degrees and then descends. When it descends to 245 degrees, the corresponding BGA flatness tested is 47 μm.

[0044] Figure 4 This is a data chart showing the BGA flatness of an AI computing power card BGA tested at different temperatures according to one embodiment of the present invention. DETAILED DESCRIPTION

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0047] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. In the description of the embodiments of the present application, it should be understood that the orientation or position relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the application is usually placed when in use, or is the orientation or position relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0048] It should be noted that, unless there is any conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0049] The technical solution in this application will be described below with reference to the accompanying drawings.

[0050] Example 1: AI computing card BGA flatness test method

[0051] S1. Pre-test pre-processing

[0052] Place the BGA to be tested in an oven and bake it under one of the following two conditions:

[0053] 1. Bake at 125℃ for 12 hours;

[0054] 2. Bake at 140℃ for 8 hours.

[0055] S2. Temperature Cycle Test

[0056] The BGA is heated and cooled, and the specific stages and parameters are as follows:

[0057] Heating stage:

[0058] 1. Room temperature to 150°C: heating rate 0.7°C / s, tolerance ±0.1°C / s;

[0059] 2.150℃ to 200℃: heating rate 0.35℃ / s, tolerance ±0.07℃ / s;

[0060] 3.200℃ to 260℃: heating rate 0.5℃ / s, tolerance ±0.07℃ / s.

[0061] Cooling section:

[0062] 1.260℃ to 200℃: cooling rate 0.6℃ / s, tolerance ±0.08℃ / s;

[0063] 2.200℃ to 150℃: cooling rate 0.5℃ / s, tolerance ±0.07℃ / s;

[0064] 3.150℃ to room temperature: cooling rate 0.4℃ / s, tolerance ±0.07℃ / s.

[0065] S3. Optical interference detection

[0066] During the heating and cooling process, Shadow Moire optical interferometry is used to collect images of the BGA surface. The specific steps are as follows:

[0067] 1. Use a Ronchi grating with a specific angle (line density is X lines / mm) to project onto the BGA surface to generate a moiré fringe image;

[0068] 2. Calculate the flatness H = Δd × K based on the pixel offset Δd, where K is the calibration factor.

[0069] 3. Two cycles of testing are required. The second test method is the same as the first. The maximum value of the two tests is used as the basis for final judgment.

[0070] S4. Determination

[0071] Take the maximum value of BGA flatness during the test process. If the maximum value is ≤100μm, it is considered qualified.

[0072] Technical effects of this embodiment

[0073] Full-process high-temperature adaptability: Through the coordinated design of baking pretreatment and multi-stage temperature cycling, the BGA thermal load path from soldering preheating to cooling and curing is fully reproduced, ensuring that the test data truly reflects the deformation behavior of the package under actual working conditions.

[0074] Dynamic detection reliability: Continuously trigger optical acquisition during the temperature rise / fall process to capture transient thermal deformation characteristics, overcoming the limitations of traditional single-point static detection.

[0075] Non-destructive testing advantages: The non-contact measurement mechanism avoids physical interference with the high-density solder ball structure, preserving the package integrity for subsequent process steps.

[0076] Example 2: BGA flatness test under 140°C baking conditions

[0077] 1. Test Sample Preparation

[0078] Sample specifications: 10 large-size BGA package samples for AI computing power cards were selected, with a package size of 70mm×90mm, 5120 pins, a solder ball diameter of 0.6mm, a pitch of 0.8mm, and a substrate material of ABF-GX92 (Japanese Ajinomoto laminated material).

[0079] Pre-processing checks:

[0080] An optical microscope (Keyence VHX-7000) was used to inspect the integrity of the solder balls on the BGA surface, and samples with collapsed, oxidized, or missing solder balls were excluded.

[0081] The thickness of the substrate was measured using a micrometer (Mitutoyo 293-831) to ensure that the thickness tolerance was within ±0.05 mm.

[0082] 2. Baking before testing

[0083] 2.1 Equipment configuration:

[0084] Baking equipment: Yamato Scientific Industrial DN63H high-temperature circulation oven, temperature control accuracy ±1°C;

[0085] Sample placement: BGA samples are placed horizontally on a high-temperature resistant ceramic tray with a spacing of ≥20mm to avoid uneven hot air circulation.

[0086] 2.2 Baking parameters:

[0087] Temperature setting: 140℃ constant temperature;

[0088] Time setting: 8 hours;

[0089] Heating rate: 3°C / min (from room temperature to 140°C) to avoid deformation of the substrate caused by thermal shock;

[0090] Cooling method: After baking, turn off the oven heating and take out the sample after it cools naturally to 55℃ (measured value 53-57℃).

[0091] 3. Temperature cycle test

[0092] 3.1 Test equipment:

[0093] Temperature control platform: ESPEC T3-3830 heat flow meter, supporting multi-stage programmable temperature control;

[0094] Data recording: Agilent 34970A data logger, sampling interval 1 second.

[0095] 3.2 Temperature curve execution:

[0096] Warming up stage:

[0097] Room temperature to 150°C: Starting at 25°C, heat at a rate of 0.7°C / s. The actual rate fluctuation range is 0.69-0.71°C / s (tolerance ±0.1°C / s). After reaching 150°C, hold for 30 seconds to homogenize the BGA temperature.

[0098] 150°C to 200°C: rate adjusted to 0.35°C / s, actual rate 0.34-0.36°C / s (tolerance ±0.07°C / s); hold at 200°C for 60 seconds to simulate the welding preheating stage.

[0099] 200°C to 260°C: The rate is increased to 0.5°C / s, with an actual rate of 0.49-0.51°C / s (tolerance ±0.07°C / s). Upon reaching 260°C, the system immediately enters the cooling phase to simulate the peak reflow temperature.

[0100] Cooling stage:

[0101] 260℃ to 200℃: rate 0.6℃ / s, actual rate 0.59~0.61℃ / s (tolerance ±0.8℃ / s); pause for 10 seconds when cooling to 200℃, and record the BGA surface status.

[0102] 200℃ to 150℃: rate 0.5℃ / s, actual rate 0.49~0.51℃ / s (tolerance ±0.07℃ / s); 150℃ to room temperature: rate 0.4℃ / s, actual rate 0.39~0.41℃ / s (tolerance ±0.07℃ / s);

[0103] The test was terminated after cooling to below 40°C.

[0104] 4. Shadow Moire flatness test

[0105] 4.1 Optical system configuration:

[0106] Grating parameters: Ronchi grating, line density 50 lines / mm, material fused silica, thermal expansion coefficient 0.55×10 -6 / ℃;

[0107] Light source angle: 45° incident, wavelength 630nm red LED, light intensity 2000lux;

[0108] Camera: Basler acA4112 ~20μm, resolution 4096×3000, frame rate 20fps, with Telecentric lens (magnification 0.5×).

[0109] 4.2 Image acquisition process:

[0110] Benchmark calibration: Use a standard flat calibration plate (flatness ≤ 5 μm) placed at the test position to capture a non-deformed moiré fringe image and establish a conversion relationship between pixel offset Δd and true height H (H = Δd × K, K = 0.25 μm / pixel).

[0111] Dynamic testing: During the temperature-controlled platform heating and cooling process, image acquisition is triggered by the following nodes:

[0112] Temperature rising section: 150℃, 200℃, 260℃;

[0113] Cooling section: 245℃, 200℃, 150℃, 50℃;

[0114] Each time, 10 frames of images were continuously captured and the average value was taken to eliminate instantaneous thermal noise interference.

[0115] 4.3 Image processing algorithm:

[0116] Preprocessing: Grayscale normalization, mapping the image grayscale value to the range of 0 to 255; filtering denoising, using a 5×5 Gaussian filter (σ=1.2) to eliminate high-frequency noise.

[0117] Moiré fringe extraction: Use the Canny edge detection algorithm to locate the fringe centerline with an accuracy of ±1 pixel; calculate the distance between adjacent fringes and filter the effective area (eliminating data within 5mm of the edge).

[0118] Offset calculation: Compare the test image with the calibration image at pixel level and calculate the X / Y direction offset Δdx and Δdy; the total offset Δd = √(Δdx 2 +Δdy 2 ).

[0119] Flatness mapping: Generate a three-dimensional height distribution map of the BGA surface based on the formula H = Δd × K; extract the maximum height difference H_max as the judgment value.

[0120] 5. Test data and judgment

[0121] 5.1 Key node data:

[0122] Temperature (℃) Flatness H_max (μm) Acquisition time (s) 150 (temperature rise) 22 180 200 (temperature rise) 35 400 260 (peak) 58 620 245 (cooling) 47 680 200 (cooling) 38 820 150 (cooling) 29 1020 50 (cooling) 18 1350

[0123] 5.2 Result Analysis:

[0124] The maximum flatness occurs at a peak temperature of 260°C (58μm), but according to customer requirements, the judgment node is 47μm when the temperature is lowered to 245°C;

[0125] Two-cycle test data consistency verification:

[0126]

[0127] Judgment conclusion: The maximum value of the two tests is 61μm<100μm, and the sample is qualified.

[0128] Technical effects of this embodiment

[0129] Stress relief optimization: Specific baking conditions combined with natural cooling strategies effectively balance the thermal stability of substrate materials and the efficiency of internal stress relief, providing a low-noise data foundation for high-temperature testing.

[0130] Thermal shock protection: The heating rate is controlled in stages to match the thermal response characteristics of the material, achieving the optimal balance between rapid testing and structural safety.

[0131] Data traceability: Multi-temperature node data collection forms a complete thermal deformation curve, providing visual feedback for packaging process parameter optimization.

[0132] Example 3: BGA flatness test under 125°C baking conditions

[0133] 1. Test samples and pretreatment

[0134] Sample batch: 10 BGA samples from the same batch, with the same specifications as in Example 1;

[0135] Baking adjustment: baking temperature 125°C; baking time 12 hours; cooling method, after baking, open the clean air circulation system (wind speed 2.0m / s±0.2m / s), forced convection cooling to 52°C (measured value 50~54°C), simulating a fast production cycle.

[0136] 2. Temperature cycle test execution

[0137] Parameter consistency: heating / cooling rates and tolerances are exactly the same as in Example 1;

[0138] Differences: Due to changes in baking conditions, the following monitoring items are added:

[0139] Substrate moisture absorption rate test: After baking, use a trace moisture meter (Mitsubishi CA-310) to measure the substrate moisture content ≤ 0.02%;

[0140] Thermal expansion coefficient compensation: Adjust the temperature control platform displacement compensation parameters according to the substrate CTE (14ppm / ℃).

[0141] 3. Shadow Moire test optimization

[0142] Anti-interference measures: Environmental isolation, nitrogen filling in the test chamber (oxygen content <50ppm) to reduce thermal airflow disturbance; synchronous triggering, hard synchronization of the temperature control platform temperature signal and the camera acquisition signal, with an error of <1ms.

[0143] Data processing enhancement: Multi-region analysis divides the BGA surface into a 5×5 grid, calculates H_max for each region separately, and takes the global maximum value; trend fitting generates a flatness-temperature curve to evaluate the nonlinear characteristics of thermal deformation.

[0144] 4. Test data and judgment

[0145] Key node data:

[0146]

[0147] Abnormal handling: H_max exceeded the threshold (100μm) at 260℃, but because the judgment standard was only for 245℃, it was still judged as qualified; root cause analysis showed that high-temperature baking (140℃) was more effective in releasing substrate stress than low-temperature baking (125℃), resulting in slightly higher deformation of the 125℃ sample at 260℃.

[0148] Conclusion: The flatness at 245°C in the two tests were 92μm and 95μm respectively, both ≤100μm, and were judged to be qualified.

[0149] Technical effects of this embodiment

[0150] Enhanced production line compatibility: The seamless integration of the forced air cooling module and baking pretreatment significantly shortens the inspection cycle and adapts to high-speed production needs.

[0151] Environmental interference suppression: Through gas environment control and signal synchronization technology, the influence of thermal radiation and airflow disturbance on optical detection accuracy in high temperature environment is eliminated.

[0152] Fault prediction capability: Based on multi-region analysis of thermal deformation trends, potential warping concentration areas are located, and hidden defect risks such as microcracks and delamination are identified in advance.

[0153] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for testing the flatness of BGA of an AI computing power card, characterized in that: The following steps are involved: S1. Pretreatment: Bake the BGA to eliminate internal stress; S2. Temperature Cycle Test: Simulates the actual BGA soldering and working environment by heating and cooling in stages, with the maximum temperature ≥ 250°C; S3. Optical interferometry: During the temperature cycling process, the Shadow Moire method is used to acquire non-contact images of the BGA surface, and the BGA flatness is calculated based on the Moire fringe offset. S4. Judgment: Qualification is determined based on the maximum flatness value at the high temperature stage (≥200°C).

2. The AI ​​computing power card BGA flatness testing method according to claim 1, characterized in that: The baking temperature in S1 is 120-150° C., and the baking time is 6-15 hours.

3. The AI ​​computing power card BGA flatness testing method according to claim 1, characterized in that: The temperature rising section in S2 includes at least three stages, and the temperature rising rates of each stage are 0.5-1.0°C / s, 0.3-0.5°C / s, and 0.4-0.6°C / s, respectively, and the temperature difference between adjacent stages is ≥50°C.

4. The AI ​​computing card BGA flatness testing method according to claim 1, characterized in that: The ShadowMoire method in S3 uses a Ronchi grating with a line density of 40 to 60 lines / mm and a light source incident angle of 30° to 60°.

5. The AI ​​computing card BGA flatness testing method according to claim 1, characterized in that: The judgment threshold in S4 is ≤100 μm, and at least two cycle tests are required to verify consistency.

6. The AI ​​computing card BGA flatness testing method according to claim 3, characterized in that: The temperature rising section specifically includes: Stage 1: room temperature to 150°C, rate 0.7°C / s±0.1°C / s; The second stage: 150℃ to 200℃, rate 0.35℃ / s±0.07℃ / s; The third stage: 200℃ to 260℃, rate 0.5℃ / s±0.07℃ / s.

7. The AI ​​computing card BGA flatness testing method according to claim 1, characterized in that: In S3 , the conversion relationship between the moiré fringe offset and the flatness is determined by a calibration plate, and the calculation formula is H=Δd×K, where K is a calibration coefficient.

8. The AI ​​computing card BGA flatness testing method according to claim 1, characterized in that: In S2, the cooling rate is faster than the heating rate, and the maximum cooling rate is 0.8°C / s±0.1°C / s.

9. The AI ​​computing card BGA flatness testing method according to claim 1, characterized in that: The determination node in S4 is the flatness value when the temperature drops to 240-250°C.

10. The AI ​​computing card BGA flatness testing method according to claim 1, characterized in that: The cooling method after baking in S1 is natural cooling or forced air cooling; wherein, during natural cooling, the sample is placed in the oven after baking and taken out after cooling to 50-60°C; during forced air cooling, clean air convection cooling with a wind speed of 1.5-3.0m / s is adopted, and the cooling end temperature is 50-60°C.

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