Voltage generating circuit

Abstract

The invention discloses a voltage generation circuit which comprises a first control unit, a second control unit, an output tube and a clamping output unit. The first control unit generates a first voltage control signal based on a voltage signal between a first voltage and a threshold voltage; the second control unit generates a second voltage control signal based on a voltage signal between a threshold voltage and a second voltage; the output tube is turned on based on the control of the first voltage control signal, and the output tube is turned off based on the control of the second voltage control signal; the clamping output unit changes to a first target voltage based on the turn-on output of the output tube, and changes to an output voltage of a second target voltage based on the turn-off output of the output tube. According to the voltage generation circuit, the first control unit and the second control unit are used for detecting the changing voltage signal so as to dynamically control the output tube, and the output tube is matched with the clamping output unit to generate the corresponding output voltage in the changing voltage signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a voltage generating circuit. Background Art

[0002] Current chip systems, due to environmental constraints and the need to simplify topology, often integrate charge pump circuits to ensure proper system operation. However, common boost charge pumps multiply the output voltage. For example, in a 2.7V-5.5V power supply system, the charge pump output will reach 5V-10V. This high voltage not only introduces system jitter but also challenges the voltage resistance of internal components.

[0003] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0004] The object of the present invention is to provide a voltage generating circuit which can reduce the voltage of an input voltage signal without using a high-voltage tube.

[0005] To achieve the above object, a specific embodiment of the present invention provides a voltage generating circuit, including: a first control unit, a second control unit, an output tube, and a clamping output unit.

[0006] The first control unit is connected to a voltage signal that varies between a first voltage and a second voltage, wherein a threshold voltage is provided between the first voltage and the second voltage, and the first control unit generates a first voltage control signal based on the voltage signal between the first voltage and the threshold voltage; the second control unit is connected to the voltage signal, and the second control unit generates a second voltage control signal based on the voltage signal between the threshold voltage and the second voltage; the first end of the output tube is connected to the voltage signal, the control end of the output tube is connected to the first control unit to be turned on based on the control of the first voltage control signal, and the control end of the output tube is connected to the second control end unit to be turned off based on the control of the second voltage control signal; the first end of the clamped output unit is connected to the voltage signal, the second end of the clamped output unit is connected to the reference voltage, and the output end of the clamped output unit is connected to the second end of the output tube to output an output voltage that varies to a first target voltage based on the turning on of the output tube, and varies to a second target voltage based on the turning off of the output tube.

[0007] In one or more embodiments of the present invention, the first control unit includes a voltage dividing module, and the voltage dividing module is used to divide the voltage signal to obtain a first voltage control signal.

[0008] In one or more embodiments of the present invention, the second control unit includes a control tube and a clamping unit, the first end of the clamping unit is connected to the voltage signal, the second end of the clamping unit is connected to the reference voltage, the clamping unit generates a clamping voltage based on the voltage signal between the threshold voltage and the second voltage, the first end of the control tube is connected to the voltage signal, the control end of the control tube is connected to the clamping unit to receive the clamping voltage, and the second end of the control tube is connected to the control end of the output tube to output the second voltage control signal.

[0009] In one or more embodiments of the present invention, the clamping unit includes a bias resistor and a first diode, the first end of the bias resistor is connected to the voltage signal, the second end of the bias resistor is connected to the control end of the control tube and the cathode of the first diode, and the anode of the first diode is connected to the reference voltage.

[0010] In one or more embodiments of the present invention, the clamp output unit includes an output resistor and a second diode, the first end of the output resistor is connected to the voltage signal, the second end of the output resistor is connected to the second end of the output tube and the cathode of the second diode, and the anode of the second diode is connected to the reference voltage.

[0011] In one or more embodiments of the present invention, the voltage generating circuit further includes a limiting circuit, which includes a regulating unit and a control unit, wherein a first end of the regulating unit is connected to the control end of the control tube, a second end of the regulating unit is connected to a reference voltage, and the control unit is connected to the regulating unit to regulate the voltage of the control end of the control tube by controlling the regulating unit.

[0012] In one or more embodiments of the present invention, the adjustment unit includes a switch and an adjustment resistor. The switch is connected in series with the control tube and is simultaneously connected to the control end of the control tube and a reference voltage. The control unit is used to generate a control signal to control the switch to be turned on or off.

[0013] In one or more embodiments of the present invention, the control unit includes a first trigger, a second trigger and an XOR gate, wherein the first input end of the first trigger is used to receive an enable signal, the second input end of the first trigger is used to receive a clock input signal, the first input end of the second trigger is connected to the output end of the first trigger, the second input end of the second trigger is used to receive the clock input signal, the first input end of the XOR gate is used to receive the enable signal, the second input end of the XOR gate is connected to the output end of the second trigger, and the output end of the XOR gate is used to output a control signal.

[0014] In one or more embodiments of the present invention, the voltage generating circuit further includes one or more charge pumps, which are connected to the power supply voltage. The charge pumps generate a voltage signal that varies between a first voltage and a second voltage based on a set of inverted clock signals, and there is a phase difference between the clock signals received by the multiple charge pumps.

[0015] In one or more embodiments of the present invention, the charge pump includes a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor, the first end of the first transistor and the first end of the second transistor are connected to a power supply voltage, the control end of the first transistor is connected to the second end of the second transistor and the second end of the second capacitor, the control end of the second transistor is connected to the second end of the first transistor and the second end of the first capacitor, the first end of the first capacitor and the first end of the second capacitor are used to receive a set of inverted clock signals, the control end of the third transistor is connected to the second end of the fourth transistor and the second end of the first capacitor, the control end of the fourth transistor is connected to the second end of the third transistor and the second end of the second capacitor, and the first end of the third transistor and the first end of the fourth transistor are connected to output a voltage signal.

[0016] Compared with the prior art, the voltage generating circuit of the present invention detects the changing voltage signal through the first control unit and the second control unit, and generates a first voltage control signal and a second voltage control signal respectively to dynamically control the output tube. The output tube cooperates with the clamping output unit to generate a corresponding output voltage within the changing voltage signal, and effectively ensures the stability of the output voltage under the changing voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments described in the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0018] Figure 1 FIG. 4 is a circuit schematic diagram of a voltage generating circuit in an embodiment of the present invention.

[0019] Figure 2 FIG. 4 is a circuit diagram of a control unit in an embodiment of the present invention.

[0020] Figure 3 FIG. 4 is a waveform diagram of some signals in an embodiment of the present invention.

[0021] Figure 4 FIG. 4 is a waveform diagram of the output voltage and the voltage signal according to an embodiment of the present invention.

[0022] Figure 5 FIG. 4 is a waveform diagram of the current and voltage signal on the second diode according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0024] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0025] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a limiting sense.

[0026] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0027] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0028] Various components and devices may be referred to or shown in the singular herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular may include multiple such elements in accordance with the teachings herein.

[0029] The specification uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," which can each refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," etc. used with respect to the embodiments of the present disclosure are synonymous.

[0030] like Figure 1 As shown, a voltage generating circuit in an embodiment of the present invention includes: a first control unit 10, a second control unit 20, an output tube M0, a clamping output unit 30 and a limiting circuit.

[0031] The first control unit 10 is connected to a voltage signal AVDD_CP that varies between a first voltage and a second voltage. The first voltage is less than the second voltage, and there is a threshold voltage between the first voltage and the second voltage. The first control unit 10 generates a first voltage control signal based on the voltage signal AVDD_CP that is between the first voltage and the threshold voltage.

[0032] The second control unit 20 is connected to the voltage signal AVDD_CP. The second control unit 20 generates a second voltage control signal based on the voltage signal AVDD_CP between the threshold voltage and the second voltage.

[0033] The first end of the output tube M0 is connected to the voltage signal AVDD_CP, the control end of the output tube M0 is connected to the first control unit 10 to be turned on based on the control of the first voltage control signal, and the control end of the output tube M0 is connected to the second control end unit to be turned off based on the control of the second voltage control signal.

[0034] A first terminal of the clamp output unit 30 is connected to the voltage signal AVDD_CP, a second terminal of the clamp output unit 30 is connected to a reference voltage, and an output terminal of the clamp output unit 30 is connected to the second terminal of the output transistor M0 to output an output voltage Vout that changes to a first target voltage when the output transistor M0 is turned on, and changes to a second target voltage when the output transistor M0 is turned off. In one embodiment, the reference voltage is ground voltage AGND.

[0035] like Figure 1As shown, the first control unit 10 includes a voltage divider module, which is used to divide the voltage signal AVDD_CP to obtain a first voltage control signal. The voltage divider module includes a first voltage divider resistor Rp1 and a second voltage divider resistor Rp2. The first end of the first voltage divider resistor Rp1 is connected to the voltage signal AVDD_CP, the second end of the first voltage divider resistor Rp1 is connected to the first end of the second voltage divider resistor Rp2 and the control end of the output transistor M0, and the second end of the second voltage divider resistor Rp2 is connected to the reference voltage. The first voltage divider resistor Rp1 and the second voltage divider resistor Rp2 divide the voltage signal AVDD_CP to obtain the first voltage control signal.

[0036] In one embodiment, the second control unit 20 includes a control transistor MK and a clamping unit. A first end of the clamping unit is connected to the voltage signal AVDD_CP, and a second end of the clamping unit is connected to a reference voltage. The clamping unit generates a clamping voltage based on the voltage signal AVDD_CP between a threshold voltage and a second voltage. A first end of the control transistor MK is connected to the voltage signal AVDD_CP, a control end of the control transistor MK is connected to the clamping unit to receive the clamping voltage, and a second end of the control transistor MK is connected to the control end of the output transistor M0 to output a second voltage control signal.

[0037] Furthermore, the clamping unit includes a bias resistor Rb and a first diode Z1, the first end of the bias resistor Rb is connected to the voltage signal AVDD_CP, the second end of the bias resistor Rb is connected to the control end of the control tube MK and the cathode of the first diode Z1, the anode of the first diode Z1 is connected to the reference voltage, and the first diode Z1 is a Zener diode.

[0038] like Figure 1 As shown, the clamp output unit 30 includes an output resistor R0 and a second diode Z2. The first end of the output resistor R0 is connected to the voltage signal AVDD_CP, the second end of the output resistor R0 is connected to the second end of the output tube M0 and the cathode of the second diode Z2, the anode of the second diode Z2 is connected to the reference voltage, and the second diode Z2 is a Zener diode.

[0039] like Figure 1 As shown, in one embodiment, the voltage generating circuit further includes a charge pump 40 , which is connected to the power supply voltage VDD. The charge pump 40 generates a voltage signal AVDD_CP varying between a first voltage and a second voltage based on a set of inverted clock signals.

[0040] In one embodiment, two charge pumps 40 are provided. One charge pump 40 receives a set of inverted clock signals CLK1 and CLK1', and the other charge pump 40 receives a set of inverted clock signals CLK2 and CLK2'. The clock signals CLK1 and CLK1', and the clock signals CLK2 and CLK2' can both be obtained by inverters. Figure 3 As shown, there is a phase difference between clock signals CLK1 and CLK2, and between clock signals CLK1' and CLK2'. The phase difference can be 1 / 4 of a clock cycle. By providing two charge pumps 40 and delaying the clock signals of the two charge pumps 40 by a phase difference of 1 / 4 of a clock cycle, the clock cycle is split, thereby reducing the ripple on the voltage signal AVDD_CP. Clock signal CLK1 and clock input signal CLK are identical signals. Clock signal CLK1 can be directly derived from clock input signal CLK, or clock signal CLK1 and clock input signal CLK can be generated separately. In other embodiments, only one or more than two charge pumps 40 can be provided, and the phase difference of the clock signals can be other values.

[0041] Taking a single charge pump 40 as an example, the charge pump 40 includes a first capacitor C1 , a second capacitor C2 , a first transistor Q1 , a second transistor Q2 , a third transistor Q3 , and a fourth transistor Q4 .

[0042] A first end of the first transistor Q1 and a first end of the second transistor Q2 are connected to a power supply voltage VDD. A control end of the first transistor Q1 is connected to a second end of the second transistor Q2 and a second end of the second capacitor C2. A control end of the second transistor Q2 is connected to a second end of the first transistor Q1 and a second end of the first capacitor C1. A first end of the first capacitor C1 and a first end of the second capacitor C2 are configured to receive a set of inverted clock signals. A control end of the third transistor Q3 is connected to a second end of the fourth transistor Q4 and a second end of the first capacitor C1. A control end of the fourth transistor Q4 is connected to a second end of the third transistor Q3 and a second end of the second capacitor C2. A first end of the third transistor Q3 and a first end of the fourth transistor Q4 are connected to output a voltage signal AVDD_CP.

[0043] like Figure 1 and Figure 2 As shown, the limiting circuit includes a regulating unit 51 and a control unit 52. The first end of the regulating unit 51 is connected to the control end of the control tube MK, and the second end of the regulating unit 51 is connected to the reference voltage. The control unit 52 is connected to the regulating unit 51 to regulate the voltage of the control end of the control tube MK by controlling the regulating unit 51.

[0044] The regulating unit 51 includes a switch K and an regulating resistor Ra. The switch K is connected in series with the control tube MK and is also connected to the control terminal of the control tube MK and a reference voltage. The control unit 52 is used to generate a control signal VO to control the switch K to be turned on or off.

[0045] The control unit 52 includes a first flip-flop DFF1, a second flip-flop DFF2, and an exclusive-OR gate XOR. The first input terminal of the first flip-flop DFF1 is used to receive an enable signal EN, and the second input terminal of the first flip-flop DFF1 is used to receive a clock input signal CLK (as Figure 3 shown, the clock input signal CLK and the clock signal CLK1 are in-phase signals). The first input terminal of the second flip-flop DFF2 is connected to the output terminal of the first flip-flop DFF1, the second input terminal of the second flip-flop DFF2 is used to receive the clock input signal CLK, the first input terminal of the exclusive-OR gate XOR is used to receive the enable signal EN, the second input terminal of the exclusive-OR gate XOR is connected to the output terminal of the second flip-flop DFF2, and the output terminal of the exclusive-OR gate XOR is used to output a control signal VO.

[0046] In one embodiment, the power supply voltage VDD is 2.7 - 5.5V, and the voltage signal AVDD_CP output by the charge pump 40 can reach 5 - 10V (i.e., the first voltage is 5V and the second voltage is 10V). In other embodiments, the range of the power supply voltage VDD and the output range of the charge pump 40 can both be adjusted according to actual needs.

[0047] As Figure 1 shown, by using the clamping characteristic of the first diode Z1, when the voltage signal AVDD_CP output by the charge pump 40 < Vz, where Vz represents the clamping voltage of the first diode Z1, the output transistor M0 always operates as a switching transistor, providing a low on-resistance to ensure the output voltage Vout; when the voltage signal AVDD_CP > Vz, the output transistor M0 operates in the saturation region for a period of time, and the output resistance R0 serves as a current-limiting resistance to ensure that the overall power consumption is within an acceptable range. By turning on the output transistor M0 when the voltage signal AVDD_CP is low and turning off the output transistor M0 when the voltage signal AVDD_CP is high, it is possible to avoid using a high-voltage transistor as the output transistor M0, thereby reducing the manufacturing cost of the chip.

[0048] The second diode Z2 serves as an output clamping device to ensure the output voltage Vout and the driving ability of the entire circuit. The clamping characteristic of the second diode Z2 can reduce the ripple of the output voltage Vout; the output transistor M0 cooperates with the output resistance R0 as a dynamic current-limiting resistance to reduce the device area required for the second diode Z2. The specific working principle is as follows:

[0049] When the power supply voltage VDD=2.7V, the voltage signal AVDD_CP output by the charge pump 40 is approximately 5V. Based on the device electrical parameters, the clamping voltage Vz of the first diode Z1 is approximately 5.6V. At this time, the control terminal of the output transistor M0 is fully turned on due to the voltage division by the first voltage-dividing resistor Rp1 and the second voltage-dividing resistor Rp2, resulting in a small on-resistance of the output transistor M0. This results in a small voltage drop when the output current Iout is 1mA. The output voltage Vout=AVDD_CP-Iout*RdsM0, where the output current Iout is the current output by the entire circuit (at this time, due to the low voltage signal AVDD_CP, the second diode Z2 is not turned on, and the current flowing through the second diode Z2 is zero. At the same time, the output resistor R0 is large and there is almost no current, so the output current Iout is substantially equal to the current on the output transistor M0). RdsM0 is the on-resistance of the output transistor M0.

[0050] In addition, since the voltage signal AVDD_CP is low, the first diode Z1 cannot be turned on. The voltage at the control end of the control transistor MK is determined by the bias resistor Rb and the second diode Z2. The design ensures that the control transistor MK is not turned on at this time.

[0051] When the power supply voltage VDD increases, causing the first diode Z1 to turn on, the voltage at the control terminal of the control transistor MK is clamped to 5.6V. The control transistor MK turns on, providing pull-up capability for the control terminal of the output transistor M0, thereby increasing the on-resistance of the output transistor M0. As a result, the impedance seen from the second terminal of the output transistor M0 to the voltage signal AVDD_CP gradually increases and finally stabilizes at the resistance value of the output resistor R0 (it can be considered that the resistance at the second terminal of the output transistor M0 at this time is the total resistance of the on-resistance of the output transistor M0 and the output resistor R0 in parallel).

[0052] At this time, when the second diode Z2 is turned on and clamped, the output voltage VOUT=5.6V (assuming that the clamping voltage of the second diode Z2 is equal to the clamping voltage of the first diode Z1).

[0053] The current Iz2 flowing through the second diode Z2 is calculated as follows: (AVDD_CP-Vout) / R0-Iout. At this time, due to the contribution of the output resistor R0, the system's requirement on the overcurrent capability of the second diode Z2 is reduced, thereby reducing the area cost.

[0054] Further, such as Figure 4As shown, when the voltage signal AVDD_CP is 5V (i.e., the first voltage of the voltage signal AVDD_CP), the output tube M0 is in the on state, the second diode Z2 is turned off, and the output voltage Vout = 5-Iout*RdsM0 (the output current Iout is equal to the current on the output tube M0). When the voltage signal AVDD_CP rises to Vz (i.e., the threshold voltage between the first voltage and the second voltage), the output tube M0 is in a critical state from the linear region to the saturation region, the second diode Z2 is still turned off, and the output voltage Vout = Vz-Iout*RdsM0. When the voltage signal AVDD_CP rises to Vz+VthM0 or even 10V (i.e., the second voltage of the voltage signal AVDD_CP), the output tube M0 is in the off state, the second diode Z2 is turned on, the output voltage Vout is clamped by the second diode Z2, and the output voltage Vout = Vz.

[0055] like Figure 5 As shown, when the voltage signal AVDD_CP is 5V, the output tube M0 is in the on state, the second diode Z2 is off, and the current Iz2 on the second diode Z2 is 0. When the voltage signal AVDD_CP rises from 5V to Vz, the output tube M0 is in the on state. Since the voltage signal AVDD_CP is small, the current Iz2 on the second diode Z2 is still 0. When the voltage signal AVDD_CP rises from Vz to Vz+VthM0, the output tube M0 is in the critical state from the linear region to the saturation region, the second diode Z2 is turned on, and the current Iz2 on the second diode Z2 is equal to VthM0 / R0-Iout (in the critical state, the source-drain voltage of the output tube M0 is equal to its turn-on voltage VthM0). When the voltage signal AVDD_CP continues to rise from Vz+VthM0, the output tube M0 is in the off state, the second diode Z2 plays a clamping role, and the current Iz2 on the second diode Z2 is equal to (AVDD_CP-Vz) / R0-Iout.

[0056] like Figure 3 、 Figure 2 and Figure 1As shown, before the charge pump 40 is started, the enable signal EN is first pulled high. When the clock input signal CLK is not generated, the second flip-flop DFF2 initially outputs 0, the control signal VO is high, and the switch K is turned on. With the generation of the clock input signal CLK, the charge pump 40 begins to build up. At this time, the voltage signal AVDD_CP is equal to VDD-2Vdio, where 2Vdio is the sum of the turn-on voltage of the parasitic diode of the second transistor Q2 and the turn-on voltage of the parasitic diode of the third transistor Q3. Simultaneously, the control signal VO continues to maintain a high level. Under the voltage divider control of the bias resistor Rb and the adjustment resistor Ra, the control transistor MK is turned on, thereby pulling up the voltage at the control terminal of the output transistor M0 and turning off the output transistor M0. This prevents the output transistor M0 from drawing current from the charge pump 40 through the parasitic diodes of the second transistor Q2 and the third transistor Q3 during the initial build-up of the charge pump 40. This prevents the output transistor M0 from generating a large current in the crossover state between the output transistor M0 and the output resistor R0, which could affect the stability of the charge pump 40. Furthermore, there is no power loss in the branch where the control transistor MK and the second voltage divider resistor Rp2 are located.

[0057] After two cycles of the clock input signal CLK, the charge pump 40 is fully established. The second flip-flop DFF2 outputs a high level, the control signal VO transitions to a low level, the switch K opens, and the circuit begins normal operation. In one embodiment, the delay generated by the first flip-flop DFF1 and the second flip-flop DFF2 turns off the output transistor M0, thereby skipping the charge pump 40's establishment phase.

[0058] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0059] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A voltage generating circuit, characterized in that: include: a first control unit connected to a voltage signal varying between a first voltage and a second voltage, wherein a threshold voltage exists between the first voltage and the second voltage, and wherein the first control unit generates a first voltage control signal based on the voltage signal between the first voltage and the threshold voltage; a second control unit connected to the voltage signal, the second control unit generating a second voltage control signal based on the voltage signal between the threshold voltage and the second voltage; an output tube, wherein a first end of the output tube is connected to a voltage signal, a control end of the output tube is connected to a first control unit to be turned on based on the control of the first voltage control signal, and a control end of the output tube is connected to a second control end unit to be turned off based on the control of the second voltage control signal; as well as A clamp output unit, wherein a first end of the clamp output unit is connected to a voltage signal, a second end of the clamp output unit is connected to a reference voltage, and an output end of the clamp output unit is connected to the second end of the output tube to output an output voltage that changes to a first target voltage based on the output tube being turned on and changes to a second target voltage based on the output tube being turned off.

2. The voltage generating circuit according to claim 1, wherein: The first control unit includes a voltage dividing module, which is used to divide the voltage signal to obtain a first voltage control signal.

3. The voltage generating circuit according to claim 1, wherein: The second control unit includes a control tube and a clamping unit, the first end of the clamping unit is connected to the voltage signal, the second end of the clamping unit is connected to the reference voltage, the clamping unit generates a clamping voltage based on the voltage signal between the threshold voltage and the second voltage, the first end of the control tube is connected to the voltage signal, the control end of the control tube is connected to the clamping unit to receive the clamping voltage, and the second end of the control tube is connected to the control end of the output tube to output a second voltage control signal.

4. The voltage generating circuit according to claim 3, wherein: The clamping unit includes a bias resistor and a first diode, the first end of the bias resistor is connected to the voltage signal, the second end of the bias resistor is connected to the control end of the control tube and the cathode of the first diode, and the anode of the first diode is connected to the reference voltage.

5. The voltage generating circuit according to claim 1, wherein: The clamp output unit includes an output resistor and a second diode, the first end of the output resistor is connected to the voltage signal, the second end of the output resistor is connected to the second end of the output tube and the cathode of the second diode, and the anode of the second diode is connected to the reference voltage.

6. The voltage generating circuit according to claim 3, wherein: The voltage generating circuit also includes a limiting circuit, which includes a regulating unit and a control unit. The first end of the regulating unit is connected to the control end of the control tube, the second end of the regulating unit is connected to the reference voltage, and the control unit is connected to the regulating unit to regulate the voltage of the control end of the control tube by controlling the regulating unit.

7. The voltage generating circuit according to claim 6, wherein: The regulating unit includes a switch and a regulating resistor. The switch is connected in series with the control tube and is also connected to the control terminal of the control tube and a reference voltage. The control unit is used to generate a control signal to control the switch to be turned on or off.

8. The voltage generating circuit according to claim 6, wherein: The control unit includes a first trigger, a second trigger and an XOR gate, wherein the first input end of the first trigger is used to receive an enable signal, the second input end of the first trigger is used to receive a clock input signal, the first input end of the second trigger is connected to the output end of the first trigger, the second input end of the second trigger is used to receive the clock input signal, the first input end of the XOR gate is used to receive an enable signal, the second input end of the XOR gate is connected to the output end of the second trigger, and the output end of the XOR gate is used to output a control signal.

9. The voltage generating circuit according to claim 1, wherein: The voltage generating circuit also includes one or more charge pumps, which are connected to the power supply voltage. The charge pumps generate a voltage signal that varies between a first voltage and a second voltage based on a set of inverted clock signals, and there is a phase difference between the clock signals received by the multiple charge pumps.

10. The voltage generating circuit according to claim 9, wherein: The charge pump includes a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor, the first end of the first transistor and the first end of the second transistor are connected to a power supply voltage, the control end of the first transistor is connected to the second end of the second transistor and the second end of the second capacitor, the control end of the second transistor is connected to the second end of the first transistor and the second end of the first capacitor, the first end of the first capacitor and the first end of the second capacitor are used to receive a set of inverted clock signals, the control end of the third transistor is connected to the second end of the fourth transistor and the second end of the first capacitor, the control end of the fourth transistor is connected to the second end of the third transistor and the second end of the second capacitor, and the first end of the third transistor is connected to the first end of the fourth transistor to output a voltage signal.

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