Clock monitoring method, monitoring processing device, circuit, controller and carrying tool
By monitoring the clock frequency, operating voltage and clock switch signal and clearing the clock counter count value, the high false alarm rate problem of the clock monitoring circuit in dynamic scenarios is solved, and higher monitoring accuracy and adaptability are achieved.
Patent Information
- Application Number
- CN202410330064.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-21
- Publication Date
- 2025-09-23
AI Technical Summary
Existing clock monitoring circuits have a high rate of clock error and false alarms in frequency modulation, voltage regulation, and dynamic gating scenarios, resulting in low monitoring accuracy.
By monitoring the clock frequency, operating voltage and clock switching signal of the module under test, the count value of the clock counter under test is cleared when the preset conditions are met, including clock frequency changes, operating voltage changes and clock gating signal state switching, to ensure the accuracy of the clock monitoring circuit in dynamic scenarios.
It reduces the false alarm rate of clock monitoring and improves the accuracy of clock monitoring. It is suitable for dynamic frequency and voltage regulation scenarios and meets the automotive regulations of automotive chips.
Smart Images
Figure CN120686949A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of chip technology, and in particular relates to a clock monitoring method, a monitoring processing device, a circuit, a controller, and a vehicle. Background Art
[0002] When an integrated circuit chip is operating, each component requires at least one or more clocks to ensure coordinated operation. If the IC chip is affected by harsh operating environments, such as electromagnetic interference or power supply interference, and the clocks become abnormal during operation, the circuit's operation and functionality can be significantly impacted. Therefore, to improve the reliability and stability of the IC chip and ensure proper functioning, a clock monitoring circuit is required to monitor the clock source and the clocks of each component in the chip, ensuring they remain in proper working order. Furthermore, by monitoring the clock signal, the clock monitoring circuit can provide the system with feedback on clock performance, helping the system optimize its clock settings for higher performance or lower power consumption.
[0003] However, current monitoring of integrated circuit chip clock signals typically involves monitoring a fixed-frequency clock. However, in operating scenarios where frequency adjustment is required, this monitoring method can result in a high rate of false alarms, meaning that clock monitoring accuracy is low. This means the monitoring circuit may mistakenly believe a clock anomaly is occurring when it is not. Summary of the Invention
[0004] The embodiments of the present application provide a clock monitoring method, a monitoring processing device, a circuit, a controller and a carrier, which can solve the problem of high clock error false alarm rate in the current clock monitoring circuit under the working scenarios of frequency modulation, voltage regulation and dynamic gating.
[0005] In a first aspect, an embodiment of the present application provides a clock monitoring method, comprising:
[0006] monitoring at least one of a clock frequency, an operating voltage of the module under test, and a clock switch signal sent by the module under test;
[0007] When at least one of the clock frequency, the operating voltage and the clock switch signal meets a preset condition, the count value of the clock counter under test in the current monitoring cycle is cleared; the clock counter under test is used to count clock pulses of the module under test.
[0008] Therefore, when the clock monitoring method provided by the present application detects that the clock frequency or operating voltage of the module under test has changed, or the clock gating signal is turned off, that is, it is determined that the module under test is operating in the frequency modulation, voltage regulation and dynamic gating scenario, the count value of the clock counter under test in the current monitoring cycle is cleared, that is, the clock count value in the current monitoring cycle is not reported, thereby reducing the clock monitoring false alarm rate and improving the accuracy of clock monitoring.
[0009] In a possible implementation of the first aspect, the method is applied to a clock monitoring circuit, where the clock monitoring circuit includes a reference clock counter and the measured clock counter; and the preset condition includes at least one of the following conditions:
[0010] The clock frequency of the module under test changes;
[0011] The operating voltage of the module under test changes;
[0012] According to the clock switch signal, it is determined that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test and the reference clock counter do not satisfy a one-to-one correspondence relationship.
[0013] In a possible implementation of the first aspect, the method is applied to a clock monitoring circuit, where the clock monitoring circuit includes a reference clock counter and the measured clock counter; the method further includes:
[0014] When it is determined according to the clock switch signal that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test corresponds to the reference clock counter one-to-one, the count value of the clock counter under test is reported.
[0015] Therefore, the clock monitoring method provided by the present application makes the reference clock counter and the measured clock counter correspond one to one. In this case, the error tolerance range that the clock monitoring circuit can accept is larger, so the count value can be reported normally. The clock monitoring circuit can promptly obtain some minor errors that are not easy to find. Therefore, this embodiment improves the accuracy of clock monitoring, reduces the granularity of clock monitoring, and can realize fine-grained clock monitoring.
[0016] In a possible implementation of the first aspect, the method further includes:
[0017] If it is determined that the clock frequency of the module under test has changed, determining a preset counting reference interval according to the changed clock frequency of the module under test;
[0018] Obtaining a first count value output by the clock counter under test;
[0019] determining whether the first count value is outside the preset count reference interval;
[0020] If so, clock error information is generated according to the first count value and reported.
[0021] Therefore, the clock monitoring method provided in the present application continues to execute the counting of the clock counter under test after the frequency modulation is stabilized. At the same time, the clock counting comparator switches the clock counting reference information to the above-mentioned preset counting reference interval according to the clock information value, thereby realizing timely dynamic update of the clock counting reference information, achieving the purpose of clock monitoring in the dynamic frequency modulation scenario, and facilitating ensuring the accuracy of clock monitoring in the dynamic frequency modulation scenario.
[0022] In a possible implementation of the first aspect, it is applied to a clock monitoring circuit; the clock monitoring circuit is deployed in a chip system, and the various clock information nodes in the chip system form a clock network; the module under test is located at a leaf node of the clock network; the clock monitoring circuit collects a detection signal from the leaf node of the clock network, and obtains the clock frequency and operating voltage of the module under test based on the detection signal.
[0023] Therefore, the clock monitoring method provided in this application can monitor the entire clock tree, making the signal detection path more complete, meeting the automotive regulations of automotive chips such as assisted driving chips, and making the clock monitoring more accurate.
[0024] In the second aspect, an embodiment of the present application provides a monitoring and processing device, which is used to monitor the clock frequency, operating voltage and at least one of the clock switch signals sent by the module under test; when at least one of the clock frequency, the operating voltage and the clock switch signal meets the preset conditions, the count value of the clock counter under test in the current monitoring cycle is cleared; the clock counter under test is used to count the clock pulses of the module under test.
[0025] In a possible implementation manner of the second aspect, the apparatus is connected to a reference clock counter; and the preset condition includes at least one of the following conditions:
[0026] The clock frequency of the module under test changes;
[0027] The operating voltage of the module under test changes;
[0028] According to the clock switch signal, it is determined that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test and the reference clock counter do not satisfy a one-to-one correspondence relationship.
[0029] In a possible implementation of the second aspect, the device is connected to a reference clock counter; the device is also used to report the count value of the clock counter under test when it is determined that the clock gating signal of the module under test is switched from the on state to the off state according to the clock switch signal, and the clock counter under test and the reference clock counter correspond one to one.
[0030] In a third aspect, an embodiment of the present application provides an integrated circuit, comprising the monitoring processing device described in any one of the second aspects above.
[0031] In a fourth aspect, an embodiment of the present application provides a controller comprising the integrated circuit described in the third aspect above.
[0032] In a fifth aspect, an embodiment of the present application provides a vehicle, which includes the controller described in the fourth aspect above.
[0033] In a sixth aspect, an embodiment of the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the clock monitoring method described in any one of the first aspects above when executing the computer program.
[0034] In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the clock monitoring method described in any one of the above-mentioned first aspects is implemented.
[0035] It can be understood that the beneficial effects of the second to seventh aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0037] Figure 1 This is a flowchart of a clock monitoring method provided by an embodiment of the present application;
[0038] Figure 2 is a flowchart of a clock monitoring method provided by another embodiment of the present application;
[0039] Figure 3 This is a schematic diagram of the structure of an integrated circuit disclosed in one embodiment of the present application;
[0040] Figure 4 is a schematic structural diagram of an integrated circuit disclosed in another embodiment of the present application;
[0041] Figure 5 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0042] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.
[0043] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.
[0044] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
[0045] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.
[0046] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.
[0047] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.
[0048] One embodiment of the present application discloses a clock monitoring method. The clock monitoring method is applied to a clock monitoring circuit. The clock monitoring circuit is integrated into a chip, such as a SoC (System on a Chip). By way of example and not limitation, the SoC may be a chip for implementing an autonomous driving function for a vehicle. The clock monitoring circuit is connected to a module under test. The module under test is a module in the chip, such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit).
[0049] Specifically, in this embodiment, the clock monitoring circuit includes a measured clock counter, a reference clock counter, and a clock count comparator. The measured clock counter and the reference clock counter are both connected to the clock count comparator. The measured clock counter is connected to the module under test and is configured to count the clock pulse signals output by the module under test, i.e., to count the clock pulses of the module under test.
[0050] like Figure 1 As shown, the clock monitoring method provided in this embodiment includes the steps of:
[0051] S110 , monitoring at least one of a clock frequency and an operating voltage of the module under test and a clock switch signal sent by the module under test.
[0052] S120: When at least one of the clock frequency, operating voltage, and clock switch signal satisfies a preset condition, clear the count value of the clock counter under test during the current monitoring period. The clock counter under test is used to count clock pulses of the module under test. The preset condition indicates that the module under test is operating in at least one of frequency modulation, voltage modulation, and dynamic gating scenarios.
[0053] Specifically, the above-mentioned preconditions include at least one of the following conditions:
[0054] The clock frequency of the module under test changes;
[0055] The operating voltage of the module under test changes;
[0056] According to the clock switch signal, it is determined that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test and the reference clock counter do not satisfy a one-to-one correspondence relationship.
[0057] That is, as long as at least one of the above three conditions is triggered, the count value of the clock counter under test in the current monitoring period is cleared.
[0058] In this embodiment, the clock monitoring circuit receives a clock pulse signal sent by the module under test, and can monitor the clock frequency of the module under test at the current moment based on the clock pulse signal. When it is detected that the clock frequency of the module under test at the current moment is different from the clock frequency at the previous moment, it means that the clock frequency of the module under test has changed, that is, it is determined that the module under test is in a frequency adjustment working scenario, and the count value of the clock counter under test in the current monitoring cycle is cleared. In other words, the counter value in the current monitoring cycle is not reported and is deleted from the counting record. In other words, the counter count value reported by the clock counter under test to the clock monitoring circuit does not include the count value of the current monitoring cycle. Among them, the above-mentioned current monitoring cycle refers to the monitoring cycle at the current moment when the clock frequency of the module under test is detected to have changed.
[0059] This prevents the clock monitoring circuit from misjudging the current monitoring cycle as a clock error, which could result in a false alarm. This reduces the false alarm rate of the clock monitoring circuit in functional module frequency modulation scenarios and improves clock monitoring accuracy. The correct total value of the counter within each monitoring cycle is the quotient of the monitoring cycle and the clock frequency.
[0060] When it is detected that the working voltage of the module under test changes at the current moment, that is, it is detected that the working voltage of the module under test at the current moment is different from the working voltage at the previous moment, or the difference between the working voltage at the current moment and the working voltage at the previous moment exceeds the preset threshold range, it indicates that the module under test is operating in a voltage adjustment scenario, that is, dynamic voltage regulation. In this case, the counting pattern of the clock counter under test will change significantly, while the counting pattern of the count value output by the reference clock counter will not change. The count value of the clock counter under test and the count value of the reference clock counter will no longer match. At this time, the system may falsely report a clock error. Then, this embodiment clears the count value of the clock counter under test in the above-mentioned current monitoring cycle, thereby avoiding false clock errors and improving the accuracy of clock monitoring. In addition, when the working voltage of the module under test changes, its clock frequency will inevitably change, that is, it will inevitably be in a frequency modulation working scenario.
[0061] When the clock switch signal switches from a non-zero level to a zero level, the clock gating signal of the module under test is determined to be turned off, i.e., switched from an on state to an off state. Correspondingly, when the clock switch signal switches from a zero level to a non-zero level, the clock gating signal of the module under test is determined to be turned on, i.e., switched from an off state to an on state. Since the clock gating signal is suddenly turned off during the current monitoring cycle, the system may falsely report a clock error. Therefore, this embodiment avoids false clock error reports by clearing the count value of the clock counter under test during the current monitoring cycle, thereby improving clock monitoring accuracy.
[0062] The count value output by the reference clock counter serves as a reference for determining whether the count value of the clock counter under test is correct. During the judgment and comparison process, the count value output by the reference clock counter and the count value of the clock counter under test do not necessarily need to be the same. Even if they are different, they can still serve as a reference for judgment. The clock count comparator compares the count value of the clock counter under test and the count value output by the reference clock counter at the same moment to see if they match. Specifically, a reference interval is determined based on the count value output by the reference clock counter. If the count value of the clock counter under test is within the above-mentioned reference interval, it is determined that the two match. If the count value of the clock counter under test is outside the above-mentioned reference interval, it is determined that the two do not match.
[0063] If the numbers match, the clock counter under test is counting correctly. If they don't, the clock counter under test is counting incorrectly, indicating a clock error in the module under test. This incorrect clock signal can then be captured, generating clock error information that is reported to other processing modules, such as the CPU.
[0064] After the clock counting comparator determines that the clock counter under test has a clock counting error, it continues to determine whether the module under test is adjusting its clock frequency. If it is in a frequency modulation operating scenario, the counting pattern of the clock counter under test will change significantly, while the counting pattern of the count value output by the reference clock counter will not change. The count value of the clock counter under test and the count value of the reference clock counter will no longer match. In this case, the system may falsely report a clock error. In this case, the present embodiment clears the count value of the clock counter under test during the current monitoring period, thereby avoiding false clock error reports.
[0065] In a specific implementation, a reference clock counter may correspond to multiple measured clock counters, that is, a reference clock counter may provide clock counting reference information for multiple measured clock counters. Alternatively, a reference clock counter and a measured clock counter may correspond one-to-one, that is, a reference clock counter may provide clock counting reference information only for its corresponding measured clock counter.
[0066] In this embodiment, when it is detected that the clock frequency or operating voltage of the module under test changes, or the clock gating signal is turned off, that is, it is determined that the module under test operates in the frequency modulation, voltage regulation and dynamic gating scenario, the count value of the clock counter under test in the current monitoring cycle is cleared, that is, the clock count value in the current monitoring cycle is not reported, thereby reducing the clock monitoring false alarm rate and improving the accuracy of clock monitoring.
[0067] In some optional embodiments, in the above Figure 1 On the basis of the corresponding embodiment, the following steps are further included:
[0068] S130: If it is determined that the clock frequency of the module under test has changed, a preset counting reference interval is determined according to the changed clock frequency of the module under test.
[0069] S140, obtaining a first count value output by the clock counter under test.
[0070] S150: Determine whether the first count value is outside a preset count reference interval.
[0071] If yes, execute step S160: generate clock error information according to the first count value and report it.
[0072] If not, it means that the first count value is normal, that is, the clock of the module under test is normal, and no operation needs to be performed.
[0073] After determining that the module under test is operating in a frequency modulation scenario and the clock frequency adjustment is stable, this embodiment continues to execute the counting of the clock counter under test. At the same time, the clock counting comparator switches the clock counting reference information to the above-mentioned preset counting reference interval according to the clock information value, thereby realizing timely dynamic updating of the clock counting reference information, achieving the purpose of clock monitoring in the dynamic frequency modulation scenario, and facilitating ensuring the accuracy of clock monitoring in the dynamic frequency modulation scenario.
[0074] In some optional embodiments, such as Figure 2 As shown, step S120 is replaced by step S121:
[0075] When the above-mentioned clock frequency and / or operating voltage meet the preset conditions, the count value of the clock counter under test in the current monitoring cycle is cleared; and / or, when the above-mentioned clock switch signal meets the preset conditions, the count value of the clock counter under test in the current monitoring cycle is cleared, and the clock counter under test is turned off.
[0076] In this embodiment, the monitoring method further includes step S170: when it is monitored that the clock gating signal of the module under test is switched from the off state to the on state, controlling the clock counter under test to restart.
[0077] Specifically, the clock gating signal of the module under test is turned off, which means that the clock signal is in the off state. In this case, turning off the clock counter under test can avoid false triggering of clock error reporting on the one hand, and on the other hand, avoid wasting system resources due to continuous clock monitoring.
[0078] In another embodiment of the present application, another clock monitoring method is disclosed. Figure 1 On the basis of the corresponding embodiment, step S180 is further included:
[0079] When it is determined according to the clock switch signal that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test corresponds to the reference clock counter one by one, the count value of the clock counter under test is reported.
[0080] This embodiment adds corresponding reference clock counters according to the number of clocks under test, so that the reference clock counters and the clock counters under test correspond one to one. In this case, the clock monitoring circuit can tolerate a larger error range, so the count value can be reported normally. The clock monitoring circuit can promptly learn of some minor errors that are not easy to detect. Therefore, this embodiment improves the accuracy of clock monitoring, reduces the granularity of clock monitoring, and can achieve fine-grained clock monitoring.
[0081] In some optional embodiments, in the above Figure 1 On the basis of the corresponding embodiment, the clock monitoring circuit is deployed in a chip system, and the various clock information nodes in the above-mentioned chip system form a clock network. The clock source is located at the root node of the clock network. The above-mentioned module under test is arranged at the leaf node of the above-mentioned clock network. The clock monitoring circuit is connected to the leaf node of the above-mentioned clock network. The clock monitoring circuit collects and obtains a detection signal from the leaf node of the above-mentioned clock network, and obtains information such as the clock frequency and operating voltage of the module under test based on the detection signal. That is, the above-mentioned detection signal is output from the leaf node. Among them, the above-mentioned clock network is a tree structure, that is, a tree structure, for example, it can be a binary tree structure.
[0082] In this way, the clock monitoring circuit can monitor the entire clock tree, making the signal detection path more complete, meeting the automotive regulations for automotive chips such as assisted driving chips, and making clock monitoring more accurate.
[0083] Another embodiment of the present application discloses a monitoring and processing device. The monitoring and processing device is configured to monitor at least one of the clock frequency, operating voltage, and clock switch signal transmitted by a module under test, and to clear the count value of a clock counter under test within the current monitoring cycle when at least one of the clock frequency, operating voltage, and clock switch signal meets a preset condition. The clock counter under test is configured to count clock pulses of the module under test.
[0084] In this embodiment, when it is detected that the clock frequency or operating voltage of the module under test changes, or the clock gating signal is turned off, that is, it is determined that the module under test operates in the frequency modulation, voltage regulation and dynamic gating scenario, the count value of the clock counter under test in the current monitoring cycle is cleared, that is, the clock count value in the current monitoring cycle is not reported, thereby reducing the clock monitoring false alarm rate and improving the accuracy of clock monitoring.
[0085] In some optional embodiments, the monitoring processing device is connected to a reference clock counter. The preset condition includes at least one of the following conditions:
[0086] The clock frequency of the module under test changes;
[0087] The operating voltage of the module under test changes;
[0088] According to the clock switch signal, it is determined that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test and the reference clock counter do not satisfy a one-to-one correspondence relationship.
[0089] In some optional embodiments, the monitoring processing device is connected to a reference clock counter. The monitoring processing device is further configured to report a count value of the clock counter under test when it is determined, based on the clock switch signal, that the clock gating signal of the module under test has switched from an on state to an off state, and the clock counter under test corresponds to the reference clock counter.
[0090] This embodiment adds corresponding reference clock counters according to the number of clocks under test, so that the reference clock counters and the clock counters under test correspond one to one. In this case, the clock monitoring circuit can tolerate a larger error range, so the count value can be reported normally. The clock monitoring circuit can promptly detect some minor errors. Therefore, this embodiment improves the accuracy of clock monitoring, reduces the granularity of clock monitoring, and can achieve fine-grained clock monitoring.
[0091] In some optional embodiments, the monitoring and processing device is applied to a clock monitoring circuit. The clock monitoring circuit is deployed in a chip system, and the various clock information nodes in the chip system form a clock network. The clock source is located at the root node of the clock network. The module under test is located at the leaf node of the clock network. The clock monitoring circuit is connected to the leaf node of the clock network. The clock monitoring circuit collects and obtains a detection signal from the leaf node of the clock network, and obtains information such as the clock frequency and operating voltage of the module under test based on the detection signal. That is, the detection signal is output from the leaf node. The clock network is a tree structure, that is, a tree structure, for example, it can be a binary tree structure.
[0092] In this way, the clock monitoring circuit can monitor the entire clock tree, making the signal detection path more complete, meeting the automotive regulations for automotive chips such as assisted driving chips, and making clock monitoring more accurate.
[0093] Another embodiment of the present application discloses an integrated circuit. The integrated circuit can be a clock monitoring circuit. The integrated circuit is integrated in a chip. The integrated circuit is connected to a module under test. The module under test is a module in the above chip, such as a CPU module or a GPU module. Figure 3 As shown, in this embodiment, the integrated circuit includes a measured clock counter 51, a reference clock counter 52, a clock counting comparator 53, a clock information receiving module 54 and a monitoring processing device 55 disclosed in any of the above embodiments.
[0094] The measured clock counter 51 and the reference clock counter 52 are both connected to a clock count comparator 53. The measured clock counter 51 is connected to the module under test and is configured to count the clock pulse signals output by the module under test. A clock information receiving module 54 is connected to the measured clock counter 51 and the reference clock counter 52, respectively. The clock information receiving module 54 is also connected to the clock count comparator 53. A monitoring processing device 55 is connected to the clock count comparator 53.
[0095] The clock information receiving module 54 is used to obtain the current clock frequency of the module under test and sends the obtained clock frequency to the clock counter under test 51 and the reference clock counter 52 respectively.
[0096] The count value output by the reference clock counter serves as a reference for determining whether the count value of the clock counter under test is correct. During the judgment and comparison process, the count value output by the reference clock counter and the count value of the clock counter under test do not necessarily need to be the same. Even if they are different, they can still serve as a reference for judgment. The clock count comparator 53 compares the count value of the clock counter under test and the count value output by the reference clock counter at the same time to see if they match. Specifically, a reference interval is determined based on the count value output by the reference clock counter. If the count value of the clock counter under test is within the reference interval, the two are determined to match. If the count value of the clock counter under test is outside the reference interval, the two are determined to not match.
[0097] If the numbers match, the clock counter under test is counting correctly. Otherwise, the clock counter under test is counting incorrectly, indicating a clock error in the module under test. This incorrect clock signal can then be captured, generating clock error information that is reported to other processing modules, such as the CPU.
[0098] After the clock counting comparator determines that the clock counter under test has a clock counting error, the monitoring processing device 55 continues to determine whether the module under test is adjusting its clock frequency. If the module under test is in a frequency modulation operating scenario, the counting pattern of the clock counter under test will change significantly, while the counting pattern of the count value output by the reference clock counter will not change. The count value of the clock counter under test and the count value of the reference clock counter will no longer match, and the system may falsely report a clock error. In this case, the present embodiment clears the count value of the clock counter under test during the current monitoring period to avoid false clock error reports.
[0099] The clock information receiving module receives the current clock frequency information of the module under test. If, based on this clock frequency information, the module under test is determined to be operating in a frequency adjustment mode and the measured clock counter value does not match the reference clock counter value, the monitoring processing device clears the measured clock counter value for the current monitoring period. Specifically, the counter value for the current monitoring period is not reported and is deleted from the record. In other words, the counter value reported by the measured clock counter to the clock monitoring circuit does not include the count value for the current monitoring period.
[0100] This prevents the clock monitoring circuit from misjudging the current monitoring cycle as a clock error, which could result in a false alarm. This reduces the false alarm rate of the clock monitoring circuit in functional module frequency modulation scenarios and improves clock monitoring accuracy. The correct total value of the counter within each monitoring cycle is the quotient of the monitoring cycle and the clock frequency.
[0101] In a specific implementation, a reference clock counter may correspond to multiple measured clock counters, that is, a reference clock counter may provide clock counting reference information for multiple measured clock counters. Alternatively, a reference clock counter and a measured clock counter may correspond one-to-one, that is, a reference clock counter may provide clock counting reference information only for its corresponding measured clock counter.
[0102] In this embodiment, when it is detected that the clock frequency or operating voltage of the module under test changes, or the clock gating signal is turned off, that is, it is determined that the module under test operates in the frequency modulation, voltage regulation and dynamic gating scenario, the count value of the clock counter under test in the current monitoring cycle is cleared, that is, the clock count value in the current monitoring cycle is not reported, thereby reducing the clock monitoring false alarm rate and improving the accuracy of clock monitoring.
[0103] In some optional embodiments, in the above Figure 3 Based on the corresponding embodiment, the clock counting comparator is further configured to determine a preset counting reference interval based on the clock frequency after the clock pulse signal changes; obtain a first count value output by the clock counter under test; and determine whether the first count value is outside the preset counting reference interval. If so, the monitoring and processing device generates and reports clock error information based on the first count value. If not, it indicates that the first count value is normal, that is, the clock of the module under test is normal, and no further action is required.
[0104] In this embodiment, after the frequency modulation is stabilized, the counting of the clock counter under test continues to be executed. At the same time, the clock counting comparator switches the clock counting reference information to the above-mentioned preset counting reference interval according to the clock information value, thereby realizing timely dynamic update of the clock counting reference information, achieving the purpose of clock monitoring in the dynamic frequency modulation scenario, and helping to ensure the accuracy of clock monitoring in the dynamic frequency modulation scenario.
[0105] In some optional embodiments, in the above Figure 3 On the basis of the corresponding embodiment, the above-mentioned integrated circuit is deployed in a chip system, and the various clock information nodes in the above-mentioned chip system form a clock network. The clock source is located at the root node of the clock network. The above-mentioned module under test is arranged at the leaf node of the above-mentioned clock network. The integrated circuit is connected to the leaf node of the above-mentioned clock network. The integrated circuit collects and obtains the detection signal from the leaf node of the above-mentioned clock network, and obtains information such as the clock frequency and operating voltage of the module under test based on the detection signal. That is, the above-mentioned detection signal is output from the leaf node. Among them, the above-mentioned clock network is a tree structure, that is, a tree structure, for example, it can be a binary tree structure.
[0106] In this way, the integrated circuit can monitor the entire clock tree, making the signal detection path more complete, meeting the automotive regulations for automotive chips such as assisted driving chips, and making clock monitoring more accurate.
[0107] Another embodiment of the present application discloses another integrated circuit. Figure 4 As shown, the integrated circuit 60 is integrated into a chip and includes: a clock counter under test 51, a reference clock counter 52, a clock count comparator 53, a clock information receiving module 54, and a monitoring processing device 55. The chip also includes a clock source module 63, a frequency division module 64, a clock source selection and frequency division module 62, and a clock information sending module 61. The clock counter under test 51 is used to count the clock pulse signals output by the module under test.
[0108] The measured clock counter 51, the reference clock counter 52, and the clock information receiving module 54 are all connected to the clock count comparator 53. The clock count comparator 53 is connected to the monitoring processing device 55. The clock information receiving module 54 is connected to the clock information sending module 61. The measured clock counter 51 is respectively connected to the clock source selection and frequency division module 62 and the clock source module 63. The clock source selection and frequency division module 62 is also respectively connected to the clock source module 63 and the frequency division module 64.
[0109] The clock output by the module under test, or the measured clock, can be any clock. It can be a high-frequency PLL (Phase Locked Loop) output clock or a low-frequency external crystal oscillator clock. Clock counter comparator 53 determines a reference interval based on reference clock counter 52 and compares the count value of measured clock counter 51 with the reference interval. If the comparison results in a value outside the reference interval, monitoring processing unit 55 generates a related fault interrupt to the CPU system.
[0110] In this integrated circuit, there can be multiple clock source selection and frequency division modules 62, that is, they are used to receive information from multiple modules under test, namely, the clocks under test. There can be multiple measured clock counters 51, that is, they are used to receive clock information from multiple modules under test. There can be multiple clock information sending modules 61, that is, they are used to send clock information from multiple modules under test. There can be multiple clock information receiving modules 54, that is, they are used to receive clock information from multiple modules under test, where this information includes clock gating information, PLL output frequency information, clock source selection and frequency division information, and SoC external input clock frequency information. There can be multiple monitoring and processing devices 55, that is, they are used to process information from multiple modules under test.
[0111] When the system switches scenes, such as performing dynamic voltage and frequency regulation, this embodiment clears the measured clock counter value of the current monitoring period according to the clock information. After the frequency regulation stabilizes, the measured clock counting continues. At the same time, the clock counting comparator switches the reference comparison value according to the clock information value, thereby achieving the purpose of clock monitoring in the dynamic voltage and frequency regulation scenario.
[0112] If the clock under test is dynamically gated, this embodiment clears the clock under test counter value of the current monitoring cycle based on the clock information. After the gate is opened again, the clock under test counter and the clock counting comparator are controlled to restart, thereby achieving the purpose of monitoring the dynamically gated clock.
[0113] Optionally, the integrated circuit may include multiple reference clock counters, with each reference clock counter corresponding to the clock counter under test. In this case, the clock monitoring circuit can tolerate a wider range of errors, allowing it to report count values normally. The clock monitoring circuit can promptly detect minor, or less easily detected, errors. This embodiment improves the accuracy of clock monitoring, reduces the granularity of clock monitoring, and enables fine-grained clock monitoring.
[0114] The present application also provides a controller including the clock monitoring circuit disclosed in any of the above embodiments. The controller may be a domain controller on a vehicle.
[0115] The embodiment of the present application further provides a vehicle, comprising the controller disclosed in the above embodiment. The vehicle may be a vehicle.
[0116] The present application also provides an electronic device, such as Figure 5 As shown, the electronic device 70 includes: at least one processor 701, a memory 702, and a computer program 703 stored in the memory and executable on the at least one processor, and the processor implements the steps of any of the above method embodiments when executing the computer program.
[0117] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned various method embodiments can be implemented.
[0118] An embodiment of the present application provides a computer program product. When the computer program product is run on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned various method embodiments when executing the computer program product.
[0119] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, which can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / electronic device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. For example, USB flash drive, mobile hard disk, magnetic disk or optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.
[0120] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.
[0121] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0122] In the embodiments provided in this application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0123] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.
[0124] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.
Claims
1. A clock monitoring method, characterized in that: include: monitoring at least one of a clock frequency, an operating voltage of a module under test, and a clock switch signal sent by the module under test; When at least one of the clock frequency, the operating voltage and the clock switch signal meets a preset condition, clearing the count value of the clock counter under test in the current monitoring cycle; The clock counter under test is used to count clock pulses of the module under test.
2. The clock monitoring method according to claim 1, wherein: The method is applied to a clock monitoring circuit, wherein the clock monitoring circuit includes a reference clock counter and the clock counter under test; the preset condition includes at least one of the following conditions: The clock frequency of the module under test changes; The operating voltage of the module under test changes; According to the clock switch signal, it is determined that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test and the reference clock counter do not satisfy a one-to-one correspondence relationship.
3. The clock monitoring method according to claim 1, wherein: The method is applied to a clock monitoring circuit, wherein the clock monitoring circuit includes a reference clock counter and the clock counter under test; the method further includes: When it is determined according to the clock switch signal that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test corresponds to the reference clock counter one-to-one, the count value of the clock counter under test is reported.
4. The clock monitoring method according to claim 1, wherein: The method further comprises: If it is determined that the clock frequency of the module under test has changed, determining a preset counting reference interval according to the changed clock frequency of the module under test; Obtaining a first count value output by the clock counter under test; determining whether the first count value is outside the preset count reference interval; If so, clock error information is generated according to the first count value and reported.
5. The clock monitoring method according to any one of claims 1 to 4, wherein: Applied to a clock monitoring circuit; the clock monitoring circuit is deployed in a chip system, and the various clock information nodes in the chip system form a clock network; the module under test is located at a leaf node of the clock network; the clock monitoring circuit collects a detection signal from the leaf node of the clock network, and obtains the clock frequency and operating voltage of the module under test based on the detection signal.
6. A monitoring processing device, characterized in that: The device is used to monitor at least one of a clock frequency, an operating voltage, and a clock switch signal sent by a module under test; when at least one of the clock frequency, the operating voltage, and the clock switch signal meets a preset condition, clear the count value of the clock counter under test in the current monitoring cycle; The clock counter under test is used to count clock pulses of the module under test.
7. The monitoring processing device according to claim 6, wherein: The device is connected to a reference clock counter; the preset condition includes at least one of the following conditions: The clock frequency of the module under test changes; The operating voltage of the module under test changes; According to the clock switch signal, it is determined that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test and the reference clock counter do not satisfy a one-to-one correspondence relationship.
8. The monitoring processing device according to claim 6, wherein: The device is connected to a reference clock counter; the device is also used to report the count value of the clock counter under test when it is determined according to the clock switch signal that the clock gating signal of the module under test is switched from the on state to the off state, and the clock counter under test and the reference clock counter correspond one to one.
9. An integrated circuit, characterized in that: The method comprises the monitoring and processing device as described in any one of claims 6 to 8.
10. A controller, characterized in that: comprising the integrated circuit of claim 9.
11. A vehicle, characterized in that: Comprising the controller of claim 10.