Chip temperature control method and device, storage medium and program product

Abstract

The invention relates to a chip temperature control method and device, a storage medium and a program product. The method comprises the following steps: monitoring a power consumption value of any local module in a chip; comparing the power consumption value of the local module with a first power consumption threshold value corresponding to the local module; and reducing the utilization rate of the local module in response to the fact that the power consumption value of the local module exceeds the first power consumption threshold value corresponding to the local module. According to the invention, through real-time monitoring and dynamic adjustment of the power consumption of the local module, accurate and efficient control of the chip temperature is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a chip temperature control method, a chip temperature control device, a non-volatile computer-readable storage medium, and a computer program product. Background Art

[0002] Temperature control is a crucial technical issue in chip design and electronic devices. With increasing chip integration and power consumption, localized overheating is becoming increasingly common. This not only affects chip performance and stability but can also trigger overheat protection mechanisms (such as thermal shutdown), causing unexpected device shutdown or damage. Therefore, efficiently and quickly controlling chip temperature has become a pressing technical challenge in this field. Summary of the Invention

[0003] In view of this, the present disclosure provides a chip temperature control technology solution.

[0004] According to one aspect of the present disclosure, a chip temperature control method is provided, comprising:

[0005] For any local module in the chip, monitoring the power consumption value of the local module;

[0006] comparing the power consumption value of the local module with a first power consumption threshold corresponding to the local module;

[0007] In response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, the utilization rate of the local module is reduced.

[0008] In a possible implementation, in response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, reducing the utilization rate of the local module includes:

[0009] In response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, the utilization rate of the local module is reduced until the power consumption value of the local module is lower than a second power consumption threshold corresponding to the local module, wherein the second power consumption threshold is less than the first power consumption threshold.

[0010] In a possible implementation, reducing the utilization rate of the local module includes:

[0011] Inserting a no-operation instruction into the instruction pipeline of the local module.

[0012] In a possible implementation, inserting a no-operation instruction into the instruction pipeline of the local module includes:

[0013] Determine the insertion density of no-op instructions;

[0014] According to the insertion density, no-operation instructions are inserted into the instruction pipeline of the local module.

[0015] In a possible implementation, determining the insertion density of the no-operation instructions includes:

[0016] Determine the insertion density of the no-operation instructions in the first cooling cycle according to the preset insertion density;

[0017] For the Nth cooling cycle, the insertion density of the no-operation instructions of the Nth cooling cycle is determined according to the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

[0018] In a possible implementation, reducing the utilization rate of the local module includes:

[0019] The local module is controlled to idle.

[0020] In a possible implementation, controlling the local module to idle includes:

[0021] Determine the proportion of idle cycles;

[0022] The local module is controlled to idle at the idle cycle ratio.

[0023] In a possible implementation, determining the idle cycle ratio includes:

[0024] According to the preset idle cycle ratio, determine the idle cycle ratio of the first cooling cycle;

[0025] For the Nth cooling cycle, the idle period ratio of the Nth cooling cycle is determined according to the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

[0026] In a possible implementation, monitoring the power consumption value of the local module includes:

[0027] The power consumption value of the local module is monitored by a hardware counter corresponding to the local module.

[0028] In a possible implementation, monitoring the power consumption value of the local module by using a hardware counter corresponding to the local module includes:

[0029] Within a preset time window, recording the number of current signal pulses of the local module by a hardware counter corresponding to the local module, wherein the number of current signal pulses of the local module represents the number of times the current signal strength of the local module exceeds a preset current strength;

[0030] The power consumption value of the local module is determined according to the number of current signal pulses of the local module.

[0031] In a possible implementation, the local module includes a microprocessor-level module.

[0032] According to another aspect of the present disclosure, a chip temperature control device is provided, comprising:

[0033] A monitoring module, configured to monitor the power consumption of any local module in the chip;

[0034] a comparing module, configured to compare the power consumption value of the local module with a first power consumption threshold corresponding to the local module;

[0035] The reducing module is configured to reduce the utilization rate of the local module in response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module.

[0036] In a possible implementation, the reducing module is configured to:

[0037] In response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, the utilization rate of the local module is reduced until the power consumption value of the local module is lower than a second power consumption threshold corresponding to the local module, wherein the second power consumption threshold is less than the first power consumption threshold.

[0038] In a possible implementation, the reducing module is configured to:

[0039] Inserting a no-operation instruction into the instruction pipeline of the local module.

[0040] In a possible implementation, the reducing module is configured to:

[0041] Determine the insertion density of no-op instructions;

[0042] According to the insertion density, no-operation instructions are inserted into the instruction pipeline of the local module.

[0043] In a possible implementation, the reducing module is configured to:

[0044] Determine the insertion density of the no-operation instructions in the first cooling cycle according to the preset insertion density;

[0045] For the Nth cooling cycle, the insertion density of the no-operation instructions of the Nth cooling cycle is determined according to the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

[0046] In a possible implementation, the reducing module is configured to:

[0047] The local module is controlled to idle.

[0048] In a possible implementation, the reducing module is configured to:

[0049] Determine the proportion of idle cycles;

[0050] The local module is controlled to idle at the idle cycle ratio.

[0051] In a possible implementation, the reducing module is configured to:

[0052] According to the preset idle cycle ratio, determine the idle cycle ratio of the first cooling cycle;

[0053] For the Nth cooling cycle, the idle period ratio of the Nth cooling cycle is determined according to the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

[0054] In a possible implementation, the monitoring module is configured to:

[0055] The power consumption value of the local module is monitored by a hardware counter corresponding to the local module.

[0056] In a possible implementation, the monitoring module is configured to:

[0057] Within a preset time window, recording the number of current signal pulses of the local module by a hardware counter corresponding to the local module, wherein the number of current signal pulses of the local module represents the number of times the current signal strength of the local module exceeds a preset current strength;

[0058] The power consumption value of the local module is determined according to the number of current signal pulses of the local module.

[0059] In a possible implementation, the local module includes a microprocessor-level module.

[0060] According to another aspect of the present disclosure, a chip temperature control device is provided, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0061] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0062] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program implements the steps of the above method when executed by a processor.

[0063] In an embodiment of the present disclosure, by monitoring the power consumption value of any local module in the chip, comparing the power consumption value of the local module with the first power consumption threshold corresponding to the local module, and in response to the power consumption value of the local module exceeding the first power consumption threshold corresponding to the local module, reducing the utilization rate of the local module, thereby achieving accurate and efficient control of the chip temperature by real-time monitoring and dynamic adjustment of the power consumption of the local module. The embodiment of the present disclosure utilizes the strong correlation between power consumption value and temperature, and by directly obtaining the power consumption data of the local module, avoids the delay and hardware complexity brought by traditional temperature sensors, and significantly improves the response speed and control accuracy. Due to the use of module-level fine-grained control, only the overheated local module is subject to power consumption control, and other modules can still maintain high-performance operation, thereby effectively suppressing the temperature rise while minimizing performance loss. This indirect temperature control method based on power consumption is not only applicable to various types of high-performance computing chips, but can also seamlessly cooperate with traditional global temperature control methods (such as PID control or global frequency reduction), providing a more flexible and reliable solution for chip thermal management.

[0064] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0066] Figure 1 A flow chart of a chip temperature control method provided by an embodiment of the present disclosure is shown.

[0067] Figure 2 A schematic diagram showing the dynamic control process of the chip temperature control method provided by an embodiment of the present disclosure.

[0068] Figure 3 A block diagram of a chip temperature control device provided by an embodiment of the present disclosure is shown.

[0069] Figure 4 is a block diagram showing a chip temperature control device 1900 according to an exemplary embodiment. DETAILED DESCRIPTION

[0070] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0071] As used herein, the terms "comprises," "comprising," "having," or variations thereof are open ended and include one or more stated features, integers, elements, steps, parts, or functions, but do not preclude the presence or addition of one or more other features, integers, elements, steps, parts, functions, or groups thereof.

[0072] When an element is referred to as being "connected," "coupled," "responsive" or variations thereof to another element, it can be directly connected, coupled or responsive to the other element or intervening elements may be present.

[0073] Although the terms first, second, third, etc. may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another element / operation. Therefore, without departing from the teachings of the present invention, the first element / operation in some embodiments may be referred to as the second element / operation in other embodiments.

[0074] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0075] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0076] In related technologies, common chip temperature control methods mainly include the following:

[0077] 1. Direct temperature control using temperature sensors: This approach uses temperature sensors to monitor chip temperature in real time. When the temperature exceeds a preset threshold, it triggers frequency or power reduction. However, this approach relies on the accuracy and response speed of the temperature sensor, and the deployment of the sensor can increase hardware complexity and cost.

[0078] 2. Traditional PID (Proportional-Integral-Derivative) control method: This method uses analog calculations and iterative adjustments to control temperature. While this method is effective in some scenarios, its response speed is slow and cannot meet the needs of rapid temperature control under high dynamic loads.

[0079] 3. Global power consumption control: This method indirectly controls temperature by adjusting the power consumption of the entire chip. The disadvantage of this method is that it lacks local targeting, which may lead to excessive performance loss or unsatisfactory temperature control.

[0080] In summary, the chip temperature control solutions in related technologies mainly have the following problems: slow response speed, which cannot meet the needs of high dynamic load scenarios; reliance on temperature sensors, which increases hardware complexity and cost; and the lack of flexibility in the global control method, making it difficult to achieve local precise temperature control.

[0081] In order to solve technical problems similar to those described above, an embodiment of the present disclosure provides a chip temperature control method, which monitors the power consumption value of any local module in the chip, compares the power consumption value of the local module with the first power consumption threshold corresponding to the local module, and reduces the utilization rate of the local module in response to the power consumption value of the local module exceeding the first power consumption threshold corresponding to the local module, thereby achieving accurate and efficient control of the chip temperature by real-time monitoring and dynamic adjustment of the power consumption of the local module. The embodiment of the present disclosure utilizes the strong correlation between power consumption value and temperature, and directly obtains the power consumption data of the local module, thereby avoiding the delay and hardware complexity brought by traditional temperature sensors, and significantly improving the response speed and control accuracy. Due to the use of module-level fine-grained control, only the overheated local module is subject to power consumption control, and other modules can still maintain high-performance operation, thereby effectively suppressing temperature rise while minimizing performance loss. This power-based indirect temperature control method is not only applicable to various types of high-performance computing chips, but can also seamlessly cooperate with traditional global temperature control methods (such as PID control or global frequency reduction), providing a more flexible and reliable solution for chip thermal management.

[0082] The chip temperature control method provided by the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0083] Figure 1A flow chart of a chip temperature control method provided by an embodiment of the present disclosure is shown. In one possible implementation, the execution subject of the chip temperature control method may be a chip temperature control device. For example, the chip temperature control method may be executed by a terminal device or a server or other electronic device. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device, etc. In some possible implementations, the chip temperature control method may be implemented by a processor calling computer-readable instructions stored in a memory. As Figure 1 As shown, the chip temperature control method includes steps S11 to S13.

[0084] In step S11 , for any local module in the chip, the power consumption value of the local module is monitored.

[0085] In step S12, the power consumption value of the local module is compared with a first power consumption threshold corresponding to the local module.

[0086] In step S13 , in response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, the utilization rate of the local module is reduced.

[0087] The chip in the embodiment of the present disclosure may be various types of chips, such as various types of high-performance computing chips. For example, the chip in the embodiment of the present disclosure may be a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence acceleration chip (such as a neural network processor (NPU)), a system on chip (SoC) or an application-specific integrated circuit (ASIC), etc. These chips usually contain a plurality of independently controllable local modules (such as processor cores, computing units, memory controllers, etc.), and are prone to local overheating problems due to high integration. The chip temperature control method provided by the embodiment of the present disclosure dynamically regulates the power consumption of local modules, which can not only accurately suppress temperature rise, but also avoid the performance loss of traditional global temperature control methods, and is particularly suitable for chip scenarios that require high computing power and are sensitive to temperature.

[0088] In the disclosed embodiments, a local module may refer to a subunit or component with independent functionality within a chip, such as a microprocessor (MP), GPU core, DDR (Double Data Rate) controller, or PCIe (Peripheral Component Interconnect Express) module. These local modules generate independent power consumption and heat during operation. By monitoring and controlling their power consumption, their utilization can be dynamically adjusted, thereby indirectly limiting local temperature increases and preventing overheating of the entire chip.

[0089] In one possible implementation, the local module includes a microprocessor-level module. A microprocessor-level module may refer to the smallest independently working computing unit in a chip. For example, a microprocessor-level module may include a single core in a CPU / GPU / NPU (such as a CUDA core in a GPU), a dedicated computing unit (such as a Tensor Core in an AI accelerator), a processing unit in a microcontroller (MCU), and so on.

[0090] Modern chips (such as mobile phone SoCs) use multi-core heterogeneous designs, and the loads on different cores vary significantly. Traditional global temperature control (such as overall frequency reduction) results in performance loss, while microprocessor-level control is more suitable for dynamic load balancing.

[0091] In another possible implementation, multiple microprocessor-level modules may be treated as one local module.

[0092] In the disclosed embodiment, chip temperature control can adopt two monitoring strategies based on actual needs: one is to perform real-time, comprehensive power consumption monitoring of all local modules in the chip to ensure that the operating status of each local module can be accurately controlled; the other is to selectively monitor the power consumption values ​​of key local modules (such as high-frequency computing units or modules known to be prone to overheating) based on historical data or chip architecture characteristics. This targeted monitoring can reduce system overhead while ensuring temperature control. Both strategies can dynamically identify power consumption anomalies and achieve rapid temperature control by adjusting the utilization of local modules. The former is suitable for high-performance scenarios that are sensitive to temperature, while the latter focuses more on resource efficiency. Users can flexibly choose based on chip type and application requirements.

[0093] In a possible implementation, monitoring the power consumption value of the local module includes: monitoring the power consumption value of the local module through a hardware counter corresponding to the local module.

[0094] In this implementation, dedicated hardware counter circuits are integrated within each local module, allowing real-time capture of current fluctuations. The count values ​​obtained by the hardware counters can be converted into quantifiable power consumption values. This implementation overcomes the physical limitations of traditional temperature sensors, enabling predictive temperature trends without waiting for heat conduction, thus enabling preventive temperature control.

[0095] As an example of this implementation method, the power consumption value of the local module is monitored by the hardware counter corresponding to the local module, including: within a preset time window, the number of current signal pulses of the local module is recorded by the hardware counter corresponding to the local module, wherein the number of current signal pulses of the local module represents the number of times the current signal strength of the local module exceeds the preset current strength; and the power consumption value of the local module is determined based on the number of current signal pulses of the local module.

[0096] In this example, within each preset time window (e.g., 1 microsecond), the hardware counter can accurately count the number of pulses in which the current signal strength in the local module power supply line exceeds the preset current strength. These pulses directly reflect the instantaneous current fluctuations caused by the transistor switching activity. This example utilizes the characteristics of digital circuits—the greater the current strength, the more pulses that exceed the threshold (preset current strength) per unit time, and the two are positively correlated. Through a pre-established pulse number-power consumption correspondence model (e.g., stored in a lookup table on the chip), the pulse number can be converted into a corresponding power consumption value. For example, when a CPU core suddenly enters a computationally intensive task, its current pulse number may surge from the normal 1,000 times / microsecond to 5,000 times / microsecond. The system can immediately recognize this anomaly and trigger cooling measures.

[0097] This example converts complex analog signal monitoring into simple digital pulse counting, ensuring monitoring accuracy while significantly reducing implementation complexity.

[0098] In one example, the value of the preset current intensity can be dynamically adjusted according to the characteristics of different local modules, so that the same monitoring architecture can adapt to the monitoring requirements of various functional modules in the chip.

[0099] In the embodiment of the present disclosure, for any local module, the power consumption value of the local module obtained by real-time monitoring can be compared with the first power consumption threshold corresponding to the local module. In the embodiment of the present disclosure, the first power consumption thresholds corresponding to different local modules can be different or the same.

[0100] In one possible implementation, hardware counters can be used to monitor the power consumption fluctuations of local modules under actual workloads over a long period of time. After collecting a large amount of operating data, a statistical method can be used to determine the first power consumption threshold. For example, a GPU shader core can be stress-tested for 72 hours, its power consumption profile recorded, and the first power consumption threshold set at 90% to 95% of the historical peak power consumption. This approach covers the vast majority of operating conditions while providing a safety margin for sudden loads. This data-driven approach accurately reflects the actual operating characteristics of local modules, and the threshold setting is highly aligned with the microarchitectural characteristics of the specific module.

[0101] In another possible implementation, an oscilloscope can be used to directly measure the current / voltage waveform of the local module power supply circuit. By capturing the instantaneous power consumption peak under extreme workloads (such as the matrix multiplication burst cycle during AI inference), the first power consumption threshold can be set to a level slightly lower than the measured maximum value. For example, if an NPU module observes an instantaneous power consumption spike of 12.8W during ResNet50 inference, the first power consumption threshold can be set to 12W to ensure that even if there are instantaneous fluctuations, the current limit will not be falsely triggered.

[0102] In another possible implementation, a gradual stress test can be performed to gradually increase the load on a local module until the chip's overheat protection (such as shutdown) is triggered. The critical power consumption value for stable operation before the trigger is recorded, and the first power consumption threshold is set to 80% to 85% of this value. For example, if the read and write bandwidth of a DDR controller is continuously increased and the system shutdown is triggered at 9.5W, the first power consumption threshold can be set to 8W.

[0103] The above three solutions can be used individually or in combination, taking into account both accuracy and safety.

[0104] In one possible implementation, in response to the power consumption value of the local module exceeding the first power consumption threshold corresponding to the local module, reducing the utilization of the local module includes: in response to the power consumption value of the local module exceeding the first power consumption threshold corresponding to the local module, reducing the utilization of the local module until the power consumption value of the local module is lower than the second power consumption threshold corresponding to the local module, wherein the second power consumption threshold is lower than the first power consumption threshold.

[0105] This implementation uses a dual-threshold control strategy for power management. When a hardware counter detects that a local module's real-time power consumption exceeds a preset first power threshold, cooling measures are immediately initiated. The system monitors power consumption changes in the local module in real time and stops adjusting the system only when the module's power consumption falls below a lower second power threshold, thus creating a stable buffer zone on the power consumption curve.

[0106] In this implementation, the first power consumption threshold serves as a trigger defense line, and its set value can be close to but not exceed the thermal design power (TDP) of the chip to ensure early intervention before the temperature gets out of control. The lower second power consumption threshold creates a safety margin to avoid frequent oscillations of the system near the critical point. For example, the first power consumption threshold of an AI (Artificial Intelligence) acceleration module can be set to 15W, and the second power consumption threshold can be set to 12W. When the power consumption is detected to reach 15W, the utilization rate of the AI ​​acceleration module can be gradually reduced until the power consumption stabilizes below 12W.

[0107] In the embodiment of the present disclosure, when the real-time power consumption value of a local module is monitored to exceed its first power consumption threshold, the dynamic adjustment mechanism can be immediately activated to achieve power consumption control by reducing the utilization rate of the local module. This adjustment is a closed-loop process. The system can continuously monitor the power consumption changes of the local module and dynamically adjust the control intensity until the power consumption value of the local module falls back to a safe range. This precise regulation based on real-time power consumption feedback can effectively prevent local overheating while ensuring the overall performance of the chip, while avoiding the unnecessary performance loss caused by the traditional global frequency reduction solution.

[0108] In a possible implementation, reducing the utilization rate of the local module includes: inserting a no-operation instruction into the instruction pipeline of the local module.

[0109] In this implementation, no-operation (NOP) instructions with no actual computational function can be injected into the instruction pipeline to reduce instruction-level parallelism, thereby reducing the number of transistor state flips per unit time. This method of introducing bubbles directly reduces the rate of dynamic power generation by reducing the throughput of valid computational instructions without changing the operating state of the hardware circuit. From a system-level perspective, this implementation enables software-controllable adjustment of computing resource utilization, enabling power consumption control with fine-grained instruction cycle-level control capabilities while maintaining transparency of the hardware architecture—that is, power consumption management can be achieved solely through instruction scheduling without modifying the microarchitecture design. This implementation reverse-engineers the traditional instruction scheduling mechanism for performance optimization and applies it to the field of power consumption control, achieving temperature control targets by negatively adjusting instruction density.

[0110] As an example of this implementation, inserting no-operation instructions into the instruction pipeline of the local module includes: determining an insertion density of no-operation instructions; and inserting no-operation instructions into the instruction pipeline of the local module according to the insertion density.

[0111] In this example, the density of no-op instructions determines the mix of no-op instructions and valid instructions in the instruction pipeline, which directly affects the computational throughput and power consumption of local modules. The system can use different density determination methods based on preset policies or real-time requirements. For example, it can support static configuration with fixed values ​​or allow dynamic adjustment based on operating status.

[0112] In one example, a corresponding model of insertion density and power consumption can be established by analyzing the microarchitecture characteristics and thermal design goals of the local module. Based on this model, the initial insertion density of no-operation instructions can be determined. The initial insertion density of no-operation instructions can be a fixed ratio (such as inserting one no-operation instruction for every 10 valid instructions), or a dynamic strategy can be adopted (such as calculating the optimal density in real time based on the current load conditions). The instruction scheduling unit can insert no-operation instructions at appropriate positions in the instruction pipeline according to the determined insertion density, forming a regular instruction stream throttling effect.

[0113] Fixed density mode is simple and reliable, suitable for scenarios requiring high stability. Dynamic density adjustment, on the other hand, better adapts to changing workloads and enables more refined power consumption control. Either approach reduces dynamic power consumption by adjusting the distribution of active computing instructions and precisely controlling transistor switching. This approach ensures the integrity of computing functionality while providing instruction-level control for chip thermal management.

[0114] In one example, determining the insertion density of the no-operation instructions includes: determining the insertion density of the no-operation instructions for the first cooling cycle based on a preset insertion density; for the Nth cooling cycle, determining the insertion density of the no-operation instructions for the Nth cooling cycle based on the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

[0115] In this example, a periodic control strategy can be adopted to divide the cooling process into continuous cooling cycles. The insertion density of no-operation instructions in each cooling cycle can be adjusted according to the historical control effect to form a closed-loop control system.

[0116] In the initial stage (the first cooling cycle), a preset insertion density can be used. The preset insertion density can be calculated based on the nominal power consumption characteristics and safety thresholds of the local modules. Starting from the second cooling cycle, the control effect of the previous cooling cycle (the N-1 cooling cycle) can be analyzed. For example, key indicators such as the deviation between the actual power consumption reduction and the expected target and the power consumption change trend can be included. Based on this feedback data, the optimal insertion density can be recalculated through a specific control algorithm (such as PID control or fuzzy logic) to achieve dynamic optimization of the control parameters.

[0117] In this example, historical data feedback can help avoid performance loss caused by over-regulation or temperature control failure caused by under-regulation. Secondly, a periodic iteration approach allows the system to gradually approach the optimal operating point, achieving the best balance between power consumption control and computing performance. Furthermore, this adaptive nature enables the solution to intelligently respond to varying workloads and operating environments.

[0118] As another example of this implementation, inserting no-operation instructions into the instruction pipeline of the local module includes: determining the number of no-operation instructions to be inserted; and inserting no-operation instructions into the instruction pipeline of the local module according to the number of insertions.

[0119] In another possible implementation, reducing the utilization rate of the local module includes: controlling the local module to idle.

[0120] This implementation manages the power consumption of local modules through hardware-level operational state control. Specifically, by temporarily suspending the computational activity of a local module, placing it in an inactive state (i.e., idling), the dynamic power consumption of that module can be directly reduced. This control does not rely on instruction stream modification, but rather can be achieved at the hardware level through clock management or power management units to switch operational states.

[0121] Idle control can be achieved through a variety of low-level mechanisms, including but not limited to clock gating (temporarily blocking the clock signal to freeze the circuit state), power gating (cutting off power to non-critical circuits), or local module disabling (disabling specific local modules). These methods can quickly reduce the power consumption level of the module while maintaining its functional integrity.

[0122] This implementation allows hardware to directly intervene in the running state, avoiding delays caused by software scheduling. Furthermore, this control method is decoupled from specific computing tasks, making it suitable for unified management of various functional modules.

[0123] As an example of this implementation, controlling the local module to idle includes: determining an idling cycle ratio; and controlling the local module to idle with the idling cycle ratio.

[0124] In this example, the local module's operating cycle can be divided into working and idle periods, and the idle period ratio can be precisely controlled using the idle period ratio parameter. The idle period ratio reflects the effective utilization of the local module per unit time. For example, if the idle period ratio is set to 30%, the local module will be forced to idle for 300 microseconds per millisecond.

[0125] In one example, a 32-bit register can be used to precisely control the idle cycle ratio of a local module. The register value can be inversely proportional to the idle cycle ratio, with a zero register value indicating a complete idle cycle, and a maximum value indicating continuous operation.

[0126] In one example, determining the idle cycle ratio includes: determining the idle cycle ratio of the first cooling cycle based on a preset idle cycle ratio; for the Nth cooling cycle, determining the idle cycle ratio of the Nth cooling cycle based on the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

[0127] This example proposes an adaptive idling control strategy based on feedback regulation, achieving dynamic power consumption management through iterative optimization. In this example, the temperature control process can be divided into continuous cooling cycles. The idling period ratio of each cooling cycle can be adjusted based on historical control results, forming a closed-loop control system.

[0128] In the initial stage (the first cooling cycle), the preset idle cycle ratio can be used as the control benchmark. Among them, the preset idle cycle ratio can be calculated based on the thermal design parameters and nominal power consumption characteristics of the local module. Starting from the second cooling cycle, the actual control effect of the previous cooling cycle (the N-1 cooling cycle) can be analyzed. For example, key indicators such as the deviation between the actual power consumption reduction and the expected target, and the power consumption change trend can be included. Based on these feedback data, the idle cycle ratio can be re-determined to achieve dynamic optimization of the idle cycle ratio.

[0129] In this example, historical data feedback can help avoid performance loss caused by over-regulation or temperature control failure caused by under-regulation. Secondly, a periodic iteration approach allows the system to gradually approach the optimal operating point, achieving the best balance between power consumption control and computing performance. Furthermore, this adaptive nature enables the solution to intelligently respond to varying workloads and operating environments.

[0130] As another example of this implementation, controlling the local module to idle includes: determining an idling duration; and controlling the local module to idle within the idling duration.

[0131] The chip temperature control method provided by the embodiments of the present disclosure can be applied to technical fields such as temperature regulation and power consumption control, and is not limited here.

[0132] The chip temperature control method provided by the embodiment of the present disclosure is described below through a specific application scenario.

[0133] Figure 2A schematic diagram showing the dynamic control process of the chip temperature control method provided by the embodiment of the present disclosure. Figure 2 As shown, the process begins with the chip power-on initialization phase. The system can first perform local module damage detection to ensure that all local modules are functioning properly. Subsequently, the pre-stored power consumption thresholds (the first power consumption threshold and the second power consumption threshold corresponding to each local module) can be loaded.

[0134] When the hardware counter detects that the actual power consumption of a local module exceeds the first power consumption threshold corresponding to that local module (for example, a GPU shader core experiences a power surge due to a sudden load), the temperature control function can be immediately triggered. This temperature control function can reduce the utilization of the local module by inserting no-op instructions or forcing it to idle.

[0135] The system can continuously determine whether the power consumption of the local module after regulation has fallen below the second power consumption threshold. If it has not fallen below the second power consumption threshold, the regulation intensity can be increased; if it has fallen below the second power consumption threshold, the regulation can be terminated.

[0136] Experimental data shows that when the chip temperature control method provided by the embodiments of this disclosure is used to set power consumption limits, the average power consumption of local modules is significantly reduced. For example, at a clock frequency of 1800MHz, when a power consumption limit of 9W is set, the average power consumption drops from 10719mW to 8909mW, a 17% decrease, while the GPU clock frequency remains stable. This shows that the chip temperature control method provided by the embodiments of this disclosure can effectively control the temperature of local modules without affecting baseline performance.

[0137] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0138] In addition, the present disclosure also provides a chip temperature control device, a non-volatile computer-readable storage medium, and a computer program product, all of which can be used to implement any chip temperature control method provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method section and will not be repeated here.

[0139] Figure 3 FIG. 1 is a block diagram of a chip temperature control device according to an embodiment of the present disclosure. Figure 3 As shown, the chip temperature control device includes:

[0140] A monitoring module 31 is configured to monitor the power consumption of any local module in the chip;

[0141] a comparing module 32, configured to compare the power consumption value of the local module with a first power consumption threshold corresponding to the local module;

[0142] The reducing module 33 is configured to reduce the utilization rate of the local module in response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module.

[0143] In a possible implementation, the reducing module 43 is configured to:

[0144] In response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, the utilization rate of the local module is reduced until the power consumption value of the local module is lower than a second power consumption threshold corresponding to the local module, wherein the second power consumption threshold is less than the first power consumption threshold.

[0145] In a possible implementation, the reducing module 43 is configured to:

[0146] Inserting a no-operation instruction into the instruction pipeline of the local module.

[0147] In a possible implementation, the reducing module 43 is configured to:

[0148] Determine the insertion density of no-op instructions;

[0149] According to the insertion density, no-operation instructions are inserted into the instruction pipeline of the local module.

[0150] In a possible implementation, the reducing module 43 is configured to:

[0151] Determine the insertion density of the no-operation instructions in the first cooling cycle according to the preset insertion density;

[0152] For the Nth cooling cycle, the insertion density of the no-operation instructions of the Nth cooling cycle is determined according to the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

[0153] In a possible implementation, the reducing module 43 is configured to:

[0154] The local module is controlled to idle.

[0155] In a possible implementation, the reducing module 43 is configured to:

[0156] Determine the proportion of idle cycles;

[0157] The local module is controlled to idle at the idle cycle ratio.

[0158] In a possible implementation, the reducing module 43 is configured to:

[0159] According to the preset idle cycle ratio, determine the idle cycle ratio of the first cooling cycle;

[0160] For the Nth cooling cycle, the idle period ratio of the Nth cooling cycle is determined according to the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

[0161] In a possible implementation, the monitoring module 41 is configured to:

[0162] The power consumption value of the local module is monitored by a hardware counter corresponding to the local module.

[0163] In a possible implementation, the monitoring module 41 is configured to:

[0164] Within a preset time window, recording the number of current signal pulses of the local module by a hardware counter corresponding to the local module, wherein the number of current signal pulses of the local module represents the number of times the current signal strength of the local module exceeds a preset current strength;

[0165] The power consumption value of the local module is determined according to the number of current signal pulses of the local module.

[0166] In a possible implementation, the local module includes a microprocessor-level module.

[0167] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0168] An embodiment of the present disclosure further provides a chip temperature control device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0169] An embodiment of the present disclosure further provides a non-volatile computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0170] An embodiment of the present disclosure further provides a computer program product, including a computer program, or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program implements the steps of the above method when executed by a processor.

[0171] Figure 4FIG1 is a block diagram of a chip temperature control device 1900 according to an exemplary embodiment. For example, the device 1900 can be provided as a server or a terminal device. Figure 4 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions, such as an application, that can be executed by the processing component 1922. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0172] The device 1900 may also include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input / output interface 1958 (I / O interface). The device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2003. TM , MacOS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0173] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the apparatus 1900 to perform the above-described method.

[0174] A computer-readable storage medium can be a tangible device that can hold and store programs / instructions used by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0175] The computer programs (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0176] The computer program (or computer program instructions) for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, by utilizing state information of computer-readable program instructions to personalize and customize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0177] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0178] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0179] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0180] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0181] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0182] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0183] If the technical solutions of the embodiments of the present disclosure involve personal information, the products applying the technical solutions of the embodiments of the present disclosure have clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solutions of the embodiments of the present disclosure involve sensitive personal information, the products applying the technical solutions of the embodiments of the present disclosure have obtained the individual's separate consent before processing the sensitive personal information, and at the same time meet the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that they agree to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload their personal information. The personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0184] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip temperature control method, characterized in that: include: For any local module in the chip, monitoring the power consumption value of the local module; comparing the power consumption value of the local module with a first power consumption threshold corresponding to the local module; In response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, the utilization rate of the local module is reduced.

2. The method according to claim 1, characterized in that In response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, reducing the utilization rate of the local module includes: In response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module, the utilization rate of the local module is reduced until the power consumption value of the local module is lower than a second power consumption threshold corresponding to the local module, wherein the second power consumption threshold is less than the first power consumption threshold.

3. The method according to claim 1, characterized in that The reducing the utilization rate of the local module includes: Inserting a no-operation instruction into the instruction pipeline of the local module.

4. The method according to claim 3, characterized in that The inserting of a no-operation instruction into the instruction pipeline of the local module comprises: Determine the insertion density of no-op instructions; According to the insertion density, no-operation instructions are inserted into the instruction pipeline of the local module.

5. The method according to claim 4, characterized in that Determining the insertion density of the no-operation instructions includes: Determine the insertion density of the no-operation instructions in the first cooling cycle according to the preset insertion density; For the Nth cooling cycle, the insertion density of the no-operation instructions of the Nth cooling cycle is determined according to the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

6. The method according to claim 1, characterized in that The reducing the utilization rate of the local module includes: The local module is controlled to idle.

7. The method according to claim 6, characterized in that The controlling the local module to idle includes: Determine the proportion of idle cycles; The local module is controlled to idle at the idle cycle ratio.

8. The method according to claim 7, characterized in that Determining the idle cycle ratio includes: According to the preset idle cycle ratio, determine the idle cycle ratio of the first cooling cycle; For the Nth cooling cycle, the idle period ratio of the Nth cooling cycle is determined according to the power consumption suppression effect of the N-1th cooling cycle, where N is an integer greater than or equal to 2.

9. The method according to any one of claims 1 to 8, characterized in that The monitoring of the power consumption value of the local module includes: The power consumption value of the local module is monitored by a hardware counter corresponding to the local module.

10. The method according to claim 9, characterized in that The monitoring of the power consumption value of the local module by using a hardware counter corresponding to the local module includes: Within a preset time window, recording the number of current signal pulses of the local module by a hardware counter corresponding to the local module, wherein the number of current signal pulses of the local module represents the number of times the current signal strength of the local module exceeds a preset current strength; The power consumption value of the local module is determined according to the number of current signal pulses of the local module.

11. The method according to any one of claims 1 to 8, characterized in that The local modules include microprocessor-level modules.

12. A chip temperature control device, characterized in that: include: A monitoring module, configured to monitor the power consumption of any local module in the chip; a comparing module, configured to compare the power consumption value of the local module with a first power consumption threshold corresponding to the local module; The reducing module is configured to reduce the utilization rate of the local module in response to the power consumption value of the local module exceeding a first power consumption threshold corresponding to the local module.

13. A chip temperature control device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 11.

14. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

15. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

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