User data block level access counter

Abstract

The invention relates to a user data block level access counter. In some embodiments, a memory device may receive a request to access host data stored in a user data block, wherein the user data block includes a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored and an access counter portion in which access counters associated with a number of accesses to the user data block are stored. The memory device may access the block of user data. The memory device may incremented the access counter based on accessing the user data block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 567,195, filed on March 19, 2024, entitled “USERDATA BLOCK LEVEL ACCESS COUNTER.” The disclosure of the prior application is considered part of and incorporated by reference into this patent application. Technical Field

[0003] The present disclosure generally relates to memory devices, memory device operations, and, for example, a user data block-level access counter. Background Art

[0004] Memory devices are widely used to store information in various electronic devices. Memory devices include memory cells. A memory cell is an electronic circuit that can be programmed into one of two or more data states. For example, a memory cell can be programmed into a data state representing a single binary value, typically represented by a binary "1" or a binary "0." As another example, a memory cell can be programmed into a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device can write to or program a group of memory cells. To access the stored information, the electronic device can read or sense the stored state from the group of memory cells.

[0005] There are various types of memory devices, including random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (e.g., NAND memory and NOR memory), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for extended periods of time even in the absence of an external power source. Volatile memory (e.g., DRAM) may lose stored data over time unless the volatile memory is refreshed by power. In some examples, a memory device may be associated with a compute express link (CXL). For example, the memory device may be a CXL-compatible memory device and / or may include a CXL interface. Summary of the Invention

[0006] In one aspect, the present disclosure provides a memory device comprising: one or more components configured to: receive a request from a host device to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which an access counter associated with a number of accesses to the user data block is stored; access the user data block; and increment the access counter based on accessing the user data block.

[0007] In another aspect, the present disclosure provides a method comprising: receiving, by a memory device, a request from a host device to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which an access counter associated with a number of accesses to the user data block is stored; accessing, by the memory device, the user data block; and incrementing, by the memory device, the access counter based on accessing the user data block.

[0008] In another aspect, the present disclosure provides a memory device comprising: one or more components configured to: receive a request from a host device to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which a plurality of access counters associated with a number of accesses to the user data block are stored; access the user data block; increment a first access counter of the plurality of access counters based on accessing the user data block; and decrement a second access counter of the plurality of access counters concurrently with incrementing the first access counter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating an example system capable of implementing a user data block-level access counter.

[0010] Figures 2A to 2H is a diagram of instances associated with user data block-level access counters.

[0011] Figure 3 is a flow chart of an example method associated with using a user data block-level access counter. DETAILED DESCRIPTION

[0012] In some memory systems, a controller can track the number of accesses (e.g., read operations and / or write operations) to a portion of memory. For example, a memory system can use an access counter (sometimes referred to herein as a heat counter (HC)) to determine whether a portion of memory is accessed relatively frequently (sometimes referred to as "hot") or relatively infrequently (sometimes referred to as "cold"). In such systems, the memory system can use the HC to make informed decisions about data management, such as by maintaining frequently accessed data (e.g., hot data) in memory locations that are easily accessible to the system to speed up access times, moving rarely used data (e.g., cold data) to slower storage devices, and / or the like. Implementing the HC can be resource-intensive because the memory system may use high memory overhead to store the HC and / or because the memory system may need to consume high power, computational, and other resources to track accesses and / or increment and / or decrement the HC as needed. Furthermore, the granularity of HCs may provide limited information about which portions of memory are hot or cold and / or which data is hot or cold because HCs may track accesses to relatively large portions of memory (eg, blocks and / or pages of memory).

[0013] Compared to traditional HC or similar devices, some embodiments described herein implement user data block-level access counters with reduced overhead and / or resource consumption. A user data block refers to a portion of volatile memory that can be accessed during a single access of the volatile memory. In some examples, a user data block may include portions of multiple memory components (e.g., dies). For example, a first user data block may be associated with a first portion of each memory component; a second user data block may be associated with a second portion of each memory component; and so on. In some embodiments, a memory device may store an access counter at a user data block, such as a 64-byte (B) user data block that stores data, error correction information associated with the data (e.g., parity information, cyclic redundancy check (CRC) information, and / or the like), and / or metadata. In such embodiments, a portion of the metadata storage device may be used to store an access counter, which in turn is incremented each time a user data block is accessed to track accesses at the user data block level. Thus, a memory system can monitor the hotness and / or coldness of each individual user data block, thereby enabling informed decisions regarding which user data blocks to promote to main memory, which user data blocks to compress and / or demote from main memory, and / or which user data blocks to move to a deep sleep state; enabling provision of enhanced monitoring data to a host, e.g., for statistical analysis and / or for making memory-related decisions; and / or enabling tracking of row hammering attacks in certain memory systems (e.g., Compute Express Link (CXL)-compatible memory systems); and / or other examples. Thus, user data block-level access counters can be less resource-intensive than conventional HCs because no additional overhead is required to store the access counters (e.g., the access counters can be stored within the user data blocks) and / or can provide improved granularity (e.g., the access counters can track the hotness or coldness of individual user data blocks) compared to conventional HCs, thereby enabling more efficient memory operations and thereby reducing power, computational, and other resource consumption. Additionally or alternatively, user data block level access counters may be able to provide perfect access tracking (e.g., user data block access counters may be referred to as perfect memory access analyzers), rather than relying on statistical methods as is the case with certain conventional access counters, thereby enabling more accurate access tracking and, therefore, improved memory operation.

[0014] Figure 11 is a diagram illustrating an example system 100 capable of implementing user data block-level access counters. System 100 may include one or more devices, apparatuses, and / or components for performing the operations described herein. For example, system 100 may include a host system 105 and a memory system 110. Memory system 110 may include a memory system controller 115 and one or more memory devices 120, shown as memory devices 120-1 through 120-N (where N ≥ 1). The memory devices may include a local controller 125 and one or more memory arrays 130. Host system 105 may communicate with memory system 110 (e.g., memory system controller 115 of memory system 110) via a host interface 140. Memory system controller 115 and memory devices 120 may communicate via respective memory interfaces 145, shown as memory interfaces 145-1 through 145-N (where N ≥ 1).

[0015] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, a mobile phone, a wired or wireless communication device, a network device, a server, a device in a data center, a device in a cloud computing environment, a vehicle (e.g., a car or airplane), and / or an Internet of Things (IoT) device. Host system 105 can include host processor 150. Host processor 150 can include one or more processors configured to execute instructions and store data in memory system 110. For example, host processor 150 can include a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and / or another type of processing component.

[0016] The memory system 110 may be any electronic device or apparatus configured to store data in memory. For example, the memory system 110 may be a hard disk drive, a solid-state drive (SSD), a flash memory system (e.g., a NAND flash memory system or a NOR flash memory system), a universal serial bus (USB) drive, a memory card (e.g., a secure digital (SD) card), an auxiliary storage device, a non-volatile memory express (NVMe) device, an embedded multimedia card (eMMC) device, a dual in-line memory module (DIMM), and / or a random access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device.

[0017] The memory system controller 115 can be any device configured to control the operation of the memory system 110 and / or the operation of the memory devices 120. For example, the memory system controller 115 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the memory system controller 115 can communicate with the host system 105 and can instruct one or more memory devices 120 regarding memory operations to be performed by those memory devices 120 based on one or more instructions from the host system 105. For example, the memory system controller 115 can provide instructions to the local controllers 125 regarding memory operations to be performed by the local controllers 125 in conjunction with the corresponding memory devices 120.

[0018] The memory device 120 may include a local controller 125 and one or more memory arrays 130. In some implementations, the memory device 120 includes a single memory array 130. In some implementations, each memory device 120 of the memory system 110 may be implemented in a separate semiconductor package or on a separate die that includes a respective local controller 125 and a respective memory array 130 for that memory device 120. The memory system 110 may include multiple memory devices 120.

[0019] The local controller 125 can be any device configured to control the memory operations of the memory device 120 in which it is included (e.g., and not control the memory operations of other memory devices 120). For example, the local controller 125 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some implementations, the local controller 125 can communicate with the memory system controller 115 and can control operations performed on the memory array 130 coupled to the local controller 125 based on one or more instructions from the memory system controller 115. As an example, the memory system controller 115 can be an SSD controller, and the local controller 125 can be a NAND controller.

[0020] The memory array 130 may include an array of memory cells configured to store data. For example, the memory array 130 may include a non-volatile memory array (e.g., a NAND memory array or a NOR memory array) or a volatile memory array (e.g., an SRAM array or a DRAM array). In some implementations, the memory system 110 may include one or more volatile memory arrays 135. The volatile memory array 135 may include an SRAM array and / or a DRAM array, among other examples. The one or more volatile memory arrays 135 may be included in the memory system controller 115, in one or more memory devices 120, and / or in both the memory system controller 115 and the one or more memory devices 120. In some implementations, the memory system 110 may include both non-volatile memory capable of maintaining stored data after the memory system 110 is powered off, and volatile memory (e.g., the volatile memory array 135) that requires power to maintain stored data and loses stored data after the memory system 110 is powered off. For example, the volatile memory array 135 may cache data read from or to be written to the non-volatile memory and / or may cache instructions to be executed by the controller of the memory system 110 .

[0021] The host interface 140 enables communication between the host system 105 (e.g., the host processor 150) and the memory system 110 (e.g., the memory system controller 115). The host interface 140 may include, for example, a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, an NVMe interface, a USB interface, a universal flash storage (UFS) interface, an eMMC interface, a double data rate (DDR) interface, and / or a DIMM interface.

[0022] The memory interface 145 enables communication between the memory system 110 and the memory device 120. The memory interface 145 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Additionally or alternatively, the memory interface 145 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a DDR interface.

[0023] In some examples, memory system 110 may be a CXL-compatible memory system (sometimes referred to herein simply as a CXL memory system) and / or one or more of memory devices 120 may be CXL-compatible memory devices (sometimes referred to herein simply as CXL memory devices). CXL is a high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation performance. CXL technology maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. CXL is designed as an industry-standard open interface for high-speed communication. CXL technology is built on the PCIe infrastructure, leveraging the PCIe physical and electrical interfaces to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols, and coherent interfaces.

[0024] In some examples, the memory system 110 may include a PCIe / CXL interface (e.g., the host interface 140 may be associated with a PCIe / CXL interface), which may be a physical interface configured to connect a CXL memory system and / or CXL memory device to a CXL-compatible host device. In such examples, the PCIe / CXL interface may conform to the CXL standard specification for physical connectivity, thereby ensuring broad compatibility and ease of integration into existing systems using the CXL protocol. Additionally or alternatively, the CXL memory system and / or CXL memory device may be designed to efficiently interface with a computing system (e.g., the host system 105) by utilizing the CXL protocol. For example, the CXL memory system and / or CXL memory device may be configured to utilize the high-speed, low-latency interconnect capabilities of CXL, for example, to make the CXL memory system and / or CXL memory device suitable for high-performance computing, data center applications, artificial intelligence (AI) applications, and / or the like.

[0025] A CXL memory system and / or CXL memory device may include a CXL memory controller (e.g., memory system controller 115 and / or local controller 125) that may be configured to manage data flow between a memory array (e.g., volatile memory array 135 and / or memory array 130) and a CXL interface (e.g., a PCIe / CXL interface, such as host interface 140). In some examples, a CXL memory controller may be configured to handle one or more CXL protocol layers, such as an I / O layer (e.g., a layer associated with the CXL.io protocol, which may be used for purposes such as device discovery, configuration, initialization, I / O virtualization, direct memory access (DMA) using incoherent load-store semantics, and / or the like); a cache coherency layer (e.g., a layer associated with the CXL.cache protocol, which may be used for purposes such as caching host memory using a modified, exclusive, shared, invalid (MESI) coherency protocol, or the like); or a memory protocol layer (e.g., a layer associated with the CXL.memory (sometimes referred to as CXL.mem) protocol, which may enable a CXL memory device to expose host-managed device memory (HDM) to allow a host device to manage and access memory similar to local DDR connected to a host); and other examples.

[0026] The CXL memory system and / or CXL memory device may further include and / or be associated with one or more high-bandwidth memory modules (HBMMs) or similar memory arrays (e.g., volatile memory array 135 and / or memory array 130). For example, the CXL memory system and / or CXL memory device may include multiple layers of DRAM (e.g., stacked and / or interconnected via advanced through-silicon via (TSV) technology) to maximize storage density and / or enhance data transfer speeds between memory layers. Additionally or alternatively, the CXL memory system and / or CXL memory device may include a power management unit that may be configured to regulate power consumption associated with the CXL memory system and / or CXL memory device and / or may be configured to improve the energy efficiency of the CXL memory system and / or CXL memory device. Additionally or alternatively, the CXL memory system and / or CXL memory device may include additional components, such as one or more error correction code (ECC) engines, for example, to detect and / or correct data errors to ensure data integrity and / or improve the overall reliability of the CXL memory system and / or CXL memory device.

[0027] Although the example memory system 110 described above includes a memory system controller 115, in some embodiments, the memory system 110 does not include a memory system controller 115. For example, an external controller (e.g., included in the host system 105) and / or one or more local controllers 125 included in one or more corresponding memory devices 120 may perform the operations described herein as being performed by the memory system controller 115. Furthermore, as used herein, "controller" may refer to the memory system controller 115, the local controller 125, or an external controller. In some embodiments, a set of operations described herein as being performed by a controller may be performed by a single controller. For example, the entire set of operations may be performed by a single memory system controller 115, a single local controller 125, or a single external controller. Alternatively, a set of operations described herein as being performed by a controller may be performed by more than one controller. For example, a first subset of operations may be performed by the memory system controller 115, and a second subset of operations may be performed by the local controller 125. Furthermore, depending on the context, the term "memory device" may refer to either the memory system 110 or the memory device 120.

[0028] A controller (e.g., memory system controller 115, local controller 125, or external controller) can control operations performed on a memory (e.g., memory array 130), for example, by executing one or more instructions. For example, memory system 110 and / or memory device 120 can store one or more instructions as firmware in memory, and the controller can execute those one or more instructions. Additionally or alternatively, the controller can receive one or more instructions from host system 105 and / or from memory system controller 115 and can execute those one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) can store a set of instructions (e.g., one or more instructions or code) for execution by the controller. The controller can execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of the set of instructions by the controller causes the controller, memory system 110, and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, hardwired circuitry is used instead of one or more instructions or in combination with one or more instructions to perform one or more operations or methods described herein. Additionally or alternatively, a controller may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as "commands."

[0029] For example, a controller (e.g., memory system controller 115, local controller 125, or external controller) can transmit signals to and / or receive signals from a memory (e.g., one or more memory arrays 130) based on one or more instructions, such as to transfer data to (e.g., write or program) all or a portion of a memory (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of memory), transfer data from (e.g., read), erase, and / or refresh all or a portion of the memory. Additionally or alternatively, the controller can be configured to control access to the memory and / or provide a translation layer between the host system 105 and the memory (e.g., for mapping logical addresses to physical addresses of the memory array 130). In some embodiments, the controller can translate host interface commands (e.g., commands received from the host system 105) into memory interface commands (e.g., commands for performing operations on the memory array 130).

[0030] In some embodiments, Figure 1 One or more systems, devices, apparatuses, components and / or controllers may be configured to receive a request to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which an access counter associated with a number of accesses to the user data block is stored; access the user data block; and increment the access counter based on accessing the user data block.

[0031] In some embodiments, Figure 1 One or more systems, devices, apparatuses, components and / or controllers may be configured to receive a request from a host device to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which a plurality of access counters associated with a number of accesses to the user data block are stored; access the user data block; increment a first access counter of the plurality of access counters based on accessing the user data block; and decrement a second access counter of the plurality of access counters concurrently with incrementing the first access counter.

[0032] Figure 1 The number and arrangement of components shown in FIG are provided as examples. Figure 1 There may be additional components, fewer components, different components, or components arranged differently than those shown. Figure 1 Two or more components shown may be implemented in a single component, or Figure 1 A single component shown may be implemented as multiple distributed components. Additionally or alternatively, Figure 1 The illustrated set of components (e.g., one or more components) may execute the functions described as being Figure 1 Another set of components is shown performing one or more operations.

[0033] Figures 2A to 2H is a diagram of an instance associated with a user data block-level access counter. Figures 2A to 2H The operations described may be performed by the memory system 110 and / or one or more components of the memory system 110 , such as the memory system controller 115 , the one or more memory devices 120 , and / or the one or more local controllers 125 .

[0034] Figure 2A An example user data block 200 is shown that is associated with an HC (e.g., an access counter). In some implementations, the user data block 200 may additionally or alternatively be referred to as a memory frame, a memory stripe, a data block, a data frame, a device physical address (DPA), a cache line, and / or similar terms. The user data block 200 may correspond to the memory block described above in conjunction with Figure 1 1. A portion of the volatile memory array 135 is depicted. In some embodiments, the user data block 200 can be associated with a memory channel (e.g., a data path between a memory and other components of the memory device, such as a memory controller and / or a processor), where the "width" of the memory channel (e.g., measured in bits) refers to the number of bits that can be transferred in one operation and / or one memory cycle. For example, the user data block 200 can be associated with a 40-bit channel, and thus a memory device associated with the user data block 200 can be referred to as a 40-bit memory device. For example, the memory device can be a double data rate 5 (DDR5) 40-bit memory device or the like.

[0035] User data block 200 may be associated with multiple components (e.g., dies) of memory for storing data bits, parity bits, metadata bits, HC bits, or the like. In other words, in some examples, multiple data bits, parity bits, metadata bits, HC bits, and / or other bits may be striped across multiple dies associated with user data block 200. For example, user data block 200 is associated with ten dies indexed as Die 0 through Die 9 (e.g., ten DRAM dies), where Dies 0 through 7 are used to store data bits (and therefore are referred to herein as data dies 202), and Dies 8 through 9 are used to store error correction bits (e.g., parity bits and / or CRC bits), metadata bits, HC bits, and / or the like (and therefore are referred to herein as additional dies 204). As indicated by reference numeral 206, user data block 200 may be associated with a burst length of 16 (e.g., sixteen bit lines indexed 0 through 15), and / or, as indicated by reference numeral 208, each die may be configured in a "by four" (x4) configuration, such that each die includes four input / output pins (sometimes referred to as DQ pins). In this regard, each die of user data block 200 may be capable of storing 64 bits (e.g., 8 bytes). In some examples, user data block 200 may be associated with 64B of data (corresponding to eight data dies 202, each capable of storing 8B) and 16B of error correction bits, metadata bits, HC bits, or the like (corresponding to two additional dies 204, each capable of storing 8B).

[0036] More specifically, in Figure 2A In the example shown in FIG, die 9 may store 8B of parity information (e.g., information associated with a locked redundant array of independent disks (LRAID) ECC or similar ECC), and / or die 8 may store 4B of CRC information, 3B of metadata information, and 1B of HC information. In some other embodiments, die 8 may store more or less CRC information (e.g., less than 4B of CRC information or more than 4B of CRC information), more or less metadata information (e.g., less than 3B of metadata information or more than 3B of metadata information), and / or more or less HC information (e.g., less than 1B of HC information or more than 1B of HC information) without departing from the scope of the present disclosure. Additionally or alternatively, in some embodiments, the metadata information and the HC information may be collectively referred to as metadata information, such that the portion of user data block 200 storing the metadata information and the HC information (e.g., the 4B of die 8) may be referred to as an extended metadata portion of user data block 200. Additionally, as indicated by reference numeral 210, a memory stripe may be associated with a 40-bit channel, of which 32 bits may be associated with data bits (as indicated by reference numeral 212) and 8 bits may be associated with parity bits, CRC bits, metadata bits, and / or HC bits (as indicated by reference numeral 214).

[0037] In some implementations, the HC may be associated with one or more configurable parameters that enable user data block-level access tracking (e.g., to track accesses to the user data block 200, such as read and / or write operations). For example, parameters such as the HC size, the HC threshold, the HC type (e.g., the type of access to be tracked by the HC), and / or the reset / decay type (e.g., whether HC reset / decay is enabled and / or the decay factor associated with the HC reset / decay) may be user-configurable parameters, which are described below in conjunction with Figures 2F to 2H Additionally or alternatively, the HC may be updated during host access (e.g., read access and / or write access) to the user data block 200, for example by incrementing the HC in response to access to the user data block 200. In some embodiments, the HC may be periodically reset (e.g., reduced to zero) or decayed (e.g., reduced to a value other than zero, for example, according to a user-configurable decay factor), for example as described below in conjunction with Figures 2D to 2H During special refresh operations discussed in more detail. In this regard, the HC may track reads, writes, or both read and write accesses to the user data block 200, thereby implementing user data block-level access counting.

[0038] In some embodiments, when an HC threshold is met (e.g., when the HC reaches a threshold, which may be a user-configurable parameter), an alert signal (sometimes referred to as Alert_n) may be asserted to alert the memory controller, host device, and / or another component that the user data block 200 is hot. In some embodiments, the HC value of the user data block 200 may be tracked over time and / or the HC value may be used to form an HC map over time, such that the evolution of the HC map may be used to determine whether the user data block 200 should be promoted to main memory, determine whether the user data block 200 should be compressed and / or demoted from main memory, determine whether the user data block 200 should be moved to a deep sleep state (e.g., for the purpose of reducing power consumption in the memory device), provide monitoring data (e.g., to a host device) for statistical analysis and / or making certain memory allocation decisions, and / or provide tracking of row hammering attacks in a CXL system or similar system.

[0039] In some implementations, incrementing the HC of the user data block 200 (e.g., an accessed user data block) may include activating multiple HCs (e.g., activating HCs associated with multiple user data blocks) and incrementing the HC of the user data block 200 while avoiding incrementing HCs associated with other (e.g., non-accessed) user data blocks. Figure 2B, and as indicated by reference numeral 216, in some embodiments, certain memory components (e.g., dies associated with user data block 200) may be organized into rows, such as row i indicated by reference numeral 218, with each row organized into columns, such as columns indicated by reference numeral 220. In such embodiments, the HC of a given user data block (sometimes referred to herein as HC j ) may include activating the row that includes the HC (eg, row i), and then incrementing the HC of the column corresponding to the user data block (eg, HC=HC+1).

[0040] More specifically, in some implementations, memory dies (e.g., DRAM dies) may be organized into 1024B rows. Thus, on a given die (e.g., die 8 of user data block 200) used to store CRC bits, extended metadata bits 222, and / or similar bits, where each 8B of the die corresponds to a given user data block (e.g., where 4B corresponds to CRC information for user data block 200, 3B corresponds to metadata information for user data block 200, and / or 1B corresponds to HC information for user data block 200), a row activation may identify 128 HCs. In other words, because the prefetch size in some memory devices may be 8B (corresponding to a x4 DQ configuration multiplied by a burst length of 16), each 1024B row may include 128 columns (e.g., 1024B / 8B prefetch = 128), which are Figure 2B The indexes are columns 0 to 127, where each column contains a corresponding HC. Thus, as indicated by reference numeral 224, to increment a given HC (e.g., HC j ), for example, in response to accessing a block of user data associated with a HC, the memory device may activate a row including the HC and a plurality of other HCs (e.g., 127 other HCs), may select a column including the HC from the activated row, and may increment the HC within the selected column (e.g., HC j ) while avoiding increasing other HCs in the row (eg, the other 127 HCs in the activated row).

[0041] In some embodiments, the tick associated with the HC can be masked at a controller (e.g., memory system controller 115, which can be an ASIC controller in a CXL device) or driven to a fixed value during reads and / or writes associated with a user data block 200, so that the lane parity (e.g., parity bits stored on die 9 of a user data block 200 and / or CRC bits stored on die 8 of a user data block) does not need to be updated every time the HC for a given user data block is updated. In this way, the HC can be incremented and / or decremented without changing the CRC bits (e.g., bits used for error detection) and / or the LRAID parity bits (e.g., bits used for error correction).

[0042] For example, Figure 2C As shown in FIG. 1 and indicated by reference numeral 226, during a read command, the memory device may read the die storing CRC information, metadata information, and / or HC information (as well as other die described above in connection with user data block 200). In some embodiments, the memory device may read the actual value of the HC during a read operation, such as Figure 2C In such embodiments, the value of HC may be masked to an error manager component of the memory device (e.g., an error manager ASIC in a CXL device, among other examples) so that the error manager component can perform error correction operations without affecting the channel parity and / or ECC (e.g., CRC information, channel parity information such as LRAID information, and / or similar information may be used to detect any errors in read data). In some other embodiments, a fixed value (e.g., 0, in Figure 2C In one embodiment, the HC bits are replaced with a fixed value (e.g., 00h) in the HC beat to determine parity information and / or other error correction information. In such an implementation, a fixed value (e.g., 00h) may be imposed on the HC beat during a read operation so as not to change the lane parity and / or otherwise affect the ECC and / or error correction capabilities of the error manager component.

[0043] Similarly, as indicated by reference numeral 228, in some embodiments, the memory device may write an X value to the HC bit during a write operation. In such embodiments, the HC value may be masked from the error manager component so that the error manager can determine error correction information (e.g., CRC information, channel parity information such as LRAID information, and / or similar ECC information) without using the HC value (e.g., X). In some other embodiments, when determining error correction information during a write operation, a fixed value (e.g., 00h) may be imposed on the HC beat so as not to change the channel parity and / or otherwise affect the ECC and / or error correction capabilities of the error manager component.

[0044] Figure 2D Operations performed at various stages and / or layers of the memory device 120, including a command / address (CA) stage as indicated by reference numeral 232, an HC stage as indicated by reference numeral 234, a warning stage as indicated by reference numeral 236, and / or a data stage as indicated by reference numeral 240, are shown, for example, for the purpose of implementing a user data block-level access counter. First, as shown in conjunction with reference numeral 232, the memory device may issue an activate (ACT) command to the memory component, which may identify a plurality (e.g., 128) of HCs to be activated, as described above in conjunction with Figure 2BThe activation command may be followed by a timing parameter associated with a row-to-column delay (tRCD), which may refer to the amount of time required between a row being activated (e.g., a row address being sent to a memory component) and the data in the row being available for a read or write operation. Thus, as shown in conjunction with reference numeral 234, the above Figure 2B A similar manner as described activates all HCs in the row containing the HC to be incremented during tRCD.

[0045] As further shown by element symbol 232, after the activation command, the memory device may issue a read / write (RD / WR) command to the memory component, which may identify the user data block to be accessed (e.g., to be read and / or written) (e.g., user data block 200). Therefore, during a read latency / write latency (RL / WL) time period (e.g., the time period between issuing a read command and the moment the first bit of the requested data is available on the data bus, and / or the time period between issuing a write command and the data being actually written to the memory array), the HC associated with the user data block being accessed may be incremented by 1, thereby reflecting that the user data block is being accessed. As indicated by element symbol 240, after the RL / WL time period, the data to be read and / or newly written may be available at the data bus. For ease of description, only the memory components of the user data blocks containing HCs (e.g., die 8 of user data block 200) are shown at the data bus. Furthermore, because in some embodiments, the data bus may be in a x4 DQ configuration, in combination Figure 2D Each box shown in the data bus in FIG may correspond to 4 bits. In this regard, the first two boxes (indicated using diagonal shading) may correspond to 8 bits associated with the HC (e.g., 1B), the next six boxes (indicated using horizontal and vertical shading) may correspond to 24 bits associated with other metadata (e.g., 3B), and / or the remaining eight boxes (indicated using diagonal shading) may correspond to 32 bits associated with other CRC information (e.g., 4B). In this regard, the value of the HC may be available to the memory device via a read operation (e.g., via a DQ pin).

[0046] Furthermore, as shown by reference numeral 236, if the HC meets a threshold, the memory device may cause an alert signal (sometimes referred to herein as Alert_n) to be asserted. The alert signal (e.g., Alert_n) may alert a memory controller, a host device, and / or another device that a user data block is relatively hot. Asserting Alert_n when the HC meets a threshold may enable more efficient memory operation because the memory device, the host device, and / or another device may perform certain actions in real time when the user data block becomes hot. Furthermore, during a read operation, information provided on the data bus (e.g., DQ pins) and Alert_n may be transmitted in the same direction (e.g., from the memory to the controller), whereas during a write operation, information provided on the data bus (e.g., DQ pins) and Alert_n may be transmitted in opposite directions because the controller is writing information on the DQ pins and receiving Alert_n from the memory.

[0047] As further indicated by element number 232, the memory device may then issue a precharge (PRE) command to the memory component, which may cause a plurality of HCs (e.g., 128 HCs associated with the activated row) to be stored (as indicated by element number 234). Additionally or alternatively, and as further indicated by element number 232, the memory device may periodically issue a special refresh (SREF) command to the memory component. For example, the memory device may determine that a time period associated with tracking one or more blocks of user data has elapsed, and thus the memory device may issue a special refresh command to the memory component in order to reduce the number of HCs stored in a bank of the memory. In other words, in some embodiments, the SREF command may operate at the bank level, and thus all HCs physically stored in the bank may be reset in response to the memory device issuing the SREF command. In some embodiments, the time period may be an integer multiple of a reference time period (tREF), which may be equal to a refresh rate of the memory component (e.g., a refresh rate of a DRAM memory component). Additionally or alternatively, in some embodiments, tREF may be 32 milliseconds (ms), and thus the time period for tracking accesses to a user data block (e.g., user data block 200) (after which the HC will be reduced) may be an integer multiple of 32 ms. Based on receipt of a special refresh command, the memory device may reduce the HC, for example, by resetting the HC to zero or decaying the HC to a non-zero value according to a user-configured decay factor, which is described in more detail below.

[0048] More specifically, Figure 2EAn example 242 is shown plotting the magnitude of HC (as indicated by reference numeral 244) over time (as indicated by reference numeral 246) for two example user data blocks, user data block m (as indicated by reference numeral 248) and user data block n (as indicated by reference numeral 250). In some implementations, HC may be compared to an HC threshold (as indicated by reference numeral 252 and as described above in conjunction with Figure 2D ) and a maximum value (as indicated by reference numeral 254 and which may correspond to the count at which the HC reaches a maximum value (e.g., 255 for an 8-bit counter, 4,095 for a 12-bit counter, or 65,535 for a 16-bit counter, among other examples). As shown by the curve indicated by reference numeral 248, user data block m may be a relatively hot user data block (e.g., compared to user data block n), and thus the HC associated with the user data block (shown as HC m ) can increase relatively quickly. If the user data block is configured so that the warning signal (e.g., Alert_n) is enabled, then when the HC m When the HC threshold is met, a warning may be asserted, as indicated by reference numeral 256. In some embodiments, the HC m The increment may continue for each additional access until the maximum value of HC is reached, at which point HC m As indicated by reference numeral 258, the HC may become saturated (eg, reach a maximum value), and thus m Can be kept at the maximum value until HC m until it is reset and / or decayed.

[0049] As shown by the curve indicated by reference numeral 250, user data block n may be a relatively cold user data block (eg, compared to user data block m), and thus the HC associated with user data block n (shown as HC n ) can increase relatively slowly. In this regard, if the user data block is configured so that the warning signal (e.g., Alert_n) is enabled, then when the HC n When the HC threshold is met, a warning may be asserted, as indicated by reference numeral 260, which may be used in response to an HC threshold. m In some embodiments, HC n The increment may continue for each additional access, but the saturation point (eg, the maximum value of HC) may never be reached within a given time period because the user data blocks are relatively cool.

[0050] As indicated by reference numeral 262, after a certain period of time (which may be tREF (e.g., 32 milliseconds) or an integer multiple of tREF (e.g., 64 milliseconds, 96 milliseconds, etc.)), a special refresh signal (e.g., SREF) may be issued to reset or decay the HCs, as indicated by reference numeral 262. For example, in some embodiments, SREF may reset all HCs physically stored in a bank of the memory (e.g., HCs associated with user data block m, HCs associated with user data block n, and / or HCs associated with other user data blocks belonging to the same user data block bank as user data block m and user data block n), because the SREF command may operate at the bank level. Figure 2E In the example shown in FIG, HC is reset to zero, and thus HC may start counting from zero during subsequent time periods. However, in some other embodiments, a special refresh command may decay HC to some non-zero value (e.g., according to a user-configured decay factor), which is described below in conjunction with Figures 2F to 2G Describe in more detail.

[0051] In some embodiments, access to user data blocks tracked via HCs may be suspended during special refresh periods (e.g., time periods when HCs are reset and / or decayed). Thus, in some embodiments, multiple HCs may be utilized to perform alternating tracking of user data blocks (sometimes referred to herein as ping-pong tracking of user data blocks), wherein a first HC (sometimes referred to herein as a PING HC) is active while a second HC (sometimes referred to herein as a PONG HC) is being refreshed, and wherein a second HC (e.g., a PONG HC) is active while a first HC (e.g., a PING HC) is being refreshed. In such embodiments, continuous tracking of user data blocks may be achieved because tracking of user data blocks does not need to be suspended when an HC is reset or decayed. Detailed description of the exemplary embodiments of the present invention is provided below in conjunction with the exemplary embodiments of the present invention. Figure 2H The aspect of using multiple HCs to alternately track user data blocks is described in more detail.

[0052] Additionally or alternatively, special refresh commands may operate at the bank level. A "bank" of memory may refer to a subset and / or partition of an overall memory array (e.g., memory array 130, which may be a DRAM array or the like in the context of a CXL device). In some embodiments, a bank of memory may include multiple (e.g., 8,192) rows. Furthermore, in embodiments associated with a DRAM array, each memory cell within the DRAM may need to be refreshed according to a certain periodicity, sometimes referred to as a refresh rate. For example, in some embodiments, each memory cell within the DRAM may need to be refreshed every 32 ms. Thus, in embodiments where a bank of memory includes 8,192 rows, the bank of memory may require a refresh command every approximately 3.9 microseconds (μs) (e.g., 8,192 rows x 3.9 μs / row = 32 ms, or the refresh rate). In such embodiments, refresh commands may be sent to the bank of memory, and the memory may internally manage a row counter to sequentially refresh all 8,192 rows of the bank.

[0053] In some embodiments, the SREF command may rely on the need to periodically refresh a memory array (e.g., a DRAM array) according to a refresh rate (e.g., 32 ms). More specifically, in addition to the required refresh of the memory cells described above, the SREF command may also be used to provide a reset and / or decay of memory cells used as HCs. In such embodiments, the SREF command may be sent to a bank of memory, and the memory may internally manage row counters to perform the reset / decay of the HCs in a sequential manner on all rows within the bank (e.g., on all 8,192 rows of the bank, among other examples). Additionally or alternatively, the SREF may be performed on multiple banks of a memory device, for example by sending a corresponding SREF command to each of multiple banks of the memory (which in some embodiments may include 16 banks or another number of banks). As described above, in some embodiments, a second HC (e.g., a PONG HC) may be used to track accesses to user data blocks during a time period when a first HC (e.g., a PING HC) is reset or decayed, so that continuous tracking of user data blocks may be achieved, which will be described below in conjunction with Figure 2H Describe in more detail.

[0054] In some implementations, a memory device (e.g., memory device 120) may receive configuration information that configures one or more parameters associated with a HC, for example, via one or more mode registers (MRs) associated with a monitored user data block (e.g., user data block 200). For example, an operating point (OP) of the one or more MRs may be set to indicate certain parameters associated with the HC, such as an HC threshold, a size of a portion of a user data block for storing the HC, enablement of the HC, support for the HC, enablement of a reduction of the HC, a reduction type for reducing the HC, a type of one or more accesses to the user data block to be counted by the HC, or enablement of one of a plurality of HCs associated with the user data block (e.g., PING and PONG HCs), among other parameters.

[0055] For example, Figure 2F 264 in the figure indicates an MR that can be used to configure HC. In some embodiments, the MR indicated by the element symbol 264 can be referred to as the first HC MR, or simply HC1. HC1 can include eight OPs, indexed as OP0 to OP7. OP0 can be a read-only bit that indicates whether HC is supported for a given memory component. For example, as described above in conjunction with Figure 2A As described, user data block 200 may include ten components (e.g., dies), where HC is included on only one of the ten components (e.g., die 8). Therefore, the MR for the component that includes HC (e.g., die 8) may have OP0 set to 1b, indicating that the component supports HC. This is sometimes referred to as "blowing the fuse" of a memory component to indicate that it is a component that supports and / or stores HC. OP1 may be a read / write bit that indicates whether HC is enabled for a given component (e.g., a memory component with a blown fuse). For example, when OP1 is set to 0b, HC may be disabled (which may be the default setting), and when OP1 is set to 1b, HC may be enabled. In this regard, only a component with a blown fuse (e.g., a memory component with OP0 set to 1b indicating HC support) may have OP1 set to 1b (e.g., enabling HC). More specifically, in some implementations, an MR write command to update the MR may be transmitted in parallel to all components of a channel (e.g., all ten dies of user data block 200), but only the component of the channel that blew the fuse (e.g., die 8) may have the HC enabled (e.g., OP1=1b).

[0056] OP2 and OP3 may be used to indicate the size of the HC. For example, when OP2 and OP3 are set to 00b (e.g., the default setting), the HC size may be 0b; when OP2 and OP3 are set to 01b, the HC size may be 8b (which may be able to count up to 2 user data blocks). 8-1 access, or 255 accesses); when OP2 and OP3 are set to 10b, the HC size can be 12b (which can be able to count up to 2 accesses to user data blocks) 12 -1 access, or 4,095 accesses); or when OP2 and OP3 are set to 11b, the HC size can be 16b (which can be able to count up to 2 accesses to user data blocks). 16 -1 access, or 65,535 accesses); and other examples. In addition, OP4 and OP5 can be used to indicate the HC threshold. For example, when OP4 and OP5 are set to 00b (e.g., the default setting), the HC threshold can be 0b; when OP4 and OP5 are set to 01b, the HC threshold can be 3b (e.g., the HC threshold can be 2 3 =8); when OP4 and OP5 are set to 10b, the HC threshold may be 6b (for example, the HC threshold may be 2 6 =64); or, when OP4 and OP5 are set to 11b, the HC threshold may be 9b (eg, the HC threshold may be 2 9 =512); and other examples. In some cases, certain OPs (e.g., Figure 2F OP6 and OP7 in the implementation shown in ) may be reserved for future use.

[0057] Figure 2GElement number 268 in FIG. 2 indicates another MR that can be used to configure the HC. In some embodiments, the MR indicated by element number 268 may be referred to as a second HC MR, or simply HC2. HC2 may also include eight OPs, indexed as OP0 through OP7. OP0 and OP1 may be used to indicate the HC start / type. For example, when OP0 and OP1 are set to 00b (e.g., the default setting), the HC may not count accesses to the user data block; when OP0 and OP1 are set to 01b, the HC may only count read accesses to the user data block; when OP0 and OP1 are set to 10b, the HC may only count write accesses to the user data block; or when OP0 and OP1 are set to 11b, the HC may count both read and write accesses to the user data block; and other examples. Furthermore, OP2 and OP3 may be used to indicate the HC reset / decay type. For example, when OP2 and OP3 are set to 00b (e.g., the default setting), HC reset / decay may be disabled (e.g., the refresh command may be standard without reset and / or decay capabilities); when OP2 and OP3 are set to 01b, HC reset may be enabled (e.g., the HC may be reset to zero); when OP2 and OP3 are set to 10b, 1 / 4 HC decay may be enabled (e.g., the HC may be set to 1 / 4 of its current value); or when OP2 and OP3 are set to 11b, 1 / 2 HC decay may be enabled (e.g., the HC may be set to 1 / 2 of its current value); and other examples. In this regard, any value other than 00b in OP2 and OP3 may enable the above-described combination of Figure 2D and 2E In some cases, some OPs (e.g., Figure 2G OP4, OP5, OP6, and OP7 in the implementation scheme shown in may be reserved for future use.

[0058] As described above, in some implementations, multiple HCs associated with a user data block (e.g., user data block 200) may be utilized, such as in implementations where a PING HC is used to track accesses concurrently with a PONG HC being reduced (e.g., decayed and / or reset), and / or where a PONG HC is used to track accesses concurrently with a PING HC being reduced (e.g., decayed and / or reset). Thus, in some implementations, one or more of the reserved OPs described above may be used to indicate certain parameters associated with multiple HCs (e.g., PING HC and / or PONG HC).

[0059] More specifically, Figure 2H272 in the figure indicates another MR that can be used to configure the HC. In some embodiments, the MR indicated by the element symbol 268 can be another embodiment of HC2. In this embodiment, HC2 can also include eight OPs, indexed as OP0 to OP7. In addition, similar to the above combination Figure 2G In the described embodiment, OP0 and OP1 can be used to indicate HC start / type, and / or OP2 and OP3 can be used to indicate HC reset / decay type. However, in this embodiment, OP4 can be used to indicate HC mode selection. For example, when OP4 is set to 0b, the first HC (e.g., PING HC) will start counting, while the second HC (e.g., PONG HC) will be decayed and / or reset. On the other hand, when OP4 is set to 1b, the second HC (e.g., PONG HC) will start counting, while the first HC (e.g., PING HC) will be decayed and / or reset. This allows at least one HC to always be active, allowing access to user data blocks (e.g., user data block 200) to be tracked even during special refresh commands. In other words, during the period when OP4 of this embodiment of HC2 is set to 0b, tracking can be activated by the PING HC, and tracking can be suspended for the PONG HC (e.g., allowing it to be reset and / or decayed according to the reset / decay type indicated by OP2 and OP3). Periodically, to reset or decay the PING HC, OP4 of HC2 may be set to 1b, at which point tracing may be started for the PONG HC and paused for the PING HC (e.g., so that it may be reset and / or decayed according to the reset / decay type indicated by OP2 and OP3). In such an implementation, twice as many bits as for a single HC may be used in the memory array to store the HC, since two separate HCs may be stored in the user data block (e.g., in Figure 2A 8 of the die 8 of the user data block 200 shown in FIG.

[0060] As instructed above, Figures 2A to 2H are provided as examples. Other examples may differ from those regarding Figures 2A to 2H described.

[0061] Figure 33 is a flow chart of an example method 300 associated with using a user data block-level access counter. In some implementations, a memory device (e.g., memory device 120) may perform or be configured to perform method 300. In some implementations, another device or group of devices (e.g., system 100 and / or memory system 110) that is independent of or includes the memory device may perform or be configured to perform method 300. Additionally or alternatively, one or more components of the memory device or another device or group of devices (e.g., memory system controller 115 and / or local controller 125, among other examples) that is independent of or includes the memory device may perform or be configured to perform method 300. Thus, means for performing method 300 may include a memory device (e.g., memory device 120) and / or one or more components of the memory device, and / or a memory system (e.g., memory system 110) and / or one or more components of the memory system. Additionally or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by a memory device or memory system (e.g., local controller 125 of memory device 120 and / or memory system control 115), cause the memory device and / or memory system to perform method 300.

[0062] like Figure 3 , method 300 may include receiving a request to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which an access counter associated with the number of accesses to the user data block is stored (block 310). For example, memory device 120 may receive a request to access (e.g., read and / or write) user data block 200, which includes a data portion (e.g., data die 202), an error correction portion (e.g., a portion of additional die 204 for storing parity information and / or CRC information), a metadata portion (e.g., a portion of additional die 204 for storing metadata), and an access counter portion (e.g., a portion of additional die 204 for storing HC, the HC being one example of an access counter). As shown in FIG. Figure 3 As further shown in FIG. 3 , method 300 may include accessing a user data block (block 320 ). For example, memory device 120 may access host data stored on data die 202 of user data block 200 , such as by performing read and / or write operations. Figure 3 As further shown in FIG. 3 , method 300 may include incrementing an access counter based on accessing the user data block (block 330). For example, the memory device may increment the HC stored in the additional die 204 of the user data block 200, as described above in conjunction with FIG. Figures 2B to 2H describe.

[0063] Method 300 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0064] In a first aspect, a user data block includes a plurality of memory components, wherein a data portion is associated with a first subset of memory components in the memory components, wherein an error correction portion is associated with a second subset of memory components in the memory components, and wherein an access counter portion and a metadata portion are contained on memory components in the second subset of memory components. For example, user data block 200 may include a plurality (e.g., ten) of dies, wherein the data portion is associated with a first subset of dies (e.g., dies 0-7), wherein the error correction portion is associated with a second subset of dies (e.g., dies 8-9), and wherein the access counter portion and the metadata portion are contained on a die in the second subset of dies (e.g., die 8).

[0065] In a second aspect, alone or in combination with the first aspect, the method 300 includes one of: masking a tick associated with an access counter when determining lane parity information for a user data block, or replacing the tick associated with the access counter with a fixed value when performing at least one of a read operation or a write operation for the user data block. For example, the memory device 120 may mask the HC tick on the ASIC error manager so that the actual HC tick is read from the DQ without changing the lane parity, and / or the memory device 120 may impose a fixed value (e.g., 00h) on the HC tick when reading so as to preserve the error correction capability of the parity bit, as described above in conjunction with Figure 2C describe.

[0066] In a third aspect, alone or in combination with one or more of the first and second aspects, incrementing the access counter comprises: activating the access counter portion and a plurality of other access counter portions associated with the plurality of other access counters; incrementing the access counter; and refraining from incrementing the plurality of other access counters. Figure 2B and 2D As described, the memory device 120 may activate multiple HCs (eg, HC0 to HC 127 ), and the memory device 120 may activate one of the activated HCs (eg, HC j ), while avoiding activation of other activated HCs.

[0067] In a fourth aspect, alone or in combination with one or more of the first to third aspects, the method 300 includes: using an access counter by the memory device to identify that the number of accesses to the user data block meets a threshold; and causing the memory device to transmit an alert signal based on identifying that the number of accesses to the user data block meets the threshold. For example, when the HC exceeds the threshold, the memory device 120 may cause an alert (e.g., Alert_n) to be asserted, as described above in conjunction with Figure 2D and 2E describe.

[0068] In a fifth aspect, alone or in combination with one or more of the first to fourth aspects, the method 300 includes: determining, by the memory device, that a time period has elapsed; and decrementing, by the memory device, an access counter based on determining that the time period has elapsed. For example, the memory device 120 may use an SREF command to decay and / or reset the HC, as described above in conjunction with Figures 2D to 2H describe.

[0069] In a sixth aspect, alone or in combination with one or more of the first through fifth aspects, method 300 includes decrementing, by the memory device, a plurality of access counters associated with a plurality of other blocks of user data based on determining that a time period has elapsed. For example, memory device 120 may decay and / or reset HCs associated with an entire row of a memory array (e.g., HC m and HC n and others), as above combined Figure 2E describe.

[0070] In a seventh aspect, alone or in combination with one or more of the first to sixth aspects, the time period is an integer multiple of a reference time period. For example, the time period may be a multiple of 32 ms and / or another reference time period (e.g., tREF), as described above in conjunction with Figure 2E describe.

[0071] In an eighth aspect, alone or in combination with one or more of the first to seventh aspects, the method 300 includes receiving, by the memory device via one or more mode registers associated with the user data block, configuration information for configuring one or more parameters associated with the access counter. For example, the memory device 120 may receive, via the above-mentioned combination Figures 2F to 2G One or more of the described MRs receive configuration information.

[0072] In a ninth aspect, alone or in combination with one or more of the first to eighth aspects, the one or more parameters include at least one of: an access counter threshold, a size of an access counter portion, enabling of an access counter, support of an access counter, enabling of decrement of an access counter, a decrement type for decrementing an access counter, a type of one or more accesses to a user data block to be counted by the access counter, or enabling of an access counter among a plurality of access counters associated with a user data block. For example, the configuration information may be configured using the configuration information described above in conjunction with Figures 2F to 2G The MR describes the OP to indicate various parameters.

[0073] In a tenth aspect, alone or in combination with one or more of the first to ninth aspects, the user data block is associated with another access counter, and wherein the method further comprises decrementing, by the memory device, the other access counter concurrently with incrementing the access counter. For example, the user data block 200 may be associated with a PING HC and a PONG HC, such that one of the PING HC or the PONG HC is incremented during a time period in which the other of the PING HC or the PONG HC is reset or decayed, as described above in conjunction with Figure 2G and 2H describe.

[0074] although Figure 3 Example blocks of method 300 are shown, but in some embodiments, Figure 3 Method 300 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than depicted in

[0045] . Additionally or alternatively, two or more blocks of method 300 may be executed in parallel. Method 300 is an example of a method that may be performed by one or more devices described herein. Such one or more devices may perform or be configured to perform one or more other methods based on the operations described herein.

[0075] In some implementations, a memory device includes one or more components configured to: receive a request from a host device to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which an access counter associated with a number of accesses to the user data block is stored; access the user data block; and increment the access counter based on accessing the user data block.

[0076] In some implementations, a method includes: receiving, by a memory device, a request from a host device to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which an access counter associated with a number of accesses to the user data block is stored; accessing, by the memory device, the user data block; and incrementing, by the memory device, the access counter based on accessing the user data block.

[0077] In some implementations, a memory device includes one or more components configured to: receive a request from a host device to access host data stored in a user data block, wherein the user data block includes: a data portion in which the host data is stored, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which a plurality of access counters associated with a number of accesses to the user data block are stored; access the user data block; increment a first access counter of the plurality of access counters based on accessing the user data block; and decrement a second access counter of the plurality of access counters while incrementing the first access counter.

[0078] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments described herein.

[0079] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." As used herein, "satisfies a threshold value" may refer to a value that is greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, equal to a threshold value, not equal to a threshold value, or the like, depending on the context.

[0080] Even if a particular combination of features is described in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in a manner not specifically described in the claims and / or disclosed in the specification. For example, the present disclosure includes each dependent claim in the claim set and each other individual claim in the claim set and each combination of multiple claims in the claim set. As used herein, a phrase referring to "at least one" in a list of items refers to any combination of those items, including a single member. For example, "at least one of a, b, or c" is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination with multiples of the same element (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other arrangement of a, b, and c).

[0081] When a "component" or "one or more components" (or another element, such as a "controller" or "one or more controllers") is described or claimed (either within a single claim or across multiple claims) as performing or being configured to perform multiple operations, this language is intended to broadly cover a variety of architectures and environments. For example, unless expressly stated otherwise (e.g., through use of "a first component" and "a second component" or other language that distinguishes components in the claims), this language is intended to encompass a single component that performs or is configured to perform all operations, a group of components that collectively perform or are configured to perform all operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that perform or are configured to perform operations. For example, when a claim has the form "one or more components configured to: perform X; perform Y; and perform Z," the claim should be interpreted to mean "one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (possibly different) components configured to perform Z."

[0082] Unless explicitly described, any element, behavior or instruction used herein should not be interpreted as critical or necessary. Moreover, as used herein, the article "a / an" is intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the article "the" is intended to include one or more items cited in conjunction with the article "the" and can be used interchangeably with "the one or more". If it is desired to use only one item, then the phrase "only one", "single" or similar language is used. In addition, as used herein, the term "has / have / having" or the like is intended to be an open term that does not limit the element it modifies (for example, an element "having" A may also have B). In addition, the phrase "based on" is intended to mean "at least partially based on", unless otherwise explicitly stated. As used herein, the term "multiple" can be replaced with "multiple", and vice versa. Furthermore, as used herein, the term "or" is intended to be inclusive when used in a series and is used interchangeably with "and / or" unless expressly stated otherwise (e.g., if used in combination with "either" or "only one of...").

Claims

1. A memory device comprising: One or more components configured to: receiving a request from a host device to access host data stored in a user data block, wherein the user data block comprises: A data portion storing said host data, an error correction portion in which error correction bits associated with correcting errors in said host data are stored, a metadata portion in which metadata bits associated with said host data are stored, and an access counter portion in which an access counter associated with the number of accesses to the user data block is stored; accessing the user data block; and The access counter is incremented based on accessing the user data block.

2. The memory device of claim 1 , wherein the userable data block comprises a plurality of memory elements, wherein the data portion is associated with a first subset of memory components of the memory components, wherein the error correction portion is associated with a second subset of memory components of the memory components, and wherein the access counter portion and the metadata portion are included on memory components of the second subset of the memory components.

3. The memory device of claim 1 , wherein the one or more components are further configured to: masking the beats associated with the access counter when determining the channel parity information for the user data block, or When at least one of a read operation or a write operation is performed on the user data block, the tick associated with the access counter is replaced with a fixed value.

4. The memory device of claim 1 , wherein the one or more components for incrementing the access counter are configured to: activating the access counter portion and a plurality of other access counter portions associated with a plurality of other access counters; Incrementing the access counter; and Incrementing the plurality of other access counters is avoided.

5. The memory device of claim 1 , wherein the one or more components are further configured to: identifying, using the access counter, that the number of accesses to the user data block satisfies a threshold; and A warning signal is caused to be transmitted based on identifying that the number of accesses to the user data block meets the threshold.

6. The memory device of claim 1 , wherein the one or more components are further configured: confirm that the time period has elapsed; and The access counter is decremented based on a determination that the time period has elapsed.

7. The memory device of claim 6, wherein the one or more components are further configured to decrement a plurality of access counters associated with a plurality of other blocks of user data based on determining that the time period has elapsed. The memory device of claim 6 , wherein the time period is an integer multiple of a reference time period.

9. The memory device of claim 1, wherein the one or more components are further configured to receive configuration information configuring one or more parameters associated with the access counter via one or more mode registers associated with the user data block.

10. The memory device of claim 9, wherein the one or more parameters include at least one of: Access counter threshold, The size of the access counter portion, The access counter is enabled, The access counter supports, The access counter is decremented to enable, a decrement type for decrementing the access counter, the type of one or more accesses to the user data block to be counted by the access counter, or An enabling of an access counter among a plurality of access counters associated with the user data block.

11. The memory device of claim 1 , wherein the user data block is associated with another access counter, and Wherein the one or more components are further configured to decrement the another access counter concurrently with incrementing the access counter.

12. A method comprising: A request is received by a memory device from a host device to access host data stored in a user data block, wherein the user data block comprises: A data portion storing said host data, an error correction portion in which error correction bits associated with correcting errors in the host data are stored, a metadata portion in which metadata bits associated with the host data are stored, and an access counter portion in which an access counter associated with the number of accesses to the user data block is stored; accessing the user data block by a memory device; and The access counter is incremented by the memory device based on accessing the block of user data.

13. The method of claim 12, wherein incrementing the access counter comprises: activating, by the memory device, the access counter portion and a plurality of other access counter portions associated with a plurality of other access counters; incrementing the access counter by the memory device; and Incrementing the plurality of other access counters by the memory device is avoided.

14. The method according to claim 12, further comprising: identifying, by the memory device, using the access counter, that the number of accesses to the user data block satisfies a threshold; and A warning signal is caused to be transmitted by the memory device based on identifying that the number of accesses to the user data block meets the threshold.

15. The method of claim 12, further comprising: determining, by the memory device, that a time period has elapsed; and The access counter is decremented by the memory device based on determining that the time period has elapsed.

16. The method of claim 12, wherein the block of user data is associated with another access counter, and wherein the method further comprises decrementing, by the memory device, the another access counter concurrently with incrementing the access counter.

17. A memory device comprising: One or more components configured to: receiving a request from a host device to access host data stored in a user data block, wherein the user data block comprises: A data portion storing said host data, an error correction portion in which error correction bits associated with correcting errors in said host data are stored, a metadata portion in which metadata bits associated with the host data are stored; and an access counter section storing a plurality of access counters associated with the number of accesses to the user data block; accessing the user data block; incrementing a first access counter of the plurality of access counters based on accessing the user data block; and A second access counter of the plurality of access counters is decremented concurrently with incrementing the first access counter.

18. The memory device of claim 17, wherein the one or more components are further configured to do one of the following: masking the beats associated with the access counter when determining the channel parity information for the user data block, or When at least one of a read operation or a write operation is performed on the user data block, the tick associated with the access counter is replaced with a fixed value.

19. The memory device of claim 17, wherein one or more components for incrementing the first access counter are configured to: activating the access counter portion and a plurality of other access counter portions associated with a plurality of other access counters; Incrementing the first access counter; and Incrementing the plurality of other access counters is avoided.

20. The memory device of claim 17, wherein the one or more components are further configured to: identifying, using the first access counter, that the number of accesses to the user data block satisfies a threshold; and A warning signal is caused to be transmitted based on identifying that the number of accesses to the user data block meets the threshold.

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