Layout structure of microcontroller chip and microcontroller chip

Abstract

The invention relates to a layout structure of a microcontroller chip and the microcontroller chip. The layout structure comprises an input / output interface layout area, a program memory layout area, a data memory layout area, a peripheral memory layout area, a firmware memory layout area and a digital logic circuit layout area, according to the layout structure, seven layout areas including an input and output interface layout area, a program memory layout area, a data memory layout area, a peripheral memory layout area, a firmware memory layout area and a digital logic circuit layout area are reasonably and compactly arranged, so that the area optimization of a chip is realized, the cost of the chip is reduced, the time sequence requirement of the chip is met at the same time, and the reliability of the chip is improved. And high performance and high reliability are realized. And through the program memory layout area, the data memory layout area, the peripheral memory layout area and the firmware memory layout area, the memories can be accessed in parallel and do not influence one another, so that the execution speed is accelerated.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of microelectronics technology, and in particular to a layout structure of a microcontroller chip and a microcontroller chip. Background Art

[0002] Microcontroller units (MCUs) integrate a central processing unit (CPU), memory, bus, and peripheral interfaces onto a single chip, forming a chip-level computer. They are widely used in a variety of fields, including automotive, industrial control, and consumer electronics. Microcontroller chip design primarily involves RTL (Register-Transfer Level) code development, functional verification, logic synthesis, and layout and routing. Layout and routing involves arranging the gate-level netlist generated by logic synthesis within a specific area according to specific rules, connecting the various devices, and generating the chip layout structure, which is then delivered to the chip manufacturer for production. Layout significantly impacts the area, timing, cost, and reliability of the microcontroller chip.

[0003] However, in existing technologies, the layout structure of current microcontroller chips includes multiple analog circuit areas and only one memory area, without further distinguishing between program memory, data memory, peripheral memory, and firmware memory areas, and without properly arranging these areas. This layout structure results in a larger chip area, which in turn increases chip cost. Summary of the Invention

[0004] In view of the above problems, a layout structure of a microcontroller chip and a microcontroller chip are proposed to overcome the above problems or at least partially solve the above problems.

[0005] Specifically, the present invention provides a layout structure of a microcontroller chip, the layout structure comprising: an input / output interface layout area, a memory layout area, and a digital logic circuit layout area; wherein the memory layout area comprises a program memory layout area, a data memory layout area, a peripheral memory layout area, and a firmware memory layout area;

[0006] The digital logic circuit layout area includes a central processing unit layout area and a controller area network bus layout area; the digital logic circuit layout area is arranged in the central area of ​​the layout structure;

[0007] The input and output interface layout area is close to the digital logic circuit layout area;

[0008] The program memory layout area and the data memory layout area are respectively connected to the central processing unit layout area, and the central processing unit layout area is arranged in an area close to the program memory layout area and the data memory layout area;

[0009] The peripheral memory layout area is connected to the controller area network bus layout area, and the controller area network bus layout area is arranged in an area close to the peripheral memory layout area;

[0010] The firmware memory layout area is connected to the digital logic circuit layout area and the program memory layout area respectively. The firmware memory layout area is arranged in an area close to the middle of the layout structure and close to the program memory layout area.

[0011] Furthermore, the digital logic circuit layout area also includes a secure digital output and input layout area, and the peripheral memory layout area is respectively connected to the controller local area network bus layout area and the secure digital output and input layout area, and the controller local area network bus layout area and the secure digital output and input layout area are arranged in an area close to the peripheral memory layout area.

[0012] Furthermore, the input and output interface layout area includes interfaces; the interfaces include input and output interfaces, power interfaces, ground interfaces, interfaces corresponding to clock signals, interfaces corresponding to reset signals, and interfaces corresponding to startup mode signals;

[0013] The interfaces are evenly distributed in the edge area of ​​the layout structure.

[0014] Furthermore, the program memory layout area includes a first memory, and the data memory layout area includes a second memory; the first memory and the off-chip flash memory are connected after logical judgment through the digital logic circuit layout area, and the program memory layout area and the data memory layout area are respectively connected to the central processing unit layout area, including:

[0015] The program memory layout area stores a first program required for the central processing unit in the central processing unit layout area to run based on the first memory;

[0016] The data memory layout area stores temporary data executed by the central processing unit in the central processing unit layout area based on the second memory.

[0017] Furthermore, the peripheral memory layout area includes a third memory and a fourth memory, and the peripheral memory layout area is connected to the controller area network bus layout area and the secure digital input and output layout area respectively, including:

[0018] The peripheral memory layout area stores first data received and sent by the controller area network bus in the controller area network bus layout area based on the third memory, and stores second data received and sent by the safety digital output and input in the safety digital output and input layout area based on the fourth memory.

[0019] Furthermore, the firmware memory layout area includes a fifth memory, and the firmware memory layout area is connected to the digital logic circuit layout area and the program memory layout area respectively, including:

[0020] The firmware memory layout area stores a second program based on the fifth memory. When the microcontroller chip cannot start, the second program is read and started based on the program memory layout area.

[0021] Furthermore, the layout structure further includes: a phase-locked loop layout area; the phase-locked loop layout area is respectively connected to the input / output interface layout area, the digital logic circuit layout area, the program memory layout area, the data memory layout area, and the peripheral memory layout area, and the phase-locked loop layout area is arranged in an area close to the input / output interface layout area and the digital logic circuit layout area, and away from the memory layout area;

[0022] The phase-locked loop layout area is used to generate a target clock signal and output it to the microcontroller chip. The phase-locked loop layout area is arranged in the middle area of ​​the microcontroller chip.

[0023] Furthermore, the phase-locked loop layout area includes a phase detector layout area, a charge pump layout area, a low-pass filter layout area, a voltage-controlled oscillator layout area and a frequency divider layout area.

[0024] Furthermore, the first memory, the second memory, the third memory and the fourth memory are different types of static random access memories, and the fifth memory is a read-only memory;

[0025] The area of ​​the program memory layout area is determined by the first memory;

[0026] The area of ​​the data memory layout region is determined by the second memory;

[0027] The area of ​​the peripheral memory layout area is determined by the third memory and the fourth memory;

[0028] The area of ​​the firmware memory layout area is determined by the fifth memory;

[0029] The area of ​​the program memory layout area is larger than the areas of the data memory layout area, the peripheral memory layout area, and the firmware memory layout area.

[0030] Furthermore, the digital logic circuit layout area also includes: on-chip bus layout area, reset and clock management unit layout area, interrupt and event management unit layout area, timer layout area, watchdog layout area, general input / output layout area, direct memory access layout area, serial peripheral interface / audio bus layout area, universal synchronous / asynchronous receiver and transmitter layout area and integrated circuit bus layout area.

[0031] The present invention also provides a microcontroller chip, comprising the layout structure of the microcontroller chip as described above.

[0032] Beneficial effects of the present invention:

[0033] In an embodiment of the present invention, a layout structure of a microcontroller chip is proposed, in which a memory layout area is subdivided into a program memory layout area, a data memory layout area, a peripheral memory layout area, and a firmware memory layout area, and an input / output interface layout area, a program memory layout area, a data memory layout area, a peripheral memory layout area, a firmware memory layout area, and a digital logic circuit layout area are arranged in a reasonable and compact manner. The program memory layout area and the data memory layout area are arranged in a ring around a central processing unit layout area in the digital logic layout area, thereby enabling the central processing unit layout area to quickly access the program memory layout area and the data memory layout area. The controller local area network bus layout area and the secure digital output and input layout area in the digital logic layout area are arranged in a ring around the peripheral memory layout area, thereby enabling the controller local area network bus layout area and the secure digital output and input layout area to quickly access the peripheral memory layout area. This can optimize the area of ​​the microcontroller chip, reduce the cost of the microcontroller chip, meet the chip timing requirements, and achieve high performance and high reliability. Moreover, through the four layout areas of program memory layout area, data memory layout area, peripheral memory layout area and firmware memory layout area, each memory can be accessed in parallel without affecting each other, that is, the access of the central processing unit layout area in the digital logic layout area to the program memory layout area, data memory layout area and firmware memory layout area and the access of the controller local area network bus layout area and the secure digital output and input layout area in the digital logic layout area to the peripheral memory layout area are independent of each other, thereby speeding up the execution speed and achieving a shorter circuit connection delay between the central processing unit layout area, the controller local area network bus layout area and the secure digital output and input layout area in the digital logic circuit layout area and their corresponding memory layout areas, thereby increasing the clock frequency and improving the performance of the microcontroller chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic diagram of the layout structure of a microcontroller chip according to an embodiment of the present invention;

[0035] Figure 2 This is an example diagram of the layout structure of a microcontroller chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are also within the scope of protection of the present invention.

[0037] The core idea of ​​the embodiment of the present invention is to subdivide the memory layout area into a program memory layout area, a data memory layout area, a peripheral memory layout area and a firmware memory layout area, and to reasonably and compactly layout the input and output interface layout area, the program memory layout area, the data memory layout area, the peripheral memory layout area, the firmware memory layout area and the digital logic circuit layout area. The program memory layout area and the data memory layout area are arranged in a ring around the central processing unit layout area in the digital logic layout area, so as to realize fast access of the central processing unit layout area to the program memory layout area and the data memory layout area. The controller local area network bus layout area and the secure digital output and input layout area in the digital logic layout area are arranged in a ring around the peripheral memory layout area, so as to realize fast access of the controller local area network bus layout area and the secure digital output and input layout area to the peripheral memory layout area. This can realize area optimization of the microcontroller chip, reduce the cost of the microcontroller chip, meet the chip timing requirements at the same time, and achieve high performance and high reliability. Moreover, through the four layout areas of program memory layout area, data memory layout area, peripheral memory layout area and firmware memory layout area, each memory can be accessed in parallel without affecting each other, that is, the access of the central processing unit layout area in the digital logic layout area to the program memory layout area, data memory layout area and firmware memory layout area and the access of the controller local area network bus layout area and the secure digital output and input layout area in the digital logic layout area to the peripheral memory layout area are independent of each other, thereby speeding up the execution speed and achieving a shorter circuit connection delay between the central processing unit layout area, the controller local area network bus layout area and the secure digital output and input layout area in the digital logic circuit layout area and their corresponding memory layout areas, thereby increasing the clock frequency and improving the performance of the microcontroller chip.

[0038] Reference Figure 1 , shows a schematic diagram of the layout structure of a microcontroller chip according to an embodiment of the present invention, which may include the following layout areas:

[0039] Input / output interface layout area 110, memory layout area and digital logic circuit layout area 170; wherein the memory layout area includes program memory layout area 120, data memory layout area 130, peripheral memory layout area 140 and firmware memory layout area 150;

[0040] In an embodiment of the present invention, the memory layout area is subdivided into four different types of memory layout areas: program memory layout area 120, data memory layout area 130, peripheral memory layout area 140, and firmware memory layout area 150. The main purpose of this subdivision of memory layout areas is to enable each part of the system to have its own corresponding dedicated memory, and each memory can be accessed in parallel without affecting each other. That is, the access of the central processing unit layout area in the digital logic layout area to the program memory layout area, data memory layout area, and firmware memory layout area is independent of the access of the controller local area network bus layout area and the secure digital input and output layout area in the digital logic layout area to the peripheral memory layout area, thereby accelerating execution speed. In addition, in an embodiment of the present invention, there is only one analog circuit layout area, namely the phase-locked loop layout area 160. The area of ​​the microcontroller chip with only one analog circuit layout area is reduced, which correspondingly reduces the cost of the microcontroller chip.

[0041] The digital logic circuit layout area 170 includes a central processing unit layout area 171 and a controller area network bus layout area 172; the digital logic circuit layout area is arranged in the central area of ​​the layout structure;

[0042] In the embodiment of the present invention, the CPU layout area includes the CPU, which needs to read and run the program stored in the program logic layout area, and the CAN bus layout area includes the CAN bus, which is a peripheral device that receives and sends data. Figure 1 As shown, the overall layout of the microcontroller chip in this embodiment of the present invention is a square. To facilitate rapid access to various memories, the digital logic circuit layout area is placed in the center of the microcontroller chip's layout structure, followed by various memory layout areas. This layout also facilitates the routing of digital logic circuits within the digital logic circuit layout area.

[0043] The input and output interface layout area 110 is close to the digital logic circuit layout area 170;

[0044] like Figure 1As shown, the layout of the microcontroller chip in the embodiment of the present invention has four edges as a whole, and there are 252 interfaces in the input and output interface layout area, which need to be arranged in an area close to the digital logic circuit layout area, that is, they need to be evenly distributed on the edge area of ​​the layout structure of the microcontroller chip, so there are 63 interfaces on each edge.

[0045] The program memory layout area 120 and the data memory layout area 130 are respectively connected to the central processing unit layout area, and the central processing unit layout area is arranged in an area close to the program memory layout area and the data memory layout area;

[0046] The CPU needs to read and run the program stored in the program logic layout area, and the temporary data obtained needs to be stored in the data logic layout area. Therefore, the program logic layout area and the data storage layout area need to be connected to the CPU layout area for data exchange. To facilitate data exchange between the program logic layout area, the data storage layout area and the CPU layout area, the CPU layout area needs to be laid out in an area close to the program memory layout area and the data memory layout area.

[0047] like Figure 1As shown, the data storage layout area in the embodiment of the present invention includes two static random-access memories (SRAMs) with a bit width of 32 bits and a capacity of 32KB (kilobytes). The layout area is rectangular in shape and has a large area. During layout, the digital logic circuits need to be placed as close together as possible. Therefore, memories such as SRAM cannot be placed in the central area of ​​the layout structure. Therefore, they need to be placed on one side of the digital logic circuit layout area. Here, they can be placed on the right side of the digital logic circuit layout area. The side of the data storage layout area 130 that exchanges data with the digital logic circuit layout area 170 is placed toward the digital logic circuit layout area 170 to facilitate wiring. The program memory layout area contains 4 static random access memories (SRAMs) with a bit width of 32 bits and a capacity of 32KB. Due to the large number of memories in this layout area and the relationship between the bit width and capacity, the area of ​​this layout area is the largest memory layout area in the layout structure of the microcontroller chip, and the 4 SRAMs used in the program memory layout area are all rectangular, which determines that the shape of the program memory layout area is also rectangular. Because of the shape of its memory and the interface that its memory needs to communicate with the digital logic circuit at the bottom, it is determined that the program memory layout area needs to be laid out directly above the layout structure to facilitate the wiring of the digital logic circuit. Therefore, the program memory layout area is laid out in the area on the side of the digital logic circuit layout area away from the short side of the data memory layout area, that is, it can be the shorter side of the data memory layout area (that is, the width of the rectangle), and it is the area on the side where the short side of the data memory layout area is farther away from the digital logic circuit layout area. The side of the program memory layout area 120 that exchanges data with the digital logic circuit layout area 170 is arranged toward the digital logic circuit layout area 170 to facilitate wiring.

[0048] The peripheral memory layout area 140 is connected to the controller area network bus layout area 172, and the controller area network bus layout area is arranged in an area close to the peripheral memory layout area;

[0049] The CAN bus layout area includes the CAN bus. This peripheral receives and sends data, and this data is stored in the memory in the peripheral memory area. Different data types correspond to different memory types. Therefore, to facilitate data exchange between the CAN bus layout area and the peripheral memory layout area, the CAN bus layout area needs to be placed close to the peripheral memory layout area.

[0050] like Figure 1As shown, the peripheral memory layout area includes 6 static random access memories (SRAMs) with a bit width of 32 bits and a capacity of 128B and 1 static random access memory (SRAM) with a bit width of 32 bits and a capacity of 512B. Due to the relationship between the memory bit width and capacity in the peripheral memory layout area, the peripheral memory layout area is rectangular in shape and its area is smaller than the area of ​​the digital logic circuit layout area. Therefore, in order to leave a more regular area for the digital logic circuit, the larger the memory area, the more likely it is to be laid out in the outer area of ​​the layout structure. Therefore, the peripheral memory layout area can be laid out in the area on the side of the data memory layout area close to the long side of the program memory layout area, and the peripheral memory layout area is located in the area on the side close to the long side of the program memory layout area, that is, it can be the area on the side where the long side of the data memory layout area (i.e., the length of the rectangle) is farthest from the edge of the digital logic circuit layout area. The side where the peripheral memory layout area 140 and the digital logic circuit layout area 170 interact with each other is laid out towards the digital logic circuit layout area 170, which is convenient for wiring.

[0051] The firmware memory layout area 150 is connected to the digital logic circuit layout area 170 and the program memory layout area 120 respectively. The firmware memory layout area is arranged near the middle of the layout structure and close to the program memory layout area.

[0052] The firmware memory layout area is primarily used to store the microcontroller chip's bootloader firmware. When the microcontroller chip cannot be started by other means, the bootloader program can be read from the firmware memory layout area and restarted in the program memory layout area. Therefore, the firmware memory layout area needs to be connected to the program memory layout area for data transmission, so the firmware memory layout area needs to be laid out in an area close to the program memory layout area. The firmware memory layout area also needs to be connected to the digital logic circuit layout area. This startup method of reading the bootloader program from the firmware memory layout area and restarting in the program memory layout area is the last startup method for the microcontroller chip. Therefore, the firmware memory layout area has higher security requirements and needs to be laid out in the middle area of ​​the digital logic circuit layout area, that is, in the middle of the layout structure, to reduce the possibility of physical damage.

[0053] like Figure 1As shown, the firmware memory layout area includes a 32-bit read-only memory (ROM) with a capacity of 4KB. Due to the relationship between the memory bit width and capacity in the firmware memory layout area, the area of ​​the firmware memory layout area is the smallest memory layout area in the layout structure of the microcontroller chip, and its area is smaller than the area of ​​the peripheral memory layout area. Therefore, the firmware memory layout area can be arranged on the side of the peripheral memory layout area away from the long side of the edge of the data memory layout area, that is, it can be the longer side of the peripheral memory layout area (i.e., the length of the rectangle), and the side of the peripheral memory layout area is farthest from the edge of the digital logic circuit layout area. In addition, when the microcontroller chip cannot be started by loading the program from an external Flash or directly reading the program in the program memory layout area, it is necessary to load the program stored in the firmware memory layout area 150 into the program memory layout area 120 to enter the flash mode. Therefore, the firmware memory layout area needs to be arranged in an area close to the program memory layout area. The side of the firmware memory layout area 150 that exchanges data with the digital logic circuit layout area 170 is arranged toward the digital logic circuit layout area 170 to facilitate wiring.

[0054] Since the analog circuit in the phase-locked loop layout area has no interference with the read-only memory in the firmware memory layout area, there is no need to consider placing the firmware memory layout area in an area far away from the phase-locked loop layout area.

[0055] The embodiment of the present invention refines the memory layout area into a program memory layout area, a data memory layout area, a peripheral memory layout area and a firmware memory layout area, and reasonably and compactly arranges the input and output interface layout area, the program memory layout area, the data memory layout area, the peripheral memory layout area, the firmware memory layout area and the digital logic circuit layout area. The program memory layout area and the data memory layout area are arranged in a ring around the central processing unit layout area in the digital logic layout area, so as to realize fast access of the central processing unit layout area to the program memory layout area and the data memory layout area. The controller local area network bus layout area and the secure digital output and input layout area in the digital logic layout area are arranged in a ring around the peripheral memory layout area, so as to realize fast access of the controller local area network bus layout area and the secure digital output and input layout area to the peripheral memory layout area. This can realize area optimization of the microcontroller chip, reduce the cost of the microcontroller chip, meet the chip timing requirements at the same time, and realize high performance and high reliability. Moreover, through the four layout areas of program memory layout area, data memory layout area, peripheral memory layout area and firmware memory layout area, each memory can be accessed in parallel without affecting each other, that is, the access of the central processing unit layout area in the digital logic layout area to the program memory layout area, data memory layout area and firmware memory layout area and the access of the controller local area network bus layout area and the secure digital output and input layout area in the digital logic layout area to the peripheral memory layout area are independent of each other, thereby speeding up the execution speed and achieving a shorter circuit connection delay between the central processing unit layout area, the controller local area network bus layout area and the secure digital output and input layout area in the digital logic circuit layout area and their corresponding memory layout areas, thereby increasing the clock frequency and improving the performance of the microcontroller chip.

[0056] In one embodiment of the present invention, the digital logic circuit layout area 170 also includes a secure digital output and input layout area 173, and the peripheral memory layout area 140 is respectively connected to the controller local area network bus layout area 172 and the secure digital output and input layout area 173, and the controller local area network bus layout area and the secure digital output and input layout area are arranged in an area close to the peripheral memory layout area.

[0057] Specifically, the CAN bus layout area includes the CAN bus, and the SDI layout area includes the SDI. The CAN bus and SDI peripherals receive and send data, which is stored in the memory in the peripheral memory layout area. Different data types correspond to different memory types. Therefore, to facilitate data exchange between the CAN bus layout area, the SDI layout area, and the peripheral memory layout area, the CAN bus layout area and the SDI layout area need to be placed close to the peripheral memory layout area.

[0058] In one embodiment of the present invention, the input / output interface layout area 110 includes interfaces; the interfaces include an input / output interface, a power interface, a ground interface, an interface corresponding to a clock signal, an interface corresponding to a reset signal, and an interface corresponding to a startup mode signal;

[0059] The interfaces are evenly distributed in the edge area of ​​the layout structure.

[0060] Specifically, the input / output interface layout area 110 includes a total of 252 interfaces, each evenly distributed on the edge of the layout structure, including 84 signal input / output interfaces. At the same time, it provides the power interface and ground interface required for the operation of the microcontroller chip, interfaces corresponding to clock signals, interfaces corresponding to reset signals, and interfaces corresponding to boot mode signals. Among them, the power interface includes 12 3.3V power interfaces and 15 1.8V power interfaces, and the number of ground interfaces is 24. The clock signals include LSI (Low Speed ​​Inter, low-speed internal clock), HSI (High Speed ​​Inter, high-speed internal clock), LSE (Low Speed ​​Ester, low-speed external clock), and HSE (High Speed ​​Ester, high-speed external clock). The LSI, HSI, and LSE clocks each have a single signal input. The HSE clock is a connected external crystal oscillator with one input signal and one output signal. The input signal refers to the clock signal that can be used within the microcontroller chip, and the output signal is the signal used for the operation of the external crystal oscillator. Then the number of interfaces corresponding to the clock signal is 5 in total, and the number of interfaces corresponding to the reset signal and the number of interfaces corresponding to the startup mode signal are both 2.

[0061] In one embodiment of the present invention, the program memory layout area 120 includes a first memory, and the data memory layout area 130 includes a second memory; the first memory and the off-chip flash memory are connected after logical judgment is performed by the digital logic circuit layout area, and the program memory layout area 120 and the data memory layout area 130 are respectively connected to the central processing unit layout area 171, including:

[0062] The program memory layout area 120 stores the first program required for the central processing unit to run in the central processing unit layout area 171 based on the first memory;

[0063] The data memory layout area 130 stores temporary data executed by the CPU in the CPU layout area 171 based on the second memory.

[0064] Among them, the program memory layout area and the data memory layout area are mainly used to store the programs and temporary data required for the operation of the central processing unit in the digital logic circuit layout area. When the CPU (Central Processing Unit) executes the program, it involves reading and writing data. Temporary data during the program operation needs to be stored. However, as the execution speed of the CPU becomes faster, the speed of storing temporary data also needs to keep up with the speed of the CPU. Therefore, the memory in the data memory layout area can be selected from static random access memory (SRAM) with high-speed characteristics. In this way, when the CPU runs the program, it will copy the temporary data to the SRAM, and the next time it is used, it can be read directly from the SRAM, thereby improving the running speed of the program.

[0065] Specifically, the program memory layout area 120 includes 4 first memories, and the first memory is a static random access memory (SRAM) with a bit width of 32 bits and a capacity of 32KB. Since there is no built-in flash memory (Flash) in the microcontroller chip, when the microcontroller chip is powered on and started, the program memory layout area will read the first program stored in the off-chip flash memory (Flash) and store it in the first memory. The microcontroller chip will read the first program in the first memory through the central processing unit (CPU) in the digital logic circuit layout area and execute it. The data memory layout area 130 includes 2 second memories, and the second memory is a static random access memory (SRAM) with a bit width of 32 bits and a capacity of 32KB. The second memory in the data memory layout area is mainly used to store temporary data generated when the CPU in the central processing unit (CPU) layout area executes the first program, such as some variables, cached data and other data during the operation of the first program.

[0066] In one embodiment of the present invention, the peripheral memory layout area 140 includes a third memory and a fourth memory, and the peripheral memory layout area 140 is connected to the controller area network bus layout area 172 and the secure digital input and output layout area 173, respectively, including:

[0067] The peripheral memory layout area 140 stores the first data received and sent by the controller area network bus in the controller area network bus layout area based on the third memory, and stores the second data received and sent by the safety digital output and input in the safety digital output and input layout area based on the fourth memory.

[0068] The peripheral memory layout area is used to store data received and to be sent by the two peripherals, the controller area network bus and the secure digital input and output in the digital logic circuit layout area.

[0069] Specifically, the peripheral memory layout area 140 includes six third memories and one fourth memory. The third memory is a static random access memory (SRAM) with a bit width of 32 bits and a capacity of 128 bytes, and the fourth memory is a static random access memory (SRAM) with a bit width of 32 bits and a capacity of 512 bytes. The controller area network bus layout area in the digital logic circuit layout area 170 includes three CAN / CANFD (Controller Area Network / CAN with Flexible Data Rate) channels. Each CAN / CANFD channel requires two SRAMs for temporary storage of send and receive data. The secure digital input and output layout area includes an SDIO (Secure Digital Input and Output) interface. The third memory is used for data transmission and reception buffering of the three CAN / CANFD channels. The third memory is an SRAM exclusively for CAN communication and can only be accessed by the CAN communication module. The fourth memory is used for data transmission and reception buffering of SDIO.

[0070] CAN / CANFD channels require data caching during transmission and reception to ensure data sequentiality and real-time performance. Using two independent SRAMs allows for separate storage of transmit and receive data, avoiding data conflicts and confusion. This effectively isolates transmit and receive data, preventing data interference and errors. This allows for more convenient processing of transmit and receive data, improving data processing efficiency. This allows for parallel transmission and reception, increasing data transmission efficiency and system response speed.

[0071] SDIO is a peripheral interface evolved from the SD memory card interface. SDIO typically uses single-channel data transmission, meaning only one channel of data can be sent or received at a time. SDIO typically features a data flow control mechanism, allowing software to control the data transmission and reception rates to prevent data loss and overflow. This allows a single memory device to suffice for data transmission and reception. Compared to CAN / CANFD channels, SDIO data processing is generally simpler, eliminating the need for complex data caching and processing mechanisms. In summary, a single memory device can meet the data transmission and reception buffering requirements of SDIO.

[0072] The third and fourth memories here cannot use the same type of SRAM. Since different components in the system require different storage spaces, different types of SRAM need to be selected during design based on the storage space requirements of the components. Using the same type of SRAM for both may result in a large amount of waste. For example, SDIO only requires 512B of SRAM. If a second memory with a capacity of 32KB is used for both, a large amount of microcontroller chip area will be wasted, thereby increasing the cost of the microcontroller.

[0073] In one embodiment of the present invention, the firmware memory layout area 150 includes a fifth memory, and the firmware memory layout area 150 is connected to the digital logic circuit layout area and the program memory layout area respectively, including:

[0074] The firmware memory layout area 150 stores a second program based on the fifth memory. When the microcontroller chip cannot start, the second program is read and started based on the program memory layout area.

[0075] Among them, the firmware memory layout area mainly stores the Bootloader firmware of the microcontroller chip. When the microcontroller chip cannot be started by other means, the Bootloader program can be read from the firmware memory layout area and loaded into the program memory layout area to restart.

[0076] Specifically, the firmware memory layout area 150 includes a fifth memory, which is a read-only memory (ROM) with a bit width of 32 bits and a capacity of 4KB. The fifth memory is used to store the second program, namely the Bootloader program. When the microcontroller chip cannot be started from the external Flash loader program, or directly read the program in the program memory layout area, the fifth memory can provide the second program for the microcontroller chip to enter the flash mode and flash the program for the off-chip flash memory. Since the Bootloader program needs to be stored in a memory that cannot be tampered with and can keep the data from being lost after the system power is off, ROM has this feature and is suitable for storing the Bootloader program, while the data stored in SRAM can be modified, and the data therein will be lost after the system power is off, so it is not suitable for storing the Bootloader program. Therefore, it is different from the types of the aforementioned first memory, second memory, third memory and fourth memory.

[0077] The bootloader is a program loading code stored in Flash memory, connecting the underlying hardware to the application. Its main function is to initialize the microprocessor and peripheral circuits for normal operation, establish a memory map, bring the system's hardware and software environment to a suitable state, and load the system program from Flash memory.

[0078] The layout of each of the aforementioned memory layout areas is primarily based on leaving as much space as possible for the digital logic circuit layout area 170, facilitating the wiring of the digital logic circuits within the digital logic circuit layout area 170. Furthermore, after the aforementioned refinement of the memory layout areas, the circuit connections between the CPU layout area, the CAN bus layout area, and the secure digital input / output layout area within the digital logic circuit layout area and their corresponding memories have relatively shorter delays, thereby increasing the clock frequency and, in turn, improving the performance of the microcontroller chip.

[0079] In one embodiment of the present invention, Figure 1 As shown, the layout structure further includes: a phase-locked loop layout area 160; the phase-locked loop layout area 160 is respectively connected to the input / output interface layout area 110, the digital logic circuit layout area 170, the program memory layout area 120, the data memory layout area 130, and the peripheral memory layout area 140, and the phase-locked loop layout area is arranged in an area close to the input / output interface layout area and the digital logic circuit layout area, and away from the memory layout area;

[0080] The phase-locked loop layout area 160 is used to generate a target clock signal and output it to the microcontroller chip. The phase-locked loop layout area is arranged in the middle area of ​​the microcontroller chip.

[0081] The highest system clock signal generated by the PLL frequency multiplication in the PLL layout area is the microcontroller chip's primary clock signal, or target clock signal. This signal is used by all layout areas within the microcontroller chip, meaning the PLL layout area must be connected to the input / output interface layout area, the digital logic circuit layout area, and the memory layout area. To ensure relatively stable and synchronized clock delays across each layout area, the target clock signal output by the PLL layout area should be symmetrically output to each layout area of ​​the microcontroller chip (similar to a fishbone diagram). This reduces the number of clock buffers required in the clock tree during clock tree synthesis, thereby reducing the microcontroller chip's area, power consumption, and cost.

[0082] In addition, the phase-locked loop in the phase-locked loop layout area is mainly composed of analog circuits, which will generate certain electromagnetic interference when working, which has a greater impact on high-speed static random access memory that has high requirements for timing and stability. However, since the read-only memory has the characteristics of not being tampered with and maintaining data even after the system power is off, the electromagnetic interference generated by the analog circuit in the phase-locked loop layout area when working will not affect the read-only memory. Therefore, the phase-locked loop layout area needs to be laid out in an area away from the program memory layout area, the data memory layout area and the peripheral memory layout area. The layout away from the static random access memory can reduce the impact of electromagnetic interference, thereby reducing the use of other electromagnetic shielding measures, such as the need to set up multiple power domains, clock and signal wiring, thereby reducing the area of ​​the microcontroller chip and reducing the cost of the microcontroller chip.

[0083] To summarize, the phase-locked loop layout area needs to be arranged close to the input and output interface layout area and the digital logic circuit layout area, and away from the program memory layout area, the data memory layout area and the peripheral memory layout area.

[0084] like Figure 1 As shown, the phase-locked loop layout area 160 needs to receive the clock signal input from the outside through the input and output interface layout area 110, and will multiply the received clock signal to generate the highest system clock signal and output it to each layout area of ​​the microcontroller chip. In order to ensure that the clock delay of each layout area is relatively stable and synchronized, the phase-locked loop layout area processing needs to be arranged in an area close to the input and output interface layout area and the digital logic circuit layout area, and away from the program memory layout area, the data memory layout area and the peripheral memory layout area. It needs to be arranged in an area close to the input and output interface layout area and in the middle area of ​​the layout structure.

[0085] Therefore, the phase-locked loop layout area can be arranged in the area on the side of the data storage layout area that is away from the digital logic circuit layout area on the long side. Here, since the data storage layout area is located in the right area of ​​the digital logic circuit layout area, the phase-locked loop layout area can be arranged in the middle area on the left side of the digital logic circuit layout area.

[0086] There are several possibilities for electromagnetic interference generated by analog circuits in the phase-locked loop layout area when working: (1) High-frequency clock signal: Phase-locked loops often involve the generation and transmission of high-frequency clock signals. These high-frequency signals will cause electromagnetic radiation in the circuit, thereby generating electromagnetic interference. (2) Signal transmission line: The analog circuits in the phase-locked loop usually need to transmit signals through signal transmission lines, and long or high-speed signal transmission lines may cause signal crosstalk and radiation, leading to electromagnetic interference. (3) Power supply noise: The analog circuits in the phase-locked loop have high requirements for power supply stability. The noise of the power supply will affect the stability of the phase-locked loop, thereby generating electromagnetic interference. (4) Ground return path: In the analog circuit of the phase-locked loop, the design of the ground return path will also affect electromagnetic compatibility. Poor ground design will lead to a blocked ground return path, generating electromagnetic interference. (5) Electromagnetic compatibility design: Whether the layout and design of the phase-locked loop analog circuit meet the electromagnetic compatibility requirements will also affect the generation of electromagnetic interference.

[0087] In one embodiment of the present invention, the phase-locked loop layout area 160 includes a phase detector layout area, a charge pump layout area, a low-pass filter layout area, a voltage-controlled oscillator layout area, and a frequency divider layout area.

[0088] The target clock signal generated by the phase-locked loop frequency multiplication in the phase-locked loop layout area is used by all layout areas in the microcontroller chip. That is, the phase-locked loop layout area needs to be connected to the input and output interface layout area, the digital logic circuit layout area, and the memory layout area. To ensure that the clock delays in each layout area are relatively stable and synchronized, the target clock signal output by the phase-locked loop layout area should be symmetrically output to each layout area of ​​the microcontroller chip (similar to the shape of a fishbone diagram). This can reduce the number of clock buffers added to the clock tree during clock tree synthesis, thereby reducing the area of ​​the microcontroller chip, reducing power consumption and the cost of the microcontroller chip.

[0089] For example, the highest system clock frequency in a microcontroller chip can reach 80MHz, while the off-chip input clock frequency is generally 8MHz or 16MHz, requiring frequency multiplication to meet the system's operating frequency requirements. Therefore, the phase-locked loop (PLL) layout area 160 needs to multiply the off-chip input clock to generate the highest system clock signal. This means that the PLL layout area 160 receives the external clock signal input via the input / output interface layout area 110 and multiplies the received clock signal to generate the highest system clock signal, i.e., the target clock signal. This target clock signal is primarily used for the digital logic circuit portion of the digital logic circuit layout area 170. The operating principle of the PLL is primarily based on negative feedback control. It detects the phase difference between the input and output signals and converts this phase difference into a voltage signal to control the frequency of the voltage-controlled oscillator (VCO), thereby ensuring that the frequency and phase of the output signal remain consistent with the input signal. Specifically, the core of the PLL layout area 160's frequency multiplication of the received clock signal is the VCO layout area.

[0090] Because phase-locked loop (PLL) layout area 160 is an analog circuit module, the layout of the phase detector, charge pump, low-pass filter, voltage-controlled oscillator, and frequency divider areas requires detailed circuit simulation to ensure that the output target clock signal frequency meets the required frequency. Furthermore, the present embodiment contains only one analog circuit module, namely a PLL (Phase-locked Loop), in phase-locked loop (PLL) layout area 160. Compared to conventional microcontroller chips that include multiple analog circuit modules, the microcontroller chip in the present embodiment has a smaller area, and accordingly, the cost of the microcontroller chip is reduced.

[0091] The phase detector layout is responsible for detecting the phase difference between the input and output signals and converting this phase difference into a voltage signal. The charge pump layout is primarily responsible for converting the clock phase difference output by the phase detector into an electric charge, which is then passed to the low-pass filter layout to generate a voltage that controls the voltage-controlled oscillator layout. The low-pass filter layout is used to filter out high-frequency noise, retaining only low-frequency components to ensure a stable voltage signal output by the phase detector layout. The voltage-controlled oscillator layout adjusts its frequency based on the voltage signal output by the phase detector to keep the frequency and phase of the output signal consistent with the input signal. The frequency divider layout is responsible for dividing the output signal of the voltage-controlled oscillator layout.

[0092] In one embodiment of the present invention, the digital logic circuit layout area 170 also includes: an on-chip bus layout area, a reset and clock management unit layout area, an interrupt and event management unit layout area, a timer layout area, a watchdog layout area, a general input / output layout area, a direct memory access layout area, a serial peripheral interface / audio bus layout area, a universal synchronous / asynchronous receiver / transmitter layout area and an integrated circuit bus layout area.

[0093] Specifically, in the digital logic circuit layout area 170, synthesis tools convert the RTL code into a circuit consisting of AND, OR, NOT gates, and flip-flops, known as a gate-level netlist. The gate-level netlist contains actual circuit information, such as the fan-in and fan-out coefficients of the logic gate units, delays, and so on. Placement and routing tools then perform physical layout and routing on the gate-level netlist, determining the location and connection of each logic gate to meet performance, power consumption, and area requirements. The digital logic circuit layout area 170 includes layout areas for the on-chip bus, reset and clock management unit (RCMU), interrupt and event management unit (IEMU), timer (TIMMER), watchdog timer (IWDG / WWDG), general-purpose input / output (GPIO), direct memory access (DMA), serial peripheral interface / audio bus (SPI / I2S), universal synchronous / asynchronous receiver / transmitter (USART), and integrated circuit bus (I2C).

[0094] The digital logic circuit layout area 170 mainly contains the digital logic circuit part. The layout of each internal layout area is mainly automatically performed by EDA (Electronic Design Automation) tools, which mainly depends on the constraints during logic synthesis. EDA tools can generally be divided into three categories: (1) Comprehensive design tools. Mainly used in Fabless factories (fabless factories) to complete various levels of design such as system integration, logic synthesis, layout and routing. (2) Simulation tools. Verify the correctness of the design and optimize the design structure, including circuit simulation and verification, physical design rule checking, etc. (3) Test and data management tools. Mainly used in Foundry factories (foundries) to complete the design of test chips, improve test accuracy, and conduct data analysis of manufacturing processes and finished products.

[0095] In one embodiment of the present invention, the first memory, the second memory, the third memory, and the fourth memory are different types of static random access memories, and the fifth memory is a read-only memory;

[0096] The area of ​​the program memory layout area is determined by the first memory;

[0097] The area of ​​the data memory layout region is determined by the second memory;

[0098] The area of ​​the peripheral memory layout area is determined by the third memory and the fourth memory;

[0099] The area of ​​the firmware memory layout area is determined by the fifth memory;

[0100] The area of ​​the program memory layout area is larger than the areas of the data memory layout area, the peripheral memory layout area, and the firmware memory layout area.

[0101] Specifically, due to SRAM's fast operating speed, which is closer to that of registers, on-chip memory is generally chosen over other types of memory. Therefore, the first, second, third, and fourth memories are all SRAM, with the quantity, bit width, and capacity of the different memories being set according to the requirements of the corresponding components in the different memory layout areas. Because ROM can store data without losing it after a system power outage and cannot be modified, ROM is selected as the fifth memory for storing the bootloader program. This ensures the security and reliability of the bootloader program, thereby achieving high performance and reliability.

[0102] The size of each memory layout area is determined by the number, bit width, and capacity of the corresponding memory in the layout area. The area of ​​SRAM is usually proportional to its bit width. SRAM with a larger bit width requires more memory cells and data lines, and therefore requires more transistors and circuits, thus occupying a larger chip area. The area of ​​SRAM is also usually proportional to its capacity. SRAM with a larger capacity requires more memory cells, and therefore requires more transistors and circuits, thus occupying a larger chip area. Due to the relationship between the memories, the shape of each memory layout area is rectangular, and the area of ​​the program memory layout area is larger than the area of ​​the data memory layout area, the peripheral memory layout area, and the firmware memory layout area.

[0103] In an embodiment of the present invention, the memory layout area is subdivided into a program memory layout area, a data memory layout area, a peripheral memory layout area, and a firmware memory layout area, and the seven layout areas, namely the input / output interface layout area, the program memory layout area, the data memory layout area, the peripheral memory layout area, the firmware memory layout area, the phase-locked loop layout area, and the digital logic circuit layout area, are rationally and compactly arranged. The program memory layout area and the data memory layout area are arranged in a ring around the central processing unit layout area in the digital logic layout area, so that the central processing unit layout area can quickly access the program memory layout area and the data memory layout area. The controller area network bus layout area and the secure digital output and input layout area in the digital logic layout area are arranged in a ring around the peripheral memory layout area, so that the controller area network bus layout area and the secure digital output and input layout area can quickly access the peripheral memory layout area. This can optimize the area of ​​the microcontroller chip, reduce the cost of the microcontroller chip, meet the chip timing requirements, and achieve high performance and high reliability. Moreover, through the four layout areas of program memory layout area, data memory layout area, peripheral memory layout area and firmware memory layout area, each memory can be accessed in parallel without affecting each other, that is, the access of the central processing unit layout area in the digital logic layout area to the program memory layout area, data memory layout area and firmware memory layout area and the access of the controller local area network bus layout area and the secure digital output and input layout area in the digital logic layout area to the peripheral memory layout area are independent of each other, thereby speeding up the execution speed and achieving a shorter circuit connection delay between the central processing unit layout area, the controller local area network bus layout area and the secure digital output and input layout area in the digital logic circuit layout area and their corresponding memory layout areas, thereby increasing the clock frequency and improving the performance of the microcontroller chip.

[0104] Reference Figure 2 , shows an example diagram of the layout structure of a microcontroller chip according to an embodiment of the present invention, Figure 2 It also includes an input and output interface layout area 210, a program memory layout area 220, a data memory layout area 230, a peripheral memory layout area 240, a firmware memory layout area 250, a phase-locked loop layout area 260 and a digital logic circuit layout area 270.

[0105] An embodiment of the present invention further provides a microcontroller chip, which may include the layout structure of the microcontroller chip as described above.

[0106] In practical applications, an MCU is a multifunctional chip that combines a processor core, memory, and peripheral functions. MCU chip types include 8-bit, 16-bit, and 32-bit architectures to meet different application requirements. 8-bit MCU chips are typically used in low-power and cost-sensitive applications, such as home appliances and small electronic devices. 16-bit MCU chips are generally suitable for medium-complexity applications, such as communications equipment and industrial control. 32-bit MCU chips are suitable for high-end applications, such as automotive electronics and smartphones.

[0107] As a complete system, the MCU chip has multiple functions to meet various needs. First, it has a processor core that can perform tasks such as arithmetic operations, logical operations, and data processing. Different types of MCU chips may use different processor cores.

[0108] MCU chips have a variety of memories, including flash memory, RAM (Random Access Memory), and EEPROM (Electrically Erasable Programmable Read-Only Memory). These memories are used to store program code, data, and configuration information. Flash memory is usually used to store rewritable program code, RAM is used for temporary data storage, and EEPROM is used to store non-volatile data.

[0109] In addition to the processor core and memory, MCU chips also include a large number of peripheral functions to meet the connection requirements of various external devices. Common peripherals include general-purpose input and output (GPIO), timers, serial communication interfaces (SPI, I2C, UART), and analog-to-digital converters (ADCs). These peripherals enable MCU chips to communicate with other devices, collect sensor data, and control external devices.

[0110] MCU chips also have the characteristics of low power consumption and real-time performance. Low power consumption is because MCU chips are usually used in portable devices and battery-powered systems, and the battery life needs to be extended as much as possible. Real-time performance means that the MCU chip can respond to external events in a timely manner and perform corresponding tasks, such as real-time control systems.

[0111] The microcontroller chip provided in the embodiments of the present invention can be applied to the automotive field, such as engine management systems, body control systems, audio systems, safety systems, etc. In these systems, the MCU chip can realize data acquisition, processing, control, communication and other functions, thereby improving the performance, safety and comfort of the car; the microcontroller chip can also be applied to the industrial control field, such as PLC (Programmable Logic Controller), industrial robots, smart instruments, sensors, etc. In these applications, the MCU chip can realize data acquisition, processing, control, communication and other functions, thereby improving the intelligence level and production efficiency of industrial control; the microcontroller chip can also be applied to the consumer electronics field, such as mobile phones, tablets, smart watches, smart speakers, etc. In these products, the MCU chip can realize data processing, communication, timing control and other functions, thereby improving the intelligence level of electronic products and user experience.

[0112] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0113] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0114] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0115] The above is a detailed introduction to the layout structure of a microcontroller chip and a microcontroller chip provided. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A layout structure of a microcontroller chip, characterized in that: The layout structure includes: an input and output interface layout area, a memory layout area, and a digital logic circuit layout area; wherein the memory layout area includes a program memory layout area, a data memory layout area, a peripheral memory layout area, and a firmware memory layout area; The digital logic circuit layout area includes a central processing unit layout area and a controller area network bus layout area; the digital logic circuit layout area is arranged in the central area of ​​the layout structure; The input and output interface layout area is close to the digital logic circuit layout area; The program memory layout area and the data memory layout area are respectively connected to the central processing unit layout area, and the central processing unit layout area is arranged in an area close to the program memory layout area and the data memory layout area; The peripheral memory layout area is connected to the controller area network bus layout area, and the controller area network bus layout area is arranged in an area close to the peripheral memory layout area; The firmware memory layout area is connected to the digital logic circuit layout area and the program memory layout area respectively. The firmware memory layout area is arranged in an area close to the middle of the layout structure and close to the program memory layout area.

2. The layout structure of the microcontroller chip according to claim 1, characterized in that: The digital logic circuit layout area also includes a secure digital output and input layout area. The peripheral memory layout area is connected to the controller area network bus layout area and the secure digital output and input layout area respectively. The controller area network bus layout area and the secure digital output and input layout area are arranged in an area close to the peripheral memory layout area.

3. The layout structure of the microcontroller chip according to claim 1, characterized in that: The input and output interface layout area includes interfaces; the interfaces include input and output interfaces, power interfaces, ground interfaces, interfaces corresponding to clock signals, interfaces corresponding to reset signals, and interfaces corresponding to startup mode signals; The interfaces are evenly distributed in the edge area of ​​the layout structure.

4. The layout structure of the microcontroller chip according to claim 2, characterized in that: The program memory layout area includes a first memory, and the data memory layout area includes a second memory; the first memory and the off-chip flash memory are logically connected through the digital logic circuit layout area. After the judgment, the connection is performed, and the program memory layout area and the data memory layout area are respectively connected to the central processing unit layout area, including: The program memory layout area stores a first program required for the central processing unit in the central processing unit layout area to run based on the first memory; The data memory layout area stores temporary data executed by the central processing unit in the central processing unit layout area based on the second memory.

5. The layout structure of the microcontroller chip according to claim 4, characterized in that: The peripheral memory layout area includes a third memory and a fourth memory, and the peripheral memory layout area is connected to the controller area network bus layout area and the secure digital input and output layout area respectively, including: The peripheral memory layout area stores first data received and sent by the controller area network bus in the controller area network bus layout area based on the third memory, and stores second data received and sent by the safety digital output and input in the safety digital output and input layout area based on the fourth memory.

6. The layout structure of the microcontroller chip according to claim 5, characterized in that: The firmware memory layout area includes a fifth memory, and the firmware memory layout area is connected to the digital logic circuit layout area and the program memory layout area respectively, including: The firmware memory layout area stores a second program based on the fifth memory. When the microcontroller chip cannot start, the second program is read and started based on the program memory layout area.

7. The layout structure of the microcontroller chip according to claim 1, characterized in that: The layout structure further includes: a phase-locked loop layout area; the phase-locked loop layout area is respectively connected to the input / output interface layout area, the digital logic circuit layout area, the program memory layout area, the data memory layout area, and the peripheral memory layout area, and the phase-locked loop layout area is arranged in an area close to the input / output interface layout area and the digital logic circuit layout area, and away from the memory layout area; The phase-locked loop layout area is used to generate a target clock signal and output it to the microcontroller chip. The phase-locked loop layout area is arranged in the middle area of ​​the microcontroller chip.

8. The layout structure of the microcontroller chip according to claim 7, characterized in that: The phase-locked loop layout area includes a phase detector layout area, a charge pump layout area, a low-pass filter layout area, a voltage-controlled oscillator layout area and a frequency divider layout area.

9. The layout structure of the microcontroller chip according to claim 6, characterized in that: The first memory, the second memory, the third memory and the fourth memory are different types of static random access memories, and the fifth memory is a read-only memory; The area of ​​the program memory layout area is determined by the first memory; The area of ​​the data memory layout region is determined by the second memory; The area of ​​the peripheral memory layout area is determined by the third memory and the fourth memory; The area of ​​the firmware memory layout area is determined by the fifth memory; The area of ​​the program memory layout area is larger than the areas of the data memory layout area, the peripheral memory layout area, and the firmware memory layout area.

10. The layout structure of the microcontroller chip according to claim 9, characterized in that: The digital logic circuit layout area also includes: on-chip bus layout area, reset and clock management unit layout area, interrupt and event management unit layout area, timer layout area, watchdog layout area, general input / output layout area, direct memory access layout area, serial peripheral interface / audio bus layout area, universal synchronous / asynchronous receiver / transmitter layout area and integrated circuit bus layout area.

11. A microcontroller chip, characterized in that: The microcontroller chip includes: the layout structure of the microcontroller chip according to any one of claims 1 to 10.

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