Quantum chip design method and system

Abstract

The invention discloses a quantum chip design method and system. The design method comprises the steps of blank layout generation, device selection and insertion, automatic layout and wiring, simulation and iterative optimization of parameters, anti-interference structure and mark addition and the like. The system comprises an automatic design system, a simulation system and a layout generation system, and can automatically perform layout, wiring, geometric parameter simulation and the like and generate a final layout. According to the method, an integrated system is constructed, an automatic module is integrated, an intelligent algorithm and multi-simulation mutual verification are combined, full-process automation is achieved, the design efficiency and precision of the superconducting quantum chip are improved, personal errors are reduced, the limitation of traditional module splitting and manual parameter adjustment is broken through, and an efficient and accurate scheme is provided for rapid research and development of large-scale chips.

Description

Technical Field

[0001] The present invention belongs to the field of quantum chip technology, and specifically relates to a quantum chip design method and system. Background Art

[0002] Superconducting quantum computing, one of the mainstream implementations of quantum computing, has made significant progress in multiple research areas. Superconducting qubits, due to their efficient quantum state manipulation, relatively long coherence time, and ease of integration and scalability, have become a promising candidate for large-scale quantum computing. However, as the number of qubits increases, the automated design and implementation of large-scale superconducting quantum chips faces numerous technical obstacles due to increased design complexity and precision requirements.

[0003] To address this issue, related technologies, such as Chinese patent CN113705149A, provide an architectural implementation method for a quantum chip design assistance tool. Although this method can provide some auxiliary functions for chip design, manual adjustment of design parameters, control circuits, and quantum bit layout is still required during the actual design process, which can easily introduce human errors. This not only reduces design efficiency, but also leads to insufficient performance and accuracy of the designed chip, reducing the reliability of quantum computing. Summary of the Invention

[0004] The purpose of the present invention is to propose a quantum chip design method and system to solve the problems in the prior art.

[0005] To this end, the present invention provides a quantum chip design method, which specifically includes the following steps:

[0006] Obtaining devices required for quantum chip design, automatically laying out quantum bits on the quantum chip based on the configuration task, and automatically routing the laid-out quantum chip to generate an initial chip layout;

[0007] receiving the initial chip layout, and performing simulation optimization on the quantum chip based on the quantum chip parameter indicators of the configuration task to obtain layout parameters that meet the design indicators;

[0008] Based on the initial chip layout and the layout parameters, air bridges, magnetic flux traps, and markers are generated on the initial chip layout to generate a final layout.

[0009] Optionally, the step of obtaining devices required for quantum chip design, automatically laying out quantum bits of the quantum chip based on the configuration task, and automatically routing the laid-out quantum chip to generate an initial chip layout includes:

[0010] S100, generating a blank chip layout;

[0011] S200, selecting a custom device or a preset device, initializing functional parameters of the device, and inserting the device into the blank chip layout;

[0012] S300, automatically laying out quantum bits of the quantum chip according to the configuration task, processing external parameters according to the configuration task, and determining interface positions of pins of the quantum chip;

[0013] S400: Generate wiring paths between devices in a chip layout based on wiring constraints, optimize and adjust the wiring paths, and generate an initial chip layout.

[0014] Optionally, the step of receiving the initial chip layout and performing simulation optimization on the quantum chip based on the chip parameter indicators of the configuration task to obtain layout parameters that meet design indicators includes:

[0015] S500, obtaining a subsystem in the initial chip layout, applying design parameters to the subsystem, and starting simulation;

[0016] S600: After completing the simulation, obtain basic characteristic parameters of the quantum bit for quantization calculation, obtain a first quantum chip index, and compare the first quantum chip index with the quantum chip parameter index of the configuration task to determine whether it is necessary to iteratively optimize the design parameters. If not, go to step S700; if so, return to step S500 for iterative optimization;

[0017] S700, determining whether there is an adjustable coupler;

[0018] If not, calculate the ZZ coupling strength between the quantum bits and compare the ZZ coupling strength with the quantum chip parameter index of the configuration task to determine whether it is necessary to iteratively optimize the design parameters. If so, go to step S500 for iterative optimization; otherwise, go to step S900;

[0019] If yes, go to step S800;

[0020] S800, calculating the full Hamiltonian, and obtaining the second quantum chip index through the full Hamiltonian, and comparing it with the quantum chip parameter index of the configuration task to determine whether it meets the requirements of the quantum chip parameter index. If so, proceed to step S900; if not, return to step S500 for iterative optimization;

[0021] S900, save the actual indicator parameters and exit.

[0022] Optionally, the step of generating air bridges, flux traps, and markers on the initial chip layout based on the initial chip layout and the layout parameters to generate a final layout includes:

[0023] S1000, obtaining the initial chip layout and the layout parameters;

[0024] S1100, generating air bridges and magnetic flux traps on the initial chip layout;

[0025] S1200, establish a Josephson junction, each device corresponds to a different Josephson junction;

[0026] S1300, dividing the initial chip layout into a plurality of sub-layouts, and obtaining corresponding layout parameters for each sub-layout;

[0027] S1400: Mark the initial chip layout or a plurality of sub-layouts to obtain a final chip layout.

[0028] Optionally, in step S400 , the routing constraints include routing length, distance between lines, and number of bends.

[0029] Optionally, in step S500, the subsystem includes at least a quantum bit and a coupling device.

[0030] Optionally, in step S500 , when performing simulation, the corresponding simulation mode adopted includes Q3D mode, EPR intrinsic mode or black-box mode.

[0031] Optionally, in step S600, the first quantum chip indicators include quantum bit frequency, resonant cavity frequency, anharmonicity, and coupling strength.

[0032] Optionally, in step S800, the step of calculating the full Hamiltonian includes:

[0033] Calculate the system energy level and draw an energy level diagram to observe whether there is a two-level system in the magnetic flux modulation path of the adjustable coupler through the energy level diagram;

[0034] Calculate and plot the ZZ coupling strength versus frequency and flux to determine the on / off ratio.

[0035] Calculate and plot the effective coupling strength as a function of frequency and magnetic flux to determine the cut-off frequency.

[0036] On the other hand, a quantum chip design system is also provided, comprising:

[0037] An automated design system acquires the devices required for quantum chip design, automatically lays out the quantum bits of the quantum chip based on the configuration task, and automatically routes the laid-out quantum chip to generate an initial chip layout;

[0038] An automated simulation system receives the initial chip layout and simulates and optimizes the quantum chip based on chip parameter indicators of the configuration task to obtain layout parameters that meet design indicators;

[0039] The layout generation system generates air bridges, flux traps, and marks on the initial chip layout based on the initial chip layout and the layout parameters to generate a final layout.

[0040] Optionally, the automated design system includes:

[0041] Custom device library module, used to select preset devices and store them;

[0042] An automatic layout module, configured to automatically layout quantum bits of the quantum chip according to a configuration task;

[0043] An automatic wiring module is used to automatically wire the quantum chip after layout.

[0044] Optionally, the automated simulation system includes:

[0045] A geometric parameter iteration module, used for iteratively optimizing the design parameters of the quantum chip;

[0046] The full Hamiltonian calculation module is used to calculate the full Hamiltonian and obtain the second quantum chip index, and compare the second quantum chip index with the quantum chip parameter index to determine whether iterative optimization is needed;

[0047] The resonant cavity automatic simulation module is used to automatically simulate the resonant cavity length at a specific frequency.

[0048] Optionally, the layout generation system includes at least an automatic air bridge module for automatically generating air bridges on the initial chip layout;

[0049] A flux trap generation module, used to automatically generate flux traps on the initial chip layout;

[0050] The mark generation module is used to mark the plurality of sub-layouts divided on the initial chip layout.

[0051] Beneficial effects:

[0052] The present invention provides a quantum chip design method and system. By constructing an integrated system for superconducting quantum chip design, simulation and layout generation, the system integrates automated modules such as automatic layout, wiring, and parameter iteration. Combined with intelligent algorithms and multi-simulation mutual verification methods, it realizes full process automation from device design to layout generation, effectively improving the design efficiency and accuracy of superconducting quantum chips, reducing human errors, and breaking through the limitations of traditional tool modules that can only be adjusted manually. It provides an efficient and accurate systematic solution for the rapid development of large-scale superconducting quantum chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0054] Figure 1 This is a flow chart of the quantum chip design method provided by the present invention.

[0055] Figure 2 A flowchart of generating an initial chip layout for the quantum chip design method provided by the present invention.

[0056] Figure 3 Flowchart for simulation optimization of the quantum chip design method provided by the present invention.

[0057] Figure 4 Flowchart for generating the final layout for the quantum chip design method provided by the present invention.

[0058] Figure 5 Schematic diagram of the architecture of the quantum chip design system provided by the present invention.

[0059] Figure 6 This is a schematic diagram of the change of effective coupling strength with coupler frequency and magnetic flux in the quantum chip design system provided by the present invention.

[0060] Figure 7 This is a schematic diagram of the change of ZZ coupling strength with coupler frequency and magnetic flux in the quantum chip design system provided by the present invention.

[0061] In the figure: 100, automated design system; 110, custom device library module; 120, automatic layout module; 130, automatic wiring module; 200, automated simulation system; 210, geometric parameter iteration module; 220, full Hamiltonian calculation module; 230, resonant cavity automatic simulation module; 300, layout generation system; 310, automatic air bridge module; 320, flux trap generation module; 330, logo generation module; 400, information database. DETAILED DESCRIPTION

[0062] The present invention may be more readily understood by referring to the following detailed description of preferred embodiments of the present invention and the included Examples. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention pertains. In the event of a conflict, the definitions in this specification shall prevail.

[0063] The present invention provides a quantum chip design method and system, which solves the problem in the prior art of manually adjusting design parameters, control circuits, and quantum bit layout when designing the layout of quantum superconducting chips. This easily introduces human errors, reduces design efficiency, and affects the performance of quantum chip design. Most existing superconducting quantum chip design tools focus on the design of a single module (such as a quantum circuit), and other parts still require designers to perform a large amount of manual adjustment and manual optimization. This still leads to low efficiency and poor accuracy, which affects the performance of the final quantum chip.

[0064] The technical concept of this invention is that through an integrated system for superconducting quantum chip design, simulation and layout generation, the full-process automated design of quantum chips from device layout to simulation, parameter optimization and generation of the final layout can be realized. This can effectively improve the design efficiency and accuracy of superconducting quantum chips, reduce the errors caused by human design, and at the same time break through the modular design fragmentation in traditional design auxiliary tools, which can only be limited by manual parameter adjustment, providing an efficient and accurate systematic solution for the rapid development of large-scale superconducting quantum chips.

[0065] like Figure 1-4 As shown, a quantum chip design method is also provided, the steps comprising:

[0066] Obtaining devices required for quantum chip design, automatically laying out quantum bits on the quantum chip based on the configuration task, and automatically routing the laid-out quantum chip to generate an initial chip layout;

[0067] receiving the initial chip layout, and performing simulation optimization on the quantum chip based on the quantum chip parameter indicators of the configuration task to obtain layout parameters that meet the design indicators;

[0068] Based on the initial chip layout and the layout parameters, air bridges, magnetic flux traps, and markers are generated on the initial chip layout to generate a final layout.

[0069] In one embodiment, Figure 2 As shown, the specific steps of obtaining the devices required for quantum chip design, automatically laying out the quantum bits of the quantum chip based on the configuration task, and automatically wiring the laid-out quantum chip to generate an initial chip layout include:

[0070] S100, based on design requirements, the system will generate a completely blank chip layout as the starting point for chip design;

[0071] S200, during the design process, determine whether a custom device is needed. If so, the user can enter the custom device library module 110, define a new quantum device by setting device parameters, such as the geometric shape parameters of the quantum bit, and add the device to the design layout. If a custom device is not needed, directly select the packaged preset device from the device library, and initialize the relevant functional parameters for the selected device. Optionally, the preset device library usually contains industry-standardized quantum bits, coupling circuits, control units and other components, which can be directly selected to save design time. After confirming the device, the selected device is inserted into the above-mentioned blank chip layout through the device addition module.

[0072] S300, automatically generates the device layout according to the configuration task such as the quantum algorithm, processes the external parameters according to the requirements, and determines the interface position of the chip pins. Specifically, the system calls the automatic layout module 120 to design an efficient quantum bit layout based on the results of the algorithm requirement analysis to support frequent quantum bit interactions and gate operations in the algorithm, reduce wiring complexity and mutual interference. The automatic layout algorithm can dynamically adjust the mechanism of quantum bit connection and logic gate configuration according to the algorithm, so that the chip can automatically optimize its hardware configuration according to the algorithm being executed. Some designs of quantum chips may involve external parameters (such as the distance between the resonant cavity and the read line, etc.). If necessary, the user can set these external parameters and apply them to the design layout. If the design does not involve external parameters, you can skip this step directly to complete the layout initialization. After completing the basic layout, the user needs to confirm the specific interface positions of the functional pins and external pins of all devices to prepare for wiring.

[0073] S400, based on the wiring constraints, the wiring paths between the devices in the chip layout are automatically generated by the algorithm, the wiring paths are optimized and adjusted, and the initial chip layout is generated. Specifically, the automatic wiring module 130 uses an intelligent algorithm to generate a complete wiring connection path for the entire quantum chip. During the wiring process, the system will optimize the wiring path based on preset constraints, where the preset constraints include at least the wiring length, the spacing between lines, and the number of bends of the connecting line. After the wiring is completed, you can choose whether to fine-tune the wiring scheme. For example, when it is found that the wiring of certain devices may have efficiency problems or cannot achieve the expected performance indicators, you can enter the fine-tuning mode, which allows manual adjustment of the layout of the relevant lines. If not, you can choose whether to save the current design scheme as a template according to your needs and add it to the design library. The design library can provide a reference or template for subsequent design, thereby effectively improving the reusability and efficiency of chip design.

[0074] In one embodiment, Figure 4 As shown, the steps of receiving the initial chip layout and simulating and optimizing the quantum chip based on the quantum chip parameter indicators of the configuration task to obtain layout parameters that meet the design indicators include:

[0075] S500, obtain the subsystem in the initial chip layout generated in step S400, apply design parameters to the subsystem, and start simulation. Specifically, the automatic simulation system is used to perform automatic simulation iteration of quantum chip parameters to extract relevant subsystems from the initial chip layout. Preferably, the subsystem includes quantum bits and coupling devices in the quantum chip. By specifying the designed components, simulation and design can be combined together, and then the initial subsystem parameters are input. If there is a relevant parameter file, such as a JSON format file, the design parameters can be loaded directly by importing the JSON format file. JSON is a lightweight data exchange format with a key-value pair as the basic structure, and uses a human-readable text format to store and transmit data. In the design phase, the user enters parameters through the interface, and the system automatically generates an initial JSON file (including device library parameters, layout constraints, etc.). In the simulation phase, the simulation system reads the JSON parameters, performs HFSS electromagnetic simulation or Hamiltonian calculation, and writes the results (such as capacitance matrix, energy level data) to a new JSON file to achieve automatic update of the JSON file.

[0076] Before simulation, you can select a simulation mode, including Q3D mode (quasi-static three-dimensional simulation), EPR eigenmode (electromagnetic eigenmode analysis), or black-box (black-box quantization) mode. These modes can be cross-validated and compared to ensure the reliability of the results. The Q3D mode assumes that the electromagnetic field changes slowly (at a frequency far below the device's resonant frequency), ignores the time derivative of the displacement current, and simplifies Maxwell's equations to Laplace or Poisson's equations. The EPR eigenmode directly solves the eigenvalue problem for Maxwell's equations to determine the device's electromagnetic field distribution and resonant frequency.

[0077] At step S600, after the simulation is complete, the system quantizes the basic characteristic parameters of the qubits based on the simulation results to obtain first quantum chip indicators. Optionally, the first quantum chip indicators include qubit frequency, resonant cavity frequency, anharmonicity, and coupling strength. The system compares the first quantum chip indicators with the quantum chip parameter indicators of the configuration task to determine whether iterative optimization of the design parameters is necessary. If not, the system proceeds to step S700. If so, the system returns to step S500 for iterative optimization.

[0078] S700: Determine whether there is an adjustable coupler. If not, calculate the ZZ coupling strength between the qubits and compare the ZZ coupling strength with the quantum chip parameter index of the configuration task to determine whether iterative optimization of the design parameters is required. If so, proceed to step S500 for iterative optimization. Otherwise, proceed to step S900.

[0079] If yes, go to step S800.

[0080] S800, calculating the full Hamiltonian, and obtaining actual index parameters through the full Hamiltonian, and comparing them with the preset index parameters to determine whether they meet the requirements of the preset index parameters. If so, saving the actual index parameters; if not, proceeding to step S500 for iterative optimization;

[0081] The calculation process of the full Hamiltonian includes:

[0082] The system energy level is calculated and an energy level diagram is drawn. The energy level diagram is used to observe whether a two-level system exists in the flux modulation path of the adjustable coupler.

[0083] Calculate and plot the ZZ coupling strength as a function of frequency and flux to determine the on / off ratio.

[0084] Calculate and plot the effective coupling strength as a function of frequency and magnetic flux to determine the cut-off frequency.

[0085] After completing the calculation process, compare with the indicators to determine whether the system design requirements are met. If so, save the layout parameters as a JSON file. Otherwise, automatically enter the simulation iteration until the optimal parameters are obtained.

[0086] At the same time, after the subsystem completes the simulation iteration, the resonant cavity length will be automatically simulated and iterated. The user specifies the frequency of the resonant cavity, and the resonant cavity length is automatically simulated through an adaptive gradient descent algorithm, and compared with the design target frequency to obtain the optimal solution.

[0087] S900, after saving the actual indicator parameters and exiting, specifically, all simulation parameters of the layout are stored as a JSON file for layout generation and subsequent design data import, and the system ends the automated simulation.

[0088] In one embodiment, Figure 5 As shown, based on the initial chip layout and the layout parameters, the specific steps of generating air bridges, flux traps, and markers on the initial chip layout to generate the final layout include:

[0089] S1000, importing the initial chip layout in step S400 and the actual index parameters saved in step S900;

[0090] S1100: Generate air bridges and magnetic flux traps on the initial chip layout. Specifically, the automatic air bridge generation module 310 and the magnetic flux trap generation module 320 automatically draw air bridges and magnetic flux traps on the layout according to the layout.

[0091] S1200: Create a Josephson junction. Each device corresponds to a different Josephson junction. Specifically, users can directly import or use the device library to create a parametric Josephson junction as needed. A Josephson junction GDS file is created, with each cell corresponding to a different Josephson junction for layout use.

[0092] S1300, divide the initial chip layout into multiple sub-layouts, and obtain the corresponding layout parameters for each sub-layout; specifically, since a wafer can be cut into an N*N layout, N*N sub-layouts are created, and each sub-layout imports various layout parameters according to user needs.

[0093] S1400: The initial chip layout or multiple sub-layouts are labeled to obtain a final chip layout. Specifically, there are two methods for creating a label template: one is to add labels to the sub-layouts and then merge them into the overall layout; the other is to add labels directly to the overall layout. The minimum units of each sub-layout and the template are then unified, and each sub-layout is imported into the template to generate the overall layout.

[0094] In one embodiment, a two-bit tunable coupler chip is designed:

[0095] First, an initial layout is automatically generated. Quantum devices can be defined and parameters initialized as needed. Custom layouts can then be performed as needed. In this embodiment, the size of the adjustable coupler dual-bit superconducting quantum chip is 10mm×10mm. Two dual-bit structures are located on either side of the two readout lines, representing qubit Q1 and qubit Q2. The qubit type is a fixed-frequency Xmon type. Bits are coupled via adjustable couplers. Each bit includes a resonant cavity connected to the adjustable coupler. Coupler T1 has no control line, while coupler T2 has a control line for control. After the layout is complete, the routing module is called to route and fine-tune it, generating the initial layout.

[0096] Then, an automated simulation is performed, and the adjustable coupling subsystem is automatically extracted from the initialization layout for HFSS automated simulation. In this embodiment, the automated simulation target values ​​are as follows: qubit Q1, qubit Q2, and coupler T1 form a dual-bit connected by an adjustable coupler, whose frequencies are about 4.5 GHz and 5 GHz, respectively, and the detuning amount △= about 500 MHz. The frequency of coupler T1 is about 7 GHz. At the same time, the anharmonic Ec of coupler T1 is set to about 300 MHz, and the anharmonic Ec of qubit Q1 and qubit Q2 are both about 250 MHz. The effective coupling strength between bits is set to a switchable state (such as Figure 6 As shown), the switching ratio of the adjustable coupler is set to about 1000:1 (as shown Figure 7 Specific parameters are user-defined based on specific requirements. Q3, Q4, and T2 form another dual-bit connected by an adjustable coupler, with similar parameters to the previous adjustable coupler subsystem. Finally, a JSON parameter file is generated after the automated simulation completes.

[0097] Finally, the layout is automatically generated. After importing the JSON parameter file, a custom Josephson junction is added, and air bridges and flux traps are automatically generated according to requirements. In some embodiments, indium pillars need to be added to the flip-chip layout. At the same time, the layout logo template is automatically imported. At this point, the complete version of the layout is completed.

[0098] like Figure 1 As shown, a quantum chip design and simulation integrated system includes:

[0099] The automated design system 100 automatically lays out chip devices and automatically routes the laid-out chip devices to generate an initial chip layout. Specifically, the automated design system 100 is responsible for generating an initial parameter layout and includes at least three modules:

[0100] The custom device library module 110 allows users to independently design custom parameterized devices outside of an existing device library and add them to the existing device library, which can effectively expand the richness of components in the device library and improve the scalability of device layout.

[0101] The automated design system 100 also includes an automatic layout module 120. This module automatically lays out qubits or other chip components based on a quantum algorithm (e.g., Shor's algorithm, Grover's algorithm, or quantum Fourier transform) or pre-set configurations to achieve the optimal topology for the quantum algorithm or specific metrics. This effectively improves algorithm execution efficiency, reduces wiring complexity, minimizes mutual interference, and improves design accuracy and efficiency. Specifically, pre-set configurations include device library preset parameters, user-defined parameters, and external parameter settings.

[0102] The automated design system 100 also includes an automatic wiring module 130. After determining the layout of the quantum bit or chip device, the automatic wiring module 130 can optimize the wiring under specific constraints. Specifically, the specific constraints mainly include geometric constraints, electrical performance constraints, and process manufacturing constraints. Geometric constraints limit the wiring length, line spacing, number of line bends, and interlayer rules when wiring multiple metal layers. Electrical performance constraints limit characteristic impedance matching, noise suppression, and parasitic parameter control. Process manufacturing constraints limit the minimum line width or line spacing, and constrain the height and span of the air bridge to ensure the yield of the process. At the same time, the optimal wiring searches for the global optimal solution through an intelligent algorithm. Specifically, a heuristic search algorithm or a global optimization algorithm can be used for optimal wiring.

[0103] Automated simulation system 200 automatically simulates the chip device's geometric parameters, the relationship between chip devices and capacitors, and the chip device's resonant cavity length to obtain layout parameters that meet design specifications. Automated simulation system 200 is responsible for performing automated simulation after receiving the initial parameter layout sent by automated design system 100 to meet customized, or pre-set, overall chip specifications. Automated simulation system 200 includes at least an automatic iteration device geometric parameter module, a full Hamiltonian calculation module 220, and a resonant cavity automatic simulation module 230.

[0104] Among them, the geometric parameter iteration module 210, i.e., the automatic iteration device geometric parameter module, establishes a loss function for chip indicators (such as quantum bit frequency, anharmonicity, and ZZ coupling strength, etc.), and uses the gradient descent algorithm to optimize the geometric parameters of chip devices (such as quantum bits) to meet the local chip indicators.

[0105] The full Hamiltonian calculation module 220 uses Hamiltonian diagonalization to process the correspondence between the local indicators and capacitance of the chip to establish a chip indicator calculation system. In quantum mechanics, Hamiltonian is an operator that describes the energy of the system, including particle kinetic energy, potential energy and interaction energy. For superconducting quantum chips, the electromagnetic properties of devices such as quantum bits and couplers can be modeled by Hamiltonian, which is usually in the form of a matrix. By mathematically transforming the Hamiltonian matrix into a diagonal matrix, the diagonal elements are the energy eigenvalues ​​(energy levels) of the system, corresponding to the observable state of the quantum bit, and the diagonalization process can solve the key parameters such as the energy level structure and transition probability of the quantum system. By diagonalizing the full Hamiltonian, the energy levels of nonlinear systems (such as quantum bits containing anharmonic quantities) can be accurately solved, avoiding the deviation of simulation results caused by approximate errors, and the contribution of multiple factors such as capacitance, inductance, and Josephson junction nonlinearity to the Hamiltonian can be considered at the same time, which is suitable for accurate modeling of complex devices.

[0106] After determining the coupling strength between the qubit and the resonant cavity, the resonant cavity automatic simulation module 230 automatically simulates the resonant cavity length at a specific frequency using a gradient descent algorithm with an adaptive learning rate, achieving an accuracy of 0.05%. Compared to the existing design-then-simulation method, followed by adjustment and then simulation, this resonant cavity automatic simulation module 230 can quickly calculate the optimal length from the target frequency, effectively improving resonator simulation efficiency.

[0107] Layout generation system 300 is used to add air bridges, flux traps, and markers to the chip devices to generate the final layout. After obtaining layout parameters that meet the customized overall chip specifications, the automated simulation system 200 sends these layout parameters to layout generation system 300, which automatically generates the final layout. Layout generation system 300 includes an automatic air bridge module 310, a flux trap generation module 320, and a marker generation module 330.

[0108] Optionally, the automatic air bridge module 310 automatically adds air bridges for the resonant cavity and control line modes to reduce crosstalk between the XY line and the Z line. The XY line is a microwave control line that carries high-frequency AC signals. Its electromagnetic field is easily coupled to adjacent lines through parasitic capacitance or inductance. The Z line is a flux bias line used to adjust the energy level splitting of the quantum bit. When the XY line is parallel to or crosses the Z line, the distance is too close, resulting in electric field coupling, which may cause fluctuations in the DC bias voltage in the Z line and cause capacitive crosstalk. The alternating magnetic field generated by the high-frequency XY signal is coupled to the Z line through mutual inductance, introducing noise current, causing quantum bit decoherence, and causing inductive crosstalk. The air bridge is a suspended metal bridging structure consisting of support columns and a bridge body, usually manufactured using electron beam lithography and metal lift-off processes. The bridge body spans the two intersecting lines, separating the XY line and the Z line in the vertical direction, thereby increasing the physical distance and blocking the magnetic field coupling path.

[0109] In the resonant cavity line scenario, when the central conduction band of the resonant cavity intersects with the surrounding control lines, it is necessary to avoid crosstalk between the high-frequency electromagnetic field of the resonant cavity and the control lines. The intersection of the resonant cavity conduction band and the XY / Z line can be automatically detected through the layout analysis algorithm to optimize the width and height of the bridge body.

[0110] In control line scenarios, where the XY control lines intersect with the Z control lines, cross-layer interference between low-frequency and high-frequency signals needs to be suppressed. When automatically placing air bridges, you can first distinguish between T-shaped and cross-shaped crossings. For cross-shaped crossings, you can force the addition of air bridges. For T-shaped crossings, you can dynamically determine the spacing threshold. Then, you can optimize the bridge length and support column density.

[0111] Optionally, the flux trap generation module 320 adds a flux trap to the original layout under specific constraints to reduce the crosstalk effect of the flux. The flux crosstalk mainly comes from external environmental noise such as power frequency magnetic field and laboratory equipment and interference such as Z line inside the chip. The flux trap is usually a superconducting closed loop, which uses the Meissner effect of superconducting materials to repel the external magnetic field and keep the magnetic field inside the trap at 0. The specific constraints include that the trap structure must meet the resolution of the lithography or etching process, cannot overlap with key devices such as quantum bits, resonant cavities, wiring, etc., and at the same time, a safe distance must be maintained, the trap resonance frequency must avoid the quantum bit operating frequency, and the flux trap must not be deformed at low temperatures so that the superconducting properties can be maintained.

[0112] Alternatively, the layout of the flux trap can be achieved by the following steps:

[0113] Identify noise-sensitive areas, such as qubit cells and Z-lines;

[0114] After excluding noise-sensitive areas in the layout, a scan line algorithm is used to identify continuous blank areas and generate candidate locations;

[0115] For large blank areas, donut-shaped traps can be used, while for narrow gaps, strip-shaped traps are inserted to suppress inter-wire flux coupling.

[0116] The flux trap generation module 320 can achieve efficient suppression of magnetic flux crosstalk in superconducting quantum chips through automated layout algorithms and multi-layer constraints. This not only improves the chip's stability and coherence performance, but also accelerates the engineering process of large-scale quantum chips through standardized cell design and layout collaboration processes.

[0117] The marker generation module 330 is responsible for adding the final marker to the layout for differentiation. The function of the marker is to mark different areas on the chip layout, such as the quantum bit array area, the control circuit area, and the test area, to facilitate lithography alignment, cutting and dicing, and test positioning during process manufacturing. At the same time, the marker can also record metadata such as the chip version number, design date, and process parameters to support quality traceability and yield analysis during mass production. It can also add alignment marks, cutting guide lines, etc. to assist in wafer cutting and probe station testing.

[0118] The types of marks include text marks, graphic marks, QR codes or bar codes, alignment marks and cutting marks, etc.

[0119] Optionally, an information database 400 is included, and the information database 400 is used to store chip simulation parameters and final layout to facilitate subsequent design use.

[0120] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A quantum chip design method, characterized in that: The specific steps include: Obtaining devices required for quantum chip design, automatically laying out quantum bits on the quantum chip based on the configuration task, and automatically routing the laid-out quantum chip to generate an initial chip layout; receiving the initial chip layout, and performing simulation optimization on the quantum chip based on the quantum chip parameter indicators of the configuration task to obtain layout parameters that meet the design indicators; Based on the initial chip layout and the layout parameters, air bridges, magnetic flux traps, and markers are generated on the initial chip layout to generate a final layout.

2. The quantum chip design method according to claim 1, characterized in that: The steps of obtaining devices required for quantum chip design, automatically laying out quantum bits of the quantum chip based on the configuration task, and automatically routing the laid-out quantum chip to generate an initial chip layout include: S100, generating a blank chip layout; S200, selecting a custom device or a preset device, initializing functional parameters of the device, and inserting the device into the blank chip layout; S300, automatically laying out quantum bits of the quantum chip according to the configuration task, processing external parameters according to the configuration task, and determining interface positions of pins of the quantum chip; S400: Generate wiring paths between devices in a chip layout based on wiring constraints, optimize and adjust the wiring paths, and generate an initial chip layout.

3. The quantum chip design method according to claim 1, characterized in that: The step of receiving the initial chip layout and performing simulation optimization on the quantum chip based on the chip parameter indicators of the configuration task to obtain layout parameters that meet the design indicators includes: S500, obtaining a subsystem in the initial chip layout, applying design parameters to the subsystem, and starting simulation; S600: After completing the simulation, obtain basic characteristic parameters of the quantum bit for quantization calculation, obtain a first quantum chip index, and compare the first quantum chip index with the quantum chip parameter index of the configuration task to determine whether it is necessary to iteratively optimize the design parameters. If not, go to step S700; if so, return to step S500 for iterative optimization; S700, determining whether there is an adjustable coupler; If not, calculate the ZZ coupling strength between the quantum bits and compare the ZZ coupling strength with the quantum chip parameter index of the configuration task to determine whether it is necessary to iteratively optimize the design parameters. If so, go to step S500 for iterative optimization; otherwise, go to step S900; If yes, go to step S800; S800, calculating the full Hamiltonian, and obtaining the second quantum chip index through the full Hamiltonian, and comparing it with the quantum chip parameter index of the configuration task to determine whether it meets the requirements of the quantum chip parameter index. If so, proceed to step S900; if not, return to step S500 for iterative optimization; S900, save the actual indicator parameters and exit.

4. The quantum chip design method according to claim 1, characterized in that: The step of generating air bridges, flux traps, and marks on the initial chip layout based on the initial chip layout and the layout parameters to generate a final layout includes: S1000, obtaining the initial chip layout and the layout parameters; S1100, generating air bridges and magnetic flux traps on the initial chip layout; S1200, establish a Josephson junction, each device corresponds to a different Josephson junction; S1300, dividing the initial chip layout into a plurality of sub-layouts, and obtaining corresponding layout parameters for each sub-layout; S1400: Mark the initial chip layout or a plurality of sub-layouts to obtain a final chip layout.

5. The quantum chip design method according to claim 2, characterized in that: In step S400 , the routing constraints include routing length, distance between lines, and number of bends.

6. The quantum chip design method according to claim 3, characterized in that: In step S500, the subsystem includes at least a quantum bit and a coupling device.

7. The quantum chip design method according to claim 3, characterized in that: In step S500 , when performing simulation, the corresponding simulation modes adopted include Q3D mode, EPR intrinsic mode or black-box mode.

8. The quantum chip design method according to claim 3, characterized in that: In step S600, the first quantum chip indicators include quantum bit frequency, resonant cavity frequency, anharmonicity, and coupling strength.

9. The quantum chip design method according to claim 3, characterized in that: In step S800, the steps of calculating the full Hamiltonian include: Calculate the system energy level and draw an energy level diagram to observe whether there is a two-level system in the magnetic flux modulation path of the adjustable coupler through the energy level diagram; Calculate and plot the ZZ coupling strength versus frequency and flux to determine the on / off ratio. Calculate and plot the effective coupling strength as a function of frequency and magnetic flux to determine the cut-off frequency.

10. A quantum chip design system, characterized in that: include: An automated design system acquires the devices required for quantum chip design, automatically lays out the quantum bits of the quantum chip based on the configuration task, and automatically routes the laid-out quantum chip to generate an initial chip layout; An automated simulation system receives the initial chip layout and simulates and optimizes the quantum chip based on chip parameter indicators of the configuration task to obtain layout parameters that meet design indicators; The layout generation system generates air bridges, flux traps, and marks on the initial chip layout based on the initial chip layout and the layout parameters to generate a final layout.

11. The quantum chip design system according to claim 10, characterized in that: The automated design system includes: Custom device library module, used to select preset devices and store them; An automatic layout module, configured to automatically layout quantum bits of the quantum chip according to a configuration task; An automatic wiring module is used to automatically wire the quantum chip after layout.

12. The quantum chip design system according to claim 10, characterized in that: The automated simulation system comprises: A geometric parameter iteration module, used for iteratively optimizing the design parameters of the quantum chip; The full Hamiltonian calculation module is used to calculate the full Hamiltonian and obtain the second quantum chip index, and compare the second quantum chip index with the quantum chip parameter index to determine whether iterative optimization is needed; The resonant cavity automatic simulation module is used to automatically simulate the resonant cavity length at a specific frequency.

13. The quantum chip design system according to claim 10, characterized in that: The layout generation system includes at least an automatic air bridge module for automatically generating air bridges on the initial chip layout; A flux trap generation module, used to automatically generate flux traps on the initial chip layout; The mark generation module is used to mark the plurality of sub-layouts divided on the initial chip layout.

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