RFID reader terminal low power consumption control method and related device

Abstract

The invention discloses an RFID reader terminal low power consumption control method and a related device, and the method comprises the steps: monitoring a task state of an RFID reader, and judging whether a task mode is switched or not according to the monitored current task state during monitoring; when switching occurs, determining to execute the voltage frequency increasing operation or the voltage frequency reducing operation based on the voltage frequency table; when it is confirmed that the operation of increasing the voltage frequency is executed, boosting control is carried out, the boosted voltage is output to the processor to be adjusted, and the frequency increasing operation of the clock frequency is executed after the voltage is stabilized; and when it is confirmed that the operation of reducing the voltage frequency is executed, controlling the clock frequency generation unit to reduce the clock frequency, performing boost control after the clock frequency is reduced, and outputting the voltage after voltage reduction to the processor to be adjusted. According to the embodiment of the invention, the problem that the energy efficiency of the RFID reader-writer is seriously wasted in a fixed voltage frequency mode is solved, and the energy consumption of the RFID reader-writer is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-power consumption control method for an RFID reader terminal and a related device. Background Art

[0002] Radio Frequency Identification (RFID) technology is an automatic identification technology that uses radio frequency communication. With its non-contact object recognition characteristics, it is widely used in identity recognition, mobile payment, intelligent transportation, implantable biomedicine, electrochemical sensors, and on-chip security. Today, RFID readers have entered a stage of intensive development and need to break through bottlenecks such as power consumption, integration, stability, and reliability to promote them into a new stage of development. When designing reader terminal equipment, it is necessary to integrate the RFID reader SoC chip, power chip, crystal oscillator, capacitors, and resistors on a single PCB circuit board. Although the integration of a microcontroller chip and a single reader SoC has replaced the previous off-chip interconnect solution, simplifying the hardware architecture and achieving good area and power optimization to a certain extent, some shortcomings still exist: the off-chip power chip cannot be fully utilized to further reduce the SoC power consumption and improve its battery life; the software closed-loop adjustment algorithm delay makes it difficult to respond to the power switching requirements of RFID-intensive reading and writing. The SoC sends voltage and frequency adjustment instructions to the PMIC through software-driven, relying on a complex feedback loop (sensor monitoring ADC sampling → data processing → instruction issuance). This process has a response lag in scenarios with dynamic load changes in the microsecond range, resulting in transient power consumption spikes not being suppressed in a timely manner. As a result, the event-driven nature of RFID cannot be fully utilized to further optimize the power consumption of the SoC chip. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the existing technology. The present invention provides a low-power control method and related devices for an RFID reader terminal. Through an event-driven control strategy, efficient interconnection and dynamic coordination between the SoC and the PMIC are achieved, solving the serious energy waste problem of the RFID reader in a fixed voltage and frequency mode, and reducing the energy consumption of the RFID reader. Fast frequency switching and high clock glitch suppression rate are achieved through the clock frequency generation unit in the multi-voltage frequency adjustment circuit.

[0004] To solve the above technical problems, an embodiment of the present invention provides a low-power consumption control method for an RFID reader terminal, which is applied to an RFID reader. The RFID reader has a built-in multi-voltage frequency adjustment circuit, which includes a voltage conversion unit and a clock frequency generation unit. The method includes:

[0005] Monitoring the task status of the RFID reader and determining whether a task mode has been switched based on the monitored current task status during monitoring, wherein the task modes include a card selection task mode, an inventory task mode, an anti-collision task mode, and an access task mode performed by the RFID reader;

[0006] If the task mode corresponding to the current task state is switched, determining whether to perform a voltage-frequency increase operation or a voltage-frequency decrease operation based on a voltage-frequency table, wherein the voltage-frequency table is composed of operating voltages and clock frequencies preset according to different task modes by open-loop regulation control;

[0007] When it is determined that a voltage and frequency boost operation is to be performed, the multi-voltage and frequency adjustment circuit performs a voltage boost control, outputs the boosted voltage to the processor to be adjusted in the RFID reader, and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes. The processor to be adjusted is provided with a CSR register, and the processor to be adjusted is connected to the multi-voltage and frequency adjustment circuit based on the CSR register;

[0008] When it is confirmed that the voltage and frequency reduction operation is to be performed, the clock frequency generation unit is controlled to reduce the clock frequency. After the clock frequency is reduced, the multi-voltage frequency adjustment circuit performs a voltage boost control and outputs the reduced voltage to the processor to be adjusted in the RFID reader.

[0009] Optionally, the multi-voltage frequency adjustment circuit performs a voltage boost control, outputs the boosted voltage to the processor to be adjusted in the RFID reader, and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes, including:

[0010] The multi-voltage frequency adjustment circuit determines whether the target boost voltage is the power rail voltage;

[0011] If the target boost voltage is the power rail voltage, the multi-voltage frequency adjustment circuit controls the voltage conversion unit to perform on-chip boost switching and outputs the boosted voltage to the processor to be adjusted in the RFID reader;

[0012] If the target boost voltage is not the power rail voltage, the multi-voltage frequency adjustment circuit configures the target boost voltage as the power rail voltage in the voltage conversion unit, controls the voltage conversion unit to perform on-chip boost switching, and outputs the boosted voltage to the processor to be adjusted in the RFID reader;

[0013] After the voltage is stabilized, the clock frequency generating unit is controlled to perform a clock frequency increasing operation.

[0014] Optionally, the multi-voltage frequency adjustment circuit performs boost control to output the stepped-down voltage to the processor to be adjusted in the RFID reader, including:

[0015] The multi-voltage frequency adjustment circuit determines whether the target step-down voltage is the power rail voltage;

[0016] If the target step-down voltage is the power rail voltage, the multi-voltage frequency adjustment circuit controls the voltage conversion unit to perform on-chip step-down switching and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader;

[0017] If the target step-down voltage is not the power rail voltage, the multi-voltage frequency adjustment circuit configures the target step-down voltage as the power rail voltage in the voltage conversion unit, controls the voltage conversion unit to perform on-chip step-down switching, and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader.

[0018] Optionally, the processor to be adjusted represents the card selection task mode, inventory task mode, anti-collision task mode and access task mode that the RFID reader needs to execute in the form of a queue, and writes the state performance requirements corresponding to each task mode into the CSR register.

[0019] Optionally, the voltage conversion unit includes a multi-voltage frequency controller and a power supply chip;

[0020] The multi-voltage frequency controller includes a control state machine, a frequency configuration, an off-chip voltage regulation configuration, and an on-chip voltage switch. The control state machine is respectively communicated with the frequency configuration, the off-chip voltage regulation configuration, and the on-chip voltage switch. The off-chip voltage regulation configuration is connected to the power chip via a serial communication bus, and controls the power chip to output three power rail voltages VH, VM, and VL with different voltages to the on-chip voltage regulation switch via the serial communication bus.

[0021] Optionally, the on-chip voltage regulation switch includes a clock gating circuit, a switching circuit and a low-impedance MOS tube switch;

[0022] When the on-chip voltage regulation switch performs voltage regulation switching, the switching speed of the low-impedance MOS transistor switch is configured, and the clock gating circuit turns off the clock;

[0023] The switching circuit controls the switching sequence of the low-impedance MOS switches, first turning off a group of MOS switches currently in the on state, and then turning on another group of MOS switches originally in the off state;

[0024] After the two groups of MOS transistor switch circuits in the low-impedance MOS transistor switch complete the switching action at the configured speed, the clock gating circuit turns on the clock again.

[0025] Optionally, the clock frequency generation unit includes a ring oscillator, a configurable distributor, and glitch-free clock switching;

[0026] The ring oscillator serves as an on-chip clock generation circuit, and the oscillation frequency of the ring oscillator is configured to be 54.24Mhz when powered on;

[0027] The configurable distributor is used to divide the output clock of the ring oscillator into an even number to obtain 27.12Mhz and 13.56Mhz clock signals;

[0028] The glitch-free clock switching is used to switch the output clock between multiple divided clocks without glitch.

[0029] In addition, an embodiment of the present invention further provides a low-power consumption control device for an RFID reader terminal, which is applied to an RFID reader. The RFID reader has a built-in multi-voltage frequency adjustment circuit, which includes a voltage conversion unit and a clock frequency generation unit. The device includes:

[0030] Monitoring module: used to monitor the task status of the RFID reader and determine whether the task mode has been switched according to the monitored current task status. The task modes include the card selection task mode, inventory task mode, anti-collision task mode and access task mode executed by the RFID reader;

[0031] Confirmation module: used for confirming whether to perform a voltage-frequency increase operation or a voltage-frequency decrease operation based on a voltage-frequency table when the task mode corresponding to the current task state is switched, wherein the voltage-frequency table is composed of operating voltages and clock frequencies preset according to different task modes by open-loop regulation control;

[0032] A voltage and frequency boosting operation module is configured to, when it is determined that a voltage and frequency boosting operation is to be performed, cause the multi-voltage and frequency adjustment circuit to perform voltage boosting control, output the boosted voltage to the processor to be adjusted in the RFID reader, and control the clock frequency generation unit to perform a clock frequency boosting operation after the voltage stabilizes. The processor to be adjusted is provided with a CSR register, and the processor to be adjusted is connected to the multi-voltage and frequency adjustment circuit based on the CSR register.

[0033] The voltage reduction frequency operation module is used to control the clock frequency generation unit to reduce the clock frequency when it is confirmed that the voltage reduction frequency operation is to be performed. After the clock frequency is reduced, the multi-voltage frequency adjustment circuit performs a boost control and outputs the reduced voltage to the processor to be adjusted in the RFID reader.

[0034] In addition, an embodiment of the present invention further provides an electronic device including a processor and a memory, wherein the processor runs a computer program or code stored in the memory to implement the low power consumption control method for an RFID reader terminal as described above.

[0035] In addition, an embodiment of the present invention further provides a computer-readable storage medium for storing a computer program or code. When the computer program or code is executed by a processor, the low power consumption control method for an RFID reader terminal as described above is implemented.

[0036] In an embodiment of the present invention, a multi-voltage frequency adjustment circuit is provided in an RFID reader, the multi-voltage frequency adjustment circuit including a voltage conversion unit and a clock frequency generation unit. Then, a voltage-up frequency operation or a voltage-down frequency operation of a processor to be adjusted in the RFID reader is performed. That is, through an event-driven control strategy, efficient interconnection and dynamic coordination between the SoC and the PMIC are achieved, thereby solving the serious energy waste problem of the RFID reader in a fixed voltage frequency mode and reducing the energy consumption of the RFID reader. Fast frequency switching and a high clock glitch suppression rate are achieved through the clock frequency generation unit in the multi-voltage frequency adjustment circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 1 is a flow chart of a low power consumption control method for an RFID reader terminal in an embodiment of the present invention;

[0039] Figure 2 is a structural diagram of the interaction between the multi-voltage frequency regulation circuit and tasks in an embodiment of the present invention;

[0040] Figure 3 1 is a schematic diagram of the structure of a multi-voltage frequency controller according to an embodiment of the present invention;

[0041] Figure 4Schematic diagram of the structure of the on-chip voltage switching module in an embodiment of the present invention;

[0042] Figure 5 Schematic diagram of the structure of the clock frequency generating unit in an embodiment of the present invention;

[0043] Figure 6 1 is a schematic diagram of the structure of a ring oscillator circuit in an embodiment of the present invention;

[0044] Figure 7 Schematic diagram of the structure of a configurable frequency divider circuit in an embodiment of the present invention;

[0045] Figure 8 Schematic diagram of the structure of the glitch-free clock switching circuit in an embodiment of the present invention;

[0046] Figure 9 is a timing diagram of multi-voltage frequency conversion in an embodiment of the present invention;

[0047] Figure 10 Schematic diagram of the structure of the low-power control device of the RFID reader terminal in an embodiment of the present invention;

[0048] Figure 11 It is a schematic diagram of the structure of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0050] For example 1, please refer to Figure 1 , Figure 1 It is a flowchart of the low power consumption control method of the RFID reader terminal in an embodiment of the present invention.

[0051] like Figure 1 As shown, a low-power consumption control method for an RFID reader terminal is applied to an RFID reader. The RFID reader has a built-in multi-voltage frequency adjustment circuit, which includes a voltage conversion unit and a clock frequency generation unit. The method includes:

[0052] S101: Monitoring the task status of the RFID reader and determining whether a task mode has been switched based on the monitored current task status. The task modes include a card selection task mode, an inventory task mode, an anti-collision task mode, and an access task mode performed by the RFID reader.

[0053] Specifically, the task status of the RFID reader is monitored by a multi-voltage frequency adjustment circuit; Figure 2 As shown, by using the CSR register in the processor to be adjusted as the interface of the multi-voltage frequency adjustment circuit, registers related to the multi-voltage frequency adjustment circuit are defined in the CSR address space of the processor to be adjusted, thereby realizing dynamic voltage and frequency adjustment of the entire RFID reader; the multi-voltage frequency adjustment circuit directly interacts with the processor to be adjusted, and controls the clock frequency generation unit and the voltage conversion unit to provide the corresponding clock frequency and operating voltage for the SoC.

[0054] The processor to be adjusted represents the card selection task mode, inventory task mode, anti-collision task mode and access task mode that the RFID reader needs to execute in the form of a queue, and writes the state performance requirements corresponding to each task mode into the CSR register; wherein the form of the queue is as follows: k , k = 1, 2, ... n; the software obtains the state mode of the next command by analyzing the C code and writes the state performance requirements into the register; the control state machine reads the value of the register, obtains the target voltage and clock frequency for adjustment, and sends control signals to the voltage conversion unit and the clock frequency generation unit to adjust the voltage and clock frequency.

[0055] That is, when the current task status is monitored, it can be used to determine whether the task mode has switched. If no switch has occurred, continue monitoring; if a switch has occurred, proceed to the next step.

[0056] In this embodiment, key task commands such as card search, anti-collision, and selection in the RFID reader are all equipped with active status indication signals. These signals will enable the issuance of interrupt signals when a task switch occurs in the C code, and will be cleared when entering the next task mode. After an interrupt occurs, the processor jumps to the program execution response, and the regulation circuit makes a judgment on the target voltage and frequency of the SoC system based on the current working status of the RFID reader. If the target state does not match the current state, the value of the corresponding control register will be modified, and the corresponding control signal will be output to the configurable clock divider module, the on-chip voltage switching circuit, and the off-chip PMIC interface to adjust the system to the target voltage and frequency.

[0057] S102: If the task mode corresponding to the current task state is switched, determining whether to perform a voltage-frequency increase operation or a voltage-frequency decrease operation based on a voltage-frequency table, wherein the voltage-frequency table is composed of operating voltages and clock frequencies preset according to different task modes by open-loop regulation control;

[0058] In the specific implementation process of the present invention, the multi-voltage frequency regulation circuit is a circuit module that controls the voltage and clock frequency according to the workload of the processor, and is generally divided into two types of structures: one is open-loop regulation control; the other is closed-loop regulation control; the present embodiment is implemented through open-loop regulation control; therefore, it is necessary to select a suitable frequency voltage operating point from the working state of the processor to be regulated in the RFID reader, and then form a voltage-frequency table based on the preset working voltage and clock frequency points of the different selected task modes; at this time, when the task mode corresponding to the current task state is switched, it can be confirmed through the voltage-frequency table whether to perform a voltage-frequency increase operation or a voltage-frequency decrease operation; then the voltage-frequency increase operation or the voltage-frequency decrease operation is specifically performed according to the required operation.

[0059] S103: When it is determined that a voltage and frequency boost operation is to be performed, the multi-voltage and frequency adjustment circuit performs a voltage boost control, outputs the boosted voltage to the processor to be adjusted in the RFID reader, and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes. The processor to be adjusted is provided with a CSR register, and the processor to be adjusted is connected to the multi-voltage and frequency adjustment circuit based on the CSR register.

[0060] In a specific implementation of the present invention, the multi-voltage frequency adjustment circuit performs boost control, outputs the boosted voltage to the processor to be adjusted in the RFID reader, and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes, including: the multi-voltage frequency adjustment circuit determines whether the target boosted voltage is the power rail voltage; if the target boosted voltage is the power rail voltage, the multi-voltage frequency adjustment circuit controls the voltage conversion unit to perform on-chip boost switching and output the boosted voltage to the processor to be adjusted in the RFID reader; if the target boosted voltage is not the power rail voltage, the multi-voltage frequency adjustment circuit configures the target boosted voltage to the power rail voltage in the voltage conversion unit, controls the voltage conversion unit to perform on-chip boost switching, and outputs the boosted voltage to the processor to be adjusted in the RFID reader; and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes.

[0061] Specifically, when a voltage and frequency boost operation is required, the voltage boost operation is performed first, and after the voltage stabilizes, the frequency boost operation is performed; during the voltage boost operation, it is first confirmed whether the current voltage is the power rail voltage; if it is the power rail voltage, the multi-voltage and frequency adjustment circuit is directly used to control the voltage conversion unit to perform on-chip boost switching, and output the boosted voltage to the processor to be adjusted in the RFID reader; if it is not the power rail voltage, the multi-voltage and frequency adjustment circuit configures the target boost voltage to the power rail voltage in the voltage conversion unit, and then controls the voltage conversion unit to perform on-chip boost switching, and outputs the boosted voltage to the processor to be adjusted in the RFID reader; finally, after the voltage stabilizes, the clock frequency generation unit is controlled to perform a clock frequency boost operation.

[0062] S104: When it is confirmed that the voltage and frequency reduction operation is to be performed, the clock frequency generation unit is controlled to reduce the clock frequency. After the clock frequency is reduced, the multi-voltage frequency adjustment circuit performs a voltage boost control and outputs the reduced voltage to the processor to be adjusted in the RFID reader.

[0063] In a specific implementation of the present invention, the multi-voltage frequency regulation circuit performs boost control and outputs the stepped-down voltage to the processor to be regulated in the RFID reader, including: the multi-voltage frequency regulation circuit determines whether the target stepped-down voltage is the power rail voltage; if the target stepped-down voltage is the power rail voltage, the multi-voltage frequency regulation circuit controls the voltage conversion unit to perform on-chip step-down switching and outputs the stepped-down voltage to the processor to be regulated in the RFID reader; if the target stepped-down voltage is not the power rail voltage, the multi-voltage frequency regulation circuit configures the target stepped-down voltage as the power rail voltage in the voltage conversion unit, controls the voltage conversion unit to perform on-chip step-down switching, and outputs the stepped-down voltage to the processor to be regulated in the RFID reader.

[0064] Specifically, when performing the voltage and frequency reduction operation, the clock frequency is first reduced, and then the voltage reduction operation is performed; that is, the multi-voltage frequency adjustment circuit first controls the clock frequency generation unit to reduce the clock frequency, and after reducing the clock frequency, the multi-voltage frequency adjustment circuit determines whether the target step-down voltage is the power rail voltage; if the target step-down voltage is the power rail voltage, the multi-voltage frequency adjustment circuit controls the voltage conversion unit to perform on-chip step-down switching, and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader; if the target step-down voltage is not the power rail voltage, the multi-voltage frequency adjustment circuit configures the target step-down voltage as the power rail voltage in the voltage conversion unit, and then controls the voltage conversion unit to perform on-chip step-down switching, and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader.

[0065] In the specific implementation process of the present invention, the voltage conversion unit includes a multi-voltage frequency controller and a power supply chip; the multi-voltage frequency controller includes a control state machine, a frequency configuration, an off-chip voltage regulation configuration and an on-chip voltage switch, the control state machine is respectively connected to the frequency configuration, the off-chip voltage regulation configuration and the on-chip voltage switch in communication, the off-chip voltage regulation configuration is connected to the power supply chip via a serial communication bus, and controls the power supply chip to output three power rail voltages V with different voltages to the on-chip voltage regulation switch via the serial communication bus. H 、V M 、V L .

[0066] Specific as Figure 3 As shown in the figure, if the voltage rail voltage is not equal to the required regulation voltage, the off-chip voltage regulator module writes a voltage control code to a specific register on the off-chip PMIC chip (power supply chip) via the IIC bus (serial communication bus), thereby controlling the output voltage value of the voltage regulator chip. During the control transition of the regulation circuit, the hardware implements the state transition function through a finite state machine. To avoid timing violations, the state machine must ensure the correct order of voltage and frequency changes when adjusting. When the voltage request increases, the clock frequency must be switched only after the new high-level voltage stabilizes. When the voltage request decreases, the voltage must be reduced only after the clock frequency decreases.

[0067] like Figure 2 As shown, the voltage conversion unit includes a multi-voltage frequency controller and a power supply chip; Figure 3 As shown in the figure, the multi-voltage frequency controller includes a control state machine, frequency configuration, off-chip voltage regulation configuration, and on-chip voltage switching. After detecting the task mode switch, the control state machine reads the state performance requirement register value, obtains the target voltage and clock frequency for regulation, and sends a regulation configuration signal to the frequency configuration. Its configuration module has multiple divided clocks, which can quickly switch the clock frequency. The voltage regulation adopts a hybrid regulation architecture that combines off-chip PMIC with on-chip integrated fixed voltage rail. The function of the off-chip voltage regulation control module is to control the output voltage V of the off-chip PMIC through the IIC bus. H 、V M 、V L The on-chip voltage regulator module adjusts the working voltage V _out At three voltages V H 、V M 、V L Nanosecond level direct switching is achieved through low-impedance MOS switches.

[0068] In a specific implementation of the present invention, the on-chip voltage regulation switch includes a clock gating circuit, a switching circuit, and a low-impedance MOS transistor switch. When performing voltage regulation switching, the on-chip voltage regulation switch configures the switching speed of the low-impedance MOS transistor switch, and the clock gating circuit turns off the clock. The switching circuit controls the switching sequence of the low-impedance MOS transistor switches, first turning off a group of MOS transistor switches currently in the on state, and then turning on another group of MOS switches originally in the off state.

[0069] After the two groups of MOS transistor switch circuits in the low-impedance MOS transistor switch complete the switching action at the configured speed, the clock gating circuit turns on the clock again.

[0070] like Figure 4 As shown, the on-chip voltage regulation switch includes a clock gating circuit, a switching circuit, and a low-impedance MOS tube switch; V H 、V M 、V L There are three voltage rails with different voltages, V _out It is the virtual voltage rail of the digital load circuit; the on-chip voltage switching can switch between three voltage values ​​according to the mode requirements. Although it cannot achieve more precise control of the voltage, it meets the market demand for low power consumption, small area and low cost of embedded system RFID readers; the MOS tube gating circuit can configure different switching speeds under different voltage switching amplitudes to reduce voltage noise, and the clock gating circuit can shut down the clock during the voltage rail switching process to further reduce voltage noise; the working process of the on-chip voltage switching is as follows: first, the switching speed of the MOS tube switch is configured, and the clock gating circuit shuts down the clock; second, the switching circuit controls the switching sequence of the low-impedance MOS tube switches, first shutting down the group of MOS tube switches currently in the on state, and then turning on the other group of MOS switches that were originally in the off state; then, the two groups of MOS tube switch circuits complete the switching action at the configured speed; finally, the clock gating circuit turns the clock back on.

[0071] In a specific implementation of the present invention, the clock frequency generation unit includes a ring oscillator, a configurable distributor, and a glitch-free clock switch; the ring oscillator serves as an on-chip clock generation circuit, and upon power-on, the oscillation frequency of the ring oscillator is configured to be 54.24 MHz; the configurable distributor is used to divide the output clock of the ring oscillator by an even number to obtain 27.12 MHz and 13.56 MHz clock signals; the glitch-free clock switch is used to switch the output clock between multiple divided clocks without glitch.

[0072] Specifically, the clock frequency generation unit uses an on-chip ring oscillator and a configurable clock frequency division design. According to the configuration register value, the ring oscillator generates a 54.24Mhz high-frequency signal and performs an even-number division to generate a clock signal with the frequency required for different command modes. In the voltage regulation design, when the idle voltage rail voltage is exactly the target regulation voltage, the switching voltage rail can quickly complete the voltage regulation within nanoseconds. The voltage regulation design of switching the voltage rail requires that the frequency regulation time also be within this range, and the configurable clock frequency switching method can change the clock frequency within a few clock cycles.

[0073] like Figure 5 As shown, the clock frequency generation unit includes a ring oscillator, a configurable divider and a glitch-free clock switch; its working process is as follows: the ring oscillator serves as an on-chip clock generation circuit and can be configured to have an oscillation frequency of 54.24Mhz when powered on; the configurable clock divider divides the output clock of the ring oscillator by an even number to obtain 27.12Mhz and 13.56Mhz clock signals; the glitch-free clock switch circuit switches the output clock between multiple divided clocks without glitches; the circuit of the ring oscillator is as follows Figure 6 shown.

[0074] The frequency generation circuit adopts a programmable on-chip ring oscillator design, the core of which is composed of an odd-numbered inverter closed-loop structure. <0> To Sel <3> The select signal dynamically configures the number of inverter stages. When the Sel signal combination selects a specific number of inverter stages, the circuit triggers self-oscillation through a closed feedback path, outputting a clock signal at the required frequency. This achieves high-precision, low-jitter clock generation in a compact modular architecture.

[0075] Considering the low power consumption requirements of embedded devices, an asynchronous down-counter is chosen over a synchronous counter for the design of a configurable frequency divider. The asynchronous down-counter adopts a cascade structure, with the output of the previous stage serving as the clock for the next stage. The triggers of each stage flip in sequence, avoiding the inrush current caused by simultaneous switching of multiple bits. In addition, the asynchronous counter-type frequency divider saves area compared to the synchronous structure. Although the inter-stage delay of the asynchronous counter may cause intermediate state glitches, the glitch-free clock switching circuit in the next stage can eliminate the glitches. The circuit structure is shown in the figure. Figure 7 shown.

[0076] Glitch-free clock switching circuits such as Figure 8 As shown, the first two levels of registers are used to synchronize clk_select to avoid asynchronous problems, followed by a first-level gated clock and an OR gate. Figure 8 When performing post-simulation on the AND gate following the middle register, a gating unit with a process standard is used to implement it to avoid adverse effects on the combination of the clock signal.

[0077] In the specific implementation of state transition, such as Figure 9 As shown, in this embodiment, the multi-voltage frequency regulation circuit configures the system target voltage frequency register value to the configurable frequency modulation module and the multi-voltage rail hybrid switching module. The configurable frequency modulation module performs an even-number frequency division on the 54.24Mhz high-frequency signal generated by the on-chip ring oscillator according to the register value to generate a clock signal of the frequency required by the command mode; the multi-voltage rail hybrid switching module adjusts the output voltage according to the corresponding control signal output by the regulation circuit interface; Figure 9 It can be seen that the state of the RFID reader gradually switches from the initial idle state to the high-frequency and high-voltage working state; state ① is the initial power-on of the system, and the CPU is in the sleep state; state ② is the system waking up to run the program, the CPU starts to process the card search command, the main domain clock frequency also increases accordingly, and the working voltage is increased; after a period of time, the system switches to the anti-collision state ③, the CPU works in the high-frequency working state, the clock is at the highest frequency of 54.24Mhz, and the working voltage is maintained at 1.8V; when the system switches to the card selection, the regulation circuit adjusts the system to work in state ④, which is the second highest state of the system, with an operating frequency of 27.12MHz; after the card selection is completed correctly, the system calls back to the sleep state and maintains low-power sleep mode operation.

[0078] In an embodiment of the present invention, a multi-voltage frequency adjustment circuit is provided in an RFID reader, the multi-voltage frequency adjustment circuit including a voltage conversion unit and a clock frequency generation unit. Then, a voltage-up frequency operation or a voltage-down frequency operation of a processor to be adjusted in the RFID reader is performed. That is, through an event-driven control strategy, efficient interconnection and dynamic coordination between the SoC and the PMIC are achieved, thereby solving the serious energy waste problem of the RFID reader in a fixed voltage frequency mode and reducing the energy consumption of the RFID reader. Fast frequency switching and a high clock glitch suppression rate are achieved through the clock frequency generation unit in the multi-voltage frequency adjustment circuit.

[0079] Example 2, please refer to Figure 10 , Figure 10 It is a schematic diagram of the structure of the low power consumption control device of the RFID reader terminal in the embodiment of the present invention.

[0080] like Figure 10 As shown, a low-power control device for an RFID reader terminal is applied to an RFID reader. The RFID reader has a built-in multi-voltage frequency adjustment circuit, which includes a voltage conversion unit and a clock frequency generation unit. The device includes:

[0081] Monitoring module 1001: used to monitor the task status of the RFID reader and determine whether the task mode has been switched according to the monitored current task status. The task modes include the card selection task mode, inventory task mode, anti-collision task mode, and access task mode executed by the RFID reader;

[0082] Specifically, the task status of the RFID reader is monitored by a multi-voltage frequency adjustment circuit; Figure 2 As shown, by using the CSR register in the processor to be adjusted as the interface of the multi-voltage frequency adjustment circuit, registers related to the multi-voltage frequency adjustment circuit are defined in the CSR address space of the processor to be adjusted, thereby realizing dynamic voltage and frequency adjustment of the entire RFID reader; the multi-voltage frequency adjustment circuit directly interacts with the processor to be adjusted, and controls the clock frequency generation unit and the voltage conversion unit to provide the corresponding clock frequency and operating voltage for the SoC.

[0083] The processor to be adjusted represents the card selection task mode, inventory task mode, anti-collision task mode and access task mode that the RFID reader needs to execute in the form of a queue, and writes the state performance requirements corresponding to each task mode into the CSR register; wherein the form of the queue is as follows: k , k = 1, 2, ... n; the software obtains the state mode of the next command by analyzing the C code and writes the state performance requirements into the register; the control state machine reads the value of the register, obtains the target voltage and clock frequency for adjustment, and sends control signals to the voltage conversion unit and the clock frequency generation unit to adjust the voltage and clock frequency.

[0084] That is, when the current task status is monitored, it can be used to determine whether the task mode has switched. If no switch has occurred, continue monitoring; if a switch has occurred, proceed to the next step.

[0085] In this embodiment, key task commands such as card search, anti-collision, and selection in the RFID reader are all equipped with active status indication signals. These signals will enable the issuance of interrupt signals when a task switch occurs in the C code, and will be cleared when entering the next task mode. After an interrupt occurs, the processor jumps to the program execution response, and the regulation circuit makes a judgment on the target voltage and frequency of the SoC system based on the current working status of the RFID reader. If the target state does not match the current state, the value of the corresponding control register will be modified, and the corresponding control signal will be output to the configurable clock divider module, the on-chip voltage switching circuit, and the off-chip PMIC interface to adjust the system to the target voltage and frequency.

[0086] Confirmation module 10002: configured to, if the task mode corresponding to the current task state is switched, confirm whether to perform a voltage-frequency increase operation or a voltage-frequency decrease operation based on a voltage-frequency table, wherein the voltage-frequency table is composed of operating voltages and clock frequencies preset according to different task modes by open-loop regulation control;

[0087] In the specific implementation process of the present invention, the multi-voltage frequency regulation circuit is a circuit module that controls the voltage and clock frequency according to the workload of the processor, and is generally divided into two types of structures: one is open-loop regulation control; the other is closed-loop regulation control; the present embodiment is implemented through open-loop regulation control; therefore, it is necessary to select a suitable frequency voltage operating point from the working state of the processor to be regulated in the RFID reader, and then form a voltage-frequency table based on the preset working voltage and clock frequency points of the different selected task modes; at this time, when the task mode corresponding to the current task state is switched, it can be confirmed through the voltage-frequency table whether to perform a voltage-frequency increase operation or a voltage-frequency decrease operation; then the voltage-frequency increase operation or the voltage-frequency decrease operation is specifically performed according to the required operation.

[0088] The voltage and frequency boosting operation module 1003 is configured to, when it is determined that a voltage and frequency boosting operation is to be performed, cause the multi-voltage and frequency adjustment circuit to perform voltage boosting control, output the boosted voltage to the processor to be adjusted in the RFID reader, and control the clock frequency generation unit to perform a clock frequency boosting operation after the voltage stabilizes. The processor to be adjusted is provided with a CSR register, and the processor to be adjusted is connected to the multi-voltage and frequency adjustment circuit based on the CSR register.

[0089] In a specific implementation of the present invention, the multi-voltage frequency adjustment circuit performs boost control, outputs the boosted voltage to the processor to be adjusted in the RFID reader, and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes, including: the multi-voltage frequency adjustment circuit determines whether the target boosted voltage is the power rail voltage; if the target boosted voltage is the power rail voltage, the multi-voltage frequency adjustment circuit controls the voltage conversion unit to perform on-chip boost switching and output the boosted voltage to the processor to be adjusted in the RFID reader; if the target boosted voltage is not the power rail voltage, the multi-voltage frequency adjustment circuit configures the target boosted voltage to the power rail voltage in the voltage conversion unit, controls the voltage conversion unit to perform on-chip boost switching, and outputs the boosted voltage to the processor to be adjusted in the RFID reader; and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes.

[0090] Specifically, when a voltage and frequency boost operation is required, the voltage boost operation is performed first, and after the voltage stabilizes, the frequency boost operation is performed; during the voltage boost operation, it is first confirmed whether the current voltage is the power rail voltage; if it is the power rail voltage, the multi-voltage and frequency adjustment circuit is directly used to control the voltage conversion unit to perform on-chip boost switching, and output the boosted voltage to the processor to be adjusted in the RFID reader; if it is not the power rail voltage, the multi-voltage and frequency adjustment circuit configures the target boost voltage to the power rail voltage in the voltage conversion unit, and then controls the voltage conversion unit to perform on-chip boost switching, and outputs the boosted voltage to the processor to be adjusted in the RFID reader; finally, after the voltage stabilizes, the clock frequency generation unit is controlled to perform a clock frequency boost operation.

[0091] The voltage-reduction frequency operation module 1004 is used to control the clock frequency generation unit to reduce the clock frequency when it is confirmed that the voltage-reduction frequency operation is to be performed. After the clock frequency is reduced, the multi-voltage frequency adjustment circuit performs a voltage-boosting control and outputs the reduced voltage to the processor to be adjusted in the RFID reader.

[0092] In a specific implementation of the present invention, the multi-voltage frequency regulation circuit performs boost control and outputs the stepped-down voltage to the processor to be regulated in the RFID reader, including: the multi-voltage frequency regulation circuit determines whether the target stepped-down voltage is the power rail voltage; if the target stepped-down voltage is the power rail voltage, the multi-voltage frequency regulation circuit controls the voltage conversion unit to perform on-chip step-down switching and outputs the stepped-down voltage to the processor to be regulated in the RFID reader; if the target stepped-down voltage is not the power rail voltage, the multi-voltage frequency regulation circuit configures the target stepped-down voltage as the power rail voltage in the voltage conversion unit, controls the voltage conversion unit to perform on-chip step-down switching, and outputs the stepped-down voltage to the processor to be regulated in the RFID reader.

[0093] Specifically, when performing the voltage and frequency reduction operation, the clock frequency is first reduced, and then the voltage reduction operation is performed; that is, the multi-voltage frequency adjustment circuit first controls the clock frequency generation unit to reduce the clock frequency, and after reducing the clock frequency, the multi-voltage frequency adjustment circuit determines whether the target step-down voltage is the power rail voltage; if the target step-down voltage is the power rail voltage, the multi-voltage frequency adjustment circuit controls the voltage conversion unit to perform on-chip step-down switching, and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader; if the target step-down voltage is not the power rail voltage, the multi-voltage frequency adjustment circuit configures the target step-down voltage as the power rail voltage in the voltage conversion unit, and then controls the voltage conversion unit to perform on-chip step-down switching, and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader.

[0094] In the specific implementation process of the present invention, the voltage conversion unit includes a multi-voltage frequency controller and a power supply chip; the multi-voltage frequency controller includes a control state machine, a frequency configuration, an off-chip voltage regulation configuration and an on-chip voltage switch, the control state machine is respectively connected to the frequency configuration, the off-chip voltage regulation configuration and the on-chip voltage switch in communication, the off-chip voltage regulation configuration is connected to the power supply chip via a serial communication bus, and controls the power supply chip to output three power rail voltages V with different voltages to the on-chip voltage regulation switch via the serial communication bus. H 、V M 、V L .

[0095] Specific as Figure 3 As shown in the figure, if the voltage rail voltage is not equal to the required regulation voltage, the off-chip voltage regulator module writes a voltage control code to a specific register on the off-chip PMIC chip (power supply chip) via the IIC bus (serial communication bus), thereby controlling the output voltage value of the voltage regulator chip. During the control transition of the regulation circuit, the hardware implements the state transition function through a finite state machine. To avoid timing violations, the state machine must ensure the correct order of voltage and frequency changes when adjusting. When the voltage request increases, the clock frequency must be switched only after the new high-level voltage stabilizes. When the voltage request decreases, the voltage must be reduced only after the clock frequency decreases.

[0096] like Figure 2 As shown, the voltage conversion unit includes a multi-voltage frequency controller and a power supply chip; Figure 3 As shown in the figure, the multi-voltage frequency controller includes a control state machine, frequency configuration, off-chip voltage regulation configuration, and on-chip voltage switching. After detecting the task mode switch, the control state machine reads the state performance requirement register value, obtains the target voltage and clock frequency for regulation, and sends a regulation configuration signal to the frequency configuration. Its configuration module has multiple divided clocks, which can quickly switch the clock frequency. The voltage regulation adopts a hybrid regulation architecture that combines off-chip PMIC with on-chip integrated fixed voltage rail. The function of the off-chip voltage regulation control module is to control the output voltage V of the off-chip PMIC through the IIC bus. H 、V M 、V L The on-chip voltage regulator module adjusts the working voltage V _out At three voltages V H 、V M 、V L Nanosecond level direct switching is achieved through low-impedance MOS switches.

[0097] In a specific implementation of the present invention, the on-chip voltage regulation switch includes a clock gating circuit, a switching circuit, and a low-impedance MOS transistor switch. When performing voltage regulation switching, the on-chip voltage regulation switch configures the switching speed of the low-impedance MOS transistor switch, and the clock gating circuit turns off the clock. The switching circuit controls the switching sequence of the low-impedance MOS transistor switches, first turning off a group of MOS transistor switches currently in the on state, and then turning on another group of MOS switches originally in the off state.

[0098] After the two groups of MOS transistor switch circuits in the low-impedance MOS transistor switch complete the switching action at the configured speed, the clock gating circuit turns on the clock again.

[0099] like Figure 4 As shown, the on-chip voltage regulation switch includes a clock gating circuit, a switching circuit, and a low-impedance MOS tube switch; V H 、V M 、V L There are three voltage rails with different voltages, V _out It is the virtual voltage rail of the digital load circuit; the on-chip voltage switching can switch between three voltage values ​​according to the mode requirements. Although it cannot achieve more precise control of the voltage, it meets the market demand for low power consumption, small area and low cost of embedded system RFID readers; the MOS tube gating circuit can configure different switching speeds under different voltage switching amplitudes to reduce voltage noise, and the clock gating circuit can shut down the clock during the voltage rail switching process to further reduce voltage noise; the working process of the on-chip voltage switching is as follows: first, the switching speed of the MOS tube switch is configured, and the clock gating circuit shuts down the clock; second, the switching circuit controls the switching sequence of the low-impedance MOS tube switches, first shutting down the group of MOS tube switches currently in the on state, and then turning on the other group of MOS switches that were originally in the off state; then, the two groups of MOS tube switch circuits complete the switching action at the configured speed; finally, the clock gating circuit turns the clock back on.

[0100] In a specific implementation of the present invention, the clock frequency generation unit includes a ring oscillator, a configurable distributor, and a glitch-free clock switch; the ring oscillator serves as an on-chip clock generation circuit, and upon power-on, the oscillation frequency of the ring oscillator is configured to be 54.24 MHz; the configurable distributor is used to divide the output clock of the ring oscillator by an even number to obtain 27.12 MHz and 13.56 MHz clock signals; the glitch-free clock switch is used to switch the output clock between multiple divided clocks without glitch.

[0101] Specifically, the clock frequency generation unit uses an on-chip ring oscillator and a configurable clock frequency division design. According to the configuration register value, the ring oscillator generates a 54.24Mhz high-frequency signal and performs an even-number division to generate a clock signal with the frequency required for different command modes. In the voltage regulation design, when the idle voltage rail voltage is exactly the target regulation voltage, the switching voltage rail can quickly complete the voltage regulation within nanoseconds. The voltage regulation design of switching the voltage rail requires that the frequency regulation time also be within this range, and the configurable clock frequency switching method can change the clock frequency within a few clock cycles.

[0102] like Figure 5 As shown, the clock frequency generation unit includes a ring oscillator, a configurable divider and a glitch-free clock switch; its working process is as follows: the ring oscillator serves as an on-chip clock generation circuit and can be configured to have an oscillation frequency of 54.24Mhz when powered on; the configurable clock divider divides the output clock of the ring oscillator by an even number to obtain 27.12Mhz and 13.56Mhz clock signals; the glitch-free clock switch circuit switches the output clock between multiple divided clocks without glitches; the circuit of the ring oscillator is as follows Figure 6 shown.

[0103] The frequency generation circuit adopts a programmable on-chip ring oscillator design, the core of which is composed of an odd-numbered inverter closed-loop structure. <0> To Sel <3> The select signal dynamically configures the number of inverter stages. When the Sel signal combination selects a specific number of inverter stages, the circuit triggers self-oscillation through a closed feedback path, outputting a clock signal at the required frequency. This achieves high-precision, low-jitter clock generation in a compact modular architecture.

[0104] Considering the low power consumption requirements of embedded devices, an asynchronous down-counter is chosen over a synchronous counter for the design of a configurable frequency divider. The asynchronous down-counter adopts a cascade structure, with the output of the previous stage serving as the clock for the next stage. The triggers of each stage flip in sequence, avoiding the inrush current caused by simultaneous switching of multiple bits. In addition, the asynchronous counter-type frequency divider saves area compared to the synchronous structure. Although the inter-stage delay of the asynchronous counter may cause intermediate state glitches, the glitch-free clock switching circuit in the next stage can eliminate the glitches. The circuit structure is shown in the figure. Figure 7 shown.

[0105] Glitch-free clock switching circuits such as Figure 8 As shown, the first two levels of registers are used to synchronize clk_select to avoid asynchronous problems, followed by a first-level gated clock and an OR gate. Figure 8 When performing post-simulation on the AND gate following the middle register, a gating unit with a process standard is used to implement it to avoid adverse effects on the combination of the clock signal.

[0106] In the specific implementation of state transition, such as Figure 9 As shown, in this embodiment, the multi-voltage frequency regulation circuit configures the system target voltage frequency register value to the configurable frequency modulation module and the multi-voltage rail hybrid switching module. The configurable frequency modulation module performs an even-number frequency division on the 54.24Mhz high-frequency signal generated by the on-chip ring oscillator according to the register value to generate a clock signal of the frequency required by the command mode; the multi-voltage rail hybrid switching module adjusts the output voltage according to the corresponding control signal output by the regulation circuit interface; Figure 9 It can be seen that the state of the RFID reader gradually switches from the initial idle state to the high-frequency and high-voltage working state; state ① is the initial power-on of the system, and the CPU is in the sleep state; state ② is the system waking up to run the program, the CPU starts to process the card search command, the main domain clock frequency also increases accordingly, and the working voltage is increased; after a period of time, the system switches to the anti-collision state ③, the CPU works in the high-frequency working state, the clock is at the highest frequency of 54.24Mhz, and the working voltage is maintained at 1.8V; when the system switches to the card selection, the regulation circuit adjusts the system to work in state ④, which is the second highest state of the system, with an operating frequency of 27.12MHz; after the card selection is completed correctly, the system calls back to the sleep state and maintains low-power sleep mode operation.

[0107] In an embodiment of the present invention, a multi-voltage frequency adjustment circuit is provided in an RFID reader, the multi-voltage frequency adjustment circuit including a voltage conversion unit and a clock frequency generation unit. Then, a voltage-up frequency operation or a voltage-down frequency operation of a processor to be adjusted in the RFID reader is performed. That is, through an event-driven control strategy, efficient interconnection and dynamic coordination between the SoC and the PMIC are achieved, thereby solving the serious energy waste problem of the RFID reader in a fixed voltage frequency mode and reducing the energy consumption of the RFID reader. Fast frequency switching and a high clock glitch suppression rate are achieved through the clock frequency generation unit in the multi-voltage frequency adjustment circuit.

[0108] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the method for controlling low power consumption of an RFID reader terminal according to any of the above embodiments is implemented. The computer-readable storage medium includes, but is not limited to, any type of disk (including floppy disks, hard disks, optical disks, CD-ROMs, and magneto-optical disks), ROM (Read-Only Memory), RAM (Random Access Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, magnetic cards, or optical cards. In other words, a storage device includes any medium that can store or transmit information in a readable form by a device (e.g., a computer or a mobile phone), and can be a read-only memory, a disk, or an optical disk.

[0109] An embodiment of the present invention further provides a computer application program that runs on a computer and is used to execute the low power consumption control method for an RFID reader terminal according to any one of the above embodiments.

[0110] also, Figure 11 It is a schematic diagram of the structure of an electronic device in an embodiment of the present invention.

[0111] The embodiment of the present invention further provides an electronic device, such as Figure 11 The electronic device includes a processor 1102, a memory 1103, an input unit 1104, a display unit 1105 and other components. Those skilled in the art will understand that Figure 11 The structural components of the electronic device shown do not constitute a limitation on all devices, and may include more or fewer components than shown, or combine certain components. The memory 1103 can be used to store the application 1101 and various functional modules, and the processor 1102 runs the application 1101 stored in the memory 1103, thereby executing various functional applications and data processing of the device. The memory can be an internal memory or an external memory, or include both internal and external memories. The internal memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, or a random access memory. The external memory may include a hard disk, a floppy disk, a ZIP disk, a USB flash drive, a magnetic tape, etc. The memory disclosed in the present invention includes but is not limited to these types of memories. The memory disclosed in the present invention is only an example and not a limitation.

[0112] The input unit 1104 is used to receive input signals and keywords entered by the user. The input unit 1104 may include a touch panel and other input devices. The touch panel can collect user touch operations on or near it (such as operations performed by the user using a finger, stylus, or any other suitable object or accessory on or near the touch panel) and drive the corresponding connected device according to a pre-set program; other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (such as playback control keys, on / off keys, etc.), a trackball, a mouse, a joystick, etc. The display unit 1105 can be used to display information entered by the user or information provided to the user, as well as various menus of the terminal device. The display unit 1105 can be in the form of a liquid crystal display, an organic light-emitting diode, etc. The processor 1102 is the control center of the terminal device, connecting the various parts of the entire device using various interfaces and lines. It performs various functions and processes data by running or executing software programs and / or modules stored in the memory 1103 and calling data stored in the memory.

[0113] As an embodiment, the electronic device includes: one or more processors 1102, a memory 1103, and one or more applications 1101, wherein the one or more applications 1101 are stored in the memory 1103 and are configured to be executed by the one or more processors 1102, and the one or more applications 401 are configured to execute the corresponding RFID reader terminal low power consumption control method in any one of the above embodiments.

[0114] In an embodiment of the present invention, a multi-voltage frequency adjustment circuit is provided in an RFID reader, the multi-voltage frequency adjustment circuit including a voltage conversion unit and a clock frequency generation unit. Then, a voltage-up frequency operation or a voltage-down frequency operation of a processor to be adjusted in the RFID reader is performed. That is, through an event-driven control strategy, efficient interconnection and dynamic coordination between the SoC and the PMIC are achieved, thereby solving the serious energy waste problem of the RFID reader in a fixed voltage frequency mode and reducing the energy consumption of the RFID reader. Fast frequency switching and a high clock glitch suppression rate are achieved through the clock frequency generation unit in the multi-voltage frequency adjustment circuit.

[0115] In addition, the above is a detailed introduction to a low-power control method for an RFID reader terminal and related devices provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A low power consumption control method for an RFID reader terminal, characterized in that: Applied to an RFID reader, the RFID reader has a built-in multi-voltage frequency adjustment circuit, the multi-voltage frequency adjustment circuit includes a voltage conversion unit and a clock frequency generation unit; the method includes: Monitoring the task status of the RFID reader and determining whether a task mode has been switched based on the monitored current task status during monitoring, wherein the task modes include a card selection task mode, an inventory task mode, an anti-collision task mode, and an access task mode performed by the RFID reader; If the task mode corresponding to the current task state is switched, determining whether to perform a voltage-frequency increase operation or a voltage-frequency decrease operation based on a voltage-frequency table, wherein the voltage-frequency table is composed of operating voltages and clock frequencies preset according to different task modes by open-loop regulation control; When it is determined that a voltage and frequency boost operation is to be performed, the multi-voltage and frequency adjustment circuit performs a voltage boost control, outputs the boosted voltage to the processor to be adjusted in the RFID reader, and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes. The processor to be adjusted is provided with a CSR register, and the processor to be adjusted is connected to the multi-voltage and frequency adjustment circuit based on the CSR register; When it is confirmed that the voltage and frequency reduction operation is to be performed, the clock frequency generation unit is controlled to reduce the clock frequency. After the clock frequency is reduced, the multi-voltage frequency adjustment circuit performs a voltage boost control and outputs the reduced voltage to the processor to be adjusted in the RFID reader.

2. The low power consumption control method of the RFID reader terminal according to claim 1, characterized in that: The multi-voltage frequency adjustment circuit performs a voltage boost control, outputs the boosted voltage to the processor to be adjusted in the RFID reader, and controls the clock frequency generation unit to perform a clock frequency boost operation after the voltage stabilizes, including: The multi-voltage frequency adjustment circuit determines whether the target boost voltage is the power rail voltage; If the target boost voltage is the power rail voltage, the multi-voltage frequency adjustment circuit controls the voltage conversion unit to perform on-chip boost switching and outputs the boosted voltage to the processor to be adjusted in the RFID reader; If the target boost voltage is not the power rail voltage, the multi-voltage frequency adjustment circuit configures the target boost voltage as the power rail voltage in the voltage conversion unit, controls the voltage conversion unit to perform on-chip boost switching, and outputs the boosted voltage to the processor to be adjusted in the RFID reader; After the voltage is stabilized, the clock frequency generating unit is controlled to perform a clock frequency increasing operation.

3. The low power consumption control method of the RFID reader terminal according to claim 1, characterized in that: The multi-voltage frequency adjustment circuit performs a voltage boost control and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader, including: The multi-voltage frequency adjustment circuit determines whether the target step-down voltage is the power rail voltage; If the target step-down voltage is the power rail voltage, the multi-voltage frequency adjustment circuit controls the voltage conversion unit to perform on-chip step-down switching and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader; If the target step-down voltage is not the power rail voltage, the multi-voltage frequency adjustment circuit configures the target step-down voltage as the power rail voltage in the voltage conversion unit, controls the voltage conversion unit to perform on-chip step-down switching, and outputs the stepped-down voltage to the processor to be adjusted in the RFID reader.

4. The low power consumption control method of the RFID reader terminal according to claim 1, characterized in that: The processor to be adjusted represents the card selection task mode, inventory task mode, anti-collision task mode and access task mode that the RFID reader needs to execute in the form of a queue, and writes the state performance requirements corresponding to each task mode into the CSR register.

5. The low power consumption control method of the RFID reader terminal according to claim 1, characterized in that: The voltage conversion unit includes a multi-voltage frequency controller and a power supply chip; The multi-voltage frequency controller includes a control state machine, a frequency configuration, an off-chip voltage regulation configuration, and an on-chip voltage switch. The control state machine is respectively connected to the frequency configuration, the off-chip voltage regulation configuration, and the on-chip voltage switch in communication. The off-chip voltage regulation configuration is connected to the power chip via a serial communication bus, and controls the power chip to output three power rail voltages V with different voltages to the on-chip voltage regulation switch via the serial communication bus. H 、V M 、V L .

6. The low power consumption control method of the RFID reader terminal according to claim 5, characterized in that: The on-chip voltage regulation switch includes a clock gating circuit, a switching circuit and a low-impedance MOS tube switch; When the on-chip voltage regulation switch performs voltage regulation switching, the switching speed of the low-impedance MOS transistor switch is configured, and the clock gating circuit turns off the clock; The switching circuit controls the switching sequence of the low-impedance MOS switches, first turning off a group of MOS switches currently in the on state, and then turning on another group of MOS switches originally in the off state; After the two groups of MOS transistor switch circuits in the low-impedance MOS transistor switch complete the switching action at the configured speed, the clock gating circuit turns on the clock again.

7. The low power consumption control method of the RFID reader terminal according to claim 1, characterized in that: The clock frequency generation unit includes a ring oscillator, a configurable distributor and glitch-free clock switching; The ring oscillator serves as an on-chip clock generation circuit, and the oscillation frequency of the ring oscillator is configured to be 54.24Mhz when powered on; The configurable distributor is used to divide the output clock of the ring oscillator into an even number to obtain 27.12Mhz and 13.56Mhz clock signals; The glitch-free clock switching is used to switch the output clock between multiple divided clocks without glitch.

8. A low power consumption control device for an RFID reader terminal, characterized in that: Applied to an RFID reader, the RFID reader has a built-in multi-voltage frequency adjustment circuit, the multi-voltage frequency adjustment circuit includes a voltage conversion unit and a clock frequency generation unit; the device includes: Monitoring module: used to monitor the task status of the RFID reader and determine whether the task mode has been switched according to the monitored current task status. The task modes include the card selection task mode, inventory task mode, anti-collision task mode and access task mode executed by the RFID reader; Confirmation module: used for confirming whether to perform a voltage-frequency increase operation or a voltage-frequency decrease operation based on a voltage-frequency table when the task mode corresponding to the current task state is switched, wherein the voltage-frequency table is composed of operating voltages and clock frequencies preset according to different task modes by open-loop regulation control; A voltage and frequency boosting operation module is configured to, when it is determined that a voltage and frequency boosting operation is to be performed, cause the multi-voltage and frequency adjustment circuit to perform voltage boosting control, output the boosted voltage to the processor to be adjusted in the RFID reader, and control the clock frequency generation unit to perform a clock frequency boosting operation after the voltage stabilizes. The processor to be adjusted is provided with a CSR register, and the processor to be adjusted is connected to the multi-voltage and frequency adjustment circuit based on the CSR register. The voltage reduction frequency operation module is used to control the clock frequency generation unit to reduce the clock frequency when it is confirmed that the voltage reduction frequency operation is to be performed. After the clock frequency is reduced, the multi-voltage frequency adjustment circuit performs a boost control and outputs the reduced voltage to the processor to be adjusted in the RFID reader.

9. An electronic device comprising a processor and a memory, characterized in that: The processor runs the computer program or code stored in the memory to implement the low power consumption control method for the RFID reader terminal according to any one of claims 1 to 7.

10. A computer-readable storage medium for storing a computer program or code, characterized in that: When the computer program or code is executed by a processor, the low power consumption control method for an RFID reader terminal according to any one of claims 1 to 7 is implemented.

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