Neuromorphic processor supporting asynchronous event driving

Abstract

The invention discloses a neuromorphic processor supporting asynchronous event driving, and the processor comprises an event scheduler which is used for receiving an event, and transmitting the event to a neuromorphic processing core or an event queue according to a current time step state; the event scheduler is configured to ensure the correctness of an event processing sequence through time step conflict detection and a timestamp-based scheduling strategy; the event queue is used for caching non-current time step events or events which cannot be processed immediately; the neuromorphic processing core is used for executing an event processing program based on a neuromorphic instruction set architecture; the neuromorphic instruction set comprises a BRE instruction and is used for dynamically skipping to a corresponding processing program according to an event type and cooperating with the clock gating module to realize low-power-consumption mode switching; and the processor executes the BRE instruction after event processing is completed, enters a dormant state, and pauses the clock signal through clock gating until a new event arrives. The system has the advantages of good compatibility, good adaptability, low power consumption and the like.

Description

Technical Field

[0001] The present invention relates generally to the field of processor technology, and in particular to a neuromorphic processor supporting asynchronous event-driven operation. Background Art

[0002] Neuromorphic computing is a new computing paradigm that has rapidly developed in recent years. By simulating the computational methods of the human brain, it achieves more efficient perception, learning, and reasoning capabilities. This computing approach is widely used in the field of artificial intelligence, especially in deep learning, pattern recognition, and signal processing. However, compared with traditional architectures, neuromorphic computing emphasizes sparse computing and event-driven characteristics, offering higher power efficiency and computing potential.

[0003] By analyzing the computational bottlenecks and requirements of Spike Neural Networks (SNNs), defining a neuromorphic-specific instruction set, and integrating neuromorphic computing with the instruction set architecture, we can leverage the efficiency of neuromorphic computing in processing sparse events. Furthermore, the scalability of the instruction set architecture provides developers with significant freedom, allowing them to define and expand the instruction set based on specific application requirements and efficiently implement various neuron models. This is particularly important for neuromorphic computing because it allows designers to design a flexible and efficient neuron model processing architecture based on the characteristics of neuromorphic computing, combined with the characteristics of neuromorphic computing, by extending instructions and event-driven mechanisms.

[0004] Spiking neural networks are the most representative model in neuromorphic computing. Unlike traditional neural networks, spiking neural networks use discrete pulse signals to transmit information, which is more biologically realistic. However, they are also more difficult to implement efficiently on traditional hardware. In recent years, hardware design has gradually shifted to support the computing needs of spiking neural networks, and researchers have developed a variety of neuromorphic processors, such as IBM's TrueNorth and Intel's Loihi processing chips, respectively. These hardware are often specifically designed to optimize the performance of spiking neural networks, which in turn leads to a lack of flexibility.

[0005] Currently, IBM TrueNorth is one of the earliest hardware for neuromorphic computing. Its structure imitates biological neural networks and it adopts a large number of low-power designs. It implements 1 million neurons and 256 million synapses, and can process 4.6 billion pulse events per second. However, TrueNorth's architecture is relatively fixed, mainly supporting specific pulse neural network models, and lacks flexibility. At the same time, its design focuses on inference tasks, and has limited support for neural network training and traditional general-purpose computing. Intel Loihi is another neuromorphic hardware that supports online learning and dynamic weight adjustment. It integrates multiple neuron cores and can efficiently handle sparse calculations of pulse neural networks. Similar to TrueNorth, it is mainly based on a dedicated architecture, supports relatively limited computing modes, and requires additional hardware adaptation when facing rapidly changing network models. In addition, although its power consumption optimization is event-driven, there is still room for improvement in energy consumption when there are no events.

[0006] Existing neuromorphic computing hardware mostly adopts a highly specialized architecture, which is usually closely integrated with specific algorithms. Although this design can provide high performance in specific application scenarios, such as excellent performance in convolutional neural networks (CNN) or pulse neural networks, it also exposes significant limitations. Due to the deep coupling of hardware architecture and algorithm, it is difficult for these hardware to flexibly adapt to the needs of rapidly updated neural network models. If developers need to provide support for new network models or functions, they often need to redesign the hardware architecture. This process not only consumes a lot of resources, but also has a lengthy development cycle, which significantly limits the flexibility and adaptability of the hardware.

[0007] In terms of power optimization, existing neuromorphic hardware lacks event-driven mechanisms to reduce energy consumption. For example, during periods of non-event triggering—when neurons are silent—many hardware modules remain active and fail to fully enter low-power mode. This design fails to fully exploit the sparse event nature of spiking neural networks, resulting in higher energy consumption during low-load or idle periods and limited power efficiency.

[0008] Furthermore, many neuromorphic hardware designs focus on processing neural network inference or training tasks, but lack the ability to support general-purpose computing. This single-task-oriented design performs poorly in multi-tasking scenarios. For example, when this hardware attempts to run traditional programs or general-purpose computing tasks, it is often inefficient, severely limiting its use in diverse application scenarios. Summary of the Invention

[0009] In response to the technical problems existing in the prior art, the present invention provides a neuromorphic processor that effectively solves the timestep conflict problem, avoids errors in the processing order of events at different timesteps, and supports asynchronous event-driven processing with low power consumption.

[0010] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0011] A neuromorphic processor supporting asynchronous event-driven operation, comprising:

[0012] an event scheduler for receiving events and sending them to a neuromorphic processing core or an event queue based on the current time step state; the event scheduler is configured to ensure the correctness of event processing order through time step conflict detection and a timestamp-based scheduling strategy;

[0013] An event queue, coupled with the event scheduler, for caching events that are not in the current time step or that cannot be processed immediately;

[0014] A neuromorphic processing core is configured to execute event handlers based on a neuromorphic instruction set architecture (NIA). The NIA is an event-oriented instruction set that includes BRE instructions for dynamically jumping to corresponding handlers based on event types and coordinating with a clock gating module to implement low-power mode switching. After event processing is complete, the processor executes the BRE instructions, enters a sleep state, and pauses the clock signal through clock gating until a new event arrives.

[0015] Preferably, the neuromorphic instruction set architecture is configured with:

[0016] Multiple function-configurable registers, some of which are general-purpose registers and others are special-function registers, used to store synaptic weights, source and destination neuron numbers, neuron states, and time delay parameters;

[0017] The neuronal instruction memory and neuronal data memory are tightly coupled with the neuromorphic processing core to support storage and computing in one operation;

[0018] The neuromorphic instruction set reserves coding space to support users to expand instruction functions through custom instruction coding.

[0019] Preferably, the special function register includes:

[0020] Neuron status register, used to store the membrane potential of the current event neuron;

[0021] Synaptic weight register, used to dynamically store the connection weight between the source neuron and the target neuron;

[0022] Membrane potential threshold register, configured to trigger neuron reset action in timestep-only events.

[0023] Preferably, the neuromorphic instruction set architecture adopts the bfloat16 data format.

[0024] Preferably, the neuromorphic instruction set architecture adopts a four-stage pipeline structure, including four stages: instruction fetch, decoding, operand fetch and execution; the instruction fetch stage is used to read instructions from the neuronal instruction memory; the decoding stage is used to parse the instruction type and operand address; the operand fetch stage is used to load data from the register or neuronal data memory; the execution stage is used to complete the calculation through the arithmetic logic unit and write the result back to the register or memory.

[0025] The present invention also discloses an asynchronous event scheduling method based on the above-mentioned neuromorphic processor supporting asynchronous event driving, comprising the steps of:

[0026] Receive input events and extract their time step identifiers;

[0027] If the event time step matches the current time step and the neuromorphic processing core is in the ready state, the event is directly transmitted to the neuromorphic processing core; otherwise, the event is written to the event queue in the order of the time step;

[0028] After the neuromorphic processing core finishes processing the current event, it selects the earliest event that entered the queue from the event queue for processing;

[0029] When the queue is empty and no new events arrive, the BRE instruction is triggered to put the processor into a low-power sleep state.

[0030] Preferably, the execution logic of the BRE instruction includes:

[0031] When a Spike-only event is detected, the weight accumulation and state update operations of the target neuron are triggered;

[0032] When a Timestep-only event is detected, the global neuron membrane potential threshold is determined, and pulses are emitted and the membrane potential of the neurons exceeding the threshold are reset;

[0033] When a Spike-with-Timestep event is detected, the postsynaptic neuron state is synchronously updated and a new spike event is generated.

[0034] Preferably, the specific process of synchronously updating the postsynaptic neuron state and generating a new pulse event is:

[0035] At each time step, the processor calculates the change in membrane potential of the postsynaptic neuron based on the pulse signal generated by the presynaptic neuron; first, it detects whether the presynaptic neuron generates a pulse in the current time step; if a pulse is detected, it calculates the impact of the pulse on the target neuron; based on the synaptic weight, it completes the state update; when the membrane potential exceeds the threshold, the neuron generates a new pulse and propagates it to subsequent neurons; otherwise, the membrane potential will continue to accumulate in the current time step until the discharge condition is met.

[0036] Preferably, the specific process of the processor entering the low-power sleep state is:

[0037] After the BRE instruction is executed, the clock signals of the neuromorphic processing core and the event scheduler are turned off;

[0038] When a new event arrives, the clock is reactivated through the interrupt signal and the program jumps to the corresponding handler entry address according to the event type;

[0039] The clock gating module is configured to reduce the power consumption of the processor to a static power consumption level during periods of inactivity.

[0040] Preferably, after processing each event, the processor automatically executes a BRE instruction to put the processor into an event waiting state; if there is no event to be processed, it enters a low power consumption state, otherwise it dynamically jumps to the corresponding event handler according to the type of event that arrives.

[0041] Compared with the prior art, the advantages of the present invention are:

[0042] This invention innovatively integrates neuromorphic computing and an asynchronous event-based instruction set architecture (AIEIA), cleverly combining the flexibility of traditional general-purpose processors with the efficiency of neuromorphic hardware. This approach addresses the challenge of balancing flexibility and specialized performance in hardware architecture. This architecture not only efficiently handles the computational tasks of spiking neural networks, but also maintains support for traditional computing requirements, demonstrating excellent compatibility and adaptability. In particular, in event-driven mode, this invention can efficiently handle the computational demands of complex neural networks, providing a highly effective system solution.

[0043] The invention also introduces event-driven clock gating technology, leveraging the event sparsity of spiking neural networks to significantly reduce ineffective energy consumption during idle periods. This design not only significantly improves energy efficiency, making it particularly suitable for low-power applications, but also simplifies hardware implementation and provides flexible and efficient scalability through a register set and pipeline architecture optimized for spiking neural network tasks.

[0044] Building on this foundation, the introduction of the event scheduler and time step concepts further optimizes the timing management of computational processes. The event scheduler effectively manages time steps, ensuring that events are triggered sequentially within the correct time step, avoiding conflicts between time steps. This not only improves computational accuracy and efficiency, but also enables the system to handle asynchronous pulse events with greater precision and efficiency.

[0045] Overall, the present invention is significantly superior to existing technologies in terms of performance, energy efficiency, flexibility, and timing management, and provides an innovative design approach for low-power, high-efficiency neuromorphic computing hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 FIG. 1 is an architectural diagram of a neuromorphic processor according to an embodiment of the present invention.

[0047] Figure 2 FIG. 1 is a structural diagram of a neuromorphic processor according to an embodiment of the present invention.

[0048] Figure 3 This is a structural diagram of the neuromorphic instruction set in the present invention.

[0049] Figure 4 Schematic diagram of the sparse event flow of the pulse neural network in the present invention.

[0050] Figure 5 This is the Spike-only event flow chart in the present invention.

[0051] Figure 6 This is the Timestep-only event flow chart in the present invention.

[0052] Figure 7 This is the Spike-with-Timestep event flow chart in the present invention.

[0053] Figure 8 This is a schematic diagram of the BRE instruction execution in the present invention. DETAILED DESCRIPTION

[0054] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0055] like Figure 1 As shown, the neuromorphic processor supporting asynchronous event-driven provided by an embodiment of the present invention includes an event scheduler, an event queue and a neuromorphic processing core;

[0056] An event scheduler, which receives events and sends them to the neuromorphic processing core or event queue based on the current time step state; the event scheduler is configured to ensure the correct order of event processing through time step conflict detection and a timestamp-based scheduling strategy (first in, first out);

[0057] The event queue, coupled with the event scheduler, is used to cache events that are not in the current time step or cannot be processed immediately;

[0058] The neuromorphic processing core is used to execute event handlers based on the neuromorphic instruction set architecture. The neuromorphic instruction set is an event-oriented instruction set that includes BRE instructions, which are used to dynamically jump to the corresponding handler based on the event type and work with the clock gating module to achieve low-power mode switching. After the event processing is completed, the processor executes the BRE instructions, enters the sleep state, and suspends the clock signal through clock gating until a new event arrives.

[0059] In the above processor architecture, the asynchronous event processing mechanism in the pulse neural network is adopted, and the concept of time step is introduced. Specifically, the events input by the network on chip (NOC) will first pass through the event scheduler to handle the time step problem of the pulse event, ensuring that events within different time steps are processed correctly. Since the pulse neural network is based on an event-driven model, the pulse events emitted by each neuron are usually asynchronous. Therefore, when processing these events, the problem of time step conflict will be faced. To solve this problem, before the pulse event enters the neuromorphic processing core, the event is first pre-processed by the event scheduler, specifically:

[0060] The event scheduler first determines whether the current pulse event belongs to the current time step. Since events at different time steps are processed independently, ensuring that each event is processed within the correct time step is one of the core tasks of the system.

[0061] The event scheduler further determines whether the event should be sent directly to the neuromorphic processing core for processing or first written to the event queue. The event queue is used to cache events that cannot be processed immediately, ensuring that events are processed in the correct order and timing.

[0062] Before being processed by the neuromorphic processing core, the event scheduler ensures that events do not conflict in their timesteps. If there are unprocessed events in the event queue, the scheduler passes them to the neuromorphic processing core according to the timestamp ordering rules. This ensures that all events are processed fairly and avoids data loss or misprocessing due to timestep conflicts.

[0063] Through this mechanism, the time step conflict problem can be effectively solved, the time step confusion of events can be avoided, and each pulse event can be guaranteed to enter the processing unit according to the predetermined time step sequence, thereby ensuring the correctness and stability of the pulse neural network model.

[0064] like Figure 2As shown, to achieve efficient computing and data processing, the innovative neuromorphic instruction set architecture (ISA), based on an event-driven mechanism, is equipped with 32 registers. These registers are extended with specific functions, such as storing synaptic weights, source and destination neuron numbers, neuron states (such as membrane potential thresholds), and time delay parameters. In addition, a 2048-byte neuron instruction memory (ICCM) and a 1024-byte neuron data memory (DCCM) are defined to support the development of various neuron models and provide integrated storage and computation. Specifically, the instruction set defines a flexible register numbering and allocation strategy, with floating-point and integer registers 0 to 15 designed as general-purpose registers to support a variety of operations, such as data transfer, arithmetic operations, and logical operations. This design ensures high register flexibility and reusability across different tasks. Furthermore, several special function registers are defined to support specific parameter management during spiking neural network operations. For example, they can store key data related to spiking neural networks, including information such as time delays, synaptic weights, and membrane potential thresholds. These parameters are crucial for simulating neuronal behavior, performing time-step updates, and triggering spiking events.

[0065] Specifically, these special registers play a crucial role in instruction execution. For example, in spike event processing within a spiking neural network, the time delay register simulates the delay between neural signals as they propagate between neurons, while the synaptic weight register stores the weights of neuronal connections, thereby influencing the strength of signal transmission. Through efficient management of these registers, the processor can complete complex neural network computations with lower energy consumption while maintaining high accuracy.

[0066] The processor utilizes a four-stage pipeline design, encompassing instruction fetch, decode, operand fetch, and execution. This structure fully utilizes hardware resources and parallelizes instruction processing by dividing instructions into stages, thereby improving instruction throughput and overall performance. This architecture optimizes the execution efficiency of complex operations in spiking neural network tasks.

[0067] During the parameter initialization phase, the processor loads the neuron model, the number of neurons, and the time window parameters for event processing, while also pointing to information such as synaptic weights and neuron connection topology. This phase ensures that the processor can correctly identify the mapping relationship between source neurons and target neurons.

[0068] The instruction set architecture of the present invention adopts the bfloat16 (BF16 for short) data format, which is a data representation method widely used in the field of deep learning. While maintaining the same numerical range as single-precision floating-point numbers (FP32 for short), bfloat16 reduces the bit width and compresses the representation of floating-point numbers from 32 bits to 16 bits, thereby reducing storage requirements and improving computing efficiency. Moreover, the computing accuracy is higher than the 8-bit integer operations commonly used in neural networks. This feature significantly improves performance and energy efficiency while reducing memory bandwidth requirements and power consumption, making it particularly suitable for large-scale neural network training and reasoning scenarios.

[0069] In order to adapt to different neural network applications, the processor instruction set of the present invention is flexible and complete and can support a variety of neuron computing models. For example, in the LIF (Leaky Integrate-and-Fire) model, the processor can perform leakage current calculations and threshold determinations as well as the accumulation of neuron membrane potentials to simulate the pulse emission characteristics of neurons. The processor instruction set also supports more complex nonlinear dynamic calculations and accurately simulates the diverse behaviors of neurons, such as the more complex Izhikevich model. Through the flexible combination of instructions, the processor can flexibly adapt to different neural network structures and algorithm requirements, and has significant versatility.

[0070] The instruction set of the present invention also includes a set of neuromorphic instruction sets, which users can flexibly expand according to the custom instruction encoding format. Figure 3 As shown in the figure, the core of the neuromorphic instruction set includes optimizing event response and sparse computing efficiency. In traditional instruction set architectures, processors usually use synchronous mode, executing instructions at a fixed rhythm in each cycle. This method is less efficient when processing discontinuous or sparse tasks. The event-driven architecture is centered on event triggering. The computing module is activated only when an event occurs. When there is no event, the processor enters a low-power mode, thereby significantly reducing energy consumption. This design is particularly critical in pulse neural networks because pulse neural networks have the characteristics of sparse excitation and time step synchronization (such as Figure 4 It is difficult for traditional hardware to process efficiently.

[0071] The processor of this invention utilizes a general-purpose computing extension approach to not only support spiking neural network computations but also offers flexible hardware and instruction set configuration capabilities. Users can extend the instruction set based on specific needs, adapting to various new neural network models. This flexible design effectively reduces hardware development costs and cycle time, significantly improving system adaptability.

[0072] The present invention also introduces an optimized event-driven mechanism, combined with clock gating technology to optimize power consumption. In the absence of events, the processor can enter a complete sleep state, significantly reducing inefficient energy consumption. This mechanism fully utilizes the sparse computing characteristics of spiking neural networks, enabling the hardware to not only excel in high-load tasks but also significantly reduce power consumption in low-load or idle states.

[0073] Through the above innovations, the present invention not only breaks through the flexibility and energy optimization limitations of traditional neuromorphic hardware and improves scalability, but also takes into account general computing capabilities, providing broader possibilities for the application of hardware in multi-tasking scenarios.

[0074] An embodiment of the present invention further provides an asynchronous event scheduling method based on the above-mentioned neuromorphic processor supporting asynchronous event driving, comprising the steps of:

[0075] Receive input events and extract their time step identifiers;

[0076] If the event time step matches the current time step and the neuromorphic processing core is in the ready state, the event is transmitted directly to the neuromorphic processing core; otherwise, the event is written to the event queue in the order of the time step;

[0077] When the neuromorphic processing core finishes processing the current event, it selects the earliest event that entered the queue from the event queue for processing;

[0078] When the queue is empty and no new events arrive, the BRE instruction is triggered to put the processor into a low-power sleep state.

[0079] Specifically, the instruction set introduces the BRE (BRanch on Event) instruction for efficiently handling multiple key event types, such as spike-only, timestep-only, and spike-with-timestep. The introduction of the BRE instruction greatly simplifies the switching time between different events and improves the processor's responsiveness in multi-event processing scenarios.

[0080] Spike-only events simulate the update of biological neuron membrane potentials during a time step. They can be used for both signal transmission in the input layer and the accumulation of neuron membrane potentials within a time step. This process forms the core mechanism of spiking neural networks. In this paper, spike-only event processing is efficiently accomplished by an optimized instruction set, whose main functions include event reception and neuron state calculation.

[0081] like Figure 5As shown in the figure, when the processor detects a spike-only event (i.e., a neuron generates a spike signal), the corresponding computational logic is rapidly triggered. Based on the event information (such as the source and target neuron IDs), the processor retrieves synaptic information and updates the membrane potential and target neuron state, including key calculations such as weight accumulation. This process relies on an event-driven mechanism for efficient processing, enabling neuronal computation to quickly respond to input spikes and complete state updates. Figure 5 The dotted box part of shows the process intuitively.

[0082] Timestep-only events are specifically designed for global control of the input layer, giving timesteps more explicit computational semantics. They can be used for time synchronization in non-spiking neural network computations, and can also serve as an auxiliary mechanism for spiking events. For example, this event can uniformly evaluate the membrane potential of all neurons at each timestep and, based on the calculated result, decide whether to fire a spike signal, thereby defining a new output event.

[0083] like Figure 6 As shown in the figure, whenever a timestep-only event is triggered, the processor performs a series of processing operations on the neuron's membrane potential. First, it checks whether the neuron's current membrane potential exceeds the set threshold voltage. For neurons that exceed the threshold, the processor triggers a corresponding event, causing the membrane potential to quickly return to its resting state and emit a pulse signal at the synapse. This process simulates the periodic membrane potential updates of biological neurons, allowing spiking neural networks to naturally incorporate the concept of timesteps. For example, in certain neuromorphic computing tasks, timestep-only events can prevent the membrane potential from accumulating indefinitely and perform normalization at appropriate timesteps to maintain computational stability. Figure 6 The dotted box in the figure intuitively shows the triggering process of the event and its role in updating the neuronal membrane potential.

[0084] like Figure 7 As shown in Figure 1, the Spike-with-Timestep event is a global control mechanism after the input layer. It gives neuronal computations explicit temporal semantics based on the time step. This supports non-spiking neural network computations and serves as an auxiliary mechanism for spike events, ensuring that interneuronal spike transmission and state updates remain synchronized. When a time step arrives, if a neuron after the input layer generates a spike, a Spike-with-Timestep event must be triggered to ensure that the spike signal propagates correctly according to the neural network computational rules.

[0085] At each time step, the processor calculates the change in membrane potential of the postsynaptic neuron based on the pulse signal generated by the presynaptic neuron. First, it detects whether the presynaptic neuron generates a pulse in the current time step. If a pulse is detected, the impact of the pulse on the target neuron is calculated. According to the synaptic weight, the state update is completed. When the membrane potential exceeds the threshold, the postsynaptic neuron generates a new pulse and propagates it to the subsequent neurons. Otherwise, the membrane potential will continue to accumulate in subsequent time steps until the discharge conditions are met. In addition, the triggering of the Spike-with-Timestep event ensures that all neurons calculate synchronously in the time step. In non-spiking neural network computing tasks, this event can also be used as a time synchronization signal to coordinate the collaborative work of different computing units and improve computing consistency.

[0086] The introduction of spike-with-timestep events enables the processor to precisely control the evolution of neuron states, ensuring that the membrane potential updates of postsynaptic neurons conform to the computational laws of biological neural networks. This mechanism also enhances computational flexibility, enabling efficient integration of spiking neural network computations with non-spiking neural network tasks, improving overall computational efficiency while ensuring accuracy. Based on an event-driven processing approach, this mechanism reduces unnecessary computational overhead, optimizing the system's efficiency and real-time performance.

[0087] After processing each event, the processor of this invention automatically executes a BRE instruction, placing the processor in an event-waiting state. If there are no events to process, the processor enters a low-power state; otherwise, it dynamically jumps to the appropriate event handler based on the type of the upcoming event. This design fully leverages the efficient nature of event-driven mechanisms and plays a key role in this architecture.

[0088] Specifically, the BRE instruction is combined with clock gating technology to effectively control the power consumption of the processor. When the BRE instruction is executed to enter the low power state when the event is completed, the processor will actively suspend the clock signal (such as Figure 8 As shown in the figure, the processor enters a low-power standby state until the next event arrives. At this point, the processor not only reduces unnecessary energy consumption but also makes good use of the sparsity characteristics of the spiking neural network to avoid performing meaningless calculations during periods without events. When a new event is triggered, the clock signal is reactivated, and the processor immediately resumes from standby mode and jumps to the corresponding program segment based on the event type. This design ensures that the processor can respond quickly to complex asynchronous events while avoiding power consumption caused by continuous operation.

[0089] This invention innovatively integrates neuromorphic computing and an asynchronous event-based instruction set architecture (AIEIA), cleverly combining the flexibility of traditional general-purpose processors with the efficiency of neuromorphic hardware. This approach addresses the challenge of balancing flexibility and specialized performance in hardware architecture. This architecture not only efficiently handles the computational tasks of spiking neural networks, but also maintains support for traditional computing requirements, demonstrating excellent compatibility and adaptability. In particular, in event-driven mode, this invention can efficiently handle the computational demands of complex neural networks, providing a highly effective system solution.

[0090] The invention also introduces event-driven clock gating technology, leveraging the sparsity of spiking neural networks to significantly reduce ineffective neuron energy consumption. This design not only significantly improves energy efficiency, making it particularly suitable for low-power applications, but also simplifies hardware implementation and provides flexible and efficient scalability through a register set and pipeline architecture optimized for spiking neural network tasks.

[0091] Building on this foundation, the introduction of the event scheduler and time step concepts further optimizes the timing management of computational processes. The event scheduler effectively manages time steps, ensuring that events are triggered sequentially within the correct time step, avoiding conflicts between time steps. This not only improves computational accuracy and efficiency, but also enables the system to handle asynchronous pulse events with greater precision and efficiency.

[0092] Overall, this invention is significantly superior to existing technologies in terms of performance, energy efficiency, flexibility, and timing management, providing innovative design ideas for the next generation of low-power, high-efficiency neuromorphic computing hardware.

[0093] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A neuromorphic processor supporting asynchronous event-driven operation, characterized in that: include: An event dispatcher, which receives events and sends them to the neuromorphic processing core or event queue based on the current time step state; The event scheduler is configured to ensure the correctness of event processing order through time step conflict detection and timestamp-based scheduling strategy; An event queue, coupled with the event scheduler, for caching events that are not in the current time step or that cannot be processed immediately; A neuromorphic processing core is configured to execute event handlers based on a neuromorphic instruction set architecture (NIA). The NIA is an event-oriented instruction set that includes BRE instructions for dynamically jumping to corresponding handlers based on event types and coordinating with a clock gating module to implement low-power mode switching. After event processing is complete, the processor executes the BRE instructions, enters a sleep state, and pauses the clock signal through clock gating until a new event arrives.

2. The neuromorphic processor supporting asynchronous event-driven according to claim 1, characterized in that The neuromorphic instruction set architecture is configured with: Multiple function-configurable registers, some of which are general-purpose registers and others are special-function registers, used to store synaptic weights, source and destination neuron numbers, neuron states, and time delay parameters; The neuronal instruction memory and neuronal data memory are tightly coupled with the neuromorphic processing core to support storage and computing in one operation; The neuromorphic instruction set reserves coding space to support users to expand instruction functions through custom instruction coding.

3. The neuromorphic processor supporting asynchronous event-driven according to claim 2, characterized in that The special function registers include: Neuron status register, used to store the membrane potential of the current event neuron; Synaptic weight register, used to dynamically store the connection weight between the source neuron and the target neuron; Membrane potential threshold register, configured to trigger neuron reset action in timestep-only events.

4. The neuromorphic processor supporting asynchronous event-driven according to claim 1, 2 or 3, characterized in that: The neuromorphic instruction set architecture uses the bfloat16 data format.

5. The neuromorphic processor supporting asynchronous event-driven according to claim 1, 2 or 3, characterized in that: The neuromorphic instruction set architecture adopts a four-stage pipeline structure, including four stages: instruction fetch, decoding, operand fetch, and execution. The instruction fetch stage is used to read instructions from the neuronal instruction memory; the decoding stage is used to parse the instruction type and operand address; the operand fetch stage is used to load data from registers or neuronal data memory. The execute stage is used to complete the calculation through the arithmetic logic unit and write the results back to registers or memory.

6. An asynchronous event scheduling method for a neuromorphic processor supporting asynchronous event-driven operation according to any one of claims 1 to 5, characterized in that: Including steps: Receive input events and extract their time step identifiers; If the event time step matches the current time step and the neuromorphic processing core is in the ready state, the event is directly transmitted to the neuromorphic processing core; otherwise, the event is written to the event queue in the order of the time step; After the neuromorphic processing core finishes processing the current event, it selects the earliest event that entered the queue from the event queue for processing; When the queue is empty and no new events arrive, the BRE instruction is triggered to put the processor into a low-power sleep state.

7. The asynchronous event scheduling method according to claim 6, characterized in that: The execution logic of the BRE instruction includes: When a Spike-only event is detected, the weight accumulation and state update operations of the target neuron are triggered; When a Timestep-only event is detected, the global neuron membrane potential threshold is determined, and pulses are emitted and the membrane potential of the neurons exceeding the threshold are reset; When a Spike-with-Timestep event is detected, the postsynaptic neuron state is synchronously updated and a new spike event is generated.

8. The asynchronous event scheduling method according to claim 7, characterized in that: The specific process of synchronously updating the state of the postsynaptic neuron and generating new spike events is: At each time step, the processor calculates the change in membrane potential of the postsynaptic neuron based on the pulse signal generated by the presynaptic neuron; first, it detects whether the presynaptic neuron generates a pulse in the current time step; if a pulse is detected, it calculates the impact of the pulse on the target neuron; based on the synaptic weight, it completes the state update; when the membrane potential exceeds the threshold, the neuron generates a new pulse and propagates it to subsequent neurons; otherwise, the membrane potential will continue to accumulate in the current time step until the discharge condition is met.

9. The asynchronous event scheduling method according to claim 6, 7 or 8, characterized in that: The specific process of the processor entering the low-power sleep state is as follows: After the BRE instruction is executed, the clock signals of the neuromorphic processing core and the event scheduler are turned off; When a new event arrives, the clock is reactivated through the interrupt signal and the program jumps to the corresponding handler entry address according to the event type; The clock gating module is configured to reduce the power consumption of the processor to a static power consumption level during periods of inactivity.

10. The asynchronous event scheduling method according to claim 6, 7 or 8, characterized in that: After processing each event, the processor will automatically execute a BRE instruction to put the processor into the event waiting state; if there is no event to be processed, it will enter the low power state, otherwise it will dynamically jump to the corresponding event handler according to the type of event that arrives.

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