Semiconductor memory device

Abstract

The invention provides a semiconductor memory device which can operate at a high speed. The semiconductor memory device includes a substrate, a plurality of memory blocks, and a control circuit. The control circuit is configured so as to be able to continuously execute the second program operation after sequentially executing the first pre-charge operation and the first program operation during the write operation in the first mode. In the first precharge operation, a predetermined voltage is supplied to the first word line. In a first program operation, a first voltage is supplied to the first select gate line, a first program voltage is supplied to the first word line, and a write path voltage smaller than the first program voltage is supplied to the second word line. In a second program operation, the first voltage is supplied to the second select gate line, a second program voltage greater than the write-via voltage is supplied to the first word line, and the write-via voltage is supplied to the second word line.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Background Art

[0002] There is known a semiconductor memory device including a substrate, a plurality of memory blocks arranged in parallel with the substrate, and a control circuit electrically connected to the plurality of memory blocks. Summary of the Invention

[0003] Provided is a semiconductor memory device capable of high-speed operation.

[0004] A semiconductor memory device according to one embodiment includes: a substrate; a plurality of memory blocks arranged side by side with the substrate in a first direction intersecting a surface of the substrate and arranged in a second direction intersecting the first direction; and a control circuit connected to the plurality of memory blocks and configured to perform a write operation. The plurality of memory blocks each include: a first drain-side selection transistor and a second drain-side selection transistor; a first source-side selection transistor and a second source-side selection transistor; a first memory cell transistor and a second memory cell transistor electrically connected in series between the first drain-side selection transistor and the first source-side selection transistor; a third memory cell transistor and a fourth memory cell transistor electrically connected in series between the second drain-side selection transistor and the second source-side selection transistor; a first bit line and a second bit line electrically connected to the first drain-side selection transistor and the second drain-side selection transistor, respectively. The first selection gate line is electrically connected to the gate electrode of the first drain side selection transistor; the second selection gate line is electrically connected to the gate electrode of the second drain side selection transistor; the third selection gate line is electrically connected to the gate electrodes of the first source side selection transistor and the second source side selection transistor; the source line is electrically connected to the first source side selection transistor and the second source side selection transistor; the first word line is electrically connected to the gate electrodes of the first memory cell transistor and the third memory cell transistor; and the second word line is electrically connected to the gate electrodes of the second memory cell transistor and the fourth memory cell transistor.

[0005] The control circuit is configured to be able to execute a first mode programming operation in which a first precharge operation and a first programming operation are sequentially executed and then a second programming operation is continuously executed.

[0006] The control circuit supplies a predetermined voltage to the first word line during a first precharge operation. In a first programming operation, the control circuit supplies a first voltage to the first select gate line, a second voltage lower than the first voltage to the second select gate line, a first programming voltage to the first word line, and a write path voltage lower than the first programming voltage to the second word line. In a second programming operation, the control circuit supplies a second voltage to the first select gate line, the first voltage to the second select gate line, a second programming voltage higher than the write path voltage to the first word line, and a write path voltage to the second word line. Furthermore, after supplying the first programming voltage and before supplying the second programming voltage, the control circuit switches the voltage of the first select gate line from the first voltage to the second voltage, and switches the voltage of the second select gate line from the second voltage to the first voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 2 is a schematic block diagram showing the configuration of the memory system 10 .

[0008] Figure 2 It is a schematic block diagram showing the structure of the memory die MD.

[0009] Figure 3 This is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0010] Figure 4 This is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0011] Figure 5 It is a schematic perspective view showing a partial configuration of the memory die MD.

[0012] Figure 6 Yes Figure 5 A schematic enlarged view of a portion of the structure.

[0013] Figure 7 This is a schematic bar graph for explaining the threshold voltage of a memory cell MC recording 1-bit data.

[0014] Figure 8 This is a timing diagram used to explain the write operation.

[0015] Figure 9 These are schematic cross-sectional views used to illustrate programming operations.

[0016] Figure 10 It is a schematic cross-sectional view for explaining the execution sequence of the write operation.

[0017] Figure 11 This is a timing chart for explaining the write operation in the first mode.

[0018] Figure 12 This is a timing chart for explaining the writing operation in the second mode.

[0019] Figure 13 This is a timing chart for explaining the write operation in the first mode of Modification 1.

[0020] Figure 14 This is a timing chart for explaining the write operation in the second mode of Modification 1.

[0021] Figure 15 This is a timing chart for explaining the write operation in the first mode of the second modification.

[0022] Figure 16 This is a timing chart for explaining the write operation in the second mode of the second modification.

[0023] Figure 17 This is a timing chart for explaining the write operation in the first mode of Modification 3.

[0024] Figure 18 This is a timing chart for explaining the write operation in the second mode of Modification 3.

[0025] Figure 19 This is a timing chart for explaining the write operation in the first mode of the second embodiment.

[0026] Figure 20 This is a timing chart for explaining the write operation in the first mode of the third embodiment. DETAILED DESCRIPTION

[0027] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the following embodiment is merely an example and is not intended to limit the present invention.

[0028] In this specification, the term "semiconductor storage device" may refer to a memory die (memory chip), a memory system that includes a controller die, such as a memory card or SSD (Solid State Drive), or a configuration that includes a host computer, such as a smartphone, tablet, or personal computer.

[0029] In this specification, when a "control circuit" is mentioned, it sometimes refers to a peripheral circuit such as a sequencer provided in a memory die, sometimes refers to a controller die or controller chip connected to a memory die, and sometimes refers to a configuration including both.

[0030] In this specification, when a first configuration is referred to as being "electrically connected to" a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even when the second transistor is in the OFF state.

[0031] In this specification, when the first configuration is mentioned as being “connected between the second configuration and the third configuration,” it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0032] In addition, in this specification, when it is mentioned that a circuit or the like "connects" two wirings or the like, for example, it may mean that the circuit or the like includes a transistor or the like, and the transistor or the like is provided in a current path between the two wirings and is in an ON state.

[0033] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0034] [First embodiment]

[0035] [Memory system 10]

[0036] Figure 1 2 is a schematic block diagram showing the configuration of the memory system 10 .

[0037] The memory system 10 reads, writes, and erases user data based on signals sent from the host computer 20. The memory system 10 is, for example, a memory chip, memory card, SSD, or other system capable of storing user data. The memory system 10 includes multiple memory chips MD that store user data, and a controller CD connected to the multiple memory chips MD and the host computer 20. The controller CD includes, for example, a processor, RAM (Random Access Memory), ROM (Read-Only Memory), and an ECC (Error Checking and Correcting) circuit, and performs processes such as logical address to physical address conversion, bit error detection / correction, and wear leveling. The controller CD also includes a storage area MEM10, described below.

[0038] [Composition of memory die MD]

[0039] Figure 2It is a schematic block diagram showing the structure of the memory die MD. Figure 3 and Figure 4 This is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0040] in addition, Figure 2 The middle figure shows a plurality of control terminals, etc. These control terminals are sometimes shown as control terminals corresponding to high active signals (positive logic signals), sometimes as control terminals corresponding to low active signals (negative logic signals), and sometimes as control terminals corresponding to both high active signals and low active signals. Figure 2 In the specification, the symbols of the control terminals corresponding to the low active signals include an overline (upper line). In the specification, the symbols of the control terminals corresponding to the low active signals include a slash (" / ").

[0041] in addition, Figure 2 The descriptions are merely examples, and the specific configuration can be adjusted as appropriate. For example, some or all high-active signals can be set to low-active signals, or some or all low-active signals can be set to high-active signals. Furthermore, the terminal RY / ( / BY) described later outputs the ready signal, which is an active-high signal, and the busy signal, which is an active-low signal. The slash mark (" / ") between RY and ( / BY) is a separator that denotes the ready and busy signals.

[0042] like Figure 2 As shown, the memory die MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA.

[0043] [Circuit Configuration of Memory Cell Array MCA]

[0044] Memory cell array MCA Figure 3 As shown, a plurality of memory blocks BLK are provided. Each of the plurality of memory blocks BLK includes a plurality of string units SU. Each of the plurality of string units SU includes a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to a peripheral circuit PC via a bit line BL. Furthermore, the other ends of each of the plurality of memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0045] The memory string MS includes a drain-side select transistor STD connected in series between a bit line BL and a source line SL, a plurality of memory cells MC (memory cell transistors), and a source-side select transistor STS. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors (STD, STS).

[0046] A memory cell MC is a field-effect transistor (memory transistor) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge accumulation film. The threshold voltage of a memory cell MC varies depending on the amount of charge in the voltage accumulation film. A memory cell MC stores one or more bits of data. The memory cell MC stores data as the magnitude of the threshold voltage. Furthermore, word lines WL are connected to the gate electrodes of the multiple memory cells MC corresponding to a memory string MS. These word lines WL are connected in common to all memory strings MS in a memory block BLK.

[0047] The selection transistor (STD, STS) is a field effect transistor having a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the drain-side selection transistor STD is connected to the drain-side selection gate line SGD. The gate electrode of the source-side selection transistor STS is connected to the source-side selection gate line SGS. The drain-side selection gate line SGD is provided corresponding to the string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK. Hereinafter, the drain-side selection gate line SGD and the source-side selection gate line SGS are sometimes referred to as the selection gate lines (SGD, SGS).

[0048] [Circuit configuration of peripheral circuit PC]

[0049] Peripheral circuit PC such as Figure 2 As shown, the MCU includes a row decoder RD, a sense amplifier module SAM, a cache memory CM, a counter CNT, a voltage generator VG, and a sequencer SQC. Furthermore, the peripheral circuit PC includes an address register ADR, a command register CMR, and a status register STR. Furthermore, the peripheral circuit PC includes an input / output control circuit I / O and a logic circuit CTR.

[0050] [Configuration of Row Decoder RD]

[0051] Row decoder RD( Figure 2 ) has the address data D ADD In addition, the row decoder RD ( Figure 2 ) has a block selection circuit and a voltage selection circuit for transmitting an operating voltage to a memory cell array MCA according to an output signal of an address decoder.

[0052] [Configuration of the Sense Amplifier Module SAM]

[0053] The sense amplifier module SAM includes, for example, a plurality of sense amplifier units SAU ( Figure 4 ).like Figure 4 As shown, the sense amplifier unit SAU includes a sense amplifier SA, a wiring LBUS, and latch circuits SDL, DL0 to DLn (n is a natural number). A charging transistor 55 for precharging is connected to the wiring LBUS ( Figure 4 ). The wiring LBUS is connected to the wiring DBUS via the switching transistor DSW.

[0054] The sense amplifier SA includes a sense transistor 41. The sense transistor 41 discharges the charge in the wiring LBUS according to the current flowing in the bit line BL. The source electrode of the sense transistor 41 is connected to a supply voltage V SS A voltage supply line (ground voltage) is provided. The drain electrode is connected to wiring LBUS via switching transistor 42. The gate electrode is electrically connected to bit line BL via sense node SEN, discharge transistor 43, node COM, clamp transistor 44, and withstand voltage transistor 45. Furthermore, sense node SEN is connected to internal control signal line CLKSA via capacitor 48.

[0055] In addition, the sense amplifier SA includes a voltage transmission circuit. The voltage transmission circuit makes the node COM and the sense node SEN connected to the supplied voltage V according to the data stored in the latch circuit SDL. DD The voltage supply line, or the voltage V SS The voltage supply line is selectively turned on. The voltage transmission circuit includes a node N1, a charging transistor 46, a charging transistor 49, a charging transistor 47, and a discharge transistor 50. The charging transistor 46 is connected between the node N1 and the sensing node SEN. The charging transistor 49 is connected between the node N1 and the node COM. The charging transistor 47 is connected between the node N1 and the supplied voltage V DD The discharge transistor 50 is connected between the node N1 and the voltage supply line V SS In addition, the gate electrodes of the charging transistor 47 and the discharging transistor 50 are commonly connected to the node INV_S of the latch circuit SDL.

[0056] Furthermore, the sensing transistor 41, the switching transistor 42, the discharging transistor 43, the clamping transistor 44, the charging transistor 46, the charging transistor 49, and the discharging transistor 50 are, for example, enhancement-mode NMOS (N-Metal Oxide Semiconductor) transistors. The withstand voltage transistor 45 is, for example, a depletion-mode NMOS transistor. The charging transistor 47 is, for example, a PMOS (P-Metal Oxide Semiconductor) transistor.

[0057] In addition, the gate electrode of the switching transistor 42 is connected to the signal line STB. The gate electrode of the discharge transistor 43 is connected to the signal line XXL. The gate electrode of the clamp transistor 44 is connected to the signal line BLC. The gate electrode of the withstand voltage transistor 45 is connected to the signal line BLS. The gate electrode of the charging transistor 46 is connected to the signal line HLL. The gate electrode of the charging transistor 49 is connected to the signal line BLX. The signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequencer SQC ( Figure 2 ).

[0058] Latch circuit SDL includes nodes LAT_S and INV_S, inverter 51, inverter 52, switching transistor 53, and switching transistor 54. Inverter 51 includes an output terminal connected to node LAT_S and an input terminal connected to node INV_S. Inverter 52 includes an input terminal connected to node LAT_S and an output terminal connected to node INV_S. Switching transistor 53 is provided in a current path between node LAT_S and wiring LBUS. Switching transistor 54 is provided in a current path between node INV_S and wiring LBUS. Switching transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of switching transistor 53 is connected to sequencer SQC via signal line STL. The gate electrode of switching transistor 54 is connected to sequencer SQC via signal line STI.

[0059] Each of the plurality of latch circuits SDL corresponding to the plurality of bit lines BL stores one bit of data written by a write operation.

[0060] Latch circuits DL0 to DLn are configured similarly to latch circuit SDL. However, as described above, node INV_S of latch circuit SDL is electrically connected to the gate electrodes of charging transistor 47 and discharging transistor 50 in sense amplifier SA. Latch circuits DL0 to DLn differ from latch circuit SDL in this respect.

[0061] Each of the plurality of latch circuits DL0 to DLn corresponding to the plurality of bit lines BL stores one bit of data written by a write operation.

[0062] The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switching transistor DSW is connected to the sequencer SQC via the signal line DBS.

[0063] The signal lines STB, HLL, XXL, BLX, BLC, and BLS are connected to all the sense amplifier units SAU included in the sense amplifier module SAM. DD The voltage supply line, and the supplied voltage V SSThe voltage supply lines are commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM. In addition, the signal lines STI and STL of the latch circuit SDL are commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM.

[0064] [Configuration of Cache Memory CM]

[0065] Cache memory CM( Figure 2 ) includes multiple latch circuits. The multiple latch circuits within the cache memory CM are connected to the latch circuits within the sense amplifier module SAM via a wiring DBUS. Data DAT contained in the multiple latch circuits within the cache memory CM is sequentially transmitted to the sense amplifier module SAM or the input / output control circuit I / O.

[0066] Furthermore, a decoding circuit and a switch circuit (not shown) are connected to the cache memory CM. The decoding circuit stores the address stored in the address register ADR ( Figure 2 ) column address CA is decoded. The switch circuit switches the latch circuit corresponding to the column address CA to the bus DB ( Figure 2 ) is turned on.

[0067] [Composition of Counter CNT]

[0068] Counter CNT( Figure 2 ) receives data sequentially transmitted from the latch circuit of the cache memory CM. In addition, the number of bits representing "0" or "1" among the bits included in the received data is counted.

[0069] [Circuit Configuration of Voltage Generating Circuit VG]

[0070] Voltage generating circuit VG( Figure 2 ) includes, for example, a step-down circuit and a step-up circuit. The step-down circuit is, for example, a regulator. The step-up circuit is, for example, a charge pump circuit. The step-down circuit and the step-up circuit are connected to the power supply voltage supply line, respectively. The power supply voltage V is supplied to the voltage generating circuit VG. CC and voltage V SS Voltage generator circuit VG generates multiple operating voltages and simultaneously outputs them to multiple voltage supply lines. These operating voltages are supplied to bit lines BL, source lines SL, word lines WL, and select gate lines (SGD, SGS) during read, write, and erase operations in memory cell array MCA. The operating voltages are appropriately adjusted based on control signals from sequencer SQC.

[0071] [Composition of Sequencer SQC]

[0072] Sequencer SQC( Figure 2) According to the command data D stored in the command register CMR CMD , outputs an internal control signal to the row decoder RD, the sense amplifier module SAM and the voltage generating circuit VG. In addition, the sequencer SQC transmits the status data D indicating the status of the memory die MD to the memory die MD. ST Appropriate output to status register STR.

[0073] Sequencer SQC also generates a ready / busy signal and outputs it to terminal RY / ( / BY). While terminal RY / ( / BY) is in the "L" state (busy period), access to memory chip MD is generally prohibited. On the other hand, while terminal RY / ( / BY) is in the "H" state (ready period), access to memory chip MD is permitted.

[0074] [Structure of address register ADR]

[0075] The address register ADR is Figure 2 As shown, it is connected to the input / output control circuit I / O and stores the address data D input from the input / output control circuit I / O. ADD The address register ADR includes, for example, a plurality of 8-bit register columns. When an internal operation such as a read operation, a write operation, or an erase operation is executed, the register column stores address data D corresponding to the internal operation during the execution period. ADD .

[0076] In addition, the address data D ADD For example, the column address CA ( Figure 2 ) and row address RA( Figure 2 ). The row address RA includes, for example, a specific memory block BLK ( Figure 3 ), the block address of a specific string unit SU and word line WL, the plane address of a specific memory cell array MCA (plane), and the chip address of a specific memory die MD.

[0077] [Composition of Command Register CMR]

[0078] The command register CMR is connected to the input / output control circuit I / O and stores the command data D input from the input / output control circuit I / O. CMD The command register CMR includes, for example, at least one 8-bit register column. If the command data D is stored in the command register CMR CMD , then send a control signal to the sequencer SQC.

[0079] [Composition of status register STR]

[0080] The status register STR is connected to the input / output control circuit I / O and stores the status data D output to the input / output control circuit I / O.ST The status register STR includes, for example, a plurality of 8-bit register columns. When an internal operation such as a read operation, a write operation, or an erase operation is executed, the register column stores status data D corresponding to the internal operation during the execution period. ST Furthermore, the register column stores, for example, ready / busy information of the memory cell array MCA.

[0081] [Configuration of Input / Output Control Circuit I / O]

[0082] Input and output control circuit I / O ( Figure 2 ) has data signal input and output terminals DQ0 to DQ7, data strobe signal input and output terminals DQS, / DQS, a shift register and a buffer circuit. Figure 2 ) Supply power voltage V CCQ .

[0083] Data input via data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, address register ADR, or command register CMR in accordance with an internal control signal from the logic circuit CTR. Furthermore, data input via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit in accordance with an internal control signal from the logic circuit CTR.

[0084] Signals input via data strobe signal input / output terminals DQS and / DQS (e.g., a data strobe signal and its complement) are used when inputting data via data signal input / output terminals DQ0 to DQ7. Data input via data signal input / output terminals DQ0 to DQ7 is extracted into a shift register within the input / output control circuit I / O at the timing of the rising edge of the voltage of the data strobe signal input / output terminal DQS (switching input signal) and the falling edge of the voltage of the data strobe signal input / output terminal / DQS (switching input signal), and at the timing of the falling edge of the voltage of the data strobe signal input / output terminal DQS (switching input signal) and the rising edge of the voltage of the data strobe signal input / output terminal / DQS (switching input signal).

[0085] [Configuration of Logic Circuit CTR]

[0086] Logic circuit CTR( Figure 2) includes a plurality of external control terminals / CE, CLE, ALE, / WE, / RE, and RE, and a logic circuit connected to the plurality of external control terminals / CE, CLE, ALE, / WE, / RE, and RE. Logic circuit CTR receives external control signals from controller CD via external control terminals / CE, CLE, ALE, / WE, / RE, and RE, and outputs internal control signals to input / output control circuit I / O based on the external control signals.

[0087] [Partial structure of memory die MD]

[0088] Figure 5 It is a schematic perspective view showing a partial configuration of the memory die MD. Figure 6 Yes Figure 5 In addition, Figure 5 and Figure 6 This is a diagram showing a schematic configuration, and the specific configuration can be appropriately changed. Figure 5 and Figure 6 In the figure, some components are omitted.

[0089] The memory cell array MCA includes a plurality of finger structures FS (memory blocks BLK) arranged in the Y direction. The finger structure FS is, for example, Figure 5 As shown, there are five string units SU arranged in the Y direction. An inter-finger structure ST is provided between two adjacent finger structures FS in the Y direction. In addition, an inter-string unit insulating member SHE such as silicon oxide (SiO2) is provided between two adjacent string units SU in the Y direction.

[0090] In this embodiment, one finger structure FS functions as one memory block BLK. However, multiple finger structures FS may function as one memory block BLK. Furthermore, the finger structure FS may include one to four string units SU, or six or more string units SU.

[0091] The finger structure FS includes a plurality of conductive layers 110 arranged in the Z direction, a wiring layer 112 provided below the plurality of conductive layers 110, and a plurality of semiconductor pillars 120 extending in the Z direction. Figure 6 As shown, gate insulating films 130 are respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120 .

[0092] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the conductive layer 110 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 (such as silicon oxide (SiO2)) is provided between the plurality of conductive layers 110 arranged in the Z direction. Figure 6 ).

[0093] The plurality of conductive layers 110 serve as word lines WL ( Figure 3 ) and the gate electrodes of the multiple memory cells MC connected to the word line WL. In the following description, this conductive layer 110 may be referred to as conductive layer 110 (WL). Each of the multiple conductive layers 110 (WL) is electrically independent for each finger structure FS. Focusing on two finger structures FS adjacent in the Y direction, the multiple conductive layers 110 (WL) arranged in the Z direction in the two finger structures FS and the multiple insulating layers 101 provided above and below them are separated in the Y direction by the inter-finger structure ST.

[0094] One or more conductive layers 110 (WL) located below the plurality of conductive layers 110 ( Figure 5 ) as the source side selection gate line SGS ( Figure 3 ) and the gate electrodes of multiple source-side select transistors STS connected to the source-side select gate line SGS function. In the following description, this conductive layer 110 is sometimes referred to as conductive layer 110 (SGS). Focusing on two finger structures FS adjacent in the Y direction, one or more conductive layers 110 (SGS) in the two finger structures FS and the multiple insulating layers 101 provided above and below them are separated in the Y direction by the inter-finger structure ST.

[0095] One or more conductive layers 110 located above the plurality of conductive layers 110 (WL) serve as drain side selection gate lines SGD ( Figure 3 ) and the gate electrodes of the plurality of drain-side selection transistors STD connected thereto function. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (SGD).

[0096] Multiple conductive layers 110 (SGD) are electrically independent for each string unit SU. In each finger structure FS, when focusing on two string units SU adjacent in the Y direction, one or more conductive layers 110 (SGD) in the two string units S are separated in the Y direction by the inter-string unit insulation element SHE. When focusing on the string unit SU closest to the other among the multiple string units SU included in one of two adjacent finger structures FS in the Y direction, and the string unit SU closest to the other among the multiple string units included in the other finger structure FS, one or more conductive layers 110 (SGD) in the two string units SU are separated in the Y direction by the inter-finger structure ST.

[0097] Wiring layer 112 ( Figure 5 ) For example, it may also include polysilicon containing N-type impurities such as phosphorus (P). In addition, a metal such as tungsten (W), a conductive member such as tungsten silicide, or other conductive members may be provided on the lower surface of the wiring layer 112. The wiring layer 112 serves as the source line SL ( Figure 3 ) part of the function.

[0098] The semiconductor pillar 120 is as follows Figure 5 As shown, a plurality of semiconductor pillars 120 are arranged in the X direction or the Y direction. The semiconductor pillar 120 is, for example, a semiconductor film such as undoped polysilicon (Si). The semiconductor pillar 120 has a substantially cylindrical shape, and an insulating film 125 such as silicon oxide is provided in the center. Figure 6 ). In addition, the outer peripheral surface of the semiconductor pillar 120 is surrounded by the conductive layer 110. The lower end of the semiconductor pillar 120 is connected to the semiconductor layer in the wiring layer 112. The upper end of the semiconductor pillar 120 is electrically connected to the bit line BL via a contact not shown. The semiconductor pillar 120 serves as a memory string MS ( Figure 3 ) contains multiple memory cells MC and the channel regions of the selection transistors STD and STS function.

[0099] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 is, for example, Figure 6 As shown, a tunnel insulating film 131, a charge accumulation film 132, and a blocking insulating film 133 are stacked between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the blocking insulating film 133 are made of, for example, silicon oxide (SiO2). The charge accumulation film 132 is made of, for example, a film capable of accumulating charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge accumulation film 132, and the blocking insulating film 133 have a substantially cylindrical shape, and are arranged along the semiconductor pillar 120 and the wiring layer 112 ( Figure 5 ) of the semiconductor column 120 outside the contact portion, extending in the Z direction.

[0100] in addition, Figure 6 The gate insulating film 130 is shown as an example including a charge storage film 132 made of silicon nitride. However, the charge storage film included in the gate insulating film 130 may be a floating gate made of polysilicon containing N-type or P-type impurities.

[0101] The isolation component SHE between string units is, for example, Figure 5 As shown, it extends in the X direction and the Z direction, and divides the plurality of conductive layers 110 (SGD) in the Y direction. The string unit inter-unit insulating component SHE includes, for example, silicon oxide (SiO2). Figure 5 As shown, the lower end of the inter-string cell insulating member SHE is located above the lower surface of the uppermost conductive layer 110 (WL). In addition, the lower end of the inter-string cell insulating member SHE is located below the lower surface of the lowermost conductive layer 110 (SGD).

[0102] Interdigital structure ST, for example Figure 5 As shown, it includes inter-finger electrodes 141 extending in the X and Z directions, and inter-finger insulating members 142 such as silicon oxide (SiO2) provided on both sides of the inter-finger electrodes 141 in the Y direction. Figure 5 As shown, the lower ends of the inter-finger electrodes 141 and the inter-finger insulating components 142 are connected to the wiring layer 112. The inter-finger electrodes 141 may be, for example, conductive components such as a laminated film including a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the inter-finger electrodes 141 may be, for example, semiconductor components such as polysilicon containing impurities such as phosphorus (P) or boron (B). The inter-finger electrodes 141 may also include both conductive components and semiconductor components. The inter-finger electrodes 141 serve as the source lines SL ( Figure 3 ) part of the function.

[0103] The bit lines BL extend in the Y direction and are arranged in the X direction. The bit lines BL may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0104] [Threshold voltage of memory cell MC]

[0105] As reference Figure 3 As described above, the memory cell MC stores data as the magnitude of the threshold voltage. This point will be described below.

[0106] Figure 7 This is a schematic bar graph for explaining the threshold voltage of a memory cell MC recording 1 bit of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

[0107] Figure 7In the example, the threshold voltage of the memory cell MC is controlled to be in two states. For example, the threshold voltage of the memory cell MC controlled to be in the low state is lower than the erase verification voltage V VFYEr In addition, the threshold voltage of the memory cell MC controlled to be in the high state is greater than the voltage V VFYS , is less than the read path voltage V READ .

[0108] also, Figure 7 In the example, the read voltage V is set between the threshold distribution corresponding to the low state and the threshold distribution corresponding to the high state. CGR .

[0109] For example, the low state corresponds to a low threshold voltage. The memory cell MC in the low state is, for example, an erased memory cell MC. For example, data "1" is assigned to the memory cell MC in the low state.

[0110] The high state corresponds to a high threshold voltage. The memory cell MC in the high state is, for example, a memory cell MC in a write state. For example, data "0" is assigned to the memory cell MC in the high state.

[0111] [Write Action]

[0112] Next, the writing operation will be described.

[0113] Figure 8 This is a timing diagram used to explain the write operation.

[0114] As reference Figure 2 As described, the memory die MD includes eight data signal input / output terminals DQ0 through DQ7. In the following description, the 8-bit data input to these eight data signal input / output terminals DQ0 through DQ7 may be represented using a two-digit hexadecimal representation. For example, if "0,0,0,0,0,0,0,0" is input to the eight data signal input / output terminals DQ0 through DQ7, the data may be represented as 00h, for example. Alternatively, if "1,1,1,1,1,1,1,1" is input, the data may be represented as FFh, for example.

[0115] Figure 8 This shows an example of the command group CS input to the memory die MD during the write operation. W The command group CS W Contains data 80h, A201, A202, A203, A204, A205, D201, D202~D2XX and data 10h.

[0116] At timing t201, the controller CD inputs data 80h as command data D to the memory die MD.CMD Specifically, the voltages of data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" depending on each bit of data 80h. With "H" input to external control terminal CLE and "L" input to external control terminal ALE, the external control terminal / WE is raised from "L" to "H." Data 80h is the command input to start the write operation.

[0117] At timing t202, the controller CD inputs data A201 as address data D to the memory die MD. ADD That is, the voltage of the data signal input / output terminals DQ0 to DQ7 is set to "H" or "L" according to each bit of data A201, and when "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the external control terminal / WE is raised from "L" to "H". Data A201 constitutes the column address CA ( Figure 2 ) is a portion of 8-bit data.

[0118] At timing t203, the controller CD inputs data A202 as address data D to the memory die MD. ADD Data A202 constitutes the column address CA ( Figure 2 ) is a portion of 8-bit data.

[0119] At timing t204, the controller CD inputs data A203 as address data D to the memory die MD. ADD Data A203 constitutes the row address RA ( Figure 2 ) is a portion of 8-bit data.

[0120] At timing t205, the controller CD inputs data A204 as address data D to the memory die MD. ADD Data A204 constitutes the row address RA ( Figure 2 ) is a portion of 8-bit data.

[0121] At timing t206, the controller CD inputs data A205 as address data D to the memory die MD. ADD Data A204 constitutes the row address RA ( Figure 2 ) is a portion of 8-bit data.

[0122] At timing t207, controller CD inputs data D201 as data DAT to memory die MD. Specifically, the voltages of data signal input / output terminals DQ0-DQ7 are set to "H" or "L" depending on each bit of data D201. While external control terminal CLE and external control terminal ALE are both input "L," the input signals to data strobe signal input / output terminals DQS and / DQS are switched (triggered). Data D201 represents the 8-bit data written into data DAT of memory cell MC during a write operation.

[0123] At timing t208, the controller CD inputs data D202 as data DAT to the memory die MD. Data D202 is 8 bits of data written to the data DAT of the memory cell MC by the write operation. Similarly, the controller CD inputs 8 bits of data to the memory die MD as data DAT.

[0124] At timing t209, the controller CD inputs data D2XX as data DAT to the memory chip MD. The data D2XX is 8 bits of data written into the data DAT of the memory cell MC by a write operation.

[0125] At timing t210, the controller CD inputs data 10h as command data D to the memory die MD. CMD Data 10h is a command indicating that the input of the command group related to the write operation has been completed.

[0126] At timing t211, the terminal RY / / BY changes from the "H" state to the "L" state, prohibiting access to the memory chip MD. In addition, a write operation is executed in the memory chip MD.

[0127] At timing t212, the write operation in the memory chip MD is completed. In addition, the terminal RY / / BY changes from the "L" state to the "H" state, allowing access to the memory chip MD.

[0128] At timing t213, the controller CD inputs data 70h, for example, as command data D to the memory die MD. CMD Data 70h is the request output stored in the status register STR ( Figure 2 ) status data D ST command.

[0129] At timing t214, the controller CD outputs data D211 from the memory die MD. The data D211 is the state data D ST ( Figure 2 ).

[0130] [Programming Action]

[0131] The write operation includes multiple operations. In the following description, one of them, namely the programming operation, is described. The programming operation is to select the word line WL S The operation of supplying a programming voltage to increase the threshold voltage of the memory cell MC.

[0132] In the following description, a word line WL to be the target of an operation such as a write operation is referred to as a selected word line WL. S The other word lines WL are called non-selected word lines WL U In the following description, a plurality of memory cells MC included in the string unit SU to be the target of an operation such as a write operation are connected to the selected word line WL. S In the following description, a configuration including a plurality of selected memory cells MC is sometimes referred to as a selected page PG.

[0133] Figure 9 These are schematic cross-sectional views used to illustrate programming operations.

[0134] In the programming operation, for example, the bit lines BL connected to the memory cells MC whose threshold voltages are adjusted among the plurality of selected memory cells MC are W Supply voltage V SS Furthermore, the bit line BL connected to the memory cell MC whose threshold voltage is not adjusted among the plurality of selected memory cells MC is P Supply voltage V DD Voltage V DD Greater than voltage V SS For example, the data written by the write operation is stored in each of the multiple latch circuits DL0 to DLn in the sense amplifier module SAM. Figure 4 The states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, L, H", and the bit line BL W Supply voltage V SS , bit line BL P Supply voltage V DD .

[0135] In addition, during the programming operation, a voltage V is supplied to the drain side selection gate line SGD. SGD .

[0136] Voltage V SGD Greater than voltage V SS In addition, the voltage V SGD With voltage V SSThe voltage difference is greater than the threshold voltage when the drain side selection transistor STD functions as an NMOS transistor. W The drain side selects the channel region of the transistor STD, forming a channel for electrons and transmitting the voltage V SS .

[0137] On the other hand, the voltage V SGD With voltage V DD The voltage difference is smaller than the threshold voltage when the drain side selection transistor STD functions as an NMOS transistor. P The drain side selection transistor STD becomes an OFF state.

[0138] In addition, during the programming operation, a voltage V is supplied to the source line SL. SRC , supply voltage V to the source side selection gate line SGS SS Voltage V SRC Slightly greater than the voltage V SS As a result, the source side selection transistor STS is turned off.

[0139] In addition, during the programming operation, the non-selected word lines WL U Supply write path voltage V PASS .Write path voltage V PASS Greater than reference Figure 7 The read path voltage V READ In addition, the write path voltage V PASS With voltage V SS Regardless of the data recorded in the memory cell MC, the voltage difference is greater than the threshold voltage when the memory cell MC functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, and the voltage V is transmitted to the write memory cell MC. SS .

[0140] In addition, during the programming operation, the selected word line WL S Supply programming voltage V PGM . Programming voltage V PGM Greater than the write path voltage V PASS .

[0141] Here, the bit line BL is connected to W The channel supply voltage V of the semiconductor column 120 SS In this case, the semiconductor pillar 120 is connected to the selected word line WL. S Thus, electrons in the channel of the semiconductor pillar 120 pass through the tunnel insulating film 131 ( Figure 6 ), tunneling to the charge accumulation film 132 ( Figure 6). As a result, the threshold voltage of the write memory cell MC increases.

[0142] On the other hand, the bit line BL is connected P The channel of the semiconductor pillar 120 becomes electrically floating, and the potential of the channel is connected to the non-selected word line WL U The capacitive coupling rises to the write path voltage V PASS In this case, the semiconductor column 120 is connected to the selected word line WL S Therefore, the electrons in the channel of the semiconductor pillar 120 do not tunnel to the charge accumulation film 132 ( Figure 6 Therefore, the threshold voltage of the memory cell MC is inhibited from increasing.

[0143] In addition, during the programming operation, for example, the bit lines BL connected to some of the memory cells MC whose threshold voltages are adjusted among the plurality of selected memory cells MC may be controlled. W , the supply voltage is greater than V SS and is less than the voltage V DD voltage.

[0144] [Write operation execution order]

[0145] Next, the execution procedure of the write operation will be described. Figure 10 It is a schematic cross-sectional view for explaining the execution sequence of the write operation.

[0146] Figure 10 Two memory blocks BLK are shown as an example. Figure 10 In the example, the memory block BLK has 5 word lines WL and 5 string units SUa to SUe. Figure 10 In the example of , the memory block BLK includes 25 pages PG. For example, when the memory cell MC stores 1-bit data, data corresponding to 25 pages PG are stored in the memory block BLK.

[0147] also, Figure 10 The execution order of the write operation is illustrated below. Figure 10 In this example, first, a write operation is performed sequentially on the five pages PG corresponding to the first word line WL from the bottom. In each write operation, the data corresponding to one page PG is stored in the erased page PG. In other words, the memory cell MC corresponding to the low state is controlled to two states through a single write operation. Next, a write operation is performed sequentially on the five pages PG corresponding to the second word line WL from the bottom. Similarly, a write operation is performed sequentially on the 15 pages PG corresponding to the third to fifth word lines WL from the bottom.

[0148] [Writing Operation in the First Mode]

[0149] As described above, the write operation includes multiple operations including the programming operation. For example, there is a precharge operation to charge the bit line BL before the programming operation, and an equalization operation to discharge the word line WL after the programming operation.

[0150] Here, for example, in the case where programming operations are performed continuously on multiple page PGs, a precharge operation, programming operation, and equalization operation are performed corresponding to the first page PG, and then a precharge operation, programming operation, and equalization operation are performed corresponding to the second page PG.

[0151] Alternatively, it is possible to perform a precharge operation and a program operation for the first page PG, then skip the discharge operation and precharge operation by one time each, and perform the program operation and the equalization operation. This method can provide a semiconductor memory device that can shorten the time required for the write operation and operate at high speed.

[0152] This method will be described below as a first-mode write operation. In the first-mode write operation, a first precharge operation and a first programming operation are sequentially performed, followed by a second programming operation. Furthermore, in the first-mode write operation, binary values ​​(1 bit) are stored in multiple memory cells MC.

[0153] Figure 11 This is a timing chart for explaining the write operation in the first mode. Figure 11 In the embodiment, the drain side selection gate lines SGD of two different string units SU in one memory block BLK are referred to as selection gate lines SGDstr0 and SGDstr1. The selection gate line SGDstr0 is the drain side selection gate line SGD corresponding to the page PG to be written in the first programming operation. The selection gate line SGDstr1 is the drain side selection gate line SGD corresponding to the page PG to be written in the second programming operation. In addition, there are multiple non-selected word lines WL U In the middle, the selected word line WL S The non-selected word line WL on the drain side select gate line SGD U Drain-side non-selected word line WL U_D , will be located at the select word line WL S Non-selected word line WL on the source side select gate line SGS side U Source-side non-selected word line WL U_S situation.

[0154] From timing t221 to timing t231, a first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage.

[0155] At the timing t221 of the first precharge operation, for example, the bit line BL is set to be in the first programming operation. W Bit line BL n Supply voltage V SS (Second voltage), the bit line BL becomes P Bit line BL n+1 Supply voltage V DD (fourth voltage), the source line SL is supplied with a voltage V SL In addition, at the timing t221 of the first precharge operation, the gate lines SGDstr0 and SGDstr1 and the word line WL are selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V PRE (3rd voltage), the voltage V SS Rising to voltage V PRE Voltage V DD , voltage V SL and voltage V PRE is greater than the voltage V SS Voltage V PRE is greater than the voltage V DD and voltage V SL Voltage V DD and voltage V SL The voltages may be of different magnitudes, but they may also be of the same magnitude.

[0156] At the timing t222 of the first precharge operation, the gate lines SGDstr0 and SGDstr1 and the word line WL are selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V SS , the voltage V PRE Rising to voltage V SS .

[0157] At timing t223 of the first precharge operation, a voltage V is supplied to the source line SL. SS , the voltage V SL Reduced to voltage V SS In addition, the source side selection gate line SGS is supplied with a voltage V SGS , the voltage V SS Rising to voltage V SGS Voltage V SGSThe source side selection transistor STS is not turned on. In addition, the voltage V is kept supplied to the source side selection gate line SGS at the timing t223 of the first precharge operation. SS The status remains unchanged.

[0158] At timing t224 of the first precharge operation, a voltage V is supplied to the source line SL. SRC , the voltage V SS Rising to voltage V SRC In addition, the voltage V may be maintained on the source line SL at the timing t224 of the first precharge operation. SS The status remains unchanged.

[0159] At timing t225 of the first precharge operation, a voltage V is supplied to the select gate line SGDstr0 to be written in the first program operation. SGD .

[0160] From timing t231 to timing t236, the first program operation is performed.

[0161] At the timing t231 of the first programming operation, for example, the bit line BL is set to be P Bit line BL n+1 Supply voltage V DD (first voltage), the bit line BL becomes W Bit line BL n Supply voltage V SS , supply voltage V to the selection gate line SGDstr0 SGD , supply voltage V to the selection gate line SGDstr1 SS In addition, at the timing t231 of the first programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th In addition, the voltage V DD For example, it is a voltage on the high voltage side of the power supply voltage. th For example, it is a voltage approximately equal to the threshold voltage of a transistor having the highest threshold voltage among a plurality of transistors electrically connected between a pad electrode supplied with a voltage on the high voltage side of the power supply voltage and the word line WL.

[0162] At timing t232 of the first programming operation, the selected word line WL S , drain side non-select word line WLU_D , source side non-select word line WL U_S , supply write path voltage V PASS At the timing t233 of the first programming operation, the word line WL is selected. S Supply the first programming voltage V PGM .

[0163] At the timing t234 of the first programming operation, the selected word line WL S Supply write path voltage V PASS , the first programming voltage V PGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , source side non-select word line WL U_S Supply voltage V DD -V th , the write path voltage V PASS Reduced to voltage V DD- V th .

[0164] At timing t235 of the first programming operation, the bit line BL n+1 , select gate line SGDstr0, select word line WL S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V SS , the bit line BL n+1 The voltage V DD , the voltage V of the selection gate line SGDstr0 SGD , select word line WL S Write path voltage V PASS , drain side non-select word line WL U_D , source side non-select word line WL U_S The voltage V DD -V th Reduced to voltage V SS .

[0165] From timing t251 to timing t271 , a recovery action is performed.

[0166] At the timing t251 of the restore operation, for example, the bit line BL is set to be in the second programming operation. P Bit line BL n Supply voltage V DD , in the first programming operation, the bit line BL W Bit line BL n+1 Supply voltage V SS .

[0167] From timing t271 to timing t276, the second programming operation is performed.

[0168] At the timing t271 of the second programming operation, for example, the bit line BL is set to be P Bit line BL n Supply voltage V DD , in the first programming operation, the bit line BL W Bit line BL n+1 Supply voltage V SS , supply voltage V to the selection gate line SGDstr1 SGD , supply voltage V to the selection gate line SGDstr0 SS In addition, at the timing t271 of the second programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th .

[0169] At timings t272 to t276 of the second program operation, the same operations as those at timings t231 to t236 of the first program operation are performed.

[0170] From timing t276 to timing t283 after the second programming operation, an equalization operation (discharge) is performed.

[0171] At the timing t281 of the equalization operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, select word line WL S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supplying an open-circuit voltage, setting the selection transistors (STD, STS) and multiple memory cells MC in the string unit SU to the on state.

[0172] At the timing t282 of the equalization operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, select word line WL S , drain side non-select word line WL U_D , source side non-select word line WL U_S , source side selection gate line SGS, source line SL, supply voltage V SS, the selection transistors (STD, STS) of the string units SU0 and SU1 and the plurality of memory cells MC are set to an OFF state.

[0173] [Writing Operation in the Second Mode]

[0174] Next, refer to Figure 12 The second mode of writing operation is described below, in which a first precharge operation and a first programming operation are sequentially performed, followed by a second precharge operation and a second programming operation. In the second mode of writing operation, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0175] Figure 12 This is a timing diagram for explaining the write operation in the second mode. Figure 12 The selection gate lines SGDstr0 and SGDstr1, the selection gate lines SGDstr0 and SGDstr1, and the drain side non-selection word line WL U_D , source side non-select word line WL U_S ,like Figure 11 As described.

[0176] From the timing t221 to the timing t231, the first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage. Figure 11 This is shown in the first precharge operation described in the first mode of programming operation.

[0177] From the timing t231 to the timing t236, the first programming operation is performed. Figure 11 The first programming operation is described in the first mode of writing operation.

[0178] From timing t236 to timing t243 after the first programming operation, an equalization operation (discharge) is performed.

[0179] At the timing t241 of the equalization operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, select word line WL S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supplying an open-circuit voltage, setting the selection transistors (STD, STS) of the string units SU0 and SU1 and the plurality of memory cells MC to an on state.

[0180] At the timing t242 of the equalization operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, select word line WLS , drain side non-select word line WL U_D , source side non-select word line WL U_S , source side selection gate line SGS, source line SL, supply voltage V SS , the selection transistors (STD, STS) of the string units SU0 and SU1 and the plurality of memory cells MC are set to an OFF state.

[0181] From timing t261 to timing t271, a second precharge operation is performed to precharge the target wiring by supplying a predetermined voltage.

[0182] At the timing t261 of the second precharge operation, for example, the bit line BL is set to be in the second programming operation. W Bit line BL n+1 Supply voltage V SS , in the second programming operation, the bit line BL P Bit line BL n Supply voltage V DD , supply voltage V to the source line SL SL In addition, the gate lines SGDstr0 and SGDstr1 and the word line WL are selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V PRE , the voltage V SS Rising to voltage V PRE .

[0183] At the timing t262 of the second precharge operation, the gate lines SGDstr0 and SGDstr1 and the word line WL are selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_D , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V SS , the voltage V PRE Reduced to voltage V SS .

[0184] At the timing t263 of the second precharge operation, the voltage V is supplied to the source line SL. SS , the voltage V SL Reduced to voltage V SS In addition, the source side selection gate line SGS is supplied with a voltage V SGS , the voltage V SS Rising to voltage V SGSIn addition, the voltage V may be supplied to the source side selection gate line SGS at the timing t263 of the precharge operation. SS The status remains unchanged.

[0185] At timing t264 of the second precharge operation, the voltage V is supplied to the source line SL. SRC , the voltage V SS Rising to voltage V SRC In addition, the voltage V supplied to the source line SL may be maintained at the timing t264 of the precharge operation. SS The status remains unchanged.

[0186] At timing t265 of the second precharge operation, a voltage V is supplied to the select gate line SGDstr1 to be written in the second program operation. SGD .

[0187] At timing t271 to timing t276, the second programming operation is performed. Figure 11 The second programming operation is described in the first mode programming operation.

[0188] After the second programming operation, at the timing t276 to the timing t283, the equalization operation (discharge) is performed. Figure 11 The equalization operation (discharge) described above is based on the writing operation in the first mode.

[0189] [Effect]

[0190] In a binary operation (SLC) in which multiple memory cells MC store two values ​​(one bit), although the data integration is low, high-speed write and read operations can be performed, and the reliability is high. The write operation of the second mode is to sequentially perform the first precharge operation and the first programming operation, and then sequentially perform the second precharge operation and the second programming operation, and perform writing according to each page PG. In contrast, the write operation of the first mode is to sequentially perform the first precharge operation and the first programming operation, and then continuously perform the second programming operation, and continuously write to two pages PG. In this way, the following semiconductor memory device can be provided: in the write operation of the first mode, the time of the equalization operation and the second precharge operation performed between the first programming operation and the second programming operation in the write operation of the second mode can be unified with the time of the first precharge operation before the first programming operation and the recovery operation after the first programming operation, thereby shortening the time for the write operation and achieving high-speed operation.

[0191] [Variation 1 of the First Embodiment] In the first embodiment, in the first precharge operation performed in the first mode write operation and the second mode write operation, the bit line BL is formed in the first programming operation. P Bit line BLn Precharge of the bit line (bit line precharge operation) and precharge of the channels of multiple memory cells MC (channel precharge operation) are performed. Furthermore, the channel precharge operation is performed from both the drain-side selection gate line SGD side and the source-side selection gate line SGS side. In contrast, in this variation, the first precharge operation is performed from the drain-side selection gate line SGD side.

[0192] [Writing Operation in the First Mode]

[0193] Next, refer to Figure 13 The programming operation in the first mode of this variation will be described. In the programming operation in the first mode of this variation, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0194] Figure 13 This is a timing chart for explaining the write operation in the first mode of Modification 1.

[0195] From timing t221 to timing t231, a first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage.

[0196] At the timing t221 of the first precharge operation, for example, the bit line BL is set to be in the first programming operation. W Bit line BL n Supply voltage V SS , in the first programming operation, the bit line BL P Bit line BL n+1 Supply voltage V DD , supply voltage V to the source line SL SL In addition, the gate lines SGDstr0 and SGDstr1 and the word line WL are selected. S , drain side non-select word line WL U_D , supply voltage V PRE , raise the voltage to V PRE In addition, the source side non-select word line WL U_S , source side select gate line SGS supply voltage V SS In this way, the channel precharge operation is performed by selecting the gate line SGD side from the drain side.

[0197] At the timing t222 of the first precharge operation, the gate lines SGDstr0 and SGDstr1 and the word line WL are selected. S , drain side non-select word line WL U_D , supply voltage V SS , the voltage V PRE Reduced to voltage V SS .

[0198] At the timing t223 to the timing t225 of the first pre-charge operation, as shown in FIG. Figure 11 This is described in conjunction with the first precharge operation described in the first mode of programming operation.

[0199] From the timing t231 to the timing t236, the first programming operation is performed. Figure 11 The first programming operation is described in the first mode of writing operation.

[0200] After the first programming operation and before the second programming operation, the recovery operation is performed from time t236 to time t271. Figure 11 The recovery operation is described in the same manner as the write operation in the first mode.

[0201] At timing t271 to timing t276, the second programming operation is performed. Figure 11 The second programming operation is described in the first mode programming operation.

[0202] After the second programming operation, at the timing t276 to the timing t283, the equalization operation (discharge) is performed. Figure 11 The equalization operation (discharge) described above is based on the writing operation in the first mode.

[0203] [Writing Operation in the Second Mode]

[0204] Next, refer to Figure 14 The second mode programming operation of this variation will be described. In the second mode programming operation of this variation, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0205] Figure 14 This is a timing chart for explaining the write operation in the second mode of Modification 1.

[0206] From the timing t221 to the timing t231, the first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage. Figure 13 This is described in detail with respect to the first precharge operation described in the first mode of programming in this variation.

[0207] From the timing t231 to the timing t236, the first programming operation is performed. Figure 11 The first programming operation is described in the first mode of writing operation.

[0208] After the first programming operation, at the timing t236 to the timing t243, an equalization operation (discharge) is performed. Figure 12 This is described with reference to the equalization operation (discharge) described with reference to the writing operation in the second mode.

[0209] From the timing t261 to the timing t271, the second precharge operation is performed to precharge the target wiring by supplying a predetermined voltage. Figure 12 This is described in the second precharge operation described in the second mode of programming operation.

[0210] At timing t271 to timing t276, the second programming operation is performed. Figure 11 The second programming operation is described in the first mode programming operation.

[0211] After the second programming operation, at the timing t276 to the timing t283, the equalization operation (discharge) is performed. Figure 11 The equalization operation (discharge) described above is based on the writing operation in the first mode.

[0212] [Variation 2 of the First Embodiment] In the first embodiment, in the first precharge operation performed in the first mode write operation and the second mode write operation, the channel precharge operation is performed from both the drain-side select gate line SGD and the source-side select gate line SGS. In contrast, in this variation, in the first precharge operation, the channel precharge operation is performed from the source-side select gate line SGS.

[0213] [Writing Operation in the First Mode]

[0214] Next, refer to Figure 15 The programming operation in the first mode of this variation will be described. In the programming operation in the first mode of this variation, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0215] Figure 15 This is a timing chart for explaining the write operation in the first mode of the second modification.

[0216] From timing t221 to timing t231, a first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage.

[0217] At the timing t221 of the first precharge operation, for example, the bit line BL is set to be in the first programming operation. W Bit line BL n Supply voltage V SS , in the first programming operation, the bit line BL P Bit line BL n+1 Supply voltage V DD , supply voltage V to the source line SL SL In addition, the word line WL is selected S , source side non-select word line WL U_S, source side select gate line SGS supply voltage V PRE , the voltage V SS Rising to voltage V PRE In addition, the gate lines SGDstr0 and SGDstr1 and the drain side non-selected word line WL U_D Supply voltage V SS In this way, the channel precharge operation is performed from the source side to the gate line SGS side.

[0218] At the timing t222 of the first precharge operation, the selected word line WL S , source side non-select word line WL U_S , source side select gate line SGS supply voltage V SS , the voltage V PRE Reduced to voltage V SS .

[0219] At the timing t223 to the timing t225 of the first pre-charge operation, as shown in FIG. Figure 11 This is described in conjunction with the first precharge operation described in the first mode of programming operation.

[0220] From the timing t231 to the timing t236, the first programming operation is performed. Figure 11 The first programming operation is described in the first mode of writing operation.

[0221] After the first programming operation and before the second programming operation, the recovery operation is performed from time t236 to time t271. Figure 11 The recovery operation is described in the same manner as the write operation in the first mode.

[0222] At timing t271 to timing t276, the second programming operation is performed. Figure 11 The second programming operation is described in the first mode programming operation.

[0223] After the second programming operation, at the timing t276 to the timing t283, the equalization operation (discharge) is performed. Figure 11 The equalization operation (discharge) described above is based on the writing operation in the first mode.

[0224] [Writing Operation in the Second Mode]

[0225] Next, refer to Figure 16 The second mode programming operation of this variation will be described. In the second mode programming operation of this variation, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0226] Figure 16This is a timing chart for explaining the write operation in the second mode of the second modification.

[0227] From the timing t221 to the timing t231, the first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage. Figure 15 This is described in detail with respect to the first precharge operation described in the first mode of programming in this variation.

[0228] From the timing t231 to the timing t236, the first programming operation is performed. Figure 11 The first programming operation is described in the first mode of writing operation.

[0229] After the first programming operation, at the timing t236 to the timing t243, an equalization operation (discharge) is performed. Figure 12 This is described with reference to the equalization operation (discharge) described with reference to the writing operation in the second mode.

[0230] From the timing t261 to the timing t271, the second precharge operation is performed to precharge the target wiring by supplying a predetermined voltage. Figure 12 This is described in the second precharge operation described in the second mode of programming operation.

[0231] At timing t271 to timing t276, the second programming operation is performed. Figure 11 The second programming operation is described in the first mode programming operation.

[0232] After the second programming operation, at the timing t276 to the timing t283, the equalization operation (discharge) is performed. Figure 11 The equalization operation (discharge) described above is based on the writing operation in the first mode.

[0233] [Variation 3 of the First Embodiment]

[0234] The write operation of the first embodiment may include a verify operation in addition to a precharge operation, a programming operation, and an equalization operation. The verify operation is performed after the programming operation and is used to confirm whether data has been properly written to each memory cell MC within the page PG. In this variation, the verification operation is performed during the write operation of the first mode and the write operation of the second mode, using the example of performing a channel precharge operation from the source gate line SGS side during the first precharge operation.

[0235] [Writing Operation in the First Mode]

[0236] Next, refer to Figure 17The programming operation in the first mode of this variation will be described. In the programming operation in the first mode of this variation, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0237] Figure 17 This is a timing chart for explaining the write operation in the first mode of Modification 3.

[0238] From the timing t221 to the timing t231, the first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage. Figure 15 This is described in conjunction with the first precharge operation described in the first mode of programming operation.

[0239] From the timing t231 to the timing t236, the first programming operation is performed. Figure 11 The first programming operation is described in the first mode of writing operation.

[0240] After the first programming operation and before the second programming operation, the recovery operation is performed from time t236 to time t271. Figure 11 The recovery operation is described in the same manner as the write operation in the first mode.

[0241] At timing t271 to timing t276, the second programming operation is performed. Figure 11 The second programming operation is described in the first mode programming operation.

[0242] After the second programming operation, at the timing t276 to the timing t283, the equalization operation (discharge) is performed. Figure 11 The equalization operation (discharge) described above is based on the writing operation in the first mode.

[0243] From timing t283 to timing t2910, the first verification operation is performed.

[0244] At the timing t291 of the first verification operation, a voltage V is supplied to the selection gate line SGDstr0, the selection gate line SGDstr1, and the source side selection gate line SGS. SG Voltage V SG The size is large enough to turn on the select transistors (STD, STS). U_D , source side non-select word line WL U_S , supply read path voltage V READ ( Figure 7 ). In addition, the word line WL is selected. S Supply voltage V VFYS ( Figure 7 )(4th voltage). In addition, the bit line BLn , bit line BL n+1 Supply voltage V DD The source line SL is supplied with a voltage V SRC .

[0245] At timing t292 of the first verification operation, a voltage V is supplied to the selection gate line SGDstr1. SS , select the voltage V of the gate line SGDstr1 VFYS Reduced to voltage V SS .

[0246] During the first verification operation, at timing t292 to t293, a sensing operation is performed. Figure 4 The sense node SEN described above is electrically connected to the bit line BL. The charge on the sense node SEN of the memory cell MC connected to the on state is discharged, turning the sense transistor 41 connected thereto off. On the other hand, the charge on the sense node SEN of the memory cell MC connected to the off state is maintained, turning the sense transistor 41 connected thereto on. In this state, if the signal line STB is turned on, data indicating whether the memory cell MC is on or off is transmitted to the wiring LBUS. This data can be latched by any of the latch circuits SDL, DL0, and DLn.

[0247] At the timing t293 of the first verification operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, drain side non-select word line WL U_D , select word line WL S , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V SS , the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, drain side non-select word line WL U_D , select word line WL S , source side non-select word line WL U_S , the voltage of the source side selection gate line SGS drops to voltage V SS .

[0248] At timing t294 of the first verification operation, a voltage V is supplied to the source line SL. SS , the voltage V of the source line SL SL Reduced to voltage V SS .

[0249] From timing t2910 to timing t2915, the second verification operation is performed.

[0250] At the timing t2911 of the second verification operation, a voltage V is supplied to the selection gate line SGDstr0, the selection gate line SGDstr1, and the source side selection gate line SGS. SG In addition, the drain side non-select word line WL U_D , source side non-select word line WL U_S , supply read path voltage V READ ( Figure 7 ). In addition, the word line WL is selected. S Supply voltage V VFYS (4th voltage). In addition, the bit line BL n , bit line BL n+1 Supply voltage V DD The source line SL is supplied with a voltage V SRC .

[0251] At timing t2912 of the second verification operation, a voltage V is supplied to the selection gate line SGDstr0. SS , select the voltage V of the gate line SGDstr0 VFY Reduced to voltage V SS .

[0252] At timings t292 to t293 of the first verification operation, a sensing operation is performed.

[0253] At the timing t2913 of the second verification operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, drain side non-select word line WL U_D , select word line WL S , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V SS , the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, drain side non-select word line WL U_D , select word line WL S , source side non-select word line WL U_S , the voltage of the source side selection gate line SGS drops to voltage V SS .

[0254] At timing t2914 of the second verification operation, a voltage V is supplied to the source line SL. SS , the voltage V of the source line SL SL Reduced to voltage V SS.

[0255] [Writing Operation in the Second Mode]

[0256] Next, refer to Figure 18 The second mode programming operation of this variation will be described. In the second mode programming operation of this variation, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0257] Figure 18 This is a timing chart for explaining the write operation in the second mode of Modification 3.

[0258] From the timing t221 to the timing t231, the first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage. Figure 15 This is described in detail with respect to the first precharge operation described in the first mode of programming in this variation.

[0259] From the timing t231 to the timing t236, the first programming operation is performed. Figure 11 The first programming operation is described in the first mode of writing operation.

[0260] After the first programming operation, at the timing t236 to the timing t243, an equalization operation (discharge) is performed. Figure 12 This is described with reference to the equalization operation (discharge) described with reference to the writing operation in the second mode.

[0261] From timing t243 to timing t261, the first verification operation is performed. Figure 17 This is described in the first verification action description.

[0262] From the timing t261 to the timing t271, the second precharge operation is performed to precharge the target wiring by supplying a predetermined voltage. Figure 12 This is described in the second precharge operation described in the second mode of programming operation.

[0263] At timing t271 to timing t276, the second programming operation is performed. Figure 11 The second programming operation is described in the first mode programming operation.

[0264] After the second programming operation, at the timing t276 to the timing t283, the equalization operation (discharge) is performed. Figure 11 The equalization operation (discharge) described above is based on the writing operation in the first mode.

[0265] From timing t283 to timing t2915, the second verification operation is performed. Figure 17This is described in the second verification action description.

[0266] [Second embodiment]

[0267] In the first embodiment, the case where two pages PG are continuously written in the first mode of writing operation is described, but three or more pages PG can also be continuously written. In this embodiment, the case where four or more pages PG are continuously written in the first mode of writing operation is described.

[0268] In addition, when executing a write operation, for example, data corresponding to three or more pages PG may be stored in three or more latch circuits D0 to DLn ( Figure 4 ). In addition, during the write operation, the data in the latch circuits D0 to DLn may be updated, and the program operation may be performed using the updated data.

[0269] [Writing Operation in the First Mode]

[0270] Next, refer to Figure 19 The programming operation in the first mode of this embodiment will be described. In the programming operation in the first mode of this embodiment, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0271] Figure 19 This is a timing chart for explaining the write operation in the first mode of the second embodiment. Figure 19 In the embodiment, the drain-side selection gate lines SGD of the four different string units SU within one memory block BLK are referred to as selection gate lines SGDSTRn, SGDSTRn+1, SGDSTRn+2, and SGDSTRn+3. The selection gate line SGDSTRn is the selection gate line SGD to be written to during the str0 programming operation. The selection gate line SGDSTRn+1 is the selection gate line SGD to be written to during the str1 programming operation. The selection gate line SGDSTRn+2 is the selection gate line SGD to be written to during the str2 programming operation. The selection gate line SGDSTRn+3 is the selection gate line SGD to be written to during the str3 programming operation.

[0272] From timing t321 to timing t331, a first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage.

[0273] At the timing t321 of the first precharge operation, for example, the bit line BL is set to 0 during the programming operation. W Bit line BL n , bit line BL n+2 , bit line BL n+3 , supply voltage V SS(Second voltage), bit line BL in the str0 programming operation P Bit line BL n+1 Supply voltage V DD (fourth voltage), the source line SL is supplied with a voltage V SL In addition, the select gate lines SGD STRn, SGD STRn+1, SGD STRn+2, SGD STRn+3, and the drain side non-select word line WL U_D , select word line WL S , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V PRE , raise the voltage to V PRE In this manner, the channel precharge operation is performed from both the drain side selection gate line SGD side and the source side selection gate line SGS side.

[0274] At the timing t322 of the first precharge operation, the selected gate lines SGD STRn, SGD STRn+1, SGD STRn+2, SGD STRn+3, and the drain-side non-selected word line WL U_D , select word line WL S , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V SS , the voltage V PRE Reduced to voltage V SS .

[0275] At timing t323 of the first precharge operation, a voltage V is supplied to the source line SL. SS , the voltage V SL Reduced to voltage V SS In addition, the source side selection gate line SGS is supplied with a voltage V SGS , the voltage V SS Rising to voltage V SGS In addition, the voltage V may be maintained on the source side selection gate line SGS at the timing t323 of the first precharge operation. SS The status remains unchanged.

[0276] At timing t324 of the first precharge operation, a voltage V is supplied to the source line SL. SGS , the voltage V SS Rising to voltage V SGS In addition, the voltage V may be maintained on the source line SL at the timing t324 of the first precharge operation. SS The status remains unchanged.

[0277] At timing t325 of the first precharge operation, a voltage V is supplied to the select gate line SGDSTRn to be written in the first program operation. SGD .

[0278] From timing t331 to timing t337, the str0 programming action is performed.

[0279] At the timing t331 of the str0 programming operation, for example, the bit line BL becomes P Bit line BL n+1 Supply voltage V DD , becomes the bit line BL in the str0 programming action W Bit line BL n , bit line BL n+2 , bit line BL n+3 , supply voltage V SS , supply voltage V to select gate line SGD STRn SGD , supply voltage V to select gate lines SGD STRn+1, SGD STRn+2, and SGD STRn+3 SS In addition, at the timing t331 of the str0 programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th .

[0280] At timing t332 of the str0 programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supplying the write path circuit V PASS At the timing t333 of the str0 programming operation, the word line WL is selected. S Supply str0 programming voltage V PGM .

[0281] At timing t334 of the str0 programming operation, the word line WL is selected. S Supply write path voltage V PASS , set str0 programming voltage V PGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , source side non-select word line WL U_S Supply voltage V DD -Vth , the write path voltage V PASS Reduced to voltage V DD -V th .

[0282] At the timing t335 of the str0 programming operation, the gate line SGD STRn and the word line WL are selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V SS , select the voltage V of the gate line SGD STRn SGD , select word line WL S Write path circuit V PASS , drain side non-select word line WL U_D , source side non-select word line WL U_S The voltage V DD -V th Reduced to voltage V SS .

[0283] At timing t336 of the str0 programming operation, the bit line BL n+1 Supply voltage V SS , the bit line BL n+1 The voltage V DD Reduced to voltage V SS .

[0284] A recovery action is performed from timing t337 to timing t351 after the str0 programming action and before the str1 programming action.

[0285] At the timing t341 of the restore operation, the bit line BL is set to 0 in the programming operation of str1. P Bit line BL n , bit line BL n+2 Supply voltage V DD , as the recovery voltage.

[0286] At the timing t342 of the restore operation, the voltage V is supplied to the select gate line SGD STRn+1 which is the target of the programming operation str1. SGD .

[0287] From timing t351 to timing t361, the str1 programming action is executed.

[0288] At the timing t351 of the str1 programming operation, for example, the bit line BL becomes P Bit line BL n , bit line BL n+2 Supply voltage V DD, becomes the bit line BL in the str1 programming action W Bit line BL n+1 , bit line BL n+3 Supply voltage V SS , supply voltage V to select gate line SGD STRn+1 SGD , supply voltage V to select gate lines SGD STRn+0, SGD STRn+2, and SGD STRn+3 SS In addition, at the timing t351 of the str1 programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th .

[0289] At timing t352 of the str1 programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supplying the write path circuit V PASS At the timing t353 of the str1 programming operation, the word line WL is selected. S Supply str1 programming voltage V PGM In addition, str0 programming voltage V PGM With str1 programming voltage V PGM They are different voltages, but can also be the same voltage.

[0290] At timing t354 of the str1 programming operation, the word line WL is selected. S Supply write path voltage V PASS , set str1 programming voltage V PGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , source side non-select word line WL U_ S Supply voltage V DD -V th , the write path voltage V PASS Reduced to voltage V DD -V th .

[0291] At the timing t355 of the str1 programming operation, the gate line SGD STRn+1 and the word line WL are selected. S , drain side non-select word line WL U_D , source side non-select word line WLU_S , supply voltage V SS , select the voltage V of the gate line SGD STRn+1 SGD , select word line WL S Write path voltage V PASS , drain side non-select word line WL U_D , source side non-select word line WL U_S The voltage V DD -V th Reduced to voltage V SS .

[0292] At timing t356 of the str1 programming operation, the bit line BL n , bit line BL n+2 Supply voltage V SS , the bit line BL n , bit line BL n+2 The voltage V DD Reduced to voltage V SS .

[0293] A recovery action is performed from timing t361 to timing t371 after the str1 programming action and before the str2 programming action.

[0294] At the timing t361 of the restore operation, the bit line BL is set to 0 in the programming operation of str2. P Bit line BL n+2 Supply voltage V DD , as the recovery voltage.

[0295] At the timing t362 of the recovery operation, the voltage V is supplied to the select gate line SGD STRn+2 which is the target of the programming operation in the str2 program operation. SGD .

[0296] From timing t371 to timing t381, the str2 programming action is executed.

[0297] At the timing t371 of the str2 programming operation, for example, the bit line BL becomes P Bit line BL n+2 Supply voltage V DD (1st voltage), becomes bit line BL in the programming operation of str2 W Bit line BL n , bit line BL n+1 , bit line BL n+3 Supply voltage V SS , supply voltage V to select gate line SGD STRn+2 SGD , supply voltage V to select gate lines SGD STRn+0, SGD STRn+1, and SGD STRn+3SS In addition, at the timing t371 of the str2 programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th .

[0298] At timing t372 of the str2 programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supplying the write path circuit V PASS At the timing t373 of the str2 programming action, the word line WL is selected. S Supply str2 programming voltage V PGM In addition, str1 programming voltage V PGM With str2 programming voltage V PGM They are different voltages, but can also be the same voltage.

[0299] At the timing t374 of the str2 programming operation, the word line WL is selected. S Supply write path voltage V PASS , set str2 programming voltage V PGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , source side non-select word line WL U_S Supply voltage V DD -V th , the write path voltage V PASS Reduced to voltage V DD -V th .

[0300] At the timing t375 of the str2 programming operation, the gate line SGD STRn+2 and the word line WL are selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V SS , select the voltage V of the gate line SGD STRn+2 SGD , select word line WL S Write path voltage V PASS , drain side non-select word line WL U_D , source side non-select word line WL U_S The voltage VDD -V th Reduced to voltage V SS .

[0301] At the timing t376 of the str2 programming operation, the bit line BL n+2 Supply voltage V SS , the bit line BL n+2 The voltage V DD Reduced to voltage V SS .

[0302] A recovery action is performed from timing t381 to timing t391 after the str2 programming action and before the str3 programming action.

[0303] At the timing t381 of the restore operation, the bit line BL is set to 0 in the programming operation of str3. P Bit line BL n+3 Supply voltage V DD , as the recovery voltage.

[0304] At the timing t382 of the recovery operation, the voltage V is supplied to the select gate line SGD STRn+3 which is the target of the programming operation in the str3 program operation. SGD .

[0305] From timing t391 to timing t401, the str3 programming action is executed.

[0306] At the timing t391 of the str3 programming operation, for example, the bit line BL becomes P Bit line BL n+3 Supply voltage V DD (1st voltage), becomes bit line BL in the programming operation of str3 W Bit line BL n , bit line BL n+1 , bit line BL n+2 Supply voltage V SS , supply voltage V to select gate line SGD STRn+3 SGD , supply voltage V to select gate lines SGD STRn+0, SGD STRn+1, and SGD STRn+2 SS In addition, at the timing t391 of the str3 programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th .

[0307] At the timing t392 of the str3 programming operation, the word line WL is selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supplying the write path circuit V PASS At the timing t393 of the str3 programming action, the word line WL is selected. S Supply str3 programming voltage V PGM In addition, str2 programming voltage V PGM With str3 programming voltage V PGM They are different voltages, but can also be the same voltage.

[0308] At the timing t394 of the str3 programming operation, the word line WL is selected. S Supply write path voltage V PASS , set str3 programming voltage V PGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , source side non-select word line WL U_S Supply voltage V DD -V th , the write path voltage V PASS Reduced to voltage V DD -V th .

[0309] At the timing t395 of the str3 programming operation, the gate line SGD STRn+3 and the word line WL are selected. S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply voltage V SS , select the voltage V of the gate line SGD STRn+3 SGD , select word line WL S Write path voltage V PASS , drain side non-select word line WL U_D , source side non-select word line WL U_S The voltage V DD -V th Reduced to voltage V SS .

[0310] At the timing t396 of the str3 programming operation, the bit line BL n+3 Supply voltage V SS , the bit line BL n+3 The voltage V DD Reduced to voltage V SS .

[0311] At timing t401 to timing t403 after the str3 programming operation, an equalization operation (discharging) is performed.

[0312] At the timing t401 of the equalization operation, the bit line BL n ~Bit line BL n+3 , select gate line SGD STRn ~ select gate line SGD STRn+3, select word line WL S , drain side non-select word line WL U_D , source side non-select word line WL U_S , supply open circuit voltage.

[0313] At the timing t402 of the equalization operation, the bit line BL n ~Bit line BL n+3 , select gate line SGD STRn ~ select gate line SGD STRn+3, select word line WL S , drain side non-select word line WL U_D , source side non-select word line WL U_S , source side selection gate line SGS, source line SL, supply voltage V SS .

[0314] [Third embodiment]

[0315] The programming operation in the first mode is also applicable to programming across the word lines WL. Hereinafter, this case will be described as the present embodiment.

[0316] [Writing Operation in the First Mode]

[0317] Next, refer to Figure 20 The first mode of programming operation of this embodiment will be described. In the first mode of programming operation of this embodiment, binary values ​​(1 bit) are also stored in a plurality of memory cells MC.

[0318] Figure 20 This is a timing chart for explaining the write operation in the first mode of the third embodiment. Figure 20 The selection gate lines SGD STRn, SGD STRn+1, SGD STRn+2, and SGD STRn+3 are as shown in FIG. Figure 19 Word line WL n and word line WL n+1 The word line WL is crossed, and when it becomes the writing target, it indicates that the word line WL is selected. S . Figure 20 , there is shown a case where the channel precharge operation is performed from the source side to the gate line SGS side in the first precharge operation.

[0319] From timing t521 to timing t531, a first precharge operation is performed to precharge the target wiring by supplying a predetermined voltage.

[0320] At the timing t521 of the first precharge operation, for example, the bit line BL is set to 0 during the programming operation. W Bit line BL n , bit line BL n+2 , bit line BL n+3 , supply voltage V SS , becomes the bit line BL in the str0 programming action P Bit line BL n+1 Supply voltage V DD , supply voltage V to the source line SL SL In addition, the word line WL n , word line WL n+1 , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V PRE , the voltage V SS Rising to voltage V PRE In addition, the select gate lines SGD STRn, SGD STRn+1, SGD STRn+2, SGD STRn+3, and the drain side non-select word line WL U_D , supply voltage V SS In this way, the channel precharge operation is performed from the source side to the gate line SGS side.

[0321] At the timing t522 of the first precharge operation, the word line WL n , word line WL n+1 , source side non-select word line WL U_S , source side select gate line SGS, supply voltage V SS , the voltage V PRE Reduced to voltage V SS .

[0322] At timing t523 of the first precharge operation, a voltage V is supplied to the source line SL. SS , the voltage V SL Reduced to voltage V SS In addition, the source side selection gate line SGS is supplied with a voltage V SGS , the voltage V SS Rising to voltage V SGS In addition, the voltage V may be supplied to the source side selection gate line SGS at the timing t523 of the first precharge operation. SS The status remains unchanged.

[0323] At timing t524 of the first precharge operation, a voltage V is supplied to the source line SL.SGS , the voltage V SS Rising to voltage V SGS In addition, the voltage V may be maintained on the source line SL at the timing t524 of the first precharge operation. SS The status remains unchanged.

[0324] At timing t525 of the first precharge operation, a voltage V is supplied to the select gate line SGDSTRn+1 to be written in the str0 program operation. SGD .

[0325] From timing t531 to timing t537, the str0 programming action is performed.

[0326] At the timing t531 of the str0 programming operation, for example, the bit line BL becomes P Bit line BL n+1 Supply voltage V DD (1st voltage), becomes bit line BL in str0 programming operation W Bit line BL n , bit line BL n+2 , bit line BL n+3 , supply voltage V SS , supply voltage V to the selection gate line SGDstr0 SGD In addition, at the timing t531 of the str0 programming operation, the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th .

[0327] At the timing t532 of the str0 programming operation, the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply write path voltage V PASS At the timing t533 of the str0 programming action, the word line WL n Supply str0 programming voltage V PGM .

[0328] At the timing t534 of the str0 programming operation, the word line WL n Supply write path voltage V PASS , set str0 programming voltage VPGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , word line WL n+1 , source side non-select word line WL U_S , supply voltage V DD -V th , the write path voltage V PASS Reduced to voltage V DD -V th .

[0329] At the timing t535 of the str0 programming operation, the gate line SGD STRn+1 and the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply voltage V SS , select the voltage V of the gate line SGD STRn+1 SGD , the write path voltage V PASS , word line WL n+1 , drain side non-select word line WL U_D , source side non-select word line WL U_S The voltage V DD -V th Reduced to voltage V SS .

[0330] At the timing t536 of the str0 programming operation, the bit line BL n+1 Supply voltage V SS , the bit line BL n+1 The voltage V DD Reduced to voltage V SS .

[0331] A recovery action is performed from timing t537 to timing t551 after the str0 programming action and before the str1 programming action.

[0332] At the timing t541 of the restore operation, the bit line BL is set to 0 in the programming operation of str1. P Bit line BL n , bit line BL n+2 Supply voltage V DD , as the recovery voltage.

[0333] At the timing t542 of the restore operation, the voltage V is supplied to the select gate line SGD STRn+2 which is the target of the programming operation of str1. SGD .

[0334] From timing t551 to timing t561, the str1 programming action is executed.

[0335] At the timing t551 of the str1 programming operation, for example, the bit line BL becomes P Bit line BL n , bit line BL n+2 Supply voltage V DD (1st voltage), becomes bit line BL in the str1 programming operation W Bit line BL n+1 , bit line BL n+3 Supply voltage V SS , supply voltage V to select gate line SGD STRn+1 SGD In addition, at the timing t551 of the str1 programming operation, the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th .

[0336] At the timing t552 of the str1 programming operation, the drain side non-selected word line WL U_D、 Word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply write path voltage V PASS .

[0337] At the timing t553 of the str1 programming operation, the word line WL n Supply str1 programming voltage V PGM .

[0338] At the timing t554 of the str1 programming operation, the word line WL n Supply write path voltage V PASS , set str1 programming voltage V PGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , word line WL n+1 , source side non-select word line WL U_S , supply voltage V DD -V th , the write path voltage V PASS Reduced to voltage V DD -V th .

[0339] At the timing t555 of the str1 programming operation, the gate line SGD STRn+2 and the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply voltage V SS , select the voltage V of the gate line SGD STRn+2 SGD , word line WL n Write path voltage V PASS , word line WL n+1 , drain side non-select word line WL U_D , source side non-select word line WL U_S The voltage V DD -V th Reduced to voltage V SS .

[0340] At the timing t556 of the str1 programming operation, the bit line BL n , bit line BL n+2 Supply voltage V SS , the bit line BL n , bit line BL n+2 The voltage V DD Reduced to voltage V SS .

[0341] A recovery action is performed from timing t561 to timing t571 after the str1 programming action and before the str2 programming action.

[0342] At the timing t561 of the restore operation, the bit line BL is set to 0 in the programming operation of str2. P Bit line BL n+2 Supply voltage V DD , as the recovery voltage.

[0343] At the timing t562 of the recovery operation, the voltage V is supplied to the select gate line SGD STRn+3 which is the target of the programming operation of str2. SGD .

[0344] From timing t571 to timing t581, the str2 programming action is executed.

[0345] At the timing t571 of the str2 programming operation, for example, the bit line BL becomes P Bit line BL n+2 Supply voltage V DD (1st voltage), becomes bit line BL in the programming operation of str2 W Bit line BLn , bit line BL n+1 , bit line BL n+3 , supply voltage V SS , supply voltage V to select gate line SGD STRn+3 SGD In addition, at the timing t571 of the str2 programming operation, the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply voltage V DD -V th , the voltage V SS Rising to voltage V DD -V th .

[0346] At the timing t572 of the str2 programming operation, the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply write path voltage V PASS At the timing t573 of the str2 programming action, the word line WL n Supply str2 programming voltage V PGM .

[0347] At the timing t574 of the str2 programming operation, the word line WL n Supply write path voltage V PASS , set str2 programming voltage V PGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , word line WL n+1 , source side non-select word line WL U_S , supply voltage V DD -V th , the write path voltage V PASS Reduced to voltage V DD -V th .

[0348] At the timing t575 of the str2 programming operation, the gate line SGD STRn+3 and the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply voltage V SS , select the voltage V of the gate line SGD STRn+3 SGD , word line WLn Write path voltage V PASS , drain side non-select word line WL U_D , word line WL n+1 , source side non-select word line WL U_S The voltage V DD -V th Reduced to voltage V SS .

[0349] At the timing t576 of the str2 programming operation, the bit line BL n+2 Supply voltage V SS , the bit line BL n+2 The voltage V DD Reduced to voltage V SS .

[0350] A recovery action is performed from timing t581 to timing t591 after the str2 programming action and before the str3 programming action.

[0351] At the timing t581 of the restore operation, the bit line BL is set to 0 in the programming operation of str3. P Bit line BL n+3 Supply voltage V DD , as the recovery voltage.

[0352] At the timing t582 of the restore operation, the voltage V is supplied to the select gate line SGD STRn+1 which is the target of the programming operation of str3. SGD .

[0353] From timing t591 to timing t601, the str3 programming action is executed.

[0354] At the timing t591 of the str3 programming operation, for example, the bit line BL becomes P Bit line BL n+3 Supply voltage V DD (1st voltage), becomes bit line BL in the programming operation of str3 W Bit line BL n , bit line BL n+1 , bit line BL n+2 , supply voltage V SS , supply voltage V to select gate line SGD STRn+1 SGD In addition, at the timing t591 of the str3 programming action, the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply voltage V DD -V th, the voltage V SS Rising to voltage V DD -V th .

[0355] At the timing t592 of the str3 programming operation, the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply write path voltage V PASS At the timing t593 of the str3 programming action, the word line WL n Supply str3 programming voltage V PGM .

[0356] At the timing t594 of the str3 programming operation, the word line WL n+1 Supply write path voltage V PASS , set str3 programming voltage V PGM Reduce to the write path voltage V PASS , for the drain side non-select word line WL U_D , word line WL n , source side non-select word line WL U_S , supply voltage V DD -V th , the write path voltage V PASS Reduced to voltage V DD -V th .

[0357] At the timing t595 of the str3 programming operation, the gate line SGD STRn+1 and the drain side non-selected word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply voltage V SS , select the voltage V of the gate line SGD STRn+1 SGD , word line WL n+1 Write path voltage V PASS , drain side non-select word line WL U_D , word line WL n , source side non-select word line WL U_S The voltage V DD -V th Reduced to voltage V SS .

[0358] At the timing t596 of the str3 programming operation, the bit line BL n+3 Supply voltage V SS , the bit line BL n+3The voltage V DD Reduced to voltage V SS .

[0359] At timing t601 to timing t603 after the str3 programming operation, an equalization operation (discharging) is performed.

[0360] At the timing t601 of the equalization operation, the bit line BL n ~Bit line BL n+3 , select gate line SGD STRn ~ select gate line SGD STRn+3, drain side non-select word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , supply open circuit voltage.

[0361] At the timing t502 of the equalization operation, the bit line BL n ~Bit line BL n+3 , select gate line SGD STRn ~ select gate line SGD STRn+3, drain side non-select word line WL U_D , word line WL n , word line WL n+1 , source side non-select word line WL U_S , source side selection gate line SGS, source line SL, supply voltage V SS .

[0362] [other]

[0363] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention and are encompassed by the invention recited in the claims and their equivalents.

[0364] [Explanation of symbols]

[0365] BLK memory block

[0366] MC storage unit

[0367] MCA Memory Cell Array

[0368] PC peripheral circuits

[0369] WL word line

[0370] BL bit line

[0371] SL Source Line

[0372] SGD Drain side select gate line

[0373] SGS Source side select gate line

[0374] STD Drain side selection transistor

[0375] STS Source Side Select Transistor

[0376] 120 Semiconductors

[0377] 130 Gate insulating film.

Claims

1. A semiconductor memory device comprising: substrate; a plurality of memory blocks arranged side by side with the substrate in a first direction intersecting the surface of the substrate and arranged in a second direction intersecting the first direction; and A control circuit, connected to the plurality of memory blocks, for executing a write operation; Each of the plurality of memory blocks comprises: a first drain side selection transistor and a second drain side selection transistor; a first source side selection transistor and a second source side selection transistor; a first memory cell transistor and a second memory cell transistor electrically connected in series between the first drain-side selection transistor and the first source-side selection transistor; a third memory cell transistor and a fourth memory cell transistor electrically connected in series between the second drain-side selection transistor and the second source-side selection transistor; a first bit line and a second bit line electrically connected to the first drain-side selection transistor and the second drain-side selection transistor, respectively; a first selection gate line electrically connected to a gate electrode of the first drain-side selection transistor; a second selection gate line electrically connected to the gate electrode of the second drain-side selection transistor; a third selection gate line electrically connected to the gate electrodes of the first source side selection transistor and the second source side selection transistor; a source line electrically connected to the first source side selection transistor and the second source side selection transistor; a first word line electrically connected to gate electrodes of the first memory cell transistor and the third memory cell transistor; and a second word line electrically connected to gate electrodes of the second memory cell transistor and the fourth memory cell transistor; The control circuit is configured to execute a first mode of writing operation in which a first precharge operation and a first programming operation are sequentially executed and then a second programming operation is continuously executed. The control circuit In the first precharge operation, a predetermined voltage is supplied to the first word line. In the first programming operation, a first voltage is supplied to the first selection gate line, a second voltage lower than the first voltage is supplied to the second selection gate line, a first programming voltage is supplied to the first word line, and a write path voltage lower than the first programming voltage is supplied to the second word line. In the second programming operation, the second voltage is supplied to the first selection gate line, the first voltage is supplied to the second selection gate line, a second programming voltage greater than the write path voltage is supplied to the first word line, and the write path voltage is supplied to the second word line. After supplying the first programming voltage and before supplying the second programming voltage, the voltage of the first selection gate line is switched from the first voltage to the second voltage, and the voltage of the second selection gate line is switched from the second voltage to the first voltage.

2. The semiconductor memory device according to claim 1, wherein The control circuit causes the first memory cell transistor and the third memory cell transistor to store binary data in the first programming operation and the second programming operation.

3. The semiconductor memory device according to claim 1, wherein the control circuit In the first programming operation, a first bit line voltage is supplied to the first bit line, and a second bit line voltage is supplied to the second bit line. In the second programming operation, a third bit line voltage is supplied to the first bit line, and a fourth bit line voltage is supplied to the second bit line. After supplying the first programming voltage and before supplying the second programming voltage, the voltage of the first bit line is switched from the first bit line voltage to the third bit line voltage, and the voltage of the second bit line is switched from the second bit line voltage to the fourth bit line voltage.

4. The semiconductor memory device according to claim 3, wherein the programming operation in the first mode further includes an equalization operation performed after the second programming operation. In the equalization operation, the control circuit switches the voltages of the first select gate line, the second select gate line, the first word line, and the second word line from the second voltage to a first open voltage that is higher than the second voltage.

5. The semiconductor memory device according to claim 1, wherein In the first pre-charging operation, the control circuit A third voltage higher than the second voltage is supplied to the first selection gate line, the second selection gate line, the first word line, the second word line, and the third selection gate line.

6. The semiconductor memory device according to claim 1, further comprising: a fifth memory cell transistor provided between the first drain-side selection transistor and the first memory cell transistor; a sixth memory cell transistor provided between the second drain side selection transistor and the third memory cell transistor; and a third word line electrically connected to the gate electrodes of the fifth memory cell transistor and the sixth memory cell transistor; and The second memory cell transistor is located between the first memory cell transistor and the first source side selection transistor. The fourth memory cell transistor is located between the third memory cell transistor and the second source side selection transistor. In the first pre-charging operation, the control circuit A third voltage higher than the second voltage is supplied to the first selection gate line, the second selection gate line, the first word line, and the third word line.

7. The semiconductor memory device according to claim 1, further comprising: a fifth memory cell transistor provided between the first drain-side selection transistor and the first memory cell transistor; a sixth memory cell transistor provided between the second drain side selection transistor and the third memory cell transistor; and a third word line electrically connected to the gate electrodes of the fifth memory cell transistor and the sixth memory cell transistor; and The second memory cell transistor is located between the first memory cell transistor and the first source side selection transistor. The fourth memory cell transistor is located between the third memory cell transistor and the second source side selection transistor. In the first pre-charging operation, the control circuit A third voltage higher than the second voltage is supplied to the first word line, the second word line, and the third selection gate line.

8. The semiconductor memory device according to claim 1, wherein The control circuit is configured to further execute a second mode of writing operation in which the first precharge operation and the first programming operation are sequentially executed, and then the second precharge operation and the second programming operation are sequentially executed. In the second precharge operation, a predetermined voltage is supplied to the first word line.

9. The semiconductor memory device according to claim 1, wherein The first mode programming operation further includes a first verification operation and a second verification operation performed after the second programming operation. The control circuit In the first verification operation, supplying a fourth voltage greater than the first voltage to the first selection gate line and the third selection gate line; supplying the second voltage to the second selection gate line, supplying a first verification voltage lower than the fourth voltage to the first word line, In the second verification operation, supplying the fourth voltage to the second selection gate line and the third selection gate line, supplying the second voltage to the first selection gate line, The first verification voltage is supplied to the first word line.

10. The semiconductor memory device according to claim 1, wherein The memory block comprises: A plurality of conductive layers arranged in the first direction; a semiconductor pillar extending in the first direction and facing the plurality of conductive layers; and a charge accumulation film disposed between the plurality of conductive layers and the semiconductor pillar; and One of the plurality of conductive layers functions as the first word line. Another one of the plurality of conductive layers functions as the second word line.

11. A method for controlling a semiconductor memory device, wherein the semiconductor memory device comprises: substrate; a plurality of memory blocks arranged side by side with the substrate in a first direction intersecting the surface of the substrate and arranged in a second direction intersecting the first direction; and A control circuit, connected to the plurality of memory blocks, for executing a write operation; Each of the plurality of memory blocks comprises: a first drain side selection transistor and a second drain side selection transistor; a first source side selection transistor and a second source side selection transistor; a first memory cell transistor and a second memory cell transistor electrically connected in series between the first drain-side selection transistor and the first source-side selection transistor; a third memory cell transistor and a fourth memory cell transistor electrically connected in series between the second drain-side selection transistor and the second source-side selection transistor; a first bit line and a second bit line electrically connected to the first drain-side selection transistor and the second drain-side selection transistor, respectively; a first selection gate line electrically connected to a gate electrode of the first drain-side selection transistor; a second selection gate line electrically connected to the gate electrode of the second drain-side selection transistor; a third selection gate line electrically connected to the gate electrodes of the first source side selection transistor and the second source side selection transistor; a source line electrically connected to the first source side selection transistor and the second source side selection transistor; a first word line electrically connected to gate electrodes of the first memory cell transistor and the third memory cell transistor; and a second word line electrically connected to gate electrodes of the second memory cell transistor and the fourth memory cell transistor; The control circuit is configured to execute a first mode of writing operation in which a first precharge operation and a first programming operation are sequentially executed and then a second programming operation is continuously executed. In the first precharge operation, a predetermined voltage is supplied to the first word line. In the first programming operation, a first voltage is supplied to the first selection gate line, a second voltage lower than the first voltage is supplied to the second selection gate line, a first programming voltage is supplied to the first word line, and a write path voltage lower than the first programming voltage is supplied to the second word line. In the second programming operation, the second voltage is supplied to the first selection gate line, the first voltage is supplied to the second selection gate line, a second programming voltage greater than the write path voltage is supplied to the first word line, and the write path voltage is supplied to the second word line. After supplying the first programming voltage and before supplying the second programming voltage, the voltage of the first selection gate line is switched from the first voltage to the second voltage, and the voltage of the second selection gate line is switched from the second voltage to the first voltage.

12. The method for controlling a semiconductor memory device according to claim 11, wherein The control circuit causes the first memory cell transistor and the third memory cell transistor to store binary data in the first programming operation and the second programming operation.

13. The method for controlling a semiconductor memory device according to claim 11, wherein In the first programming operation, a first bit line voltage is supplied to the first bit line, and a second bit line voltage is supplied to the second bit line. In the second programming operation, a third bit line voltage is supplied to the first bit line, and a fourth bit line voltage is supplied to the second bit line. After supplying the first programming voltage and before supplying the second programming voltage, the voltage of the first bit line is switched from the first bit line voltage to the third bit line voltage, and the voltage of the second bit line is switched from the second bit line voltage to the fourth bit line voltage.

14. The control method of the semiconductor memory device according to claim 13, wherein the programming operation in the first mode further includes an equalization operation performed after the second programming operation. In the equalization operation, the voltages of the first select gate line, the second select gate line, the first word line, and the second word line are switched from the second voltage to a first open voltage that is higher than the second voltage.

15. The method for controlling a semiconductor memory device according to claim 11, wherein In the first precharge operation, A third voltage higher than the second voltage is supplied to the first selection gate line, the second selection gate line, the first word line, the second word line, and the third selection gate line.

16. The method for controlling a semiconductor memory device according to claim 11, wherein The semiconductor memory device further comprises: a fifth memory cell transistor provided between the first drain-side selection transistor and the first memory cell transistor; a sixth memory cell transistor provided between the second drain side selection transistor and the third memory cell transistor; and a third word line electrically connected to the gate electrodes of the fifth memory cell transistor and the sixth memory cell transistor; and The second memory cell transistor is located between the first memory cell transistor and the first source-side transistor. The fourth memory cell transistor is located between the third memory cell transistor and the second source-side transistor. In the first precharge operation, A third voltage higher than the second voltage is supplied to the first selection gate line, the second selection gate line, the first word line, and the third word line.

17. The method for controlling a semiconductor memory device according to claim 11, wherein The semiconductor memory device further comprises: a fifth memory cell transistor provided between the first drain-side selection transistor and the first memory cell transistor; a sixth memory cell transistor provided between the second drain side selection transistor and the third memory cell transistor; and a third word line electrically connected to the gate electrodes of the fifth memory cell transistor and the sixth memory cell transistor; and The second memory cell transistor is located between the first memory cell transistor and the first source side selection transistor. The fourth memory cell transistor is located between the third memory cell transistor and the second source side selection transistor. In the first precharge operation, A third voltage higher than the second voltage is supplied to the first word line, the second word line, and the third selection gate line.

18. The method for controlling a semiconductor memory device according to claim 11, wherein The control circuit is configured to further execute a second mode of writing operation in which the first precharge operation and the first programming operation are sequentially executed, and then a second precharge operation and the second programming operation are sequentially executed. In the second precharge operation, a predetermined voltage is supplied to the first word line.

19. The method for controlling a semiconductor memory device according to claim 11, wherein The first mode programming operation further includes a first verification operation and a second verification operation performed after the second programming operation. In the first verification operation, supplying a fourth voltage greater than the first voltage to the first selection gate line and the third selection gate line; supplying the second voltage to the second selection gate line, supplying a first verification voltage lower than the fourth voltage to the first word line, In the second verification operation, supplying the fourth voltage to the second selection gate line and the third selection gate line, The first verification voltage is supplied to the first word line.

20. The control method of a semiconductor memory device according to claim 11, wherein The memory block comprises: A plurality of conductive layers arranged in the first direction; a semiconductor pillar extending in the first direction and facing the plurality of conductive layers; and a charge accumulation film disposed between the plurality of conductive layers and the semiconductor pillar; and One of the plurality of conductive layers functions as the first word line. Another one of the plurality of conductive layers functions as the second word line.

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