Preparation process of ceramic plate for three-dimensional packaging structure

Abstract

The invention relates to the technical field of semiconductor packaging, in particular to a preparation process of a ceramic plate for a three-dimensional packaging structure. The preparation process provided by the invention at least comprises the following steps: generating a light painting file; preparing each layer of mask plate, and preparing photosensitive ceramic slurry and photosensitive conductive slurry; spin-coating photosensitive ceramic slurry on the silicon substrate to form a dielectric layer; spin-coating photosensitive conductive slurry to form a conductor layer; completing a laminated structure in which all inner dielectric layers and conductor layers are alternated; sintering and curing the whole laminated structure at high temperature, separating the silicon bottom plate and grinding the surface of the ceramic plate; manufacturing lines and bonding pads on the top layer and the bottom layer through a rewiring layer process; and performing surface treatment on the ceramic plate on which wiring is completed. According to the invention, the ceramic plate is adopted to replace a traditional silicon intermediate plate, so that the integration level and the heat dissipation performance are improved, the overall power consumption performance is optimized, and the requirements of a modern high-performance and multifunctional system are better met.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a preparation process of a ceramic plate for a three-dimensional packaging structure and a three-dimensional packaging structure based on ceramics. Background Art

[0002] Moore's Law, a key guiding principle for the development of the semiconductor industry, has long driven the rapid evolution of integrated circuit technology. Its core principle is to improve performance, reduce power consumption, and optimize costs by continuously shrinking process nodes, integrating more transistors within the same chip area. However, as process technology continues to advance toward 7nm nodes and below, the process difficulty and cost pressures are increasing. The cost per unit area of ​​current advanced process chips is much higher than before, making the traditional approach of improving chip performance by shrinking process nodes unsustainable. Furthermore, simply increasing chip area to achieve higher computing power also leads to significant cost increases and reduced yields. Therefore, to maintain the performance growth curve driven by Moore's Law, the industry has gradually shifted its focus from process breakthroughs to innovations in advanced packaging technologies.

[0003] Advanced packaging technologies, particularly system-in-package (SiP) solutions represented by 2.5D and 3D packaging, have become a key approach for achieving high-performance integration. Unlike the "one package, one chip" approach of traditional planar packaging, 2.5D / 3D packaging integrates multiple heterogeneous chips (including logic chips, memory, analog devices, I / O controllers, etc.) within a single package structure, forming a complete system, significantly improving integration and system performance. SiP solutions typically integrate different functional chips into a single structure through horizontal (2.5D) or vertical (3D) interconnects, multiplying chip functionality and performance while maintaining a constant package size. Leveraging key technologies such as TSV (through silicon via), silicon interposer, and micro-bumps, advanced packaging not only significantly shortens signal transmission paths, increasing data bandwidth and interconnect speeds, but also reduces reliance on costly processes through heterogeneous integration, achieving a balance between cost and performance.

[0004] As chip functionality becomes increasingly complex and heterogeneous integration becomes increasingly demanding, SiP solutions and advanced packaging technologies are facing increasing manufacturing and reliability challenges. For example, the current mainstream silicon interposer solution has the following drawbacks:

[0005] 1) Limited number of circuit layers: Silicon interposers typically use the RDL (Redistribution Layer) process to fabricate interconnect lines on the surface. However, the RDL process has physical and cost limitations in terms of the achievable number of layers and line width / line spacing, making it difficult to meet future high-density interconnect requirements.

[0006] 2) Thermal expansion mismatch risk: There are large differences in thermal expansion coefficients between the conductor material of the RDL layer, the dielectric layer, and the silicon body. When the chip is operating at high temperatures, failures such as stress concentration and interlayer cracking are prone to occur, affecting system reliability.

[0007] 3) Impedance control difficulties: The limited variety of dielectric materials in silicon interposer structures makes it difficult to achieve precise impedance matching and loss control, which becomes a bottleneck in high-speed signal transmission applications.

[0008] 4) TSV reliability issues: Although the TSV structure in 3D packaging can achieve vertical interconnection, it uses copper as the hole-filling conductor. This is prone to cracking due to thermal mismatch under high power consumption or extreme temperature conditions, affecting the stability of the entire system.

[0009] 5) Limited heat dissipation capacity: In a multi-chip integrated structure, the overall power consumption of the system increases significantly, while the conventional organic packaging substrate has poor thermal conductivity, making it difficult to achieve effective heat dissipation, which may lead to overheating inside the chip, performance degradation, or even functional failure.

[0010] In summary, current advanced packaging technologies centered around silicon interposers and traditional organic packaging substrates still face numerous bottlenecks in high-density interconnection, thermal management, and reliability. A new material system and packaging structure are urgently needed to meet the demands of future high-performance, low-power, and multi-functional heterogeneous chip systems. Summary of the Invention

[0011] The purpose of the present invention is to provide a preparation process for a ceramic plate for a three-dimensional packaging structure and a three-dimensional packaging structure based on ceramics, so as to solve the problems of existing silicon interposers such as limited number of layers, thermal expansion mismatch, difficulty in line impedance control, insufficient TSV reliability and poor heat dissipation performance, thereby achieving higher-density multi-chip integration, better electrical performance and more stable thermal management capabilities, and meeting the needs of advanced packaging technology for development towards high performance and high reliability.

[0012] To achieve the above object, the present invention provides a process for preparing a ceramic plate for a three-dimensional packaging structure, comprising at least the following steps:

[0013] Design stacking structure and signal / power distribution scheme according to system integration requirements, determine process parameters and generate photolithography files;

[0014] Prepare each layer of mask, and prepare photosensitive ceramic slurry and photosensitive conductive slurry;

[0015] Spin-coat a photosensitive ceramic slurry on a silicon substrate, bake and solidify it, and then photolithograph to form a dielectric layer with a via structure; spin-coat a photosensitive conductive slurry, bake and solidify it, and then photolithograph to form a conductor layer; repeat this step to complete the stacking structure of all inner dielectric layers and conductor layers alternating;

[0016] The entire laminated structure is sintered and solidified at high temperature, the silicon base plate is separated and the surface of the ceramic plate is ground;

[0017] Make circuits and pads on the top and bottom layers through redistribution layer technology;

[0018] Surface treatment of the ceramic plate after wiring is completed;

[0019] The photosensitive ceramic slurry comprises ceramic powder, a photoinitiator, an ultraviolet light absorber and a sintering aid, and the photosensitive conductive slurry comprises silver powder, a photosensitive resin, a stabilizer and a dispersant.

[0020] In some embodiments, the steps of designing a stacked structure and a signal / power distribution scheme according to system integration requirements, determining process parameters, and generating a photolithography file further include:

[0021] According to the number and type of chips and signal transmission requirements, design the signal channel and power supply merging plan, determine the stacking thickness, ceramic slurry ratio and dielectric thickness, and output the photolithography file.

[0022] In some embodiments, before the step of preparing each layer of mask, the method further includes:

[0023] Perform manufacturability checks on Gerber files.

[0024] In some embodiments, the ceramic powder of the photosensitive ceramic slurry comprises at least one of barium calcium titanate, barium titanate, doped modified barium titanate, composite barium titanium zirconium, lead metaniobate, bismuth titanate, bismuth lead tantalate, and ferromagnetic magnet;

[0025] The photoinitiator of the photosensitive ceramic slurry comprises at least one of an acrylic polymer and a photoreactive compound;

[0026] The ultraviolet light absorber of the photosensitive ceramic slurry comprises a carbide ultraviolet light absorber;

[0027] The sintering aid of the photosensitive ceramic slurry includes silicate glass powder.

[0028] In some embodiments, the photoinitiator of the photosensitive ceramic slurry comprises at least one of benzoin dimethyl ether, benzoin ethyl ether, benzophenone, 2,4,6-trimethylbenzoyl-diphenylphosphine oxide, or triphenylsulfonium hexafluoroantimonate.

[0029] In some embodiments, the ultraviolet light absorber of the photosensitive ceramic slurry includes at least one of TiC, SiC, or NBC.

[0030] In some embodiments, the sintering aid of the photosensitive ceramic slurry includes at least one of borosilicate glass, alkali metal silicate glass, or lead silicate glass.

[0031] In some embodiments, the silver powder of the photosensitive conductive paste comprises at least one of nano silver ions, silver powder, or silver palladium paste.

[0032] In some embodiments, the photosensitive resin of the photosensitive conductive paste comprises at least an acrylic polymer.

[0033] In some embodiments, the photosensitive resin of the photosensitive conductive paste includes at least one of benzoin dimethyl ether, benzoin ethyl ether, benzophenone, 2,4,6-trimethylbenzoyl-diphenylphosphine oxide (TPO), or triphenylsulfonium hexafluoroantimonate.

[0034] In some embodiments, the stabilizer of the photosensitive conductive paste comprises a benzophenone or benzotriazole ultraviolet absorber;

[0035] The dispersant of the photosensitive conductive paste includes nano-barium sulfate or nano-calcium carbonate.

[0036] In some embodiments, the step of spin-coating a photosensitive ceramic slurry on a silicon substrate, and then photolithographically forming a dielectric layer having a via structure after baking and curing further comprises:

[0037] Select a silicon base plate as a temporary carrier substrate according to the product size;

[0038] Spin-coat photosensitive ceramic slurry on the silicon substrate and control the equipment parameters to achieve the specified stacking thickness;

[0039] Bake and solidify the spin-coated photosensitive ceramic slurry;

[0040] Spin-coating photoresist on the cured ceramic slurry layer, and performing UV exposure using a pre-prepared mask to transfer the via pattern to the ceramic slurry layer;

[0041] The via pattern is developed and etched to form a dielectric layer with a via structure.

[0042] In some embodiments, the step of spin-coating the photosensitive conductive paste, baking and curing it, and then photolithographically forming the conductor layer further includes:

[0043] Spin-coat the photosensitive conductive paste on the formed dielectric layer, and control the equipment parameters to make the paste reach the specified stacking thickness;

[0044] Bake and solidify the spin-coated photosensitive conductive paste;

[0045] Spin-coat photoresist on the cured conductive paste layer, perform UV exposure using a pre-prepared mask, and transfer the pattern of the corresponding circuit layer to the conductive paste layer;

[0046] The pattern corresponding to the circuit layer is developed and etched to form a conductor layer with the designed circuit pattern.

[0047] In some embodiments, the step of fabricating circuits and pads on the top and bottom layers using a redistribution layer process further includes:

[0048] Coating photoresist on the top / bottom layer of the ceramic plate and performing exposure and development to form the pattern of the top / bottom layer;

[0049] Metal electroplating is performed on the patterned area to form a top / bottom conductive layer;

[0050] Remove the residual photoresist and etch away the metal in the non-graphic area, leaving the top / bottom layer of circuits and pads.

[0051] To achieve the above objectives, the present invention provides a ceramic-based three-dimensional packaging structure, which includes at least several chips, a ceramic interposer, and a ceramic glass substrate:

[0052] The plurality of chips are mounted on the upper surface of the ceramic interposer;

[0053] The ceramic interposer is located between the chip and the ceramic glass substrate and is used to realize signal interconnection between the chips;

[0054] The ceramic glass substrate is arranged below the ceramic interposer and is electrically connected to the PCB board, and is used to fan out the chip interconnection signals to the PCB board.

[0055] In some embodiments, the plurality of chips are electrically connected to the ceramic interposer via controllably collapsible chip connection bumps;

[0056] The ceramic glass substrate and the ceramic interposer are electrically connected via controllably collapsed chip connection bumps.

[0057] In some embodiments, the ceramic intermediate plate and / or ceramic glass plate are manufactured using the above-mentioned manufacturing process.

[0058] The present invention provides a preparation process for a ceramic interposer for a three-dimensional packaging structure and a three-dimensional packaging structure based on the ceramic interposer. By replacing the traditional silicon interposer with a ceramic plate and combining high-precision photolithography and full-ceramic lamination technology, it not only improves the integration and heat dissipation performance, but also optimizes the overall power consumption performance, and can better meet the needs of modern high-performance, multi-functional systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The above and other features, properties and advantages of the present invention will become more apparent through the following description in conjunction with the accompanying drawings and embodiments, in which like reference numerals represent like features throughout, wherein:

[0060] Figure 1 A schematic diagram of a ceramic-based three-dimensional packaging structure according to an embodiment of the present invention is disclosed;

[0061] Figure 2 A step diagram of a process for preparing a ceramic plate for a three-dimensional packaging structure according to an embodiment of the present invention is disclosed.

[0062] The meanings of the reference numerals in the figures are as follows:

[0063] 1 first chip;

[0064] 2 second chip;

[0065] 3 third chip;

[0066] 4 ceramic interposer;

[0067] 5. Ceramic glass substrate;

[0068] 6. First controllably collapsed chip connection bump;

[0069] 7. Second controllably collapsed chip connection bump;

[0070] 8 solder ball bumps. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the invention and are not intended to limit the invention.

[0072] Based on the above technical problems, the present invention provides a preparation process of a ceramic board for a three-dimensional packaging structure and a three-dimensional packaging structure based on ceramics, which uses photosensitive ceramic slurry and photosensitive conductive slurry to replace traditional silicon interposer materials, effectively overcoming the shortcomings of silicon interposers in multi-layer wiring capabilities, thermal stability and TSV reliability.

[0073] Furthermore, the present invention combines ceramic boards with redistribution layer (RDL) technology to replace traditional organic substrates and construct a new packaging solution. While increasing the number and density of routing layers, it achieves better line impedance control, lower signal loss and higher thermal conductivity efficiency, significantly improving system stability and overall packaging performance.

[0074] Figure 1 A schematic diagram of a three-dimensional packaging structure based on ceramics according to an embodiment of the present invention is disclosed. Figure 1 As shown, the ceramic-based three-dimensional packaging structure proposed by the present invention includes at least several chips, a ceramic interposer 4, and a ceramic glass substrate 5:

[0075] The plurality of chips are mounted on the upper surface of the ceramic interposer 4 through a reflow soldering process;

[0076] The ceramic interposer 4 is located between the chip and the ceramic glass substrate 5 and is used to realize signal interconnection between the chips;

[0077] The ceramic glass substrate 5 is disposed below the ceramic interposer and is electrically connected to the PCB via solder balls 8 for fanning out chip interconnection signals to the PCB.

[0078] The overall architecture of the ceramic-based three-dimensional packaging structure proposed in the present invention is similar to that of 2.5D and 3D packaging structures.

[0079] In this embodiment, the plurality of chips include a first chip 1 , a second chip 2 , and a third chip 3 . These chips have different functions or are manufactured using different process technologies.

[0080] In this embodiment, interconnection lines between chips with different functions are designed inside the ceramic interposer 4 to ensure signal transmission of the entire system on chip.

[0081] The ceramic interposer 4 adopts an arbitrary layer interconnection structure, which can lead the I / O interface for external communication and the power pins required for system operation to the C4 (Controlled Collapsed Chip Connection) bump of the ceramic glass substrate 5, thereby establishing a signal and power connection channel with the external substrate and PCB.

[0082] After the ceramic interposer 4 completes the system-on-chip interconnection, the ceramic glass substrate 5 is responsible for packaging the reconstructed system-on-chip. Through the space transformer function, the ceramic glass substrate 5 converts high-density pins into a large-pitch pin package suitable for PCB soldering.

[0083] In this embodiment, the ceramic glass substrate 5 is made of a customized ceramic powder slurry through processes such as casting, punching, photolithography circuit patterning, lamination and sintering to replace the traditional ABF organic substrate.

[0084] In this embodiment, the plurality of chips are electrically connected to the ceramic interposer 4 via the first controllably collapsible chip connection bumps 6 .

[0085] The first controllably collapsed chip connection bump 6 is a controllably collapsed chip connection bump for all chips, and a flip-chip process is adopted to reflow soldering to reliably connect chips of different manufacturing processes to the ceramic interposer 4 .

[0086] These C4 bumps are manufactured by a chip bump preparation process before packaging so that their positions precisely correspond to the pads of the ceramic interposer 4 .

[0087] In this embodiment, the ceramic glass substrate 5 and the ceramic interposer 4 are electrically connected via the second controllably collapsible chip connection bumps 7 .

[0088] The second controllably collapsible chip connection bump 7 is a controllably collapsible chip connection bump of the ceramic interposer 4 itself, which is different from the first controllably collapsible chip connection bump 6 .

[0089] After the ceramic interposer 4 is fabricated, the surface pads are re-layouted using a redistribution layer (RDL) to meet solder ball spacing requirements. I / O and power signals that need to connect to the ceramic glass substrate 5 are fanned out. On the copper pad substrate after the RDL is completed, an underfill black window (UBM) process is used, including sputtering, electroplating, and solder ball reflow, completing the fabrication of the ceramic interposer 4.

[0090] The solder balls (Sold bumps) 8 are used to solder the finally packaged chip onto the PCB board.

[0091] The ceramic-based three-dimensional packaging structure proposed in the present invention comprises a ceramic interposer 4 and a ceramic glass substrate 5 which are made of a combination of a photosensitive ceramic slurry and a photosensitive conductive slurry and are prepared through photolithography, development, and sintering and curing processes.

[0092] Compared with traditional silicon interposer TSV and RDL processes, the ceramic-based three-dimensional packaging structure of the present invention uses materials that can achieve high-density arbitrary layer interconnection, effectively overcoming the technical defects of silicon interposers and breaking through the technical limitations of existing 2.5D / 3D packaging.

[0093] The present invention proposes a preparation process for a ceramic plate for a three-dimensional packaging structure. The process can be used to produce a ceramic intermediate plate 4 and a ceramic glass substrate 5. The preparation processes of the two adopt a unified technical route, and only targeted adjustments are made in the material formula to meet different functional requirements.

[0094] Figure 2 The following diagram shows a process for preparing a ceramic plate for a three-dimensional packaging structure according to an embodiment of the present invention. Figure 2 As shown, the present invention proposes a process for preparing a ceramic plate for a three-dimensional packaging structure, which comprises at least the following steps:

[0095] Step S1: Design the stacking structure and signal / power distribution scheme according to system integration requirements, determine process parameters and generate photolithography files;

[0096] Step S2, preparing each layer of mask, and preparing photosensitive ceramic slurry and photosensitive conductive slurry;

[0097] Step S3: Spin-coating a photosensitive ceramic slurry on the silicon substrate, baking and curing it, and then photolithography to form a dielectric layer with a via structure; Spin-coating a photosensitive conductive slurry, baking and curing it, and then photolithography to form a conductor layer; Repeat this step to complete the stacked structure of all inner dielectric layers and conductor layers alternating;

[0098] Step S4, sintering and curing the entire laminated structure at high temperature, separating the silicon base plate and grinding the surface of the ceramic plate;

[0099] Step S5, making circuits and pads on the top and bottom layers through a redistribution layer process;

[0100] Step S6, performing surface treatment on the ceramic plate after wiring is completed;

[0101] The photosensitive ceramic slurry comprises ceramic powder, a photoinitiator, an ultraviolet light absorber and a sintering aid, and the photosensitive conductive slurry comprises silver powder, a photosensitive resin, a stabilizer and a dispersant.

[0102] The ceramic plate includes a ceramic intermediate plate 4 and a ceramic glass substrate 5. The manufacturing processes of the ceramic intermediate plate 4 and the ceramic glass substrate 5 are completely the same. The difference mainly lies in the material selection:

[0103] The ceramic interposer 4 uses a photosensitive ceramic slurry with high dielectric properties (such as barium titanate-based materials) and a photosensitive conductive slurry with high conductivity to meet the requirements of high-density interconnection;

[0104] The ceramic glass substrate 5 uses a customized ratio of photosensitive ceramic slurry (containing glass phase) and highly conductive photosensitive conductive slurry to optimize thermal matching and mechanical strength to meet PCB-level packaging requirements.

[0105] Through the above process, the present invention realizes high-precision and high-reliability manufacturing of the ceramic interposer 4 and the ceramic glass substrate 5, and provides a ceramic plate solution with excellent performance for the three-dimensional packaging structure.

[0106] These steps will be described in detail below, using a ceramic plate as an example. It should be understood that, within the scope of the present invention, the aforementioned technical features of the present invention and the technical features described in detail below (e.g., in the embodiments) can be combined and interrelated to form a preferred technical solution.

[0107] Step S1, design planning stage: design the stacking structure and signal / power distribution scheme according to the system integration requirements, determine the process parameters and generate the photolithography file.

[0108] In this embodiment, according to the number and type of chips and signal transmission requirements, a signal channel and power supply merging scheme is designed, the stacking thickness, ceramic slurry ratio and dielectric thickness are determined, and a photolithography file is output.

[0109] More specifically, based on the number and type of chips in the packaging system and the technical requirements for signal transmission, system-level interconnect design is carried out, including signal channel design, power network design, and stacking structure design:

[0110] The signal channel is designed to plan the signal interconnection paths between different chips to ensure signal integrity;

[0111] The power network is designed to optimize the power distribution scheme of different chips and realize power merging and decoupling;

[0112] The laminate structure is designed based on the requirements of high-speed signal transmission, and the dielectric laminate thickness and conductor parameters are determined, specifically including:

[0113] Select a specific ratio of ceramic slurry to achieve precise control of the dielectric constant (DK);

[0114] Calculate and determine the thickness parameters of the ceramic dielectric layer;

[0115] Design the width and thickness specifications of the conductor material;

[0116] After the design plan is determined, the standardized photolithography file containing the graphics of each layer is output as a guide file for subsequent processing.

[0117] Step S1 focuses on signal integrity design, ensuring high-frequency signal transmission quality by optimizing the ceramic slurry ratio and stacking structure.

[0118] The photolithography file output after the design is completed defines in detail key design parameters such as the geometry of the interconnection lines of each layer, the location and size of the vias, and the pad layout.

[0119] Step S2, process preparation stage: preparing each layer of mask, and preparing photosensitive ceramic slurry and photosensitive conductive slurry;

[0120] First, a comprehensive design for manufacturability (DFM) check is required on the design output lithography file.

[0121] The manufacturability inspection will carefully check the key parameters of each layer design, such as graphic size, conductor spacing, line width, aperture, and pad diameter, to ensure that all design indicators are within the manufacturing process capabilities and to ensure the manufacturability of the inner layer graphics.

[0122] After completing the manufacturability inspection, masks for each layer need to be produced according to the requirements of the verified drawings. These high-precision masks will play a key role in the subsequent photolithography process, enabling accurate exposure and transfer of circuit patterns.

[0123] Finally, photosensitive ceramic slurries and photosensitive conductor slurries with different material ratios must be formulated based on the stacked structure and impedance control requirements. Especially for stacks with specific impedance requirements, the dielectric constant can be precisely controlled by adjusting the composition ratio of the different ceramic powder materials in the slurry, thereby meeting the performance requirements of different circuit layers.

[0124] In this embodiment, the photosensitive ceramic slurry includes ceramic powder, photoinitiator, ultraviolet light absorber and sintering aid:

[0125] Ceramic powder acts as a functional matrix material, providing the required dielectric properties and mechanical strength;

[0126] The photoinitiator is used to initiate the photocuring reaction of the slurry under ultraviolet light;

[0127] UV absorbers are used to regulate the UV absorption characteristics during the photocuring process to ensure patterning accuracy;

[0128] Sintering aids are used to promote the densification process during high-temperature sintering and improve the structural integrity of the ceramic body.

[0129] Furthermore, the ceramic powder of the photosensitive ceramic slurry contains barium calcium titanate (Ba x Ca 1-x TiO3), barium titanate (BaTiO3), doped modified barium titanate (such as PbTiO3, SiO2, TiO2, etc.), composite barium titanium zirconium (BaTi 1-x Zr x O3), lead niobate (PbNb2O6), bismuth titanate (Bi4Ti3O 12 ), lead bismuth tantalate (PbBi2Nb2O9), ferromagnetic magnet (Pb(Fe1 / 2Nb1 / 2)O3);

[0130] Furthermore, the photoinitiator of the photosensitive ceramic slurry comprises at least one of an acrylic polymer and a photoreactive compound.

[0131] Photoreactive compounds refer to a class of functional compounds that can undergo photochemical reactions (such as photodecomposition, photopolymerization, etc.) under irradiation with light of a specific wavelength.

[0132] More specifically, the photoinitiator of the photosensitive ceramic slurry comprises at least one of benzoin dimethyl ether, benzoin ethyl ether, benzophenone, 2,4,6-trimethylbenzoyl-diphenylphosphine oxide or triphenylsulfonium hexafluoroantimonate.

[0133] Furthermore, the ultraviolet light absorber of the photosensitive ceramic slurry includes inorganic powder ultraviolet light absorbers such as carbides.

[0134] More specifically, the ultraviolet light absorber of the photosensitive ceramic slurry includes at least one of TiC, SiC or NBC (boron nitride carbide).

[0135] Among them, boron nitride carbide (NBC) generally refers to a compound containing nitrogen, boron and carbon elements at the same time.

[0136] Furthermore, the sintering aid of the photosensitive ceramic slurry includes silicate glass powder to promote high-temperature sintering.

[0137] More specifically, the sintering aid of the photosensitive ceramic slurry includes at least one of borosilicate glass, alkali metal silicate glass or lead silicate glass.

[0138] In this embodiment, the photosensitive conductive paste includes silver powder, photosensitive resin, stabilizer and dispersant:

[0139] Silver powder acts as a conductive functional phase, providing the paste with electrical conductivity and current carrying capacity;

[0140] Photosensitive resin acts as a photosensitive carrier, giving the slurry UV curing properties to achieve graphic processing;

[0141] Stabilizers are used to maintain the chemical stability of slurry components to prevent performance degradation during storage or use;

[0142] Dispersants are used to improve the dispersion uniformity of silver powder in the system and ensure the integrity and reliability of the conductive network.

[0143] Furthermore, the silver powder of the photosensitive conductive paste includes at least one of nano silver ions, silver powder or silver palladium paste.

[0144] Furthermore, the photosensitive resin at least includes acrylic polymer.

[0145] More specifically, the photosensitive resin includes at least one of benzoin dimethyl ether, benzoin ethyl ether, benzophenone, 2,4,6-trimethylbenzoyl-diphenylphosphine oxide (TPO) or triphenylsulfonium hexafluoroantimonate.

[0146] Furthermore, the stabilizer comprises a benzophenone or benzotriazole ultraviolet absorber;

[0147] The dispersant comprises nano-barium sulfate or nano-calcium carbonate.

[0148] The process preparation stage of step S2 lays a solid foundation for subsequent stacking production through systematic material configuration and process verification.

[0149] First, we ensure the manufacturability of the design through rigorous DFM checks. Then, we prepare high-precision masks to achieve accurate pattern transfer. Finally, we carefully formulate a photosensitive paste system with specific functions based on the impedance control requirements:

[0150] Photosensitive ceramic slurry achieves adjustable dielectric properties and process stability by optimizing the ratio of ceramic powder, photoinitiator, UV absorber and sintering aid;

[0151] Photosensitive conductive paste ensures excellent conductivity and patterning capabilities through the synergistic effect of silver powder, photosensitive resin, stabilizer and dispersant.

[0152] Step S2 provides reliable raw material guarantee and process support for the preparation of high-performance ceramic interposers through scientific material selection and process verification.

[0153] Step S3, lamination stage: spin-coating a photosensitive ceramic slurry on the silicon substrate, baking and curing it, and then photolithography to form a dielectric layer with a via structure; spin-coating a photosensitive conductive slurry, baking and curing it, and then photolithography to form a conductor layer; repeating this step to complete the alternating lamination of all inner dielectric layers and conductor layers;

[0154] In this embodiment, the step of spin-coating a photosensitive ceramic slurry on a silicon substrate, and then photolithographically forming a dielectric layer having a via structure after baking and curing further includes:

[0155] Select a silicon base plate as a temporary carrier substrate according to the product size;

[0156] Spin-coat photosensitive ceramic slurry on the silicon substrate and control the equipment parameters to achieve the specified stacking thickness;

[0157] Bake and solidify the spin-coated photosensitive ceramic slurry;

[0158] Spin-coating photoresist on the cured ceramic slurry layer, and performing UV exposure using a pre-prepared mask to transfer the via pattern to the ceramic slurry layer;

[0159] The via pattern is developed and etched to form a dielectric layer with a via structure.

[0160] During the implementation process, a suitable silicon substrate must be selected as a temporary substrate based on the product's dimensions. The photosensitive ceramic slurry is then evenly spin-coated onto the selected silicon substrate, with precise control of the spin-coating parameters ensuring the desired film thickness. After coating, the slurry undergoes a rigorously controlled baking and curing process to ensure stable material properties.

[0161] The next stage is the pattern transfer phase, where photoresist is spin-coated onto the cured ceramic layer. UV exposure is performed using a pre-prepared mask to precisely transfer the designed via pattern to the ceramic layer. After exposure, a development process removes the material in the exposed areas, followed by an etching process to form the vertically penetrating via structure. Finally, necessary cleaning and quality inspection procedures are performed.

[0162] Taking the first layer fabrication as an example, ceramic slurry is first applied to the silicon substrate according to the design requirements, with thickness parameters strictly controlled. After coating, a pre-bake treatment is performed to initially solidify the slurry. The corresponding photomask is then used to transfer the pattern. Finally, a development and etching process is performed to form the via structure that meets the design requirements. The entire process requires strict control of process parameters at every stage to ensure the quality and reliability of the final product.

[0163] In this embodiment, the step of spin-coating the photosensitive conductive paste, baking and curing it, and then photolithographically forming the conductor layer further includes:

[0164] Spin-coat the photosensitive conductive paste on the formed dielectric layer, and control the equipment parameters to make the paste reach the specified stacking thickness;

[0165] Bake and solidify the spin-coated photosensitive conductive paste;

[0166] Spin-coat photoresist on the cured conductive paste layer, perform UV exposure using a pre-prepared mask, and transfer the pattern of the corresponding circuit layer to the conductive paste layer;

[0167] The pattern corresponding to the circuit layer is developed and etched to form a conductor layer with the designed circuit pattern.

[0168] In practice, the conductive layer is prepared immediately after the vias are fabricated. First, a photosensitive conductive paste is evenly spin-coated onto the dielectric layer with the vias. The spin-coating parameters are controlled to ensure the paste thickness meets the design requirements. After coating, the sample is placed in an oven for a carefully controlled curing process to ensure the conductive layer possesses good mechanical strength and conductivity.

[0169] After curing, the conductive layer is spin-coated with photoresist and then exposed to UV light using a pre-prepared circuit layer mask. This allows the designed circuit pattern to be precisely transferred to the conductive paste layer. After exposure, a specific developer dissolves the photoresist in the exposed areas, and a wet or dry etching process removes the exposed conductive paste, ultimately forming a precise circuit pattern. Each completed circuit pattern layer undergoes rigorous cleaning and dimensional inspection to ensure that the circuit quality meets design requirements.

[0170] Taking multilayer stacking as an example: after completing the first dielectric layer, the first conductor layer is prepared according to the above process. Then, the dielectric layer preparation process is repeated on the conductor layer to form the second dielectric layer. This alternating process is repeated, completing the second conductor layer, the third dielectric layer, the third conductor layer, and so on, until the entire stacking structure required by the design is achieved. The preparation of each layer requires strict control of process parameters to ensure interlayer alignment accuracy and interconnect reliability.

[0171] In the step S3 lamination production stage, high-precision manufacturing of multi-layer ceramic substrates was successfully achieved through precisely controlled spin coating, photolithography and etching processes. The entire process strictly controls key parameters such as spin coating thickness, baking temperature, exposure energy and development time to ensure the dimensional accuracy and interface quality of each layer structure. Through this layer-by-layer manufacturing method, not only is the high-density wiring capability of arbitrary layer interconnection achieved, but also good bonding strength and electrical connection reliability between layers are guaranteed, laying a perfect structural foundation for subsequent high-temperature sintering molding. This innovative lamination manufacturing process breaks through the layer number limit of traditional ceramic substrates and provides key substrate technology support for high-integration packaging.

[0172] Step S4, sintering and forming stage: sintering and solidifying the entire laminated structure at high temperature, separating the silicon base plate and grinding the surface of the ceramic interposer;

[0173] More specifically, the entire laminated structure is placed in a high-temperature oven for sintering and curing, so that each layer of material is completely cured and formed.

[0174] After sintering is completed, the ceramic interposer is separated from the silicon base plate, and then the surface of the ceramic interposer is precision ground to ensure that the surface flatness of the finished product is controlled within 10 microns.

[0175] For example, the high temperature sintering curing temperature is generally in the range of 850° C. to 950° C., depending on the ceramic material system.

[0176] Step S5, surface wiring production stage: circuits and pads are produced on the top and bottom layers through redistribution layer (RDL) technology;

[0177] After the ceramic interposer is sintered and ground, the redistribution layer (RDL) process is used to make the circuit and pad structures on the top and bottom layers.

[0178] In this embodiment, step S5 further includes:

[0179] Coating photoresist on the top layer / bottom layer of the ceramic interposer and performing exposure and development to form patterns of the top layer / bottom layer;

[0180] Metal electroplating is performed on the patterned area to form a top / bottom conductive layer;

[0181] Remove the residual photoresist and etch away the metal in the non-graphic area, leaving the top / bottom layer of circuits and pads.

[0182] More specifically, photoresist is first coated on the surface of the ceramic interposer, and the required circuit pattern is formed through an exposure and development process; metal electroplating is then performed on the pattern area to construct a conductive circuit layer; finally, the residual photoresist is removed, and the metal material in the non-pattern area is removed through an etching process to retain the circuit and pad structure required by the design.

[0183] This RDL process creates an additional wiring layer on the surface of a ceramic interposer, reallocating the chip's I / O ports to meet the needs of different packaging formats. The implementation involves three main steps: photoresist coating and pattern definition, conductive layer electroplating, and final patterning. Each step requires strict control of process parameters to ensure that circuit accuracy and electrical performance meet design requirements.

[0184] In step S5, the surface wiring production stage uses an innovative RDL process to achieve high-precision reconstruction of the surface circuits of the ceramic substrate, providing a reliable electrical connection interface for subsequent chip assembly and significantly improving the signal transmission performance and reliability of the packaging structure.

[0185] Step S6, surface treatment stage: performing surface treatment on the ceramic interposer after wiring is completed;

[0186] More specifically, the surface treatment of the ceramic interposer after wiring is completed mainly includes electroplating and passivation processes:

[0187] The electroplating process is used to form a solderable metal layer on the surface of the pad, which significantly improves the reliability of the subsequent welding process;

[0188] Passivation treatment forms a protective layer in non-welding areas, effectively preventing performance degradation caused by environmental factors.

[0189] After completing these processes, the subsequent chip bump reflow process can be entered.

[0190] The surface treatment stage in step S6 provides a reliable electrical connection interface and long-term stability guarantee for the ceramic interposer.

[0191] The proposed ceramic board fabrication process for 3D packaging structures innovatively utilizes a photosensitive ceramic slurry and photosensitive conductive slurry system, combined with precision photolithography patterning and multilayer lamination technology. This overcomes the technical limitations of traditional silicon interposers. From the process preparation stage, material configuration and verification (S2), precision lamination construction (S3), high-temperature sintering and molding (S4), to surface wiring fabrication (S5), and final surface treatment (S6), each process stage is closely linked to form a complete fabrication technology solution. The photosensitive slurry system enables high-precision arbitrary-layer interconnect structures, significantly improving wiring density; the all-ceramic material system exhibits excellent thermal stability and dielectric properties; and the innovative redistribution layer process enables high-precision circuit fabrication.

[0192] The ceramic plate preparation process for three-dimensional packaging structure proposed in the present invention effectively solves key technical problems such as thermal mismatch and signal integrity in advanced packaging, provides a reliable substrate solution for high-density and high-performance packaging, and shows important application value in the field of high-end packaging.

[0193] Although the above methods are illustrated and described as a series of acts for simplicity of explanation, it is to be understood and appreciated that these methods are not limited by the order of the acts, as some acts may occur in a different order and / or concurrently with other acts from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art according to one or more embodiments.

[0194] The present invention provides a process for preparing a ceramic plate for a three-dimensional packaging structure and a three-dimensional packaging structure based on ceramics, which have the following beneficial effects:

[0195] 1) Compared to existing silicon interposers, all circuits rely heavily on surface redistribution layer (RDL) routing. Limited by RDL process capabilities, mass production can only achieve three layers, making it difficult to meet the needs of higher integration. This invention replaces the silicon interposer with a ceramic interposer and combines it with high-precision photolithography technology to achieve higher routing density and a larger number of stacked layers, effectively improving the ceramic interposer's ability to support multi-chip integration.

[0196] 2) This invention utilizes an all-ceramic lamination process, resulting in better material compatibility with thermal expansion and contraction. Compared to traditional silicon interposers, which are prone to material expansion and contraction mismatches in high-temperature environments, ceramic materials offer significantly better thermal stability, effectively preventing structural deformation or cracking caused by temperature fluctuations and improving the reliability of the package structure.

[0197] 3) Ceramic interposers have a tunable dielectric constant. Compared to silicon substrates that use organic materials such as polyimide as dielectric layers, they offer stronger impedance control capabilities, making them more conducive to high-speed signal interconnection between on-chip systems and meeting the design requirements of high-frequency, high-speed chip systems.

[0198] 4) In the prior art, silicon interposers typically use through-silicon vias (TSVs) filled with copper material for vertical connection. However, in high-power applications, the thermal expansion coefficients of copper and silicon differ significantly, which can easily lead to thermal mismatch problems and, in turn, TSV cracking. The present invention uses a photosensitive conductive paste (silver paste) as the dielectric material, and by filling holes and wiring inside the ceramic interposer, it can effectively alleviate the stress concentration problem caused by thermal mismatch. At the same time, both the ceramic interposer and the ceramic glass substrate are made of ceramic materials, and the heat dissipation performance of the overall packaging structure is significantly better than that of traditional silicon interposers or organic substrate structures;

[0199] 5) In view of the higher overall power consumption of multi-chip integrated systems, the present invention adopts an all-ceramic interposer structure to replace the existing hybrid solution of organic substrate + silicon interposer, significantly improving the thermal conduction and heat dissipation efficiency, thereby effectively reducing the system thermal resistance and improving operational stability and reliability.

[0200] Although the above methods are illustrated and described as a series of acts for simplicity of explanation, it is to be understood and appreciated that these methods are not limited by the order of the acts, as some acts may occur in a different order and / or concurrently with other acts from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art according to one or more embodiments.

[0201] As used in this application and the claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not intended to refer to the singular but may include the plural. Generally speaking, the terms "comprises" and "include" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements.

[0202] Furthermore, the scope of the present invention is not limited to the particular embodiments of the processes, machines, manufacture, compositions of matter, components, methods, and steps described in the specification. A person skilled in the art will readily appreciate from this disclosure that any existing or to-be-developed process, machine, manufacture, composition of matter, component, method, or step that functions substantially the same as the corresponding embodiments described herein or that can achieve substantially the same results as the embodiments described herein may be used in accordance with the present invention. Accordingly, the scope of the appended claims is intended to include such processes, machines, manufacture, compositions of matter, components, methods, or steps.

[0203] The above embodiments are provided to persons familiar with the art for implementing or using the present invention. Personnel familiar with the art may make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the scope of protection of the present invention is not limited to the above embodiments, but should be the maximum scope of the innovative features mentioned in the claims.

Claims

1. A process for preparing a ceramic plate for a three-dimensional packaging structure, characterized in that: At least the following steps are included: Design stacking structure and signal / power distribution scheme according to system integration requirements, determine process parameters and generate photolithography files; Prepare each layer of mask, and prepare photosensitive ceramic slurry and photosensitive conductive slurry; Spin-coat a photosensitive ceramic slurry on a silicon substrate, and then form a dielectric layer with a via structure by photolithography after baking and curing; Spin-coat a photosensitive conductive slurry, and then form a conductor layer by photolithography after baking and curing; Repeat this step to complete the stacking structure of all inner dielectric layers and conductor layers alternating; The entire laminated structure is sintered and solidified at high temperature, the silicon base plate is separated and the surface of the ceramic plate is ground; Make circuits and pads on the top and bottom layers through redistribution layer technology; Surface treatment of the ceramic plate after wiring; The photosensitive ceramic slurry comprises ceramic powder, a photoinitiator, an ultraviolet light absorber and a sintering aid, and the photosensitive conductive slurry comprises silver powder, a photosensitive resin, a stabilizer and a dispersant.

2. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1, characterized in that: The steps of designing the stacking structure and signal / power distribution scheme according to the system integration requirements, determining the process parameters and generating the photolithography file further include: According to the number and type of chips and signal transmission requirements, design the signal channel and power supply merging plan, determine the stacking thickness, ceramic slurry ratio and dielectric thickness, and output the photolithography file.

3. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1, wherein: Before the step of preparing each layer of mask, the method further comprises: Perform manufacturability checks on Gerber files.

4. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1, wherein: The ceramic powder of the photosensitive ceramic slurry comprises at least one of barium calcium titanate, barium titanate, doped modified barium titanate, composite barium titanium zirconium, lead metaniobate, bismuth titanate, bismuth lead tantalate, and ferromagnetic magnet; The photoinitiator of the photosensitive ceramic slurry comprises at least one of an acrylic polymer and a photoreactive compound; The ultraviolet light absorber of the photosensitive ceramic slurry comprises a carbide ultraviolet light absorber; The sintering aid of the photosensitive ceramic slurry includes silicate glass powder.

5. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1 or claim 4, characterized in that: The photoinitiator of the photosensitive ceramic slurry comprises at least one of benzoin dimethyl ether, benzoin ethyl ether, benzophenone, 2,4,6-trimethylbenzoyl-diphenylphosphine oxide or triphenylsulfonium hexafluoroantimonate.

6. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1 or claim 4, characterized in that: The ultraviolet light absorber of the photosensitive ceramic slurry includes at least one of TiC, SiC or NBC.

7. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1 or claim 4, characterized in that: The sintering aid of the photosensitive ceramic slurry includes at least one of borosilicate glass, alkali metal silicate glass or lead silicate glass.

8. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1 or claim 4, characterized in that: The silver powder of the photosensitive conductive paste includes at least one of nano silver ions, silver powder or silver palladium paste.

9. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1 or claim 4, characterized in that: The photosensitive resin of the photosensitive conductive paste at least contains acrylic polymer.

10. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1 or claim 4, characterized in that: The photosensitive resin of the photosensitive conductive paste includes at least one of benzoin dimethyl ether, benzoin ethyl ether, benzophenone, 2,4,6-trimethylbenzoyl-diphenylphosphine oxide or triphenylsulfonium hexafluoroantimonate.

11. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1 or claim 4, characterized in that: The stabilizer of the photosensitive conductive paste comprises a benzophenone or benzotriazole ultraviolet absorber; The dispersant of the photosensitive conductive paste includes nano-barium sulfate or nano-calcium carbonate.

12. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1, wherein: The step of spin-coating a photosensitive ceramic slurry on a silicon substrate, and then photolithographically forming a dielectric layer having a via structure after baking and curing further includes: Select a silicon base plate as a temporary carrier substrate according to the product size; Spin-coat photosensitive ceramic slurry on the silicon substrate and control the equipment parameters to achieve the specified stacking thickness; Bake and solidify the spin-coated photosensitive ceramic slurry; Spin-coating photoresist on the cured ceramic slurry layer, and performing UV exposure using a pre-prepared mask to transfer the via pattern to the ceramic slurry layer; The via pattern is developed and etched to form a dielectric layer with a via structure.

13. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1, wherein: The step of spin-coating the photosensitive conductive paste, baking and curing it, and then photolithographically forming the conductor layer further comprises: Spin-coat the photosensitive conductive paste on the dielectric layer and control the equipment parameters to make the paste reach the specified stacking thickness; Bake and solidify the spin-coated photosensitive conductive paste; Spin-coat photoresist on the cured conductive paste layer, perform UV exposure using a pre-prepared mask, and transfer the pattern of the corresponding circuit layer to the conductive paste layer; The pattern corresponding to the circuit layer is developed and etched to form a conductor layer with the designed circuit pattern.

14. The process for preparing a ceramic plate for a three-dimensional packaging structure according to claim 1, wherein: The step of fabricating circuits and pads on the top and bottom layers by a redistribution layer process further includes: Coating photoresist on the top / bottom layer of the ceramic plate and performing exposure and development to form the pattern of the top / bottom layer; Metal electroplating is performed on the patterned area to form a top / bottom conductive layer; Remove the residual photoresist and etch away the metal in the non-graphic area, leaving the top / bottom layer of circuits and pads.

15. A three-dimensional packaging structure based on ceramics, characterized in that: At least include several chips, ceramic interposers, and ceramic glass substrates: The plurality of chips are mounted on the upper surface of the ceramic interposer; The ceramic interposer is located between the chip and the ceramic glass substrate and is used to realize signal interconnection between the chips; The ceramic glass substrate is arranged below the ceramic interposer and is electrically connected to the PCB board, and is used to fan out the chip interconnection signals to the PCB board.

16. The ceramic-based three-dimensional packaging structure according to claim 15, characterized in that: The plurality of chips are electrically connected to the ceramic interposer via controllably collapsed chip connection bumps; The ceramic glass substrate and the ceramic intermediate board are electrically connected via controllably collapsed chip connection bumps.

17. The ceramic-based three-dimensional packaging structure according to claim 15 or claim 16, characterized in that: The ceramic intermediate plate and / or ceramic glass plate is manufactured using the manufacturing process according to any one of claims 1 to 14.

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