Chip packaging processing method and chip packaging structure

Abstract

The invention provides a chip packaging processing method and a chip packaging structure. The method comprises the following steps: baking and dehumidifying a packaged chip; performing plasma treatment on the underfill surface of the dried chip, and forming a micro-nano structure and a chemical group which is easily combined with a low-surface-energy solution on the treated underfill surface; and coating a low-surface-energy solution on the underfill surface, and curing to form a moisture barrier layer. The chip packaging structure comprises a substrate and an underfill located on the upper surface of the substrate, and the underfill fills a gap between a silicon interposer and the substrate and makes contact with air on the outer side of a chip. A moisture barrier layer is formed on the surface of the underfill, and the moisture barrier layer is formed by performing plasma treatment on the surface of the underfill to form a chemical group which is easily combined with a low-surface-energy solution, coating the low-surface-energy solution and then curing the low-surface-energy solution. According to the invention, the moisture penetration resistance of the packaging interface can be improved, moisture absorption layering is avoided, and the yield and stability of the chip on board are ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging processing method and a chip packaging structure. Background Art

[0002] With the rapid development of heterogeneous integration technology, 2.5D / 3D packaging technologies, represented by CoWoS (Chip-on-Wafer-on-Substrate), have become the mainstream packaging solution for high-performance computing chips. CoWoS, which involves attaching chips on a wafer to a substrate, focuses on stacking different chips on a single silicon interposer, enabling efficient interconnection between multiple chips.

[0003] In the CoWoS chip packaging structure, the underfill material at the packaging interface between the chip and substrate typically uses resin as the matrix and silicon oxide as the filler. Due to its inherent chemical properties, the packaging interface has low resistance to moisture penetration and is prone to moisture absorption and delamination. The chip, underfill, and substrate are made of heterogeneous materials. The mismatch in thermomechanical properties between these heterogeneous materials can significantly increase stress at the packaging interface. After the packaged chip is unpacked, the expansion stress concentration effect caused by moisture diffusion under the coupled effect of moisture absorption and thermal reflow can cause delamination and cracking at the packaging interface, affecting the chip's board yield and stability. Summary of the Invention

[0004] The chip packaging processing method and chip packaging structure provided by the present invention can improve the moisture penetration resistance of the packaging interface, avoid moisture absorption and delamination, and thus ensure the chip board yield and stability.

[0005] In a first aspect, the present invention provides a chip packaging processing method, the method comprising:

[0006] Bake and dehumidify the packaged chips;

[0007] The underfill surface of the dried chip is subjected to plasma treatment, whereby the underfill surface is formed with micro-nano structures and chemical groups that are easily combined with low surface energy solutions;

[0008] A low surface energy solution is coated on the underfill surface and cured to form a moisture barrier layer.

[0009] Optionally, the underfill includes silicon oxide and epoxy resin, and the underfill surface of the dried chip is subjected to plasma treatment, and the micro-nano structure and chemical groups that are easily combined with low surface energy solutions are formed on the underfill surface after the treatment. The method includes: using a mixed gas of oxygen and argon, through the coordinated manner of argon ion physical bombardment and oxygen radical chemical etching, to form a micro-nano structure on the underfill surface, and forming silanol groups that are easily combined with low surface energy solutions on the silicon oxide surface in the underfill.

[0010] Optionally, coating the underfill surface with a low surface energy solution and curing the solution to form a moisture barrier layer comprises: spraying or dripping the underfill surface with the low surface energy solution and curing the solution in sections to form a moisture barrier layer.

[0011] Optionally, the segmented curing includes: volatilizing the low surface energy solution coated on the underfill surface, and forming a covalent bond between the low surface energy solution after solvent volatilization and the silanol groups formed on the underfill surface.

[0012] Optionally, the low surface energy solution is fluorosilane, fluorochlorosilane or silica sol solution.

[0013] Optionally, the solvent of the low surface energy solution includes anhydrous ethanol, isopropanol or n-butane.

[0014] Optionally, the surface energy of the moisture barrier layer is lower than 20 mJ / m² and the sliding angle is less than 10 degrees.

[0015] In a second aspect, the present invention provides a chip packaging structure obtained by the above method, wherein the chip packaging structure includes a substrate and an underfill located on the upper surface of the substrate, wherein the underfill fills the gap between the silicon interposer and the substrate and contacts the air outside the chip;

[0016] A moisture barrier layer is formed on the underfill surface. The moisture barrier layer is formed by plasma treating the underfill surface to form chemical groups that are easily combined with a low surface energy solution, coating the low surface energy solution, and then curing the solution.

[0017] Optionally, the chip includes a silicon interposer, and the silicon interposer is located above the underfill on the upper surface of the substrate.

[0018] Optionally, the low surface energy solution is fluorosilane, fluorochlorosilane or silica sol solution.

[0019] Optionally, the surface energy of the moisture barrier layer is lower than 20 mJ / m² and the sliding angle is less than 10 degrees.

[0020] The chip packaging processing method and chip packaging structure provided by the embodiments of the present invention perform plasma treatment on the underfill surface to form a micro-nano structure, which can achieve a moisture barrier effect from a physical structure perspective; the underfill surface is plasma treated to form chemical groups that are easily combined with a low surface energy solution, and the low surface energy solution is coated on the underfill surface and cured to form a moisture barrier layer, which can achieve a hydrophobic passivation effect from a chemical property perspective; the main formula of the underfill material after treatment does not change, and the nano-scale thickening of the underfill material does not change its own structure and bring about the risk of stress concentration, thereby improving the moisture penetration resistance of the packaging interface through the synergistic effect of micro-nano structure regulation and low surface energy materials, avoiding moisture absorption and delamination of the chip after unpacking, and ensuring the chip boarding yield and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of a chip packaging method according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic structural diagram of a chip packaging structure according to an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of changes in the underfill surface during the process of plasma treatment and formation of a moisture barrier layer provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0025] The embodiment of the present invention provides a chip packaging processing method, such as Figure 1 As shown, the method includes:

[0026] S11, baking and dehumidifying the packaged chips.

[0027] Specifically, after the chip is packaged, it is baked to remove moisture to prevent internal moisture from being removed. For example, the packaged chip can be baked at a temperature of 125 degrees Celsius for 24 hours.

[0028] S12, performing plasma treatment on the underfill surface of the dried chip, so that a micro-nano structure and chemical groups that are easily combined with a low surface energy solution are formed on the underfill surface after the treatment.

[0029] Specifically, the bottom filler uses resin as a matrix and silicon oxide as a filler; Figure 3 As shown, plasma etching (Plasma Etch) is performed on the bottom fill surface of the dried chip. A mixed gas of oxygen and argon can be used to form a micro-nano structure on the bottom fill surface through the physical bombardment of argon ions and the coordinated chemical etching of oxygen free radicals. Figure 3 As shown in the middle box, the arithmetic average roughness (Ra) of the underfill surface reaches hundreds of nanometers, and silanol groups that are easily combined with low surface energy solutions are formed on the micron-sized silicon oxide surface in the underfill.

[0030] Optionally, the low surface energy solution may be fluorosilane, fluorochlorosilane or silica sol solution, but is not limited thereto.

[0031] Optionally, the solvent of the low surface energy solution may be anhydrous ethanol, isopropanol or n-butane, but is not limited thereto. Ammonia water may also be added to promote the hydrolysis reaction of silane to form free silicon-oxygen bonds.

[0032] S13, coating a low surface energy solution on the underfill surface and curing the solution to form a moisture barrier layer.

[0033] Specifically, if Figure 3 As shown, the underfill surface after the treatment in step S12 is subjected to hydrophobic treatment (Hydrophobic treatment); the underfill surface is covered with a low surface energy solution by spraying or dripping, and is cured in stages to form a moisture barrier layer.

[0034] Specifically, during the staged curing, first, the low surface energy solution coated on the underfill surface is evaporated; then, the low surface energy solution after the solvent evaporation is covalently bonded to the silanol groups formed on the underfill surface, specifically as follows: Figure 3 Shown in the rightmost box.

[0035] Optionally, the surface energy of the moisture barrier layer is lower than 20 mJ / m² and the sliding angle is less than 10 degrees, but is not limited thereto.

[0036] The chip packaging processing method provided by the embodiment of the present invention performs plasma treatment on the underfill surface to form a micro-nano structure, which can achieve a moisture barrier effect from a physical structure perspective; plasma treatment is performed on the underfill surface to form chemical groups that are easily combined with a low surface energy solution, and the low surface energy solution is coated on the underfill surface and cured to form a moisture barrier layer, which can achieve a hydrophobic passivation effect from a chemical property perspective; the main formula of the underfill material after treatment does not change, and the nano-scale thickening of the underfill material does not change its own structure and bring about the risk of stress concentration, thereby improving the moisture penetration resistance of the packaging interface through the synergistic effect of micro-nano structure regulation and low surface energy materials, avoiding moisture absorption and delamination of the chip after unpacking, and ensuring the chip boarding yield and stability.

[0037] An embodiment of the present invention further provides a chip packaging structure obtained by the above method, wherein the chip packaging structure includes a substrate and an underfill located on the upper surface of the substrate, wherein the underfill fills the gap between the silicon interposer and the substrate and contacts the air outside the chip.

[0038] A moisture barrier layer is formed on the underfill surface. The moisture barrier layer is formed by plasma treating the underfill surface to form chemical groups that are easily combined with a low surface energy solution, coating the low surface energy solution, and then curing the solution.

[0039] Optionally, the chip includes a silicon interposer, and the silicon interposer is located above the underfill on the upper surface of the substrate.

[0040] Optionally, the low surface energy solution may be fluorosilane, fluorochlorosilane or silica sol solution, but is not limited thereto.

[0041] Optionally, the solvent of the low surface energy solution may be anhydrous ethanol, isopropanol or n-butane, but is not limited thereto. Ammonia water may also be added to promote the hydrolysis reaction of silane to form free silicon-oxygen bonds.

[0042] Optionally, the surface energy of the moisture barrier layer is lower than 20 mJ / m² and the sliding angle is less than 10 degrees, but is not limited thereto.

[0043] Specifically, if Figure 2 As shown, the chip packaging structure may include a ball grid array 101 arranged from bottom to top, a substrate 102, bumps 110 connecting CoW (Chip-on-Wafer) dies (i.e., dies cut after wafer-level packaging) and the substrate 102, a second underfill 111 located between the bumps 110 and the substrate 102, and the CoW dies;

[0044] The CoW die, also known as the chip described above, includes a silicon interposer 109, a micro-bump connection structure 108, and a top die 106 arranged from bottom to top, and a first underfill 107 is provided between the silicon interposer 109 and the top die 106;

[0045] The silicon interposer 109 can realize signal transmission between the top die 106 and the substrate 102 through silicon vias;

[0046] Optionally, the gaps between the top dies 106 are filled with molding compound 112 ;

[0047] Optionally, the chip packaging structure further includes a passive component 105 located at the periphery of the CoW die, and the passive component 105 is soldered to the substrate 102 via solder paste;

[0048] Optionally, a reinforcing rib 104 for fixing to the substrate 102 is further provided on the upper surface of the substrate 102 and around the passive component 105. The reinforcing rib 104 is fixedly connected to the substrate 102 via a black glue 103. The reinforcing rib is formed by integral stamping or milling, and the material may be copper or stainless steel, but is not limited thereto.

[0049] Alternatively, as Figure 2 As shown in the enlarged corner diagram in FIG, a passivation layer 113 with a thickness of micrometer level is further provided between the second underfill 111 and the interposer 109. The material of the passivation layer 113 may be silicon oxide or silicon nitride.

[0050] like Figure 2 As shown in the enlarged corner view in FIG, the second underfill 111 includes a resin matrix 115 and a silicon oxide filler 114, and a moisture barrier layer 116 is formed on the exposed surface of the second underfill 111.

[0051] In the chip packaging structure provided by the embodiment of the present invention, a micro-nano structure is formed on the underfill surface through plasma treatment, which can achieve a moisture barrier effect from a physical structure perspective; chemical groups that are easily combined with a low surface energy solution are formed on the underfill surface through plasma treatment, and a moisture barrier layer is formed after the low surface energy solution is coated and cured, which can achieve a hydrophobic passivation effect from a chemical property perspective; the main formula of the underfill material after treatment does not change, and the nano-scale thickening of the underfill material does not change its own structure and bring about the risk of stress concentration, thereby improving the moisture penetration resistance of the packaging interface through the synergistic effect of micro-nano structure regulation and low surface energy materials, avoiding moisture absorption and delamination of the chip after unpacking, and ensuring the chip boarding yield and stability.

[0052] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A chip packaging method, characterized in that: The method comprises: Bake and dehumidify the packaged chips; The underfill surface of the dried chip is subjected to plasma treatment, whereby the underfill surface is formed with micro-nano structures and chemical groups that are easily combined with low surface energy solutions; A low surface energy solution is coated on the underfill surface and cured to form a moisture barrier layer.

2. The method according to claim 1, characterized in that The underfill includes silicon oxide and epoxy resin. The underfill surface of the dried chip is subjected to plasma treatment. The micro-nano structure and chemical groups that are easily combined with low surface energy solutions are formed on the underfill surface after the treatment. The method includes: using a mixed gas of oxygen and argon, through argon ion physical bombardment and oxygen radical chemical etching in a coordinated manner, to form the micro-nano structure on the underfill surface, and to form silanol groups that are easily combined with low surface energy solutions on the silicon oxide surface in the underfill.

3. The method according to claim 2, characterized in that The method of coating the underfill surface with a low surface energy solution and curing the solution to form a moisture barrier layer includes: spraying or dripping the underfill surface with the low surface energy solution and curing the solution in sections to form a moisture barrier layer.

4. The method according to claim 3, characterized in that The segmented curing includes: volatilizing the solvent of the low surface energy solution coated on the underfill surface, and forming a covalent bond between the low surface energy solution after solvent volatilization and the silanol groups formed on the underfill surface.

5. The method according to any one of claims 1 to 4, characterized in that The low surface energy solution is fluorosilane, fluorochlorosilane or silica sol solution.

6. The method according to claim 5, characterized in that The solvent of the low surface energy solution includes anhydrous ethanol, isopropanol or n-butane.

7. The method according to any one of claims 1 to 4, characterized in that The surface energy of the moisture barrier layer is lower than 20 mJ / m² and the sliding angle is less than 10 degrees.

8. A chip packaging structure obtained by the method according to any one of claims 1 to 7, characterized in that: The chip packaging structure includes a substrate and an underfill located on the upper surface of the substrate, wherein the underfill fills the gap between the silicon interposer and the substrate and contacts the air outside the chip; A moisture barrier layer is formed on the underfill surface. The moisture barrier layer is formed by plasma treating the underfill surface to form chemical groups that are easily combined with a low surface energy solution, coating the low surface energy solution, and then curing the solution.

9. The chip packaging structure according to claim 8, wherein: The chip includes a silicon interposer located above the underfill on the upper surface of the substrate.

10. The chip packaging structure according to claim 8, wherein: The low surface energy solution is fluorosilane, fluorochlorosilane or silica sol solution.

11. The chip packaging structure according to claim 8 or 10, characterized in that: The surface energy of the moisture barrier layer is lower than 20 mJ / m² and the sliding angle is less than 10 degrees.

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