Formation method of semiconductor structure
By first increasing the actual feature size of the discrete pattern and performing difference correction during the semiconductor structure formation process, the problem of large pattern size fluctuation after wet etching is solved, higher dimensional accuracy and consistency are achieved, and production efficiency and yield are improved.
Patent Information
- Application Number
- CN202410303288.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-15
- Publication Date
- 2025-09-23
AI Technical Summary
During the semiconductor structure formation process, the pattern size formed after wet etching fluctuates greatly, resulting in a decrease in the wafer release rate, affecting production efficiency and cost.
A semiconductor structure is formed by forming a discrete pattern on a substrate whose actual feature size is larger than the standard feature size, and performing at least one round of removal process by measuring the difference until the difference between the actual feature size and the standard feature size is less than or equal to a preset value.
It improves the dimensional accuracy and consistency of discrete patterns, enhances the process window, reduces R&D complexity, and improves production efficiency and yield.
Smart Images
Figure CN120690701A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art
[0002] With the rapid development of semiconductor technology, chip integration has continued to increase, making chip manufacturing processes increasingly complex and the process window increasingly narrow. To improve yield, the requirements for the entire chip processing process and equipment will become more stringent, and the requirements for the fluctuation range of pattern dimensions will also become increasingly stringent.
[0003] In a semiconductor structure formation process, the pattern formed after wet etching has large dimensional fluctuations, resulting in a reduced wafer release rate, affecting production efficiency and production costs, and even causing yield loss.
[0004] There is an urgent need for a method for forming a semiconductor structure that can improve the accuracy and consistency of the dimensions of discrete patterns. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can improve the accuracy and consistency of the size of the obtained discrete patterns by adding a second wet etching.
[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, forming a discrete pattern on the substrate, the actual feature size of the discrete pattern being larger than the standard feature size, the standard feature size being the size of the discrete pattern that meets the standard value of the standard process specification; measuring the actual feature size of the discrete pattern, and obtaining the difference between the actual feature size and the standard feature size; in response to a first difference between the actual feature size and the standard feature size being larger than a preset value, performing at least one round of removal process on the discrete pattern until the first difference between the actual feature size and the standard feature size is less than or equal to the preset value; and forming the semiconductor structure according to the discrete pattern.
[0007] Optionally, before forming the discrete patterns on the substrate, the method further comprises: forming an initial discrete pattern on the substrate; and performing wet cleaning on the initial discrete pattern to obtain the discrete pattern.
[0008] Optionally, the discrete patterns are removed in two or more rounds; wherein the removal time in the second round of removal process is 30% to 100% of the removal time in the first round of removal process.
[0009] Optionally, the removal time in each round of the removal process is 30% to 100% of the removal time in the previous round of the removal process.
[0010] Optionally, the removal duration in each removal process starting from the second removal process remains consistent.
[0011] Optionally, the initial discrete pattern is wet cleaned using a first cleaning process parameter, and the first cleaning process parameter includes a cleaning time; the discrete pattern is removed for at least one round using a first removal process parameter, and the first removal process parameter includes a removal time; wherein the other cleaning process parameters in the first cleaning process parameter except the cleaning time are consistent with the parameters and parameter values of the other removal process parameters in the first removal process parameter except the removal time.
[0012] Optionally, an initial discrete pattern is formed on the substrate, comprising: forming a layer to be patterned on the substrate, and forming a second sidewall on the layer to be patterned; etching the layer to be patterned using the second sidewall as a mask to form a plurality of the initial discrete patterns on the layer to be patterned; wherein, the etching process parameters for etching the layer to be patterned are adjusted so that the actual feature size of the initial discrete pattern is larger than a second standard feature size, and the second standard feature size is the size of the initial discrete pattern that meets the standard value of the standard process specification.
[0013] Optionally, a first core shaft layer is formed on the layer to be patterned; the forming of the second side wall on the layer to be patterned also includes: etching the first core shaft layer on the substrate to form a plurality of first core shafts with a predetermined interval, forming a first side wall on both sides of the first core shaft, and then removing the first core shaft, wherein the substrate includes a layer to be patterned, a second core shaft layer and the first core shaft layer stacked in sequence; using the first side wall as a mask, etching the second core shaft layer to form a plurality of second core shafts; forming the second side wall covering both sides of the second core shaft, removing the second core shaft, and obtaining the second side wall.
[0014] Optionally, the etching process parameter of the layer to be patterned is the etching time or etching rate of the layer to be patterned.
[0015] Optionally, forming the semiconductor structure according to the discrete pattern includes: forming a deposition layer on the sidewall of the discrete pattern; removing the discrete pattern and retaining the deposition layer located on the sidewall of the discrete pattern; and etching the substrate using the retained deposition layer as a mask to obtain a gate trench.
[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0017] In an embodiment of the present invention, by forming discrete patterns with actual feature sizes larger than the standard feature sizes, the size of the discrete patterns can be increased before performing at least one round of removal on the discrete patterns, thereby providing a larger process window for subsequent additional removal steps. Furthermore, after the first round of removal, the larger discrete patterns can be removed again until the first difference between the actual feature size and the standard feature size is less than or equal to the preset value. This allows for improved accuracy and consistency in the size of the resulting discrete patterns through additional removal steps. Furthermore, by first increasing the size of the discrete patterns and then performing removal to reduce their size, the discrete patterns can be effectively protected even when their feature sizes are relatively small.
[0018] Furthermore, by first forming an initial discrete pattern on the substrate and then wet cleaning the initial discrete pattern to obtain the discrete pattern, the accuracy of the size of the discrete pattern can be improved. For products that already have a wet cleaning process, the existing mature process can be reused to reduce the complexity of research and development.
[0019] Furthermore, the discrete pattern is removed in two or more rounds; wherein, the removal time in the second round of removal process is 30% to 100% of the removal time in the first round of removal process, thereby enhancing the protection of the discrete pattern by reducing the removal time after the first round of removal process.
[0020] Furthermore, the removal time in each round of the removal process is 30% to 100% of the removal time in the previous round of the removal process. Therefore, by reducing the removal time in each round, the protection of the discrete patterns can be further enhanced while improving the fineness of the removal process in each round.
[0021] Furthermore, the removal time in each round of removal process starting from the second round of removal process remains consistent, so that starting from the second round of removal process, by adopting a consistent removal time, the protection of the discrete patterns can be further enhanced while improving the controllability of the round-by-round removal process.
[0022] Furthermore, the parameters and parameter values of the other cleaning process parameters except the cleaning time in the first cleaning process parameters are consistent with the parameters and parameter values of the other removal process parameters except the removal time in the first removal process parameters. Therefore, for products with existing wet cleaning processes, other parameters of existing mature processes can be reused, further reducing the complexity of research and development.
[0023] Furthermore, forming initial discrete patterns on the substrate includes: forming a layer to be patterned on the substrate, forming a second sidewall spacer on the layer to be patterned; etching the layer to be patterned using the second sidewall spacer as a mask to form a plurality of the initial discrete patterns on the layer to be patterned; wherein the etching process parameters for etching the layer to be patterned are adjusted so that the actual feature size of the initial discrete patterns is larger than a second standard feature size, where the second standard feature size is the size of the initial discrete patterns that meets the standard process specifications. Using the above solution, only the etching process parameters of the layer to be patterned with the second sidewall spacer can be adjusted, while the process parameters for forming the second sidewall spacer and the process parameters of the previous process are maintained, thereby improving process consistency and reusability.
[0024] Furthermore, the etching process parameters of the layer to be patterned are the etching time or etching rate of the layer to be patterned, thereby improving the controllability of the etching process of the layer to be patterned by utilizing the characteristics that the longer the etching time or the greater the etching rate, the greater the removal degree, and the shorter the etching time or the smaller the etching rate, the smaller the removal degree.
[0025] Furthermore, forming the semiconductor structure based on the discrete patterns includes: forming a deposition layer on the sidewalls of the discrete patterns; removing the discrete patterns while retaining the deposition layer on the sidewalls of the discrete patterns; and etching the substrate using the retained deposition layer as a mask to form a gate trench. Using this approach, a deposition layer can be formed on the sidewalls, and after removing the discrete patterns, the deposition layer on the sidewalls of the discrete patterns is retained, thereby forming a gate trench. The embodiments of the present invention help utilize the higher dimensional accuracy and consistency of the discrete patterns to further improve the refinement of the gate trench. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention;
[0027] Figure 2 is a partial flow diagram of another method for forming a semiconductor structure according to an embodiment of the present invention;
[0028] Figure 3 Schematic diagram of the positional relationship of various layers of a semiconductor structure in an embodiment of the present invention;
[0029] Figure 4 It is a schematic diagram of a partial process flow of a method for forming a semiconductor structure according to an embodiment of the present invention;
[0030] Figures 5 to 11 It is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.
[0031] Description of reference numerals:
[0032] Substrate 10, first dielectric layer 11, layer to be patterned 12, initial discrete pattern 121, discrete pattern 1211, second dielectric layer 131, second mandrel layer 122, second mandrel 1221, third dielectric layer 132, first mandrel 14, mask layer 15, first silicon nitride layer 16, first sidewall spacer 161, second silicon nitride layer 17, second sidewall spacer 171, deposition layer 18. DETAILED DESCRIPTION
[0033] As previously mentioned, chip manufacturing processes are becoming increasingly complex, with shrinking process windows and increasingly stringent requirements for pattern size fluctuations. In one semiconductor structure formation process, the pattern formed after wet etching exhibits significant dimensional fluctuations, resulting in a decrease in wafer release rates, impacting production efficiency and costs, and even resulting in yield losses.
[0034] After research, it was found that in the existing wet etching process, due to the narrow process window, there are often problems of over-etching or under-etching. Over-etching will lead to an increase in the proportion of waste films, and under-etching will also lead to increased process costs.
[0035] In an existing improvement scheme, a monitor wafer can be used to perform one or more try-runs before the wet etching process is implemented on the product. However, as the process complexity increases, the monitor wafer cannot fully reflect the etching parameters and etching environment of the product, resulting in an increase in the failure rate of the above method.
[0036] In an embodiment of the present invention, by forming discrete patterns with actual feature sizes larger than the standard feature sizes, the size of the discrete patterns can be increased before performing at least one round of removal on the discrete patterns, providing a larger process window for subsequent additional removal steps. Furthermore, after the first round of removal, the larger discrete patterns can be removed again until the first difference between the actual feature size and the standard feature size is less than or equal to the preset value. This allows for improved accuracy and consistency in the size of the resulting discrete patterns through additional removal steps. Furthermore, by first increasing the size of the discrete patterns and then performing removal to reduce their size, the discrete patterns can be effectively protected even when their feature sizes are relatively small.
[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0038] Reference Figure 1 , Figure 11 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention. The method may include steps S11 to S14:
[0039] Step S11: providing a substrate, and forming a discrete pattern on the substrate, wherein the actual feature size of the discrete pattern is larger than the standard feature size, and the standard feature size is the size of the discrete pattern that meets the standard value of the standard process specification;
[0040] Step S12: measuring the actual characteristic size of the discrete pattern, and obtaining the difference between the actual characteristic size and the standard characteristic size;
[0041] Step S13: in response to a first difference between the actual feature size and the standard feature size being greater than a preset value, performing at least one round of removal process on the discrete pattern until the first difference between the actual feature size and the standard feature size is less than or equal to the preset value;
[0042] Step S14: forming the semiconductor structure according to the discrete patterns.
[0043] In the specific implementation of step S11, the substrate may include a semiconductor substrate, and may also include a structure formed on the surface of the semiconductor substrate, and is not limited to the portion within the surface of the semiconductor substrate.
[0044] The semiconductor substrate may be a silicon substrate, or the material of the semiconductor substrate may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate on which an epitaxial layer (Epi layer) is grown.
[0045] The actual feature size of the discrete pattern is larger than the standard feature size, where the standard feature size is the size of the discrete pattern that meets the standard value of the standard process specification.
[0046] The characteristic dimension can be used to represent a specific dimension of the initial discrete pattern to indicate the size of the initial discrete pattern. For example, it can be a critical dimension (CD).
[0047] For simple patterns, such as rectangles and strips, the width or length of the pattern can be used as the characteristic dimension, or the distance between adjacent patterns can be used as the characteristic dimension. For complex patterns, such as comb-shaped, cross-shaped, F-shaped, and T-shaped patterns, the position for measurement can be set in advance, and a simple measurement pattern that can reflect the characteristics of the original pattern can be set to measure its characteristic dimension.
[0048] In the embodiment of the present invention, by forming a discrete pattern with an actual feature size larger than a standard feature size, the size of the discrete pattern can be increased before the first round of removal of the discrete pattern is performed.
[0049] Furthermore, the portion by which the actual feature size is increased compared to the standard feature size may be determined according to a standard discrete pattern formed in advance using a standard process.
[0050] It should be noted that a preset fixed value may also be used as the increase ratio of the actual feature size compared to the standard feature size.
[0051] Furthermore, before forming the discrete patterns on the substrate, the method may further include: forming an initial discrete pattern on the substrate; and performing wet cleaning on the initial discrete pattern to obtain the discrete pattern.
[0052] Reference Figure 2 , Figure 2 FIG. 1 is a partial flow diagram of another method for forming a semiconductor structure according to an embodiment of the present invention. The method for forming another semiconductor structure may include steps S21 to S22, wherein steps S21 to S22 may be performed in Figure 1 Before step S11 shown in FIG.
[0053] In step S21 , an initial discrete pattern is formed on the substrate.
[0054] In a first embodiment, the initial discrete pattern may be a standard discrete pattern formed using a standard process.
[0055] In a second specific embodiment, the initial discrete patterns can have pattern sizes that are larger than the sizes of the standard discrete patterns.
[0056] In step S22 , the initial discrete patterns are wet cleaned to obtain the discrete patterns.
[0057] In the first specific embodiment, the initial discrete pattern may be a standard discrete pattern formed by a standard process, and the discrete pattern is obtained by performing a wet cleaning process with a shorter cleaning time or lower cleaning efficiency on the initial discrete pattern.
[0058] In the second specific embodiment, the initial discrete pattern may have a pattern size larger than that of the standard discrete pattern, and the discrete pattern is obtained by a standard wet cleaning process.
[0059] In an embodiment of the present invention, by first forming an initial discrete pattern on a substrate and then wet cleaning the initial discrete pattern to obtain the discrete pattern, the accuracy of the size of the discrete pattern can be improved. For products that already have a wet cleaning process, the existing mature process can be reused to reduce the complexity of research and development.
[0060] Continue to refer to Figure 1 In the specific implementation of step S12, the actual characteristic size of the discrete pattern is measured to obtain the difference between the actual characteristic size and the standard characteristic size.
[0061] In a specific implementation, a conventional measurement method and a measurement machine may be used to measure the actual characteristic size of the discrete pattern, and the embodiment of the present invention does not impose any limitation on this.
[0062] In a specific implementation of step S13 , when a first difference between the actual feature size and the standard feature size is greater than a preset value, at least one round of removal process is performed on the discrete pattern.
[0063] Furthermore, the discrete patterns may be subjected to two or more rounds of removal, wherein the removal time in the second round of removal process is 30% to 100% of the removal time in the first round of removal process.
[0064] In an embodiment of the present invention, the removal time in the second round of removal process is 30% to 100% of the removal time in the first round of removal process. Therefore, after the first round of removal process, the protection of the discrete pattern can be enhanced by reducing the removal time, thereby avoiding the discrete pattern being too small in size due to excessive removal.
[0065] Furthermore, the removal time in each round of the removal process may be 30% to 100% of the removal time in the previous round of the removal process.
[0066] In a specific implementation, the removal time of the second removal process can be 30% to 100% of the removal time of the first removal process, the removal time of the third removal process can be 30% to 100% of the removal time of the second removal process, and so on.
[0067] In an embodiment of the present invention, the removal time in each round of the removal process is 30% to 100% of the removal time in the previous round of the removal process. Therefore, by reducing the removal time in each round, the protection of the discrete patterns can be further enhanced while improving the fineness of the removal process in each round.
[0068] Furthermore, the removal time in each removal process from the second removal process onwards remains consistent.
[0069] In a specific implementation, the removal time of the second round of removal process can be 30% to 100% of the removal time of the first round of removal process, and the removal time of the third round of removal process, the removal time of the fourth round of removal process,... the removal time of the last round of removal process can all be consistent with the removal time of the second round of removal process.
[0070] In an embodiment of the present invention, the removal duration in each round of removal process starting from the second round of removal process remains consistent, so that starting from the second round of removal process, by adopting a consistent removal duration, the protection of discrete patterns can be further enhanced while improving the controllability of the round-by-round removal process.
[0071] Furthermore, the initial discrete pattern is wet cleaned using a first cleaning process parameter, and the first cleaning process parameter includes a cleaning time; the discrete pattern is removed for at least one round using a first removal process parameter, and the first removal process parameter includes a removal time; wherein the other cleaning process parameters in the first cleaning process parameter except the cleaning time are consistent with the parameters and parameter values of the other removal process parameters in the first removal process parameter except the removal time.
[0072] Specifically, in the wet cleaning step described above and in step S22, a variety of cleaning process parameters can be used, including the cleaning time. In the removal process step described in step S13, a variety of removal process parameters can be used, including the removal time. In a specific implementation, except for the cleaning time and the removal time, the parameter values of the other cleaning process parameters and the parameter values of the other removal process parameters can be consistent.
[0073] In an embodiment of the present invention, the other cleaning process parameters except the cleaning time in the first cleaning process parameters are consistent with the parameters and parameter values of the other removal process parameters except the removal time in the first removal process parameters. Therefore, for products with existing wet cleaning processes, other parameters of existing mature processes can be reused to further reduce process complexity.
[0074] Reference Figure 3 , Figure 3 It is a schematic diagram of the positional relationship of various layers of structures in a semiconductor structure according to an embodiment of the present invention.
[0075] The initial discrete pattern in the semiconductor structure may be a self-aligned quadruple patterning (SAQP) pattern, or other appropriate patterns.
[0076] Specifically, in the SAQP process, as the line width becomes smaller and smaller, the etching load effect becomes more and more obvious, and it is necessary to measure one or more feature dimensions of the obtained pattern after each etching process, such as Figure 3 CD1 shown can be used to represent the first mandrel feature size, that is, the pattern width of the first mandrel, CD2 can be used to represent the second mandrel feature size, that is, the pattern width of the second mandrel, and CD3 can be used to represent the initial discrete pattern feature size, that is, the pattern width of the initial discrete pattern.
[0077] α, γ, and β represent the pitch characteristic size between the initial discrete patterns, that is, the spacing between adjacent initial discrete patterns. Their size directly affects the etch depth of the initial discrete patterns (such as the fins). For example, the smaller α, γ, and β are, the smaller the etch depth is, which is prone to low yield issues due to a narrow process window.
[0078] It should be pointed out that α, γ, and β are formed based on different steps, among which γ is obtained by using the second sidewall as a mask to etch the layer to be patterned. Since this process is ranked later, it has the largest fluctuation among α, γ, and β.
[0079] In an embodiment of the present invention, the etching process parameters for etching the layer to be patterned are adjusted so that the actual feature size of the initial discrete pattern is larger than the preset feature size process specification standard value. Only the etching process parameters of the last layer of the self-aligned quadruple imaging process can be adjusted, and the process parameters of the previous process can be maintained to improve the consistency and reusability of the process.
[0080] Combined with reference Figures 4 to 11 , Figure 4 FIG. 1 is a schematic diagram of a partial process flow of a method for forming a semiconductor structure according to an embodiment of the present invention. Figures 5 to 11 It is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.
[0081] The method for forming a semiconductor structure may include steps S401 to S409 , each of which is described below.
[0082] It should be pointed out that Figures 5 to 9 The content shown may correspond to Figure 4 Steps S401 to S404 are shown. Figures 10 and 11 The content shown may correspond to Figure 4 Step S409 is shown.
[0083] Step S401: etching a first mandrel layer on the substrate to form a plurality of first mandrels with a predetermined interval, forming first sidewalls on both sides of the first mandrels, and then removing the first mandrels;
[0084] Step S402: using the first sidewall spacer as a mask, etching the second mandrel layer to form a plurality of second mandrels;
[0085] Step S403: forming the second sidewalls covering both sides of the second mandrel, and removing the second mandrel to obtain the second sidewalls;
[0086] Step S404 : using the second sidewall spacer as a mask, etching the layer to be patterned to form a plurality of the initial discrete patterns on the layer to be patterned.
[0087] The following combination Figures 5 to 9 Steps S401 to S404 are described.
[0088] Reference Figure 5 , a substrate 10 can be provided, wherein the substrate 10 includes a layer to be patterned 12, a second mandrel layer 122 and the first mandrel layer (not shown) stacked in sequence.
[0089] A patterned mask layer 15 may be formed on the first mandrel layer, and the first mandrel layer is etched according to the patterned mask layer 15 to form the first mandrels 14 .
[0090] Furthermore, the substrate 10 may further include a first dielectric layer 11, and the layer to be patterned 12 is formed on the first dielectric layer 11. A second dielectric layer 131 may be formed between the layer to be patterned 12 and the second mandrel layer 122, and a third dielectric layer 132 may be formed between the second mandrel layer 122 and the first mandrel layer.
[0091] The first dielectric layer 11 may be a dielectric layer, or may be formed by stacking multiple dielectric layers. The dielectric layer may be made of silicon oxide (SiO2) or silicon nitride (Si3N4).
[0092] The material of the second dielectric layer 131 and the third dielectric layer 132 may be silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ).
[0093] The patterned mask layer 15 is used as a mask to etch the first mandrel layer on the substrate 10 to form a plurality of first mandrels 14 with predetermined intervals.
[0094] It should be pointed out that in the process of forming the first core shaft 14, amorphous silicon (A-Si) material can be used to form the first core shaft 14. Since amorphous silicon (A-Si) material is very easy to oxidize, resulting in increased thickness, it will affect the accuracy of the patterns of each layer formed subsequently.
[0095] Reference Figure 6 , remove the patterned mask layer 15 (refer to Figure 5 ), and then depositing a first silicon nitride layer 16 on the first mandrel 14.
[0096] The first silicon nitride layer 16 includes first sidewall spacers 161 deposited on both sides of the first core shaft 14 , and the first silicon nitride layer 16 also includes portions located on the top surface of the first core shaft 14 and the surface of the third dielectric layer 132 .
[0097] Reference Figure 7 , remove the first mandrel 14 and retain the first sidewall 161 formed on the side of the first mandrel 14 , and use the first sidewall 161 as a mask to etch the second mandrel layer 122 to form a plurality of second mandrels 1221 .
[0098] While the first mandrels 14 are being etched, the first silicon nitride layer 16 located on the top surface of the first mandrels 14 and the surface of the third dielectric layer 132 is also being etched, leaving only the first sidewall spacers 161 .
[0099] The first sidewalls 161 are located on both sides of the first core shaft 14 .
[0100] It should be noted that, in the case where the third dielectric layer 132 is formed, the third dielectric layer 132 and the second mandrel layer 122 are sequentially etched using the first sidewall spacer 161 as a mask.
[0101] Reference Figure 8 , remove the first sidewall 161 and the third dielectric layer 132 (refer to Figure 7 ), and then forming a second silicon nitride layer 17 on the second core shaft 1221.
[0102] The second silicon nitride layer 17 includes second sidewalls 171 formed on both sides of the second core shaft 1221 , and also includes portions located on the top surface of the second core shaft 1221 and the surface of the second dielectric layer 131 .
[0103] Reference Figure 9 The second mandrel 1221 is removed to obtain the second sidewall spacer 171. The layer to be patterned 12 is etched using the second sidewall spacer 171 as a mask to form a plurality of initial discrete patterns 121 on the layer to be patterned 12.
[0104] While etching the second mandrel 1221 , the second silicon nitride layer 17 located on the top surface of the second mandrel 1221 and the surface of the second dielectric layer 131 is also etched, leaving only the second sidewall spacer 171 .
[0105] Furthermore, the etching process parameter of the layer to be patterned is the etching time or etching rate of the layer to be patterned.
[0106] The etching amount may be equal to the product of the etching time and the etching rate. Furthermore, the etching process of the layer to be patterned is dry etching.
[0107] In a specific implementation, other parameters such as etching temperature, etching angle, and chamber pressure of the etching chamber may be used to adjust the etching process.
[0108] Since the etching time has a better linear relationship with the size of the obtained pattern than other etching process parameters, the technical solution of adjusting the etching time can more accurately enlarge and adjust the size of the initial discrete pattern.
[0109] In an embodiment of the present invention, the etching process parameters of the layer to be patterned are the etching time or etching rate of the layer to be patterned, so that the controllability of the etching process of the layer to be patterned can be improved by utilizing the characteristics that the longer the etching time or the greater the etching rate, the greater the removal degree, and the shorter the etching time or the smaller the etching rate, the smaller the removal degree.
[0110] Continue to refer to Figure 4 In step S405, the initial discrete pattern may be wet cleaned to obtain the discrete pattern.
[0111] For more information on wet cleaning, please refer to the previous article and Figure 2 The description of step S22 is shown and will not be repeated here.
[0112] In step S406 , the actual feature size of the obtained discrete patterns is measured.
[0113] Among them, Figures 5 to 11 In the illustrated embodiment, the dimension may be the width in the direction in which the discrete patterns are arranged.
[0114] For more information on actual feature sizes, see the previous article and Figure 2 The description of step S12 is shown and will not be repeated here.
[0115] In step S407 , it is determined whether the first difference between the actual characteristic size and the standard characteristic size is greater than a preset value. If the determination result is yes, the process proceeds to step S408 , otherwise, the process proceeds to step S409 .
[0116] In step S408 , a removal process is performed on the discrete patterns.
[0117] For more details about steps S407 to S408, please refer to the previous text and Figure 1 The description shown is performed and will not be repeated here.
[0118] In step S409 , the semiconductor structure is formed according to the discrete patterns.
[0119] The following combination Figures 10 and 11 , step S409 is explained.
[0120] Reference Figure 10 , a deposition layer 18 is formed on the sidewalls of the discrete pattern 1211 .
[0121] Part of the deposition layer 18 covers the sidewalls of the discrete pattern 1211 , and another part may cover the top surface of the discrete pattern 1211 and the substrate 10 , for example, formed on the first dielectric layer 11 .
[0122] Reference Figure 11 , removing the discrete pattern 1211 and retaining the deposition layer 18 located on the sidewall of the discrete pattern 1211; using the retained deposition layer 18 as a mask, etching the substrate 10 to obtain a gate trench.
[0123] In an embodiment of the present invention, a deposition layer 18 can be formed on the sidewalls. After removing the discrete pattern 1211, the deposition layer 18 on the sidewalls of the discrete pattern 1211 is retained. The retained deposition layer 18 is used as a mask to etch the substrate 10, thereby forming a gate trench. The solution of this embodiment of the present invention helps to utilize the higher dimensional accuracy and consistency of the discrete pattern 1211, further improving the refinement of the gate trench.
[0124] It should be understood that the term "and / or" as used herein simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " as used herein indicates that the related objects are in an "or" relationship.
[0125] The term "plurality" used in the embodiments of the present application refers to two or more.
[0126] The first, second, etc. descriptions appearing in the embodiments of this application are only for illustration and distinction of the description objects. There is no order, nor does it indicate any special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.
[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, forming a discrete pattern on the substrate, wherein the actual feature size of the discrete pattern is larger than the standard feature size, and the standard feature size is the size of the discrete pattern that meets the standard value of the standard process specification; measuring an actual characteristic size of the discrete pattern and obtaining a difference between the actual characteristic size and the standard characteristic size; In response to a first difference between the actual feature size and the standard feature size being greater than a preset value, performing at least one round of removal process on the discrete pattern until the first difference between the actual feature size and the standard feature size is less than or equal to the preset value; The semiconductor structure is formed according to the discrete patterns.
2. The method according to claim 1, characterized in that Before forming the discrete patterns on the substrate, the method further includes: forming an initial discrete pattern on the substrate; The initial discrete patterns are wet cleaned to obtain the discrete patterns.
3. The method according to claim 2, characterized in that performing two or more rounds of removal on the discrete pattern; The removal time in the second round of removal process is 30% to 100% of the removal time in the first round of removal process.
4. The method according to claim 3, characterized in that The removal time in each round of the removal process is 30% to 100% of the removal time in the previous round of the removal process.
5. The method according to claim 3, characterized in that The removal time in each removal process from the second removal process onwards remains the same.
6. The method according to claim 2, characterized in that wet cleaning the initial discrete pattern using first cleaning process parameters, wherein the first cleaning process parameters include a cleaning time; performing at least one round of removal on the discrete pattern using first removal process parameters, wherein the first removal process parameters include a removal time; Among them, the parameters and parameter values of the other cleaning process parameters except the cleaning time in the first cleaning process parameters are consistent with the parameters and parameter values of the other removal process parameters except the removal time in the first removal process parameters.
7. The method according to claim 2, characterized in that forming an initial discrete pattern on the substrate, comprising: forming a layer to be patterned on the substrate, and forming a second sidewall spacer on the layer to be patterned; Using the second sidewall spacer as a mask, etching the layer to be patterned to form a plurality of the initial discrete patterns on the layer to be patterned; The etching process parameters for etching the layer to be patterned are adjusted so that the actual feature size of the initial discrete pattern is larger than a second standard feature size, which is a size of a standard value of the initial discrete pattern that meets standard process specifications.
8. The method according to claim 7, characterized in that A first mandrel layer is formed on the layer to be patterned; The forming of the second sidewall spacer on the layer to be patterned further includes: Etching a first mandrel layer on the substrate to form a plurality of first mandrels with a predetermined interval, forming first sidewalls on both sides of the first mandrels, and then removing the first mandrels, wherein the substrate includes a layer to be patterned, a second mandrel layer, and the first mandrel layer stacked in sequence; Using the first sidewall spacer as a mask, etching the second mandrel layer to form a plurality of second mandrels; The second sidewalls covering both sides of the second core shaft are formed, and the second core shaft is removed to obtain the second sidewalls.
9. The method according to claim 7, characterized in that The etching process parameter of the layer to be patterned is the etching time or etching rate of the layer to be patterned.
10. The method according to claim 1, characterized in that Forming the semiconductor structure according to the discrete pattern comprises: forming a deposition layer on sidewalls of the discrete patterns; removing the discrete pattern and retaining the deposition layer located on the sidewall of the discrete pattern; The substrate is etched using the retained deposition layer as a mask to obtain a gate trench.