Method and device for determining edge stress index of silicon wafer
By conducting stress testing on the target area at the edge of the silicon wafer, eliminating interference from the notch and center area, and using the stress test data to calculate the edge stress index, the problem of low efficiency in determining the edge stress index of the silicon wafer is solved, fast and accurate stress state monitoring is achieved, and product quality and process stability are improved.
Patent Information
- Application Number
- CN202510848864.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-24
- Publication Date
- 2025-09-23
AI Technical Summary
The existing method for determining silicon wafer edge stress indicators is inefficient, causing the silicon wafer to be easily deformed or cracked during subsequent processing, affecting product quality and reliability.
By performing stress tests on the edge of the silicon wafer in the target area, multiple sets of stress test data are obtained, interference from the Notch area and the center area is eliminated, and the edge stress index is calculated using multiple sets of stress test data. Mathematical tools such as standard deviation are used to quantify the stress distribution.
The efficiency and reliability of determining silicon wafer edge stress indicators are improved, complex operating procedures are reduced, and the stress state of silicon wafer edges can be reflected quickly and accurately, thereby improving the stability of the process and product quality.
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Figure CN120690705A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method and device for determining a silicon wafer edge stress index. Background Art
[0002] During the growth, cutting, grinding, and polishing processes of silicon wafers, stress concentration is prone to occur at the edges of the wafers. This stress can cause deformation or even cracking during subsequent high-temperature processing or mechanical processing, seriously affecting the quality and reliability of the wafers, and further affecting the chip's lithography accuracy and thin film deposition uniformity.
[0003] By testing stress indicators at the wafer edge, the stability and consistency of the process can be monitored in real time. If abnormal changes in wafer edge stress are detected, process parameters such as cutting speed, grinding pressure, and etching time can be adjusted promptly to ensure process stability, reduce stress issues caused by process fluctuations, and improve product yield. However, current methods for determining wafer edge stress indicators typically require complex operational procedures, resulting in low efficiency. Summary of the Invention
[0004] In order to solve the above technical problems, the present invention provides a method and device for determining silicon wafer edge stress indicators, which can improve the efficiency of determining silicon wafer edge stress indicators.
[0005] In order to achieve the above objectives, the technical solution adopted in the embodiment of the present invention is:
[0006] An embodiment of the present invention provides a method for determining a silicon wafer edge stress index, comprising:
[0007] Performing a stress test on a target region of a silicon wafer edge to obtain multiple sets of stress test data, wherein the target region is an annular region with a center of the silicon wafer as a circle and a radius within a preset radius range, and the target region is close to a notch region, and each set of stress test data corresponds to a preset radius within the preset radius range;
[0008] An edge stress index of the silicon wafer is determined based on the multiple sets of stress test data.
[0009] In some embodiments, each set of stress test data in the plurality of sets of stress test data includes a plurality of stress parameters within a preset angle range in the target area, each stress parameter in the plurality of stress parameters corresponds to a preset angle in the preset angle range, and the preset angle range is determined according to the notch area;
[0010] Determining the edge stress index of the silicon wafer according to the multiple sets of stress test data includes:
[0011] An edge stress index of the silicon wafer is determined according to a plurality of stress parameters included in each set of stress test data in the plurality of sets of stress test data.
[0012] In some embodiments, among the multiple stress parameters corresponding to the same set of stress test data, the multiple stress parameters correspond to different preset angles in the preset angle range, and the differences between adjacent preset angles are equal.
[0013] In some embodiments, the symmetry axis of the Notch region coincides with the symmetry axis of the target region. When the preset angle corresponding to the symmetry axis of the Notch region is 0°, the preset angle range is -3° to 3°.
[0014] In some embodiments, determining the edge stress index of the silicon wafer based on the multiple stress parameters included in each set of stress test data in the multiple sets of stress test data includes:
[0015] The standard deviation of the plurality of stress parameters is calculated to obtain an edge stress index of the silicon wafer.
[0016] In some embodiments, the preset radius range is 141.5 mm to 148 mm.
[0017] In some embodiments, the multiple sets of stress test data correspond to different radii within the preset radius range, and the differences between adjacent radii are equal.
[0018] An embodiment of the present invention further provides a device for determining a silicon wafer edge stress index, comprising:
[0019] a testing module configured to perform a stress test on a silicon wafer edge at a target region to obtain multiple sets of stress test data, wherein the target region is an annular region having a radius within a preset radius range and centered at the center of the silicon wafer, and the target region is adjacent to a notch region, wherein each set of stress test data corresponds to a preset radius within the preset radius range;
[0020] A determination module is used to determine the edge stress index of the silicon wafer according to the multiple sets of stress test data.
[0021] An embodiment of the present invention further provides an electronic device comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the steps of the method for determining the edge stress index of a silicon wafer as described above are implemented.
[0022] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for determining the silicon wafer edge stress index as described above are implemented.
[0023] The beneficial effects of the present invention are:
[0024] In this embodiment, stress testing is first performed on the target wafer edge, eliminating interference from stress release in the notch region and the intrusion of stress data from the center region. This effectively focuses on the effective testing range at the edge, ensuring that the resulting multiple sets of stress test data accurately reflect the true stress distribution at the wafer edge. Subsequently, the wafer edge stress index determined based on these multiple sets of stress test data accurately characterizes the stress state at the wafer edge, improving the reliability of the wafer edge stress index. This entire process eliminates the need for complex operational procedures and focuses on batch analysis of data from target wafer regions, enabling rapid determination of the wafer edge stress index. This ensures both accuracy and efficiency while improving the determination of the wafer edge stress index. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic diagram showing a flow chart of a method for determining a silicon wafer edge stress index according to an embodiment of the present invention;
[0026] Figure 2 A schematic diagram showing the location of a target area in a silicon wafer according to an embodiment of the present invention;
[0027] Figure 3 A flow chart showing the test and analysis of silicon wafer edge stress indicators in an embodiment of the present invention;
[0028] Figure 4 It shows the integrated data flow chart in an embodiment of the present invention;
[0029] Figure 5 A schematic diagram showing the structure of a device for determining a silicon wafer edge stress index according to an embodiment of the present invention;
[0030] Figure 6 A schematic structural diagram of an electronic device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION
[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present invention.
[0032] During the growth, cutting, grinding, and polishing processes of silicon wafers, stress concentration is prone to occur at the wafer edges. This stress can cause deformation or even cracks during subsequent high-temperature processing or mechanical processing, seriously affecting the wafer's quality and reliability. By monitoring stress indicators at the wafer edges, the stability and consistency of the process can be monitored in real time.
[0033] The present invention provides a method and device for determining a silicon wafer edge stress index, which can improve the efficiency of determining the silicon wafer edge stress index.
[0034] The embodiment of the present invention provides a method for determining a silicon wafer edge stress index, such as Figure 1 As shown, including:
[0035] Step 101: Perform a stress test on a target region of a silicon wafer edge to obtain multiple sets of stress test data. The target region is an annular region with a center of the silicon wafer as the center and a radius within a preset radius range. The target region is close to a notch region. Each set of stress test data corresponds to a preset radius within the preset radius range.
[0036] In this step, the location of the target area in the silicon wafer, such as Figure 2 As shown in the figure, with the center of the silicon wafer as the center of the circle, the target area is an annular area with a radius within a preset radius range, and the target area is close to the notch area. In other words, the target area is a portion of the annular area on the silicon wafer with a radius within a preset radius range (e.g., R1 to R2, where R1 is smaller than R2) and close to the notch area.
[0037] Considering that the structural design of the notch area releases stress, if the test area overlaps the notch area during stress testing, the test is meaningless. Based on this, the maximum radius of the target area is designed so that the value of R2 is set smaller than the corresponding radius of the notch area on the silicon wafer, thereby reducing the impact of the notch area on the test results.
[0038] Furthermore, considering that if the test area is close to the center of the silicon wafer, the stress test data will be mixed with a large amount of stress data from the central area, making it impossible to characterize the stress indicators at the edge of the silicon wafer. Based on this, the minimum radius of the target area is designed so that the value R1 is larger than the radius corresponding to the silicon wafer center area, thereby reducing the impact of the center area on the test results.
[0039] In this way, stress testing is performed on the target wafer edge to obtain multiple sets of track data with radii ranging from R1 to R2. This reduces the impact of the notch area and the wafer center on the wafer edge stress test results, thereby improving the accuracy of subsequent determination of wafer edge stress indicators.
[0040] Step 102: Determine the edge stress index of the silicon wafer based on the multiple sets of stress test data.
[0041] In this step, multiple groups of stress test data can be recorded as any one of the groups of stress test data can be recorded as Track_Ri, where Ri is any preset radius from R1 to R2. In other words, each preset radius from R1 to R2 corresponds to a set of Track data. Through the above step 101, stress tests are performed on the annular areas located from R1 to R2 on the silicon wafer in sequence to obtain multiple groups of stress test data (i.e., multiple groups of Track data) corresponding to the preset radius range. Each group of Track data may include multiple stress parameters at different angular positions along the edge of the silicon wafer, and the stress parameters may be DU values (Dual Refraction Unit, birefringence unit). The DU value is proportional to the internal stress of the silicon wafer. Therefore, based on the multiple groups of stress test data, the edge stress index of the silicon wafer can be determined.
[0042] In an embodiment of the present invention, stress testing is first performed on the target region of the silicon wafer edge, specifically eliminating interference from stress release in the notch region and mixing of stress data from the center region. This effectively focuses on the effective testing range at the edge, allowing the resulting multiple sets of stress test data to accurately reflect the true stress distribution at the silicon wafer edge. Subsequently, the silicon wafer edge stress index determined based on these multiple sets of stress test data accurately characterizes the stress state at the silicon wafer edge, improving the reliability of the silicon wafer edge stress index. This entire process eliminates the need for complex operational procedures and focuses on batch analysis of data from target regions of each silicon wafer, enabling rapid determination of the silicon wafer edge stress index. This improves the efficiency of determining the silicon wafer edge stress index while maintaining accuracy.
[0043] In some embodiments, each set of stress test data in the plurality of sets of stress test data includes a plurality of stress parameters within a preset angle range in the target area, each stress parameter in the plurality of stress parameters corresponds to a preset angle in the preset angle range, and the preset angle range is determined according to the notch area;
[0044] Determining the edge stress index of the silicon wafer according to the multiple sets of stress test data includes:
[0045] An edge stress index of the silicon wafer is determined according to a plurality of stress parameters included in each set of stress test data in the plurality of sets of stress test data.
[0046] In this embodiment, the location of the target area in the silicon wafer is as follows: Figure 2 As shown. With the center of the silicon wafer as the center of the circle, the radius range of the target area in the radial direction of the silicon wafer is a preset radius range (for example, R1 to R2), and the angular range of the target area in the circumferential direction of the silicon wafer is a preset angular range (for example, -A to A). The target area is an annular area on the silicon wafer near the notch area. The preset angular range of the target area is determined based on the notch area. For details, please refer to the following description:
[0047] Taking the axis of symmetry of the Notch area (i.e., the centerline between the Notch area and the center of the silicon wafer) as a reference, the partial annular area on the annular area whose angle from the axis of symmetry of the Notch area is within the range of A is determined as the target area, so that the angle range of the target area in the circumferential direction of the silicon wafer is a preset angle range (e.g., -A to A). In this way, each preset radius from R1 to R2 corresponds to a set of Track data, and each set of Track data may include multiple stress parameters at different angular positions along the edge of the silicon wafer, that is, each set of Track data may include stress parameters (i.e., DU values) corresponding to each preset angle from -A to A. In this way, the silicon wafer edge stress index is determined based on the multiple stress parameters included in each set of stress test data in the multiple sets of stress test data, covering multiple measurement points in the circumferential and radial directions, and can accurately characterize the stress state of the silicon wafer edge, thereby improving the reliability of the silicon wafer edge stress index. The entire process does not require a complex operating process, and focuses on batch analysis data of the target area of each silicon wafer, which can quickly determine the silicon wafer edge stress index, while taking into account the accuracy of the silicon wafer edge stress index and improving the efficiency of determining the silicon wafer edge stress index.
[0048] In some embodiments, determining the edge stress index of the silicon wafer based on the multiple stress parameters included in each set of stress test data in the multiple sets of stress test data includes:
[0049] The standard deviation of the plurality of stress parameters is calculated to obtain an edge stress index of the silicon wafer.
[0050] In this embodiment, the standard deviation of multiple stress parameters in multiple sets of stress test data is calculated as the edge stress index of the silicon wafer to quantify the uniformity and stability of the stress distribution in the edge area. The smaller the standard deviation, the smaller the stress fluctuation in the target area, the higher the process consistency, and the lower the risk of cracking or performance abnormality at the edge of the silicon wafer due to stress concentration in subsequent processing; conversely, the larger the standard deviation, the higher the discreteness of the edge stress, which can accurately locate the potential defect area. This method uses statistical mathematical tools to convert stress distribution characteristics into objective quantitative indicators, and combines it with targeted testing of the target area. It not only avoids interference from invalid areas, but also improves the scientificity and reliability of edge stress assessment through standardized calculation processes, providing an efficient and accurate decision-making basis for silicon wafer production process optimization and quality control.
[0051] Among them, the silicon wafer edge stress index, that is, the stress index of the target area, is also the Notch stress index.
[0052] Specifically, such as Figure 3 As shown, the test and analysis process based on the silicon wafer edge stress index is as follows:
[0053] (1) Stress test: Stress test is performed on the edge of the silicon wafer in the target area;
[0054] (2) Data analysis: The result files obtained after the stress test are analyzed step by step to obtain the analysis results;
[0055] (3) Data acquisition: Based on the analytical results, multiple sets of stress test data (i.e., multiple sets of track data) with a radius (R1 to R2) near the Notch are acquired;
[0056] (4) Data integration: extract multiple stress parameters (i.e., multiple DU values) with angles (Angle) in the range of (-A to A) from multiple sets of track data and perform data integration;
[0057] (5) Calculate the standard deviation: Calculate the standard deviation (std) of the DU in the integrated multiple track data sets with different angle ranges;
[0058] (6) Judgment: If std>150, it is judged that the notch stress of the silicon wafer (i.e., the silicon wafer edge stress index) is too large and the product quality is NG; otherwise, the quality is OK.
[0059] Definitions include: the Notch depth is 2 mm, and the Notch angle is 0°. It should be noted that the above steps can all be performed by a designed computer program.
[0060] Among them, such as Figure 4 As shown, the integrated data process is as follows:
[0061] (41) Modular design: The code in a computer program can be divided into multiple subroutines, each responsible for an independent function. For example, one subroutine can be responsible for loading multiple sets of track data; another subroutine can be responsible for extracting the DU values for each track data set with an angle within the range (-A, A); another subroutine can be responsible for grouping and merging the DU values that meet the conditions by radius; and yet another subroutine can be responsible for calculating the standard deviation of each integrated DU as a stress indicator.
[0062] (42) Path configuration: The GetConfig function is used to read the path from the configuration table, decoupling environmental parameters such as the system path from the business code logic. When the path needs to be changed, only the independent configuration table needs to be modified without touching the code, thus avoiding the repeated compilation and deployment costs caused by hard coding. At the same time, it can quickly adapt to different environments such as development and production, reducing the risk of path spelling errors and sensitive information exposure, significantly improving the maintainability, flexibility and security of the system, and making path management more convenient and efficient.
[0063] (43) Data Processing: Use arrays to efficiently process data, reducing direct worksheet operations and improving performance. Data processing is completed through batch calculations, filtering, conversions, and other operations on arrays, and the results are ultimately written back to the worksheet at once, avoiding the frequent I / O interactions caused by direct row and column operations on cells. Compared to direct worksheet operations, this improves processing performance while reducing code complexity, making the data processing process more efficient and smoother.
[0064] (44) Statistical analysis: Use a dictionary to collect data to facilitate subsequent statistical calculations. For example, data can be efficiently grouped and stored by category (such as different angle ranges, radius intervals, etc.) through a key-value pair structure, where the key is the statistical dimension and the value is the corresponding data set or statistical intermediate value (such as count, cumulative sum). During subsequent statistical calculations, there is no need to repeatedly traverse the original data. The target data set can be quickly located directly through the key, which can conveniently complete frequency statistics (such as the number of occurrences of a certain DU value), aggregate calculations (such as sum, mean, standard deviation), and other operations, significantly reducing calculation time.
[0065] (45) Result output: Generate a report containing statistical information for easy viewing and analysis. For example, when generating a report containing statistical information, by integrating and presenting the data processing results (such as the mean, standard deviation, and distribution range of stress indicators) in a structured form (tables, charts, and text summaries), the key characteristics and abnormal trends of silicon wafer edge stress can be intuitively displayed. The report content usually covers the data source, statistical method, core indicator value, and abnormal point annotation, and supports the screening of sub-reports with different radius or angle ranges, which facilitates the rapid location of stress concentration areas or process fluctuation links.
[0066] In some embodiments, the preset radius range may be determined to be 141.5 mm to 148 mm through a verification scheme. The verification scheme may be as follows:
[0067] Verification Plan 1: Based on semiconductor silicon wafer stress testing standards, stress tests were conducted on monocrystalline silicon wafers within a radius of 148mm to 150mm, acquiring 20 sets of track stress data. The stress DU values near 0° were all found to be 0. Because this area covers the wafer's notch, which serves as a positioning reference and is designed to release stress, testing in this area cannot reflect stress in the wafer's functional areas, making the test meaningless. Subsequently, the maximum preset radius of the test area (i.e., R2) was adjusted to below 148mm.
[0068] Verification Plan 2: Based on semiconductor silicon wafer stress testing standards, stress tests were conducted on single-crystal silicon wafers within a radius of 0mm to 141.5mm, generating 20 sets of track stress data. Data analysis revealed that this region was far from the wafer's notch, and the test results were heavily mixed with stress data from the central region, making it impossible to characterize the stress state near the notch and thus useless. Subsequently, the minimum preset radius of the test area (i.e., R1) was adjusted to above 141.5mm to allow testing closer to the notch.
[0069] In this way, on the one hand, the maximum radius of the target area is designed so that the value of R2 is set to be smaller than the radius corresponding to the notch area on the silicon wafer, thereby reducing the impact of the notch area on the test results. On the other hand, the minimum radius of the target area is designed so that the value of R1 is larger than the radius corresponding to the center area of the silicon wafer, thereby reducing the impact of the center area on the test results. The preset radius range is thus determined to be 141.5mm to 148mm. When stress testing is performed on the silicon wafer edge in the target area, multiple sets of track data with a radius of 141.5mm to 148mm are obtained. This reduces the impact of the notch area and the center area of the silicon wafer on the silicon wafer edge stress test results, thereby improving the accuracy of the subsequent determination of the silicon wafer edge stress index.
[0070] In some embodiments, the symmetry axis of the Notch region coincides with the symmetry axis of the target region. When the preset angle corresponding to the symmetry axis of the Notch region is 0°, the preset angle range is -3° to 3°.
[0071] In this embodiment, a stress test is performed on the silicon wafer in an area with a radius of 141.5mm to 148mm, and the test results are analyzed to obtain 20 sets of track data. The symmetry axis of the Notch area coincides with the symmetry axis of the target area, and the preset angle corresponding to the symmetry axis of the Notch area is 0°. The stress DU values of the preset angles in the range of (0°±3°) or (0°±3.5°) are extracted from the 20 sets of track data. The test results are integrated to calculate the std of these 20 sets of track stress DU values. The results show that the std value of the preset angle in the range of (0°±3.5°) is 176.9, while the std value of the preset angle in the range of (0°±3°) is 130.72.
[0072] To verify this discrepancy, repeated testing and analysis were performed. The results showed that the std value for the preset angle within the range of (0°±3.5°) was 175.01. The std values for the preset angle within the range of (0°±3.5°) were similar in both test results. This indicates that the larger std value for the preset angle within the range of (0°±3.5°) was not due to testing error.
[0073] Analyzing the reasons, we consider that the T7 code (formed by laser marking process) on the edge of the Notch of the silicon wafer is located 3° to the right of the Notch, and the preset angle test range of (0°±3.5°) just covers it. Combined with the working principle of the stress detection equipment, it can be seen that the T7 code will interfere with the test results, and the stress DU value at this position will appear to be too high. This interference causes the std value of the preset angle in the angle range of (0°±3.5°) to be too large, and thus cannot accurately reflect that the excessive stress at the Notch is caused by its own process factors. Therefore, in order to more accurately characterize the stress situation at the Notch and avoid the interference of the T7 code, the preset angle range is finally determined to be -3° to 3°.
[0074] In some embodiments, the multiple sets of stress test data correspond to different radii within the preset radius range, and the differences between adjacent radii are equal.
[0075] In this embodiment, a stress test is performed on the edge of the silicon wafer in the target area to obtain multiple sets of stress test data. Specifically, a stress test is performed on the edge of the silicon wafer in the target area to obtain test results. The test results are opened in analysis software. Since the preset radius range of the target area set by the test method is 141.5mm to 148mm, the first set of stress test data when the analysis software is opened is track data corresponding to a radius of 141.5mm. The track data corresponding to this radius is exported and stored in a folder. The software parameters are then adjusted to increase the radius by 0.325mm, obtaining track data corresponding to a radius of 141.825mm. This is repeated by adding 0.325mm radius each time until track data corresponding to a radius of 148mm is exported, for a total of 20 sets of track data. The value of 0.325mm can be calculated according to the following formula: (148-141.5) / 20=0.325mm. In this way, the differences between the radii corresponding to adjacent groups of stress test data in multiple groups of stress test data are equal, so that the stress test collection points are evenly distributed in the radial direction of the silicon wafer, thereby improving the accuracy of subsequent determination of the silicon wafer edge stress index.
[0076] In some embodiments, among the multiple stress parameters corresponding to the same set of stress test data, the multiple stress parameters correspond to different preset angles in the preset angle range, and the differences between adjacent preset angles are equal.
[0077] In this embodiment, multiple stress parameters included in each set of stress test data are extracted from multiple sets of stress test data, specifically: the symmetry axis of the Notch area coincides with the symmetry axis of the target area, and the preset angle corresponding to the symmetry axis of the Notch area is defined as 0° or 360°, and the clockwise direction is 0.1°, 0.15°, 0.2°, 0.25°, 0.3°, ..., 359.95° and 360°. Then the preset angle range is -3° to 3°, namely 0.1°, 0.15°, 0.2°, 0.25°, 0.3°, ..., 3°, and 359.95°, 359.9°, 358.85°, 358.8°, ..., 357°. Among the 20 sets of track data obtained by the above embodiment, each track contains a batch of stress DU data with a preset angle range of -3° to 3°. The stress DU data within the range of (0°±3°) in the 20 sets of track data are integrated into a column in Excel. In this way, among the multiple stress parameters corresponding to the same set of stress test data, the differences between the preset angles corresponding to adjacent stress parameters are equal, so that the stress test collection points are evenly distributed in the circumferential direction of the silicon wafer, thereby improving the accuracy of the subsequent determination of the silicon wafer edge stress index.
[0078] Furthermore, the aforementioned extraction, integration, and calculation steps can all be completed by a designed calculation program. The entire process does not require complex operational procedures. By focusing on batch analysis data from target areas of each silicon wafer, the wafer edge stress index can be quickly determined. This improves the efficiency of determining the wafer edge stress index while also taking into account its accuracy.
[0079] In one embodiment, stress was tested at the edge of an epitaxial heavily-doped silicon wafer between 141.5 mm and 148 mm. The test results were analyzed step by step, and the track data within the range of 141.5 mm to 148 mm was divided into 20 groups, with each track separated by 0.325 mm. The stress DU values within the angle range of 0° ± 3° were extracted from the 20 groups of track data. The test data was integrated, and the std of the stress DU values for the 20 groups of track data was calculated, resulting in a value of 209.16. This wafer was judged to have excessive notch stress and was deemed of poor quality. The wafer was scrapped and could not be shipped out of the factory.
[0080] In another embodiment, stress was tested at the edge of an epitaxial heavily-doped silicon wafer between 141.5 mm and 148 mm. The test results were then analyzed step by step. The track data within the range of 141.5 mm to 148 mm was divided into 20 groups, with each track separated by 0.325 mm. The stress DU values for angles within the range of 0° ± 3° were extracted from the 20 groups of track data. The test data was then integrated and the std of the stress DU values for the 20 groups of track data was calculated, yielding a result of std = 3.25. This wafer was determined to have low notch stress and good quality. The wafer can continue to flow until it is shipped.
[0081] In summary, the entire process does not require complex operating procedures. Focusing on batch analysis data of target areas of each silicon wafer, the edge stress index of the silicon wafer can be quickly determined. While taking into account the accuracy of the silicon wafer edge stress index, the efficiency of determining the silicon wafer edge stress index is improved.
[0082] The embodiment of the present invention also provides a device for determining a silicon wafer edge stress index, such as Figure 5 Shown, including:
[0083] Testing module 21 is configured to perform a stress test on a target region of a silicon wafer edge to obtain multiple sets of stress test data, wherein the target region is an annular region having a radius within a preset radius range and centered at the center of the silicon wafer, and the target region is adjacent to a notch region, and each set of stress test data corresponds to a preset radius within the preset radius range;
[0084] The determination module 22 is configured to determine the edge stress index of the silicon wafer according to the multiple sets of stress test data.
[0085] In some embodiments, each set of stress test data in the plurality of sets of stress test data includes a plurality of stress parameters within a preset angle range in the target area, each stress parameter in the plurality of stress parameters corresponds to a preset angle in the preset angle range, and the preset angle range is determined according to the notch area;
[0086] The determination module 22 is specifically configured to:
[0087] An edge stress index of the silicon wafer is determined according to a plurality of stress parameters included in each set of stress test data in the plurality of sets of stress test data.
[0088] In some embodiments, among the multiple stress parameters corresponding to the same set of stress test data, the multiple stress parameters correspond to different preset angles in the preset angle range, and the differences between adjacent preset angles are equal.
[0089] In some embodiments, the symmetry axis of the Notch region coincides with the symmetry axis of the target region. When the preset angle corresponding to the symmetry axis of the Notch region is 0°, the preset angle range is -3° to 3°.
[0090] In some embodiments, the determination module 22 is specifically configured to:
[0091] The standard deviation of the plurality of stress parameters is calculated to obtain an edge stress index of the silicon wafer.
[0092] In some embodiments, the preset radius range is 141.5 mm to 148 mm.
[0093] In some embodiments, the multiple sets of stress test data correspond to different radii within the preset radius range, and the differences between adjacent radii are equal.
[0094] The device for determining the edge stress index of a silicon wafer is capable of implementing each process of each embodiment of the above method. The technical features correspond one to one and can achieve the same technical effect. To avoid repetition, they will not be described here.
[0095] Please refer to Figure 6 An embodiment of the present invention further provides an electronic device 30, comprising a processor 31, a memory 32, and a computer program stored in the memory 32 and executable on the processor 31. When the computer program is executed by the processor 31, the various processes of the above-mentioned embodiment of the method for determining the edge stress index of a silicon wafer are implemented, and the same technical effects can be achieved. To avoid repetition, details will not be given here.
[0096] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned embodiment of the method for determining the edge stress index of a silicon wafer are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0097] The computer-readable storage medium includes permanent and non-permanent, removable and non-removable media, and information storage can be achieved by any method or technology. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage terminal devices to be detected or any other non-transmission media that can be used to store information that can be accessed by the computer terminal devices to be detected. As defined herein, computer-readable storage media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.
[0098] The embodiment of the present invention also provides a computer program product, including computer instructions, which, when executed by a processor, implement the above Figure 1 The various processes of the method embodiment shown can achieve the same technical effect, and to avoid repetition, they will not be described here.
[0099] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.
[0100] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present invention.
[0101] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.
[0102] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, since the embodiments are generally similar to the product embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the product embodiments.
[0103] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.
Claims
1. A method for determining silicon wafer edge stress index, characterized in that: include: Performing a stress test on a target region of a silicon wafer edge to obtain multiple sets of stress test data, wherein the target region is an annular region with a center of the silicon wafer as a circle and a radius within a preset radius range, and the target region is close to a notch region, and each set of stress test data corresponds to a preset radius within the preset radius range; An edge stress index of the silicon wafer is determined based on the multiple sets of stress test data.
2. The method according to claim 1, characterized in that Each of the multiple sets of stress test data includes multiple stress parameters within a preset angle range in the target area, each of the multiple stress parameters corresponds to a preset angle in the preset angle range, and the preset angle range is determined according to the Notch area; Determining the edge stress index of the silicon wafer according to the multiple sets of stress test data includes: An edge stress index of the silicon wafer is determined according to a plurality of stress parameters included in each set of stress test data in the plurality of sets of stress test data.
3. The method according to claim 2, characterized in that Among the multiple stress parameters corresponding to the same set of stress test data, the multiple stress parameters correspond to different preset angles in the preset angle range, and the differences between adjacent preset angles are equal.
4. The method according to claim 2, characterized in that The symmetry axis of the Notch region coincides with the symmetry axis of the target region. When the preset angle corresponding to the symmetry axis of the Notch region is 0°, the preset angle range is -3° to 3°.
5. The method according to claim 2, characterized in that Determining the edge stress index of the silicon wafer according to the multiple stress parameters included in each set of stress test data in the multiple sets of stress test data includes: The standard deviation of the plurality of stress parameters is calculated to obtain an edge stress index of the silicon wafer.
6. The method according to any one of claims 1 to 5, characterized in that The preset radius range is 141.5 mm to 148 mm.
7. The method according to any one of claims 1 to 5, characterized in that The multiple sets of stress test data correspond to different radii in the preset radius range, and the differences between adjacent radii are equal.
8. A device for determining silicon wafer edge stress index, characterized in that: include: a testing module configured to perform a stress test on a silicon wafer edge at a target region to obtain multiple sets of stress test data, wherein the target region is an annular region having a radius within a preset radius range and centered at the center of the silicon wafer, and the target region is adjacent to a notch region, wherein each set of stress test data corresponds to a preset radius within the preset radius range; A determination module is used to determine the edge stress index of the silicon wafer according to the multiple sets of stress test data.
9. An electronic device, characterized in that: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the steps of the method for determining the edge stress index of a silicon wafer according to any one of claims 1 to 5 are implemented.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for determining the silicon wafer edge stress index according to any one of claims 1 to 5 are implemented.