Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging structure comprises a first wafer which comprises a device region and an edge region surrounding the device region, and a protruding step surrounding the device region is formed in the edge region of the first wafer; the second wafer is bonded on the first wafer in the device area, the surface, back on to the first wafer, of the second wafer is taken as a device top surface, the device top surface is higher than the top surface of the step, and the side walls of the first wafer and the second wafer in the device area and the step define a groove; the buffer layer is filled in the groove, and the top surface of the buffer layer is inclined downwards from the top surface of the device to the top surface of the step; and a conductive bump on the device top surface. According to the invention, the process yield of the packaging structure can be guaranteed.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor packaging technology, and in particular to a packaging structure and a packaging method. Background Art

[0002] In semiconductor manufacturing, with the development of ultra-large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to decrease. Consequently, the requirements for integrated circuit packaging are also increasing. Building on the two-dimensional packaging within the X and Y planes of multi-chip modules (MCMs), 3D packaging technology stacked along the Z direction has been fully developed, and this 3D packaging technology has higher density.

[0003] Hybrid bonding is a widely used three-dimensional integrated circuit (3D IC) bonding technology. It is achieved through inorganic-inorganic direct bonding between the top wafer (T / W) and the bottom wafer (B / W), and top wafer bond pad metal-bottom wafer bond pad metal thermal-compression bonding (T / W bond pad metal-B / W bond pad metal thermal-compression bonding). Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are beneficial to ensuring the process yield of the packaging structure.

[0005] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a first wafer, including a device area and an edge area surrounding the device area, a protruding step surrounding the device area is formed in the edge area of ​​the first wafer; a second wafer, bonded to the first wafer in the device area, with the surface of the second wafer facing away from the first wafer as the top surface of the device, the top surface of the device is higher than the top surface of the step, the side walls of the first wafer and the second wafer in the device area form a groove with the step; a buffer layer, filled in the groove, the top surface of the buffer layer is inclined downward from the top surface of the device to the top surface of the step; a conductive bump, located on the top surface of the device.

[0006] Optionally, the material of the buffer layer includes a surfactant.

[0007] Optionally, the material of the buffer layer also includes nano glass balls and adhesive.

[0008] Optionally, the width of the groove formed by the side walls of the first wafer and the second wafer in the device area and the step is 3mm to 20mm; the height of the step is 50μm to 500μm; the width of the step is 2mm to 10mm; and the height from the top surface of the device to the bottom of the groove is 50μm to 500μm.

[0009] Optionally, the packaging structure also includes: a first dielectric layer covering the top surface of the device, and a second dielectric layer covering the first dielectric layer, wherein an interconnection pad is formed in the first dielectric layer, and an opening exposing the interconnection pad is formed in the second dielectric layer; the conductive bump is located on top of the interconnection pad in the opening and is electrically connected to the interconnection pad.

[0010] Optionally, the first dielectric layer also covers the bottom and sidewalls of the groove, the top and sidewalls of the step, and the surface of the edge area of ​​the first wafer; the buffer layer covers the second dielectric layer in the groove, and the top surface of the buffer layer slopes downward from the second dielectric layer on the top surface of the device to the second dielectric layer on the top surface of the step.

[0011] Optionally, the packaging structure includes a plurality of steps sequentially surrounding from close to the device area to far away from the device area; the buffer layer further fills the grooves between adjacent steps.

[0012] Optionally, the cross-sectional shape of the step includes a rectangle or a trapezoid.

[0013] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing multiple wafers according to an embodiment of the present invention, including a first wafer and a second wafer; bonding the first wafer and the second wafer, with the bonding surfaces of the first wafer and the second wafer being arranged relative to each other.

[0014] Correspondingly, an embodiment of the present invention also provides a wafer manufacturing method, including: providing a first wafer, including a device area and an edge area surrounding the device area; bonding a second wafer on the first wafer in the device area, with the surface of the second wafer facing away from the first wafer as the top surface of the device; performing graphical processing on the edge area of ​​the first wafer, removing part of the thickness of the first wafer in a part of the edge area, forming a step protruding from the edge area and surrounding the device area, the step and the side walls of the first wafer and the second wafer in the device area forming a groove; filling the groove to form a buffer layer, the top surface of the buffer layer tilting downward from the top surface of the device to the top surface of the step; forming a conductive bump on the top surface of the device.

[0015] Optionally, in the step of filling the groove to form a buffer layer, the material of the buffer layer includes a surfactant.

[0016] Optionally, in the step of filling the groove to form a buffer layer, the material of the buffer layer further includes nano glass balls and an adhesive.

[0017] Optionally, the step of filling the groove to form a buffer layer includes: filling the groove with a mixed solution of nano glass balls, additives, surfactants and organic solvents; heating the mixed solution to obtain an initial buffer layer; and sintering and curing the initial buffer layer to obtain a buffer layer.

[0018] Optionally, an inkjet printing method is used to fill the groove with a mixed solution of nano glass balls, additives, surfactants and organic solvents.

[0019] Optionally, in the step of filling the groove with a mixed solution of nano glass balls, additives, surfactants and organic solvents, the volume ratio of the nano glass balls to the organic solvent is 40% to 90%; the volume ratio of the additives to the organic solvent is 10% to 60%; and the volume ratio of the surfactant to the organic solvent is 5% to 50%.

[0020] Optionally, in the step of filling the groove with a mixed solution of nano glass balls, additives, surfactants and organic solvents, the nano glass balls are silicates and their derivatives; the additives include acrylic adhesives; the surfactants include one or more of stearate, sodium dodecylbenzene sulfonate and sodium linear alkylbenzene sulfonate; and the organic solvents include one or more of ethanol, dichloromethane, petroleum ether, acrylic and phenolic resins.

[0021] Optionally, in the step of heating the mixed solution, the heating temperature is 80°C to 200°C.

[0022] Optionally, the initial buffer layer is sintered and solidified by ultraviolet light irradiation or laser irradiation.

[0023] Optionally, before filling the groove to form the buffer layer, the packaging method further includes: forming a first dielectric layer covering the top surface of the device, and a second dielectric layer covering the first dielectric layer, wherein an interconnection pad is formed in the first dielectric layer; the step of forming a conductive bump on the top surface of the device includes: patterning the second dielectric layer to form an opening exposing the interconnection pad; forming a conductive bump located on top of the interconnection pad in the opening, wherein the conductive bump is electrically connected to the interconnection pad.

[0024] Optionally, in the steps of forming a first dielectric layer covering the top surface of the device and a second dielectric layer covering the first dielectric layer, the first dielectric layer also covers the bottom and sidewalls of the groove, the top and sidewalls of the step, and the surface of the edge area of ​​the first wafer; in the step of filling the groove to form a buffer layer, the buffer layer covers the second dielectric layer in the groove, and the top surface of the buffer layer slopes downward from the second dielectric layer on the top surface of the device to the second dielectric layer on the top surface of the step.

[0025] Optionally, the step of patterning the second dielectric layer to form an opening exposing the interconnect pad includes: forming a mask material layer covering the second dielectric layer, the buffer layer, and the second dielectric layer on the step in the device area; patterning the mask material layer, removing the mask material layer above the interconnect pad and the mask material layer covering the buffer layer and the second dielectric layer on the step to form a mask layer; and patterning the second dielectric layer along the mask layer to form an opening exposing the interconnect pad.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] In the packaging structure provided by the embodiment of the present invention, the surface of the second wafer facing away from the first wafer is the top surface of the device, the top surface of the device is higher than the top surface of the step, the side walls of the first wafer and the second wafer in the device area and the step form a groove, the buffer layer is filled in the groove, the top surface of the buffer layer is inclined downward from the top surface of the device to the top surface of the step, and the conductive bump is located on the top surface of the device; in the embodiment of the present invention, in the step of forming the conductive bump, it is necessary to form a mask material layer located on the top surface of the device, and then pattern the mask material layer to form a mask layer, exposing the position for forming the conductive bump, so as to position the formation of the conductive bump. In the embodiment of the present invention, a downward-sloping buffer layer is formed between the top surface of the device and the top surface of the step, so that the mask material layer located at the edge of the top surface of the device has a buffering effect, thereby reducing the damage caused by the edge of the top surface of the device to the first wafer and the second wafer. The sudden change in the slope of the side wall leads to uneven surface tension of the mask material layer, and the probability of accumulation of the mask material layer at the edge of the top surface of the device is reduced. Accordingly, when patterning the mask material layer, the probability of mask layer residue due to accumulation of the mask material layer at the edge of the top surface of the device is reduced, which makes it difficult to expose the position at the edge of the top surface of the device for forming the conductive bump, thereby helping to ensure the formation quality and electrical connection performance of the conductive bump. Moreover, when removing the mask layer, the probability of difficulty in removing the mask layer residue at the edge of the top surface of the device due to accumulation is reduced. Therefore, when forming the conductive bump, the probability of the conductive bump being affected by the residual mask layer at the edge of the top surface of the device, resulting in the position displacement of the conductive bump (the conductive bump slips or the adjacent conductive bumps stick together) is reduced, which helps to ensure the process yield of the packaging structure.

[0028] In the packaging method provided by the embodiment of the present invention, the edge area of ​​the first wafer is patterned, and a part of the thickness of the first wafer in a part of the edge area is removed to form a step protruding from the edge area and surrounding the device area. The step and the side walls of the first wafer and the second wafer in the device area form a groove, and the groove is filled to form a buffer layer. The top surface of the buffer layer is inclined downward from the top surface of the device to the top surface of the step, and a conductive bump is formed on the top surface of the device. In the embodiment of the present invention, a downward-sloping buffer layer is formed between the top surface of the device and the top surface of the step, so that the mask material layer located at the edge of the top surface of the device has a buffering effect, thereby reducing the uneven surface tension of the mask material layer caused by the sudden change in slope from the edge of the top surface of the device to the side walls of the first wafer and the second wafer, and the uneven surface tension of the mask material layer on the top surface of the device. The probability of mask material layer accumulation at the edge of the surface is reduced. Accordingly, when patterning the mask material layer, the probability of mask layer residue due to the accumulation of mask material layer at the edge of the top surface of the device is reduced, which makes it difficult to expose the position at the edge of the top surface of the device for forming the conductive bump. This is beneficial to ensuring the formation quality and electrical connection performance of the conductive bump. Moreover, when removing the mask layer, the probability of difficulty in removing the mask layer residue due to accumulation at the edge of the top surface of the device is reduced. Therefore, when forming the conductive bump, the probability of the conductive bump being affected by the residual mask layer at the edge of the top surface of the device, resulting in the position displacement of the conductive bump (the conductive bump slips or the adjacent conductive bumps stick together) is reduced, which is beneficial to ensuring the process yield of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 8 It is a structural schematic diagram corresponding to each step in a packaging method;

[0030] Figure 9 It is a structural schematic diagram corresponding to an embodiment of the packaging structure of the present invention;

[0031] Figures 10 to 19 It is a structural schematic diagram corresponding to each step in an embodiment of the packaging method of the present invention. DETAILED DESCRIPTION

[0032] As can be seen from the background technology, the process yield of the current packaging structure needs to be improved. The reasons why the process yield of the packaging structure needs to be improved are analyzed in conjunction with a packaging method.

[0033] Figures 1 to 8 It is a structural schematic diagram corresponding to each step in a packaging method.

[0034] refer to Figure 1 , provide a first wafer 10, including a device area 10A and an edge area 10W surrounding the device area 10A; bond a second wafer 20 on the first wafer 10 in the device area 10A, with the surface of the second wafer 20 facing away from the first wafer 10 as the device top surface 20a.

[0035] refer to Figure 2, perform trimming processing to remove the first wafer 10 with a thickness of 10W at the edge area and the second wafer 20 with a thickness of 10W at the edge area, so as to remove the poorly bonded portion between the first wafer 10 and the second wafer 20.

[0036] refer to Figure 3 , forming a first dielectric layer 41 covering the device top surface 20 a and a second dielectric layer 42 covering the first dielectric layer 41 , wherein an interconnection pad 40 is formed in the first dielectric layer 41 .

[0037] refer to Figure 4 , a photoresist material layer 50 is formed to cover the second dielectric layer 42 of the device area 10A.

[0038] Due to the step corners from the edge of the second dielectric layer 42 on the top surface 20a of the device to the sidewalls of the first wafer 10 and the second wafer 20, the surface tension of the photoresist material layer 50 is uneven, resulting in accumulation of the photoresist material layer 50 at the edge of the top surface 20a of the device.

[0039] refer to Figure 5 , patterning the photoresist material layer 50 , removing the photoresist material layer 50 above the interconnection pad 40 , and forming a photoresist layer 51 .

[0040] Since the photoresist material layer 50 is accumulated at the edge of the device top surface 20a, when the photoresist material layer 50 is patterned, the photoresist material layer 50 accumulated at the edge of the device top surface 20a is difficult to remove completely, and the accumulation of the photoresist layer 51 still remains, making it difficult to expose the second dielectric layer 42 above the interconnection pad 40 at the edge of the device top surface 20a.

[0041] refer to Figure 6 , the second dielectric layer 42 is patterned along the photoresist layer 50 to form an opening 53 exposing the top surface of the interconnect pad 40; after the opening 53 is formed, the photoresist layer 50 is removed.

[0042] Since the second dielectric layer 42 above the interconnection pad 40 at the edge of the device top surface 20a is still covered by the photoresist layer 51, when the second dielectric layer 42 is patterned along the photoresist layer 50, the second dielectric layer 42 above the interconnection pad 40 at the edge of the device top surface 20a is difficult to be etched, so that the interconnection pad 40 at the edge of the device top surface 20a is not exposed. Moreover, when the photoresist layer 50 is removed, the photoresist layer 51 accumulated at the edge of the device top surface 20a is difficult to be completely removed, and some photoresist layer 51 remains.

[0043] Combined with reference Figure 7 and Figure 8 , a conductive bump 60 electrically connected to the interconnection pad 40 is formed in the opening 53 .

[0044] Since part of the interconnection pads 40 at the edge of the device top surface 20a is not exposed, when the conductive bump 60 is formed, part of the interconnection pads 40 at the edge of the device top surface 20a is difficult to be electrically connected to the conductive bump 60, resulting in circuit abnormality. In addition, the residue of the photoresist layer 51 at the edge of the device top surface 20a is also likely to cause the formation position of the conductive bump 60 to shift (e.g., Figure 7 For example, the conductive bump 60 may slide or the adjacent conductive bumps 60 may stick together (as shown by the dashed arrow in FIG. Figure 8 structure in the packaging), thereby causing circuit abnormalities and affecting the process yield of the packaging structure.

[0045] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a first wafer, including a device area and an edge area surrounding the device area, a protruding step surrounding the device area is formed in the edge area of ​​the first wafer; a second wafer, bonded to the first wafer in the device area, with the surface of the second wafer facing away from the first wafer as the top surface of the device, the top surface of the device is higher than the top surface of the step, the side walls of the first wafer and the second wafer in the device area form a groove with the step; a buffer layer, filled in the groove, the top surface of the buffer layer is inclined downward from the top surface of the device to the top surface of the step; a conductive bump, located on the top surface of the device.

[0046] In the embodiment of the present invention, in the step of forming the conductive bump, it is necessary to form a mask material layer located on the top surface of the device, and then pattern the mask material layer to form a mask layer, exposing the position for forming the conductive bump, so as to position the formation of the conductive bump. In the embodiment of the present invention, a downwardly inclined buffer layer is formed between the top surface of the device and the top surface of the step, so that the mask material layer located at the edge of the top surface of the device has a buffering effect, reducing the probability of the mask material layer piling up at the edge of the top surface of the device due to uneven surface tension of the mask material layer caused by the sudden change in slope from the edge of the top surface of the device to the side walls of the first wafer and the second wafer. Accordingly, when patterning the mask material layer , reducing the probability of difficulty in exposing the position for forming the conductive bump at the edge of the device top surface due to the accumulation of the mask material layer at the edge of the device top surface and the residual mask layer, thereby helping to ensure the formation quality and electrical connection performance of the conductive bump. Moreover, when removing the mask layer, reducing the probability of difficulty in removing the mask layer residual accumulation at the edge of the device top surface, thereby reducing the probability of the conductive bump being affected by the residual mask layer at the edge of the device top surface when forming the conductive bump, thereby reducing the probability of the conductive bump position being offset (the conductive bump slips or adjacent conductive bumps stick together) due to the residual mask layer at the edge of the device top surface, thereby helping to ensure the process yield of the packaging structure.

[0047] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figure 9 It is a structural schematic diagram corresponding to an embodiment of the packaging structure of the present invention.

[0049] refer to Figure 9 The packaging structure includes: a first wafer 100, including a device area 100A and an edge area 100W surrounding the device area 100A, wherein a raised step 300 surrounding the device area 100A is formed in the edge area 100W of the first wafer 100; a second wafer 200, bonded to the first wafer 100 in the device area 100A, with the surface of the second wafer 200 facing away from the first wafer 100 as the device top surface 200a, the device top surface 200a is higher than the top surface of the step 300, and the sidewalls of the first wafer 100 and the second wafer 200 in the device area 100A and the step 300 form a groove 310; a buffer layer 330, filled in the groove 310, the top surface of the buffer layer 330 is inclined downward from the device top surface 200a to the top surface of the step 300; and a conductive bump 600, located on the device top surface 200a.

[0050] In this embodiment, the first wafer 100 and the second wafer 200 are arranged opposite to each other, thereby realizing wafer-level system packaging.

[0051] In this embodiment, the first wafer 100 and the second wafer 200 both include a substrate and a dielectric layer on the substrate. The dielectric layers of the first wafer 100 and the second wafer 200 are arranged relative to each other to achieve bonding.

[0052] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0053] A circuit structure is also formed in the dielectric layer. The circuit structure is used to achieve electrical connection between the circuit structures after the first wafer 100 and the second wafer 200 are bonded, thereby achieving normal function of the packaging structure.

[0054] The first wafer 100 includes a device region 100A and an edge region 100W surrounding the device region 100A. The device region 100A is used to form a circuit structure, and the edge region 100W is used to provide support.

[0055] In this embodiment, a raised step 300 surrounding the device region 100A is formed in the edge region 100W of the first wafer 100 . The step 300 is used to form a groove 310 with the sidewalls of the first wafer 100 and the second wafer 200 to form a buffer layer 330 .

[0056] In this embodiment, the top surface 200a of the device is higher than the top surface of the step 300, and the side walls of the first wafer 100 and the second wafer 200 in the device area 100A and the step 300 form a groove 310, so that the top surface of the buffer layer 330 formed in the groove 310 can form a downwardly inclined morphology from the top surface 200a of the device to the top surface of the step 300.

[0057] It should be noted that in this embodiment, the width d1 of the groove 310 formed by the sidewalls of the first and second wafers 100, 200, and the step 300 in the device region 100A should not be too large or too small. If the width d1 of the groove 310 formed by the sidewalls of the first and second wafers 100, 200, and the step 300 in the device region 100A is too large, it may lead to unnecessary waste of material for the buffer layer 330 and may also lead to a small remaining dimension of the step 300 facing away from the groove 310, which may cause the edge of the first wafer 100 to break during the subsequent packaging process. If the width d1 of the groove 310 formed by the sidewalls of the first and second wafers 100, 200, and the step 300 in the device region 100A is too small, it may also lead to a small space in the groove 310 and may also lead to an excessively large slope from the device top surface 200a to the top surface of the step 300, which may cause the buffer layer 330 to overflow during formation, thus affecting the formation of the buffer layer 330. Therefore, in this embodiment, the width d1 of the groove 310 formed by the sidewalls of the first wafer 100 and the second wafer 200 in the device region 100A and the step 300 is 3 mm to 20 mm.

[0058] It should also be noted that in this embodiment, the width d2 of the step 300 should not be too large or too small. If the width d2 of the step 300 is too large, it will easily cause the width d1 of the grooves 310 on both sides of the step 300 and the remaining size of the step 300 facing away from the grooves 310 to be too small, resulting in too little space in the grooves 310, affecting the formation of the buffer layer 330 and easily causing the edge of the first wafer 100 to break during the subsequent packaging process. If the width d2 of the step 300 is too small, it will easily cause difficulty in forming the step 300 and easily cause the step 300 to be too thin and easily break, affecting the reliability of the packaging structure. For this reason, in this embodiment, the width d2 of the step 300 is 2mm to 10mm.

[0059] It should also be noted that in this embodiment, the height h2 of the step 300 should not be too large or too small. If the height h2 of the step 300 is too large, it will easily lead to an excessively large aspect ratio of the step 300, which can easily cause the step 300 to break. It can also easily cause the thickness of the remaining first wafer 100 at the bottom of the step 300 to be too small, resulting in insufficient support for the remaining first wafer 100 at the bottom of the step 300, which can easily break and affect the reliability of the package structure. If the height h2 of the step 300 is too small, it can easily lead to an insufficient space in the groove 310, affecting the formation of the buffer layer 330. Therefore, in this embodiment, the height h2 of the step 300 is 50μm to 500μm.

[0060] It should also be noted that in this embodiment, the height h1 from the device top surface 200a to the bottom of the groove 310 should not be too large or too small. If the height h1 from the device top surface 200a to the bottom of the groove 310 is too large, the thickness of the remaining first wafer 100 at the bottom of the step 300 may be too small, resulting in insufficient support for the remaining first wafer 100 at the bottom of the step 300 and easy breakage, affecting the reliability of the packaging structure. If the height h1 from the device top surface 200a to the bottom of the groove 310 is too small, the space in the groove 310 may be too small, affecting the formation of the buffer layer 330. For this reason, in this embodiment, the height h1 from the device top surface 200a to the bottom of the groove 310 is 50μm to 500μm.

[0061] In this embodiment, the number of steps 300 is one, the process operation is simple, and the process cost is low. In other embodiments, the packaging structure may include multiple steps sequentially surrounding from close to the device area to far away from the device area, and accordingly, the buffer layer also fills the grooves between adjacent steps to play a buffering role.

[0062] In this embodiment, the cross-sectional shape of the step 300 is not limited. Specifically, in this embodiment, the cross-sectional shape of the step 300 includes a rectangle or a trapezoid.

[0063] The buffer layer 330 is used to provide a buffering effect on the mask material layer located at the edge of the device top surface 200 a when forming a mask material layer for covering the device top surface 200 a in the process of forming the conductive bump 600 .

[0064] In the present embodiment, in the step of forming the conductive bump 600, it is necessary to form a mask material layer located on the top surface 200a of the device, and then pattern the mask material layer to form a mask layer, exposing the position for forming the conductive bump 600, so as to position the formation of the conductive bump 600. In the present embodiment, a downwardly inclined buffer layer 330 is formed between the top surface 200a of the device and the top surface of the step 300, so that the mask material layer located at the edge of the top surface 200a of the device has a buffering effect, reducing the uneven surface tension of the mask material layer caused by the sudden change in the slope from the edge of the top surface 200a of the device to the side walls of the first wafer 100 and the second wafer 200, and the accumulation of the mask material layer at the edge of the top surface 200a of the device. The residual mask layer makes it difficult to expose the position at the edge of the device top surface 200a for forming the conductive bump 600, which is beneficial to ensuring the formation quality and electrical connection performance of the conductive bump 600. Moreover, when removing the mask layer, the probability of the mask layer residue at the edge of the device top surface 200a being difficult to remove due to accumulation is reduced. Therefore, when forming the conductive bump 600, the probability of the conductive bump 600 being affected by the residual mask layer at the edge of the device top surface 200a, resulting in the position displacement of the conductive bump 600 (the conductive bump 600 slips or the adjacent conductive bumps 600 stick together) is reduced, which is beneficial to ensuring the process yield of the packaging structure.

[0065] In this embodiment, the material of the buffer layer 330 includes a surfactant.

[0066] The surfactant has good wettability, which helps to make the mask material layer easy to wet at the boundary portion where the device top surface 200a contacts the buffer layer 300, further ensuring that the mask material layer will not accumulate at the edge of the device top surface 200a.

[0067] Specifically, in this embodiment, the surfactant includes one or more of stearate, sodium dodecylbenzene sulfonate and sodium linear alkylbenzene sulfonate.

[0068] In this embodiment, the material of the buffer layer 330 further includes nano glass balls and adhesive.

[0069] The nano glass balls are used to solidify into the buffer layer 330 , and the adhesive is used to bond the nano glass balls together.

[0070] Specifically, in this embodiment, the adhesive includes an acrylic adhesive.

[0071] The conductive bumps 600 are used to achieve electrical connection between the package structure and an external circuit.

[0072] In this embodiment, the material of the conductive bump 600 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0073] For example, the conductive bump 600 can be a C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, with the same conductive bump 600 spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0074] In other embodiments, the conductive bumps may also be a ball grid array (BGA) structure.

[0075] In this embodiment, the packaging structure further includes: a first dielectric layer 410 covering the device top surface 200a, and a second dielectric layer 420 covering the first dielectric layer 410, wherein the interconnection pad 400 is formed in the first dielectric layer 410, and an opening exposing the interconnection pad 400 is formed in the second dielectric layer 420.

[0076] The first dielectric layer 410 is used to electrically isolate adjacent interconnect pads 400, and the second dielectric layer 420 is used to protect the top of the interconnect pads 400. The interconnect pads 400 are used to electrically connect to the conductive bumps 600, thereby achieving electrical connection between the conductive bumps 600 and the circuit structures of the second wafer 200 and the first wafer 100. The openings exposing the interconnect pads 400 are used to form and position the conductive bumps 600.

[0077] Accordingly, in this embodiment, the conductive bump 600 is located on top of the interconnection pad 400 in the opening and is electrically connected to the interconnection pad 400 .

[0078] In this embodiment, in the step of forming the first dielectric layer 410 and the second dielectric layer 420, the first dielectric layer 410 and the second dielectric layer 420 cover the exposed surface of the second wafer 200. Therefore, in this embodiment, the first dielectric layer 410 also covers the bottom and sidewalls of the groove 310, the top and sidewalls of the step 300, and the surface of the edge region 100W of the first wafer 100.

[0079] Accordingly, in this embodiment, the buffer layer 330 covers the second dielectric layer 420 in the groove 310 , and the top surface of the buffer layer 330 slopes downward from the second dielectric layer 420 on the device top surface 200 a to the second dielectric layer 420 on the top surface of the step 300 .

[0080] Figures 10 to 19 It is a structural schematic diagram corresponding to each step in an embodiment of the packaging method of the present invention.

[0081] refer to Figure 10 , providing a first wafer 100 including a device region 100A and an edge region 100W surrounding the device region 100A.

[0082] The first wafer 100 is used to be subsequently bonded with the second wafer to achieve wafer-level system packaging.

[0083] In this embodiment, the first wafer 100 includes a substrate and a dielectric layer located on the substrate.

[0084] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0085] A circuit structure is also formed in the dielectric layer. The circuit structure is used to achieve electrical connection between the circuit structures after the first wafer 100 and the second wafer are bonded, thereby achieving normal function of the packaging structure.

[0086] The first wafer 100 includes a device region 100A and an edge region 100W surrounding the device region 100A. The device region 100A is used to form a circuit structure, and the edge region 100W is used to provide support.

[0087] Continue to refer Figure 10 , a second wafer 200 is bonded on the first wafer 100 in the device area 100A, with the surface of the second wafer 200 facing away from the first wafer 100 being the device top surface 200 a.

[0088] In this embodiment, the first wafer 100 and the second wafer 200 are arranged opposite to each other, thereby realizing wafer-level system packaging.

[0089] In this embodiment, the second wafer 200 also includes a substrate and a dielectric layer located on the substrate. The dielectric layers of the first wafer 100 and the second wafer 200 are arranged relative to each other to achieve bonding.

[0090] A circuit structure is also formed in the dielectric layer. The circuit structure is used to achieve electrical connection between the circuit structures after the first wafer 100 and the second wafer 200 are bonded, thereby achieving normal function of the packaging structure.

[0091] refer to Figure 11 ,in, Figure 11 (b) Figure 11 (a) shows a top view of the edge region 100W of the first wafer 100 being patterned to remove a portion of the thickness of the first wafer 100 in a portion of the edge region 100W, thereby forming a step 300 protruding from the edge region 100W and surrounding the device region 100A. The step 300 and the sidewalls of the first wafer 100 and the second wafer 200 in the device region 100A form a groove 310.

[0092] The step 300 is used to form a groove 310 with the sidewalls of the first wafer 100 and the second wafer 200 for subsequent formation of a buffer layer.

[0093] It should be noted that, in this embodiment, the step of performing graphical processing on the edge area 100W of the first wafer 100 also includes: removing the first wafer 100 and the second wafer 200 relative to each other in the edge area 100W, and removing the parts of the first wafer 100 and the second wafer 200 where the bonding is poor, which is beneficial to ensuring the bonding performance of the first wafer 100 and the second wafer 200, and at the same time performing back thinning processing on the second wafer 200 (i.e., thinning the second wafer 200 along the top surface 200a of the device).

[0094] In this embodiment, after the second wafer 200 is bonded to the first wafer 100, the edge area 100W of the first wafer 100 is patterned to form a step 300 protruding from the edge area 100W and surrounding the device area 100A. The top surface 200a of the device is higher than the top surface of the step 300, and the side walls of the first wafer 100 and the second wafer 200 in the device area 100A and the step 300 form a groove 310, so that the top surface of the buffer layer formed in the groove 310 can form a downwardly inclined morphology from the top surface 200a of the device to the top surface of the step 300.

[0095] It should be noted that, in this embodiment, during the step of patterning the edge region 100W of the first wafer 100 , the width d1 of the groove 310 formed by the sidewalls of the first wafer 100 and the second wafer 200 and the step 300 in the device region 100A should not be too large or too small. If the width d1 of the groove 310 formed by the side walls of the first wafer 100 and the second wafer 200 in the device area 100A and the step 300 is too large, it is easy to cause unnecessary waste of material of the buffer layer 330, and it is also easy to cause the remaining size of the step 300 facing away from the groove 310 to be too small, which may easily cause the edge of the first wafer 100 to break in the subsequent packaging process; if the width d1 of the groove 310 formed by the side walls of the first wafer 100 and the second wafer 200 in the device area 100A and the step 300 is too small, it is easy to cause the space of the groove 310 to be too small, and it is also easy to cause the slope from the top surface 200a of the device to the top surface of the step 300 to be too large, which may cause the buffer layer to overflow when forming the buffer layer, thereby affecting the formation of the buffer layer. Therefore, in this embodiment, during the step of patterning the edge region 100W of the first wafer 100 , the width d1 of the groove 310 formed by the sidewalls of the first wafer 100 and the second wafer 200 and the step 300 in the device region 100A is 3 mm to 20 mm.

[0096] It should also be noted that in this embodiment, during the step of patterning the edge region 100W of the first wafer 100, the width d2 of the step 300 should not be too large or too small. If the width d2 of the step 300 is too large, it can easily result in the width d1 of the grooves 310 on both sides of the step 300 and the remaining size of the step 300 facing away from the grooves 310 being too small, resulting in too little space in the grooves 310, affecting the formation of the buffer layer and easily causing the edge of the first wafer 100 to break during the subsequent packaging process. If the width d2 of the step 300 is too small, it can easily cause difficulty in forming the step 300 and easily cause the step 300 to be too thin and easily break, affecting the reliability of the packaging structure. Therefore, in this embodiment, during the step of patterning the edge region 100W of the first wafer 100, the width d2 of the step 300 is 2 mm to 10 mm.

[0097] It should also be noted that in this embodiment, during the step of patterning the edge region 100W of the first wafer 100, the height h2 of the step 300 should not be too large or too small. If the height h2 of the step 300 is too large, it can easily lead to an excessively large aspect ratio of the step 300, which can easily cause the step 300 to break. It can also easily lead to the thickness of the remaining first wafer 100 at the bottom of the step 300 being too small, resulting in insufficient support for the remaining first wafer 100 at the bottom of the step 300 and easy breakage, affecting the reliability of the packaging structure. If the height h2 of the step 300 is too small, it can easily lead to an insufficient space in the groove 310, affecting the formation of the buffer layer. For this reason, in this embodiment, during the step of patterning the edge region 100W of the first wafer 100, the height h2 of the step 300 is 50μm to 500μm.

[0098] It should also be noted that in this embodiment, during the step of patterning the edge region 100W of the first wafer 100, the height h1 from the device top surface 200a to the bottom of the groove 310 should not be too large or too small. If the height h1 from the device top surface 200a to the bottom of the groove 310 is too large, the thickness of the remaining first wafer 100 at the bottom of the step 300 may be too small, resulting in insufficient support for the remaining first wafer 100 at the bottom of the step 300 and easy breakage, affecting the reliability of the package structure. If the height h1 from the device top surface 200a to the bottom of the groove 310 is too small, the space in the groove 310 may be too small, affecting the formation of the buffer layer. To this end, in this embodiment, during the step of patterning the edge region 100W of the first wafer 100, the height h1 from the device top surface 200a to the bottom of the groove 310 is 50μm to 500μm.

[0099] In this embodiment, in the step of performing patterning on the edge area 100W of the first wafer 100, the number of steps 300 is 1, the process operation is simple, and the process cost is low. In other embodiments, in the step of performing patterning on the edge area of ​​the first wafer, the packaging structure can also include multiple steps that surround from close to the device area to far away from the device area in sequence, and accordingly, the buffer layer also fills the grooves between adjacent steps, which can play a buffering role.

[0100] In this embodiment, the cross-sectional morphology of the step 300 is not limited. Specifically, in this embodiment, in the step of patterning the edge region 100W of the first wafer 100 , the cross-sectional morphology of the step 300 includes a rectangle or a trapezoid.

[0101] refer to Figure 12 Before subsequently filling the groove 310 to form a buffer layer, the packaging method further includes: forming a first dielectric layer 410 covering the top surface 200a of the device, and a second dielectric layer 420 covering the first dielectric layer 410, wherein the first dielectric layer 410 has an interconnection pad 400 formed therein.

[0102] The first dielectric layer 410 is used to electrically isolate adjacent interconnect pads 400, and the second dielectric layer 420 is used to protect the top of the interconnect pads 400. The interconnect pads 400 are used to subsequently be electrically connected to the conductive bumps, thereby achieving electrical connection between the conductive bumps 600 and the circuit structures of the second wafer 200 and the first wafer 100.

[0103] In this embodiment, in the step of forming the first dielectric layer 410 and the second dielectric layer 420, the first dielectric layer 410 and the second dielectric layer 420 cover the exposed surface of the second wafer 200. Therefore, in this embodiment, the first dielectric layer 410 also covers the bottom and sidewalls of the groove 310, the top and sidewalls of the step 300, and the surface of the edge region 100W of the first wafer 100.

[0104] Combined with reference Figure 13 and Figure 14 The groove 310 is filled to form a buffer layer 330 , and the top surface of the buffer layer 330 is inclined downward from the device top surface 200 a to the top surface of the step 300 .

[0105] The buffer layer 330 is used to provide a buffering effect on the mask material layer located at the edge of the device top surface 200 a when forming a mask material layer for covering the device top surface 200 a in the process of forming the conductive bump 600 .

[0106] In this embodiment, a downwardly inclined buffer layer 330 is formed between the top surface 200a of the device and the top surface of the step 300, so that the mask material layer located at the edge of the device top surface 200a has a buffering effect, thereby reducing the uneven surface tension of the mask material layer caused by the sudden change in the slope from the edge of the device top surface 200a to the side walls of the first wafer 100 and the second wafer 200, and reducing the possibility that the mask material layer accumulates at the edge of the device top surface 200a and has a mask layer residue, which makes it difficult to expose the position at the edge of the device top surface 200a for forming the conductive bump 600. The rate is improved, which is beneficial to ensuring the formation quality and electrical connection performance of the conductive bump 600. Moreover, when removing the mask layer, the probability of the mask layer residue at the edge of the device top surface 200a being difficult to remove is reduced. Therefore, when forming the conductive bump 600, the probability of the conductive bump 600 being affected by the mask layer residue at the edge of the device top surface 200a, resulting in the position deviation of the conductive bump 600 (the conductive bump 600 slips or adjacent conductive bumps 600 stick together) is reduced, which is beneficial to ensuring the process yield of the packaging structure.

[0107] In this embodiment, in the step of filling the groove 310 to form the buffer layer 330 , the material of the buffer layer 330 includes a surfactant.

[0108] The surfactant has good wettability, which helps to make the mask material layer easy to wet at the boundary portion where the device top surface 200a contacts the buffer layer 300, further ensuring that the mask material layer will not accumulate at the edge of the device top surface 200a.

[0109] In this embodiment, in the step of filling the groove 310 to form the buffer layer 330 , the material of the buffer layer 330 further includes nano glass balls and an adhesive.

[0110] The nano glass balls are used to solidify into the buffer layer 330 , and the adhesive is used to bond the nano glass balls together.

[0111] Accordingly, in this embodiment, in the step of filling the groove 310 to form the buffer layer 330, the buffer layer 330 covers the second dielectric layer 420 in the groove 310, and the top surface of the buffer layer 330 is inclined downward from the second dielectric layer 420 on the top surface 200a of the device to the second dielectric layer 420 on the top surface of the step 300.

[0112] Specifically, refer to Figure 13 , Figure 13 (b) Yes Figure 13 (a) is a top view, and the step of filling the groove 310 to form the buffer layer 330 includes: filling the groove 310 with a mixed solution of nano glass balls, additives, surfactants and organic solvents.

[0113] A mixed solution of nano glass balls, additives, surfactants and organic solvents is filled in the groove 310 to prepare for forming a solidified buffer layer 330 .

[0114] In this embodiment, the diameter of the nano glass balls is 3 nm to 200 nm.

[0115] In this embodiment, an inkjet printing method is used to fill the groove 310 with a mixed solution of nano glass balls, additives, surfactants and organic solvents.

[0116] The inkjet printing method has low cost and can spray the mixed solution into the groove 310 more evenly.

[0117] It should be noted that in this embodiment, during the step of filling the groove 310 with a mixed solution of nano-glass balls, additives, surfactants, and an organic solvent, the volume ratio of the nano-glass balls to the organic solvent should not be too large or too small. If the volume ratio of the nano-glass balls to the organic solvent is too large, the mixed solution will be too thick and difficult to spray evenly into the groove 310; if the volume ratio of the nano-glass balls to the organic solvent is too small, the subsequent solidification of the nano-glass balls will be insufficient, making it difficult to form a solidified buffer layer 330. To this end, in this embodiment, during the step of filling the groove 310 with a mixed solution of nano-glass balls, additives, surfactants, and an organic solvent, the volume ratio of the nano-glass balls to the organic solvent is 40% to 90%.

[0118] It should also be noted that in this embodiment, during the step of filling the groove 310 with a mixed solution of nano-glass balls, additives, surfactants, and organic solvents, the volume ratio of the additives to the organic solvent should not be too large or too small. If the volume ratio of the additives to the organic solvent is too large, it is easy to cause an excess of additives, making the mixed solution too viscous and difficult to spray evenly into the groove 310. If the volume ratio of the additives to the organic solvent is too small, it is easy to cause an insufficient amount of adhesive, making it difficult for the nano-glass balls to adhere well and forming a solidified buffer layer 330. For this reason, in this embodiment, during the step of filling the groove 310 with a mixed solution of nano-glass balls, additives, surfactants, and organic solvents, the volume ratio of the additives to the organic solvent is 10% to 60%.

[0119] It should also be noted that in this embodiment, during the step of filling the groove 310 with the mixed solution of nano-glass spheres, additives, surfactants, and organic solvent, the volume ratio of surfactant to organic solvent should be neither too large nor too small. If the volume ratio of surfactant to organic solvent is too large, it can easily undermine the stability of the buffer layer 330 and cause the subsequently formed mask material layer to have too thin coverage on the step 300, thereby affecting the patterned dimensions of the mask material layer. If the volume ratio of surfactant to organic solvent is too small, it can easily lead to poor surface wettability of the buffer layer 330, making it difficult for the subsequently formed mask material layer to wet the boundary portion where the device top surface 200a contacts the buffer layer 300, thus making it difficult to prevent accumulation of the mask material layer at the edge of the device top surface 200a. Therefore, in this embodiment, during the step of filling the groove 310 with the mixed solution of nano-glass spheres, additives, surfactants, and organic solvent, the volume ratio of surfactant to organic solvent is between 5% and 50%.

[0120] Specifically, in this embodiment, in the step of filling the groove 310 with a mixed solution of nano-glass balls, additives, surfactants and organic solvents, the nano-glass balls are silicates and their derivatives; the additives include acrylic adhesives; the surfactants include one or more of stearate, sodium dodecylbenzene sulfonate and sodium linear alkylbenzene sulfonate; and the organic solvent includes one or more of ethanol, dichloromethane, petroleum ether, acrylic and phenolic resins.

[0121] Continue to refer Figure 13 , the mixed solution is heated to obtain an initial buffer layer 320 .

[0122] The mixed solution is heated to remove the organic solvent to obtain the initial buffer layer 320, and the nano glass balls are initially aggregated. The remaining adhesive and surfactant bond the nano glass balls to prepare for the subsequent curing of the nano glass balls.

[0123] It should be noted that in this embodiment, in the step of heating the mixed solution, the temperature of the heating treatment should not be too high or too low. If the temperature of the heating treatment is too high, it is easy to cause high-temperature damage to the packaging structure; if the temperature of the heating treatment is too low, it is difficult to remove the organic solvent and form a preliminary condensed initial buffer layer 320, which in turn affects the subsequent curing of the initial buffer layer 320, making it difficult to obtain a well-cured buffer layer 330. For this reason, in this embodiment, in the step of heating the mixed solution, the temperature of the heating treatment is 80°C to 200°C.

[0124] refer to Figure 14 ,in, Figure 14 (b) Yes Figure 14(a) is a top view showing that the initial buffer layer 320 is sintered and solidified to obtain the buffer layer 330.

[0125] The initial buffer layer 320 is sintered and solidified to obtain a solid buffer layer 330 .

[0126] Specifically, in this embodiment, ultraviolet light (UV) or laser irradiation (laser) is used to perform sintering and curing treatment on the initial buffer layer 320 .

[0127] Ultraviolet light irradiation or laser irradiation is easy to operate and can achieve a good curing effect.

[0128] Combined with reference Figures 15 to 19 , a conductive bump 600 is formed on the device top surface 200 a.

[0129] The conductive bumps 600 are used to achieve electrical connection between the package structure and an external circuit.

[0130] In this embodiment, the material of the conductive bump 600 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0131] For example, the conductive bump 600 can be a C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, with the same conductive bump 600 spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.

[0132] In other embodiments, the conductive bumps may also be a ball grid array (BGA) structure.

[0133] Combined with reference Figures 15 to 17 The step of forming the conductive bump 600 on the device top surface 200 a includes: patterning the second dielectric layer 420 to form an opening 430 exposing the interconnect pad 400 .

[0134] The opening 430 exposing the interconnection pad 400 is used for positioning the conductive bump 600 .

[0135] Specifically, refer to Figure 15 The step of patterning the second dielectric layer 420 to form an opening 430 exposing the interconnect pad 400 includes forming a mask material layer 500 covering the second dielectric layer 420 of the device region 100A, the buffer layer 330 and the second dielectric layer 420 on the step 300 .

[0136] The mask material layer 500 is used to form a mask layer for patterning the second dielectric layer 420 .

[0137] In this embodiment, the mask material layer 500 is made of photoresist.

[0138] In this embodiment, the buffer layer 330 covers the second dielectric layer 420 in the groove 310, and the top surface of the buffer layer 330 is inclined downward from the second dielectric layer 420 on the device top surface 200a to the second dielectric layer 420 on the top surface of the step 300, and the buffer layer 330 contains a surfactant. Therefore, in the step of forming the mask material layer 500, there will be no photoresist accumulation on the second dielectric layer 420 at the edge of the device top surface 200a.

[0139] refer to Figure 16 , patterning the mask material layer 500 , removing the mask material layer 500 above the interconnect pad 400 and the mask material layer 500 covering the buffer layer 330 and the second dielectric layer 420 on the step 300 , and forming a mask layer 510 .

[0140] The mask layer 510 is used as an etching mask for patterning the second dielectric layer 420 .

[0141] refer to Figure 17 The second dielectric layer 420 is patterned along the mask layer 510 to form an opening 430 exposing the interconnection pad 400 .

[0142] An opening 430 is formed to expose the interconnection pad 400 in preparation for forming a conductive bump 600 electrically connected to the interconnection pad 400 .

[0143] refer to Figure 18 After patterning the second dielectric layer 420 along the mask layer 510 , the method further includes: removing the mask layer 510 .

[0144] refer to Figure 19 A conductive bump 600 is formed in the opening 430 and is located on top of the interconnection pad 400 . The conductive bump 600 is electrically connected to the interconnection pad 400 .

[0145] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: A first wafer comprises a device region and an edge region surrounding the device region, wherein a raised step surrounding the device region is formed in the edge region of the first wafer; a second wafer bonded to the first wafer in the device region, with the surface of the second wafer facing away from the first wafer serving as the device top surface, the device top surface being higher than the top surface of the step, and sidewalls of the first and second wafers in the device region and the step forming a groove; a buffer layer, filling the groove, wherein a top surface of the buffer layer is inclined downward from a top surface of the device to a top surface of the step; The conductive bump is located on the top surface of the device.

2. The packaging structure according to claim 1, wherein: The material of the buffer layer includes a surfactant.

3. The packaging structure according to claim 2, wherein: The materials of the buffer layer also include nano glass balls and adhesive.

4. The packaging structure according to claim 1, wherein: The width of the groove formed by the sidewalls of the first wafer and the second wafer in the device area and the step is 3mm to 20mm; The height of the step is 50 μm to 500 μm; The width of the step is 2 mm to 10 mm; A height from the top surface of the device to the bottom of the groove is 50 μm to 500 μm.

5. The packaging structure according to claim 1, wherein: The packaging structure further includes: a first dielectric layer covering the top surface of the device, and a second dielectric layer covering the first dielectric layer, wherein an interconnection pad is formed in the first dielectric layer, and an opening is formed in the second dielectric layer to expose the interconnection pad; The conductive bump is located on top of the interconnection pad in the opening and is electrically connected to the interconnection pad.

6. The packaging structure according to claim 5, wherein: The first dielectric layer also covers the bottom and sidewalls of the groove, the top and sidewalls of the step, and the surface of the edge region of the first wafer; The buffer layer covers the second dielectric layer in the groove, and the top surface of the buffer layer slopes downward from the second dielectric layer on the top surface of the device to the second dielectric layer on the top surface of the step.

7. The packaging structure according to claim 1, wherein: The packaging structure includes a plurality of steps sequentially surrounding from close to the device area to far away from the device area; The buffer layer further fills the grooves between adjacent steps.

8. The packaging structure according to claim 1, wherein: The cross-sectional shape of the step includes a rectangle or a trapezoid.

9. A packaging method, characterized in that: include: Providing a first wafer, comprising a device region and an edge region surrounding the device region; bonding a second wafer on the first wafer in the device area, with the surface of the second wafer facing away from the first wafer serving as the top surface of the device; Performing patterning on an edge region of the first wafer, removing a portion of the thickness of the first wafer in a portion of the edge region to form a step protruding from the edge region and surrounding the device region, wherein the step and the sidewalls of the first and second wafers in the device region form a groove; Filling the groove to form a buffer layer, wherein the top surface of the buffer layer is inclined downward from the top surface of the device to the top surface of the step; Conductive bumps are formed on the top surface of the device.

10. The packaging method according to claim 9, wherein: In the step of filling the groove to form a buffer layer, the material of the buffer layer includes a surfactant.

11. The packaging method according to claim 10, wherein: In the step of filling the groove to form a buffer layer, the material of the buffer layer further includes nano glass balls and an adhesive.

12. The packaging method according to claim 11, wherein: The step of filling the groove to form a buffer layer includes: filling the groove with a mixed solution of nano glass balls, additives, surfactants and organic solvents; heating the mixed solution to obtain an initial buffer layer; The initial buffer layer is sintered and solidified to obtain the buffer layer.

13. The packaging method according to claim 12, wherein: The groove is filled with a mixed solution of nano glass balls, additives, surfactants and organic solvents by an inkjet printing method.

14. The packaging method according to claim 12, wherein: In the step of filling the groove with a mixed solution of nano glass balls, additives, surfactants and organic solvents, the volume ratio of the nano glass balls to the organic solvent is 40% to 90%; the volume ratio of the additives to the organic solvent is 10% to 60%; and the volume ratio of the surfactant to the organic solvent is 5% to 50%.

15. The packaging method according to claim 12, wherein: In the step of filling the groove with a mixed solution of nano glass balls, additives, surfactants and organic solvents, the nano glass balls are silicates and their derivatives; the additives include acrylic adhesives; the surfactants include one or more of stearate, sodium dodecylbenzene sulfonate and sodium linear alkylbenzene sulfonate; and the organic solvents include one or more of ethanol, dichloromethane, petroleum ether, acrylic and phenolic resins.

16. The packaging method according to claim 12, wherein: In the step of heating the mixed solution, the temperature of the heating treatment is 80° C. to 200° C.

17. The packaging method according to claim 12, wherein: The initial buffer layer is sintered and solidified by ultraviolet light irradiation or laser irradiation.

18. The packaging method according to claim 9, wherein: Before filling the groove to form the buffer layer, the packaging method further comprises: forming a first dielectric layer covering the top surface of the device, and a second dielectric layer covering the first dielectric layer, wherein an interconnection pad is formed in the first dielectric layer; The step of forming a conductive bump on the top surface of the device includes: patterning the second dielectric layer to form an opening exposing the interconnect pad; forming a conductive bump located on top of the interconnect pad in the opening, the conductive bump being electrically connected to the interconnect pad.

19. The packaging method according to claim 18, wherein: In the step of forming a first dielectric layer covering the top surface of the device and a second dielectric layer covering the first dielectric layer, the first dielectric layer also covers the bottom and sidewalls of the groove, the top and sidewalls of the step, and the surface of the edge region of the first wafer; In the step of filling the groove to form a buffer layer, the buffer layer covers the second dielectric layer in the groove, and the top surface of the buffer layer slopes downward from the second dielectric layer on the top surface of the device to the second dielectric layer on the top surface of the step.

20. The packaging method according to claim 19, wherein: The step of patterning the second dielectric layer to form an opening exposing the interconnect pad includes: forming a mask material layer covering the second dielectric layer in the device area, the buffer layer, and the second dielectric layer on the step; Patterning the mask material layer, removing the mask material layer above the interconnect pad and the mask material layer covering the buffer layer and the second dielectric layer on the step, to form a mask layer; The second dielectric layer is patterned along the mask layer to form an opening exposing the interconnect pad.

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