Transmitting module and method for transmitting differential signal in serial bus system

Abstract

A transmission module and method for transmitting a differential signal in a serial bus system. The transmission module has: a first transmission stage for generating at least one transmission current for a first signal to be transmitted onto a bus of the bus system; a second transmission stage for generating at least one transmission current for a second signal to be transmitted onto the bus line as a differential signal with respect to the first signal; a third transmission stage generating at least one transmission current for the first signal; and a fourth transmission stage generating at least one transmission current for the second signal, the first to fourth transmission stages being connected in a full bridge in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, each transmission stage having at least two transistors generating at least one transmission current, wherein the first and third transmitting stages are each connected to a connection of the bus voltage supply by means of a reversed polarity diode for protection against positive feedback in the connection of the bus voltage supply and negative feedback from the connection of the ground.

Description

Technical Field

[0001] The invention relates to a transmission module and a method for transmitting differential signals in a serial bus system, wherein in particular a voltage source with Vcc=3.3 V is used for the transmitting / receiving device. Background Art

[0002] For example, in CAN bus systems or Ethernet bus systems according to the 10-BASE-T1S standard, differential signals are used for data transmission on the bus. Devices and / or other technical equipment in the vehicle are connected to the bus. Signals transmit data serially, which is transmitted via the bus for communication between devices. These devices form user stations on the bus, also known as nodes. Each user station has at least one transmitting and / or receiving device, also known as a transceiver.

[0003] For data transmission using CAN, Classical CAN and CAN FD are standardized, for example, in the international standard ISO 11898-1:2015. CAN FD is currently often used with a data bit rate of 2 Mbit / s and an arbitration bit rate of 500 kbit / s. The so-called CAN SIC transmit / receive device enables the use of CAN FD with data rates of up to 8 Mbit / s. For higher data rates of up to 20 Mbit / s, CAN XL is currently available. In all of the aforementioned CAN-based bus systems, the bus signal CAN_H is driven to the bus separately for the transmit signal TxD, and ideally, the bus signal CAN_L is driven to the bus simultaneously. In this case, at least in the first communication phase, one bus state is actively driven in the bus signals CAN_H and CAN_L. The other bus state is not driven but occurs due to the terminating resistors of the bus lines or bus wires used for the bus. Due to the different driven states, the signal shape of the bus signals CAN_H and CAN_L may differ from the actual signal shape in real bus systems with stubs, mismatches, etc. This can lead to errors in the evaluation of bus signals received from the bus.

[0004] Currently, in CAN bus systems for transmitting / receiving devices (transceivers), a voltage source of Vcc=5V is used to generate different voltage levels for differential signals on the bus.

[0005] To reduce costs, it is considered to use a voltage source with Vcc = 3.3 V for the transmitting / receiving device. This reduction in supply voltage is advantageous because many microcontrollers today use 3.3 V. In addition, this voltage can also be supplied to many other components.

[0006] Reducing the supply voltage from 5 V to 3.3 V only offers the desired advantages if existing devices can continue to be used on a CAN bus with a voltage supply of 5 V. In this case, any number of 5 V subscribers (5 V nodes) and 3.3 V subscribers (3.3 V nodes) must be able to communicate simultaneously on the bus.

[0007] Consider that today's CAN buses, due to the differential signals CAN_H and CAN_L, have an average voltage of Vcc / 2, or 2.5 V. This is achieved by each bus user attempting to maintain the bus voltage at more or less exactly 2.5 V via a standardized resistor network with the aid of a current source. The bus voltage essentially follows the lowest node voltage (the voltage at the user station) and is therefore typically slightly below 2.5 V.

[0008] When transmitting, a CAN user station (node), or more precisely, its transmit / receive device, can switch between a dominant state and a recessive state. For the dominant state, the CAN user station drives the CAN_H level to approximately 3.5V and the CAN_L level to approximately 1.5V. The difference between the CAN_H and CAN_L levels is then in the 2V range. The international standard ISO 11898-1:2015 requires a minimum of 1.5V. The transition from the recessive state to the dominant state, and vice versa, is performed as symmetrically as possible around a virtual neutral line at Vcc / 2. This keeps the sum of the CAN_H and CAN_L levels at 5V as much as possible.

[0009] A major problem is that even small deviations in the millivolt range can result in significant electromagnetic radiation, which can cause EMC interference (EMC = electromagnetic compatibility) with other electrical equipment. Consequently, there are certain limits on the maximum permissible electromagnetic radiation that must be met by every transmitting / receiving device (transceiver). However, these requirements for electromagnetic radiation present significant challenges.

[0010] Compared to CAN FD, transceivers for CAN-SIC or CAN-XL must generate a third state, the sic state, in addition to the recessive state (rec) or dominant state (dom) during the arbitration phase, also known as SIC mode or SIC operating mode. To meet the emissions requirements of standard IEC 62228-3, the common-mode voltage of the bus lines for the CAN_H and CAN_L signals must be kept within very narrow ranges in the three transmit states: recessive, dominant, and sic. This common-mode voltage is generated across a common-mode choke, which is used, in particular, during certification measurements to check compliance with standard IEC 62228-3. A common-mode choke is also known as a Common Mode Choke (CMC). Its purpose is to pass differential signals (DM) with minimal interference and to suppress common-mode signals (CM) as completely as possible. However, in actual operation, a common-mode choke generates a differential signal at the output with an undesired common-mode signal superimposed on the differential signal from a differential signal at the input without a common-mode contribution. This is disadvantageous because, from a bus perspective, this signal is then fed directly into the CAN bus and is visible to other CAN modules.

[0011] The challenges in mixed operation are even greater if there is at least one subscriber station on the bus that has a transceiver that, in the dominant state, drives different levels for CAN_H and CAN_L than the transceivers of other subscriber stations. The reasons are as follows:

[0012] If the parameters of the physical layer are changed, restoring interoperability between user stations is often very troublesome. Therefore, it is desirable that the 3.3V CAN bus function in the same way as the 5V CAN bus, except for the difference in the bus voltage. The physical layer corresponds to the bit transmission layer, or layer 1 of the known OSI model (Open Systems Interconnection Model 1).

[0013] Therefore, a 3.3V node (subscriber station) on the bus for the dominant state must bring the signal CAN_H to approximately 3V and the signal CAN_L to significantly below 1V in order to exceed the specified minimum level difference of 1.5V.

[0014] The peculiarity of hybrid operation is that the 5V node sets the bus to 2.5V during the recessive phase, while the 3V node is intended to be set to approximately 1.65V on the bus. By increasing the CAN_L voltage by 1V in the 3.3V CAN, the voltage can be raised to approximately 1.9V during the recessive state. However, a difference of approximately 500-600mV still exists between the 5V node and the 3.3V node. In this configuration, the bus receives a voltage somewhere between 1.9V and 2.5V, and current continues to flow toward the 3.3V node, but this current is in the range of a few microamperes.

[0015] However, if the user station (node) starts to transmit and enters the dominant state at this time, the user station (node) does not start from "its" neutral line, but from the neutral line of the mixed operation. As a result, the sum of the levels of CAN_H and CAN_L changes when switching and changes again when switching back.

[0016] This predictably leads to high EMC emissions. Hybrid operation is therefore not possible so easily. Summary of the Invention

[0017] The object of the present invention is therefore to provide a transmission module and a method for transmitting differential signals in a serial bus system that solve the aforementioned problems. The transmission module and the method for transmitting differential signals in a serial bus system should, in particular, enable compensation for interference variables that influence the radiation characteristic of the transmission module.

[0018] This object is achieved by a transmission module for transmitting differential signals in a serial bus system, having the features of claim 1. The transmission module comprises a first transmission stage for generating at least one transmission current for a first signal, which is to be transmitted onto a bus of the bus system; a second transmission stage for generating at least one transmission current for a second signal, which is to be transmitted onto the bus as a differential signal relative to the first signal; a third transmission stage for generating at least one transmission current for the first signal; and a fourth transmission stage for generating at least one transmission current for the second signal, wherein the first to fourth transmission stages are connected to form a full bridge, in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, wherein each of the transmission stages has at least two transistors for generating at least one transmission current, and wherein the first and third transmission stages are each connected to a connection for a bus voltage supply via a reverse polarity diode for protection against positive feedback into the connection for the bus voltage supply and negative feedback from a connection for ground.

[0019] The described transmitter module can also be operated with a 3.3V voltage supply in bus systems that comply with the international standard for CAN. Furthermore, it can also be operated in bus systems in which both 3.3V and 5V subscribers are present, allowing for mixed operation. Even in mixed operation in a CAN bus system, it is easy to ensure that the required limit values ​​for the emission of the transmitter / receiver device are also adhered to for CAN XL. In particular, the transmitter module complies with the IEC 62228-3 standard, which specifies the limit values ​​to be adhered to for the bus states dom, sic, and rec.

[0020] The transmit module described above, for example, can effectively adapt the impedance between the bus lines for the signals CAN_H and CAN_L in the sic state to the characteristic wave impedance or impedance of the bus line used. Here, Zw = 100 ohms or Zw = 120 ohms applies to the impedance Zw of the bus line used. This prevents reflections and thus allows operation at higher bit rates in the bus system.

[0021] By dividing its four transmit stages into n parts, the described transmit module enables a time-graded and controlled switching process and, in particular, can generate the required 3V CAN levels. This allows switching in accordance with a Gaussian error function. This allows for gentle behavior during the switching process. Furthermore, the possible variation of the time stages prevents the appearance of narrowband frequency lines in the radiation spectrum during switching.

[0022] Alternatively, the described transmission module can be used to perform a graded and controlled switching process with fixed time steps and variable voltage steps. This also allows the emission characteristics of the transmission module to be influenced in such a way that predefined limit values ​​are adhered to.

[0023] To this end, the described transmission module can also reduce effects caused by asymmetric characteristics of the transmission stages, which can occur in the transmission states dom, sic, and rec and degrade radiation. The transmission module compensates for the different characteristics of the components in the transmission stages A and B of the full bridge (effect 1), thereby minimizing or preventing variations in the common-mode voltage in the dom state compared to the rec state. Furthermore, the transmission module compensates for the different characteristics of the components in the transmission stages A / D and C / B of the full bridge (effect 2), thereby minimizing or preventing variations in the common-mode voltage in the sic state compared to the rec state. This is particularly advantageous because adequate radiation results can only be achieved if the common-mode levels in the dom and sic states are matched to the common-mode level in the rec state, starting from the common-mode level in the rec state. However, the causes of the characteristics that lead to effect 1 may differ from those that lead to effect 2.

[0024] Further advantageous embodiments of the transmission module are described in the dependent claims.

[0025] The output terminals of the full bridge can be provided for connection to a terminating resistor of a bus.

[0026] The reverse polarity diode is, for example, a switchable reverse polarity diode that can be bridged or short-circuited.

[0027] It is conceivable that the first transmitter stage and the third transmitter stage are connected to the connection for the bus voltage supply via the same reverse polarity diode.

[0028] The reverse polarity diode is preferably arranged in a reverse polarity circuit which further comprises a first transistor, a second transistor and a resistor, wherein the second transistor has an on-resistance value which is significantly smaller than the resistance value of the resistor.

[0029] The drain terminal of the first transistor can be connected to the anode of a counter-polarity diode, wherein the source terminal of the first transistor and the second transistor is connected to the cathode of the counter-polarity diode, wherein the gate terminal of the first transistor is connected to the drain terminal of the second transistor and to the terminal for ground via a resistor, and wherein the gate terminal of the second transistor is connected to the terminal for the bus voltage supply.

[0030] Optionally, the path from the gate terminal to the source terminal of the first transistor has a filter for protection against pulse-like interference.

[0031] In a feasible manner, the second transmission stage and the fourth transmission stage each have a reverse polarity diode for protection against positive feedback into the connection for the bus voltage supply and negative feedback from the connection for the ground line, wherein the reverse polarity diode of the second transmission stage and the fourth transmission stage are each pn-based reverse polarity diodes, which are parasitic components of the transistors and are permanently wired so that the reverse polarity diodes cannot be bridged or short-circuited.

[0032] The reverse polarity diode is preferably designed to set a bus intermediate voltage of approximately 1.9 V when the transmitting module is operated with a supply voltage of approximately 3.3 V.

[0033] The transmission module can also include a control circuit for controlling the switchable components of the first to fourth transmission stages as a function of the digital transmission signal and the operating mode set for the transmission module. The control circuit can be designed to switch at least two current levels of the transmission stages in a temporally graded and controlled manner.

[0034] According to one exemplary embodiment, each of the transmission stages has a current mirror formed by two transistors for generating at least one transmission current.

[0035] It is feasible that each of the transmitting stages has at least two current stages connected in parallel, wherein each of the at least two current stages has a transistor for generating at least one transmitting current, wherein the at least two transistors have different parameters, and wherein the number n of the at least two current stages is the same for each of the first to fourth transmitting stages, wherein n is a natural number greater than 1.

[0036] It is conceivable that the at least two transistors for generating the at least one transmission current are CMOS transistors.

[0037] The CMOS transistors of the first transmitting stage can be PMOS transistors, wherein the CMOS transistors of the second transmitting stage are NMOS transistors, wherein the CMOS transistors of the third transmitting stage are PMOS transistors, and wherein the CMOS transistors of the fourth transmitting stage are NMOS transistors.

[0038] The transmit module described above can be part of a transmit / receive device for a subscriber station of a serial bus system, which transmit / receive device also has a receive module for receiving signals from the bus.

[0039] The transmitting / receiving device can be part of a subscriber station for a serial bus system, which also has a communication control device for controlling communication in the bus system and for generating digital transmit signals for actuating the first to fourth transmitting stages.

[0040] The subscriber station is preferably designed for communication in a bus system in which exclusive, conflict-free access to a bus of the bus system is at least temporarily guaranteed to the subscriber station.

[0041] The aforementioned object is also achieved by a method for transmitting a differential signal in a serial bus system having the features of claim 19. The method is implemented using a transmitting module, wherein the method comprises the following steps: generating at least one transmitting current for a first signal, which is to be transmitted on a bus of the bus system, using a first transmitting stage; generating at least one transmitting current for a second signal, which is to be transmitted on the bus as a differential signal relative to the first signal, using a second transmitting stage; generating at least one transmitting current for the first signal, using a third transmitting stage; and generating at least one transmitting current for the second signal, using a fourth transmitting stage, wherein the first to fourth transmitting stages are connected to form a full bridge, in which the first and fourth transmitting stages are connected in series and the third and second transmitting stages are connected in series, wherein each of the transmitting stages has at least two transistors for generating the at least one transmitting current, and wherein the first and third transmitting stages are each connected to a connection for a bus voltage supply via a reverse polarity diode for protection against positive feedback into the connection for the bus voltage supply and negative feedback from the connection for ground.

[0042] The method offers the same advantages as mentioned before with respect to the sending module.

[0043] Other possible implementations of the present invention also include combinations not explicitly mentioned of the features or embodiments described above or below with respect to the embodiments. Those skilled in the art can also add various aspects as improvements or supplementary solutions to the corresponding basic forms of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will be described in more detail below based on embodiments with reference to the accompanying drawings, wherein:

[0045] Figure 1 shows a simplified block diagram of a bus system according to a first embodiment;

[0046] Figure 2 A diagram is shown for explaining the structure of a message that can be sent by a first subscriber station of a bus system according to a first exemplary embodiment;

[0047] Figure 3 shows the time profile of a digital transmit signal during operation of the bus system at a first subscriber station and / or a second subscriber station, the second subscriber station being connected to the same bus of the bus system as at least one first subscriber station;

[0048] Figure 4 shows the time profile of the bus signals CAN_H and CAN_L in the second subscriber station according to the first exemplary embodiment;

[0049] Figure 5 shows the time profile of the differential voltage VDIFF of the bus signals CAN_H and CAN_L in the first subscriber station and the second subscriber station according to the first embodiment;

[0050] Figure 6 The time variation of the digital received signal is shown. The first user station or the second user station receives the signal from the bus based on Figure 3 generating the digital received signal from the transmitted signal;

[0051] Figure 7 The time profile of the bus signals CAN_H and CAN_L is shown, which can be transmitted by the first subscriber station according to the first exemplary embodiment according to Figure 3 The sending signal is generated on the bus;

[0052] Figure 8 An example of the time profile of a digital transmit signal is shown, which is to be converted into a digital transmit signal in the arbitration phase (SIC operating mode of the transmit module). Figure 1 The bus signals CAN_H and CAN_L of the bus system;

[0053] Figure 9 The time curve of the bus signals CAN_H and CAN_L when they change between the recessive bus state and the dominant bus state and return to the recessive bus state is shown. The bus signals are based on the Figure 8 The sending signal is sent to the bus;

[0054] Figure 10 A circuit diagram of a transmitting module for a subscriber station of a bus system according to a first exemplary embodiment is shown;

[0055] Figure 11 A time chart is shown for Figure 10 Connecting conditions of different current levels of a transmitting stage of a first special example of a transmitting module;

[0056] Figure 12 Shown for Figure 10 Details of the transmit stage of the second particular example of the transmit module;

[0057] Figure 13 A circuit diagram of a transmitting module for a subscriber station of a bus system according to a second exemplary embodiment is shown;

[0058] Figure 14 shows a circuit diagram of a transmit module for a subscriber station of a bus system according to a third exemplary embodiment; and

[0059] Figure 15 A circuit diagram of a transmit module for a subscriber station of a bus system according to a fourth exemplary embodiment is shown.

[0060] Unless otherwise indicated, identical or functionally identical elements are provided with the same reference symbols in the figures. DETAILED DESCRIPTION

[0061] Figure 1 A bus system 1 is shown, which can be, for example, at least in sections a CAN bus system, a CAN-FD bus system, etc. The bus system 1 can be used in vehicles, in particular motor vehicles, aircraft, etc., or in hospitals, etc.

[0062] exist Figure 1 In FIG, bus system 1 has a plurality of subscriber stations 10, 20, 30, each of which is connected to a bus 40 or bus circuit having a first bus core 41 and a second bus core 42. In a CAN bus system, bus cores 41, 42 can also be referred to as CANH and CANL for conducting signals CAN_H, CAN_L on bus 40.

[0063] Messages 45, 46, 47 can be transmitted in the form of signals between the individual subscriber stations 10, 20, 30 via bus 40. Subscriber stations 10, 20, 30 are, for example, control units or display devices of a motor vehicle.

[0064] like Figure 1 As shown in FIG, subscriber stations 10 and 30 each have a communication control device 11 and a transmitting / receiving device 12. Transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122. Subscriber station 10 uses a supply voltage of 3.3V, or a minimum of 3.0V. At least one of subscriber stations 20 and 30 uses a supply voltage of 5V. For illustrative purposes, the following embodiments show an example for a network or bus system 1, in which subscriber station 20 has a supply voltage of 5V, and subscriber stations 10 and 30 have a supply voltage of 3.3V, or a minimum of 3.0V. Other scenarios are also conceivable.

[0065] The user station 20 includes a communication control device 21 and a transmitting / receiving device 22 . The transmitting / receiving device 22 includes a transmitting module 221 and a receiving module 222 .

[0066] The transmitting / receiving devices 12 of the subscriber stations 10 and 30 and the transmitting / receiving device 22 of the subscriber station 20 are each directly connected to the bus 40, even if Figure 1 This is not shown in .

[0067] The communication control devices 11 , 21 are each used to control the communication of the corresponding subscriber station 10 , 20 , 30 with at least one other subscriber station of the subscriber stations 10 , 20 , 30 connected to the bus 40 via the bus 40 .

[0068] The communication control device 11 creates and reads a first message 45, 47, which is, for example, a modified CAN message 45, 47. In this case, the modified CAN message 45, 47 is based on the CAN XL format, for example. The transmitting / receiving device 12 is used to transmit messages 45, 47 to the bus and to receive messages from the bus. The transmitting module 121 receives the digital transmission signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts it into a signal on the bus 40, as shown in FIG. Figure 3 、 Figure 4 and Figure 7 As described more precisely. The digital transmission signal TxD can be a pulse width modulated signal at least temporarily or sectionally. The receiving module 121 receives the signals transmitted on the bus 40 and corresponding to the messages 45 to 47 and generates therefrom a digital reception signal RxD for which the digital reception signal is Figure 6 An example is shown in FIG. The receiving module 122 sends the receiving signal RxD to the communication control device 11 .

[0069] Additionally, the communication control device 11 can optionally be designed to create and read a second message 46 , which is, for example, a CAN FD message 46 . The transmitting / receiving device 12 can be designed accordingly.

[0070] The communication control device 21 can be implemented as a conventional CAN controller according to ISO 11898-1:2015, that is, as a CAN FD-compatible classic CAN controller or a CAN FD controller or a CAN SIC controller. The communication control device 21 creates and reads second messages 46, for example CAN FD messages or CAN SIC messages. The transmitting / receiving device 22 is used to transmit messages 46 to the bus 40 and to receive messages from the bus. The transmitting module 221 receives the digital transmit signal TxD created by the communication control device 21 and converts it into a signal for the message 46 on the bus 40, as described with reference to FIG. Figure 3 and Figure 4 The receiving module 222 receives the signals corresponding to the messages 45 to 47 sent on the bus 40 and generates a digital receiving signal RxD for which the Figure 6 An example is shown in . The transmitting / receiving device 22 can be implemented as a conventional CAN FD transceiver or a CAN-SIC transceiver.

[0071] For sending messages 45 , 46 , 47 using CAN SIC or CAN XL, the proven properties responsible for the robustness and user-friendliness of CAN and CAN FD are used, in particular the frame structure with identifiers and arbitration according to the known CSMA / CR method, which is described in more detail below.

[0072] The two subscriber stations 10 , 30 can form and then transmit messages 45 , 46 , 47 in different CAN formats, in particular the CAN FD format, the CAN SIC format, or the CAN XL format, and receive such messages 45 , 46 , 47 . This is described in more detail below with respect to the message 45 .

[0073] Figure 2 Frame 450 is shown for message 45, which is in particular a CAN XL frame, such as is provided by communication control device 11 to transceiver device 12 for transmission onto bus 40. In this case, communication control device 11 creates frame 450 in a manner compatible with CAN FD in the present exemplary embodiment. Alternatively, frame 450 is compatible with any subsequent standard for CAN FD.

[0074] according to Figure 2 Frame 450 for CAN communication on bus 40 is divided into different communication phases 451 and 452, namely, arbitration phase 451 (first communication phase) and data phase 452 (second communication phase). Following the start bit SOF, frame 450 includes an arbitration field 453, a control field 454, a first handoff field 455, a data field 456, a checksum field 457, a second handoff field 458, and an end-of-frame field 459, in which an EOF (End of Frame) marker is located. Checksum field 457, second handoff field 458, and end-of-frame field 459 form the end-of-frame phases 457, 458, and 459 of frame 450. An acknowledgment field (ACK) containing at least one ACK bit and not shown in the figure may be located in end-of-frame field 459.

[0075] Different from Figure 2 In the CAN FD frame 450 used by the user station 20 for the second message 46 , the switching fields 455 , 458 are not present.

[0076] For all previously mentioned CAN versions, it is true that in an arbitration phase 451, using an identifier (ID) in an arbitration field 453, a bit-by-bit agreement is reached between the user stations 10, 20, 30 as to which user station 10, 20, 30 is to send a message 45, 46, 47 with the highest priority and, therefore, obtain exclusive access to the bus 40 of the bus system 1 for the next transmission in the subsequent data phase 452. In the arbitration phase 451, a physical layer, as used in CAN and CAN-FD, is used. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model 1).

[0077] During phase 451, the known CSMA / CR method is used, which allows user stations 10, 20, 30 to access bus 40 simultaneously without destroying higher-priority messages 45, 46, 47. This makes it relatively easy to add further bus user stations 10, 20, 30 to bus system 1, which is very advantageous.

[0078] The CSMA / CR method requires a so-called recessive state on bus 40, which can be overwritten by another subscriber station 10, 20, 30 on bus 40 with a dominant level or dominant state. In the recessive state, a high impedance characteristic exists at each subscriber station 10, 20, 30, which, combined with the parasitics of the bus wiring, results in a relatively long time constant. As a result, the maximum bit rate of the current CAN-FD physical layer in practical vehicle applications is currently limited to approximately 2 megabits per second.

[0079] At the end of the arbitration phase 451, the data phase 452 is switched. In the case of CAN XL, by means of Figure 2 The first switching field 455 is used to switch.

[0080] In data phase 452, in the case of CAN XL, in addition to part of first switching field 455, the payload data of CAN-XL frame 450 or message 45 from data field 456, as well as checksum field 457 and part of second switching field 458 are transmitted. In the case of CAN FD, the payload data of CAN-FD frame or message 46 from data field 456, as well as checksum field 457 are transmitted.

[0081] At the end of the data phase 452, the process switches back to the arbitration phase 451. In the case of CAN XL, Figure 2 The second switching field 458 is used to switch.

[0082] The transmitter of message 45 starts sending the bits of data phase 452 onto bus 40 only if subscriber station 10 as transmitter has won the arbitration and therefore has exclusive access to bus 40 of bus system 1 as transmitter for sending.

[0083] A bit sequence is provided in the end-of-frame field EOF, which marks the end of frame 450. The bit sequence of the end field (EOF) thus serves to signal the end of frame 450. The end field (EOF) ensures that seven recessive bits are transmitted at the end of frame 450. Together with the optionally present ACK delimiter in the acknowledgement field (not shown), eight recessive bits are transmitted at the end of frame 450. The aforementioned bit sequence of recessive bits is a bit sequence that cannot occur within frame 450. This allows subscriber stations 10, 30 to reliably detect the end of frame 450.

[0084] The subscriber station 10 detects the bus potential or bus voltage present on the bus 40 starting at time t1, more precisely starting from time t1 and for a duration T_M1. The detection is performed after the occurrence of event E1. Event E1 is the occurrence of a predetermined number of directly consecutive recessive bits at the end of the frame 450, more precisely in the end field (EOF).

[0085] Optionally, the subscriber station can perform a test of the bus potential or bus voltage present on bus 40 starting at time t2, more precisely starting at time t2 for a duration T_M2. The test is performed after event E2 occurs. Event E2 is the identification at the end of the first communication phase (arbitration phase 451) of a subscriber station that has exclusive access to bus 40 in the subsequent second communication phase (data phase 452) and is therefore allowed to send its message.

[0086] This detection or measurement will be described below with reference to the accompanying drawings.

[0087] After the end field (EOF) having 7 bits, the following follows in frame 450. Figure 2 The interframe space (IFS) is not shown. In the case of CAN FD, the interframe space (IFS) is designed according to ISO 11898-1:2015. The interframe space (IFS) has at least 3 bits.

[0088] Furthermore, the mentioned fields and bits are known from ISO 11898-1:2015 and are therefore not described in detail here.

[0089] Therefore, in the arbitration phase 451 as the first communication phase, subscriber stations 10 , 30 partially use the format known from CAN / CAN-FD according to ISO 11898-1:2015, in particular up to and including the FDF bit. However, in the data phase 452 as the second communication phase, the net data transmission rate can be increased compared to CAN or CAN FD, in particular to more than 10 megabits per second. Furthermore, the size of the payload data per frame can be increased, in particular to approximately 2 kilobytes or any other desired value.

[0090] Figure 3 、 Figure 5 and Figure 6 Signals generated in subscriber stations 10 , 20 , 30 during operation of bus system 1 are shown as examples. Figure 4 As an example, a signal sent by a subscriber station 20 to the bus 40 during operation of the bus system 1 is shown. As already mentioned, the subscriber station 20 uses a supply voltage of 5 V. Figure 4 An alternative to the bus signaling shown in Figure 7 The bus signals generated by each of the subscriber stations 10, 30 are shown. As already mentioned, the subscriber stations 10, 30 use a supply voltage of approximately 3.3V, a minimum of 3.0V.

[0091] During operation of the bus system 1, Figure 1 Each of the transmitting modules 121, 221 can convert the transmission signal TxD of the associated communication control device 11 serially into corresponding signals CAN_H, CAN_L for CAN or CAN FD for bus cores 41, 42, and transmit these signals to the bus 40 at the connections for CAN_H and CAN_L. Figure 3 The transmission signal TxD is sent (serially) to the associated transmission modules 121 and 221 within time t, as shown in FIG. Figure 1 As shown in .

[0092] As an example Figure 3 As shown in FIG, the transmission signal TxD has voltage states H (High=high) and L (Low=low) with corresponding voltage U. The individual bits of the signal TxD have a bit time t_bt1, as shown in FIG. Figure 3 In the case of CAN FD and CAN XL, the bits of the signal TxD can be sent in the data phase 452 with a shorter bit time t_bt2, as shown in FIG. Figure 4 As shown in .

[0093] Figure 3 The sequence of the states H and L of the transmit signal TxD and the resulting Figure 4The states 401 and 402 of the signals CAN_H and CAN_L and the resulting Figure 5 The profile of voltage VDIFF serves only to illustrate the functionality of subscriber station 10. The sequence of the data states for bus states 401, 402 can be selected as required.

[0094] according to Figure 4 In the example of FIG. 4 , the signals CAN_H and CAN_L have dominant and recessive bus levels or bus states 401, 402, as known from CAN, at least in the arbitration phase 451. Since the subscriber station 20 uses a supply voltage of 5 V, it drives the CAN_H level to approximately 3.5 V and the CAN_L level to approximately 1.5 V for the dominant state 401, as shown in FIG. Figure 4 The recessive state 402 is set to 2.5V, which is equal to the bus center voltage Vcm=2.5V.

[0095] like Figure 5 As shown in FIG. 4 , for the differential voltage VDIFF=CAN_H−CAN_L on the bus 40 , the difference between the CAN_H level and the CAN_L level for the dominant state 401 is in the range of 2V.

[0096] The receiving modules 122 and 222 are Figure 4 The signals CAN_H and CAN_L received from the bus 40 are shown in FIG. Figure 5 The differential voltage VDIFF is formed according to Figure 6 To generate the received signal RxD. Figure 6 The digital reception signal RxD of the corresponding receiving module 122, 222 uses the reception threshold as known. Figure 6 The receiving module 122 transmits the receiving signal RxD to the associated communication control device 11, 21, as shown in FIG. Figure 1 As shown in .

[0097] According to ISO 11898-1:2015, the communication control devices 11 and 21 transmit the frame 450 and the transmission signal TxD ( Figure 3 ) itself sends the bit at the sampling point AP (Sample-Point, sampling point) ( Figure 4 and Figure 5 ) is located at the receiving signal RxD( Figure 6 ) is compared with the bit observed on the bus 40. Differences are evaluated as errors, except in the case of arbitration and ACK bits.

[0098] Different from Figure 4 , Figure 7 The signals CAN_H and CAN_L generated by the subscriber stations 10, 30 on the bus 40 in the arbitration phase 451 and the data phase 452 are shown. At least in the arbitration phase 451, dominant and recessive bus levels or bus states 401, 402 are used, as already described. Figure 4 Since the subscriber station 10, 30 uses a supply voltage of 3.3V in the example mentioned, the subscriber station drives the CAN_H level to approximately 2.9V and the CAN_L level to approximately 0.9V for the dominant state 401, as shown in FIG. Figure 7 As shown in . The recessive state 402 is set to 1.9 V, which is equal to the bus intermediate voltage Vcm=1.9 V. In the data phase 452, in the case of CAN XL, a physical layer 452_P different from the physical layer 451_P in the arbitration phase 451 can be used. Therefore, the CAN_H level can be driven to the value for the state L1, L0, as shown in Figure 7 As shown in . A physical layer, as in CAN and CAN-FD, is used in the arbitration phase 451. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model 1).

[0099] The sending module 121 is for Figure 3 The transmit signal TxD is generated by bus cores 41 and 42. Figure 7 The signals CAN_H and CAN_L in CAN_H are configured such that the state L0 is configured for the state LW (low=Low). In addition, the state L1 is configured for the state HI (high=High).

[0100] In order to increase the data rate for CAN XL, the transmitting / receiving device 12 can be designed for CAN SIC.

[0101] like Figure 8 and Figure 9 As more precisely shown in FIG, the sending module 121 in the case of CAN SIC is directed to Figure 8 The transmission signal TxD is generated by the bus core lines 41 and 42 with the bus intermediate voltage Vcm_sic=1.9V. Figure 9 The signals CAN_H, CAN_L are generated such that the state 403 (sic) is additionally present. The state 403 (SIC) can have different lengths, as shown for the state 403_0 (sic) during the transition from the state 402 (rec) to the state 401 (dom) and for the state 403_1 (sic) during the transition from the state 401 (dom) to the state 402 (rec). The state 403_0 (sic) is shorter in time than the state 403_1 (sic). In order to generate the state 403 (SIC) according to Figure 9 The sending module 121 switches to the SIC operating mode (SIC mode) according to the signal.

[0102] In CiA610-3, it is not required to go through the short sic state 403_0, and the state depends on the type of implementation. The duration of the "long" state 403_1 (sic) is specified as t_sic < 530 ns for CAN-SIC and for SIC operating mode in the case of CAN-XL, starting at Figure 8 The rising edge of the transmit signal TxD.

[0103] The subscriber station 10, in particular the transmitting / receiving device 12, detects the bus potential or bus voltage present on the bus 40 starting from the time t3, more precisely after the occurrence of event E3, starting from time t3 and for a duration T_M3. Event E3 is the exit from state 401 (dom) or the switch from state 401 (dom) to state 403 (sic). Depending on the detection result, the subscriber station 10 sets either 2.5 V ( Figure 4 ) or 1.9V( Figure 7 ) is fed as bus pre-voltage to the bus 40. The bus pre-voltage or potential 2.5 V on the bus 40 can be set in particular during bit 7 of the end-of-frame field EOF or one of the following four recessive bits.

[0104] In the "long" state 403_1 (sic), transmit module 121 should adapt the impedance between bus conductors 41 (CANH) and 42 (CANL) as closely as possible to the characteristic wave impedance Zw of the bus circuit being used. Here, Zw = 100 ohms or 120 ohms applies. This adaptation prevents reflections and thus allows operation at higher bit rates. For simplicity, reference will always be made to state 403 (sic) or sic state 403 below.

[0105] The transmission module 121 can be used to generate signals for the following CAN-type buses 40 : CAN-FD, CAN-SIC, and CAN-XL.

[0106]

[0107] Table 1: CAN_Type for Transmitter Module 121

[0108] Therefore, the module status sic can be sent not only in the case of CAN-SIC or CAN-XL (xl_sic), but also in the case of CAN-FD. However, in CAN-FD, the time for sending the module status sic can be shorter than in the case of CAN-SIC or CAN-XL.

[0109] Figure 10 The basic structure of a transmission module 121 for one of the user stations 10, 30 is shown. The transmission module 121 can generate Figure 9 The signals CAN_H, CAN_L with states 401, 402, 403 and Figure 7 The signals CAN_H, CAN_L with states L0, L1 are as described above.

[0110] The transmitting module 121 has four transmitting stages, namely, a first transmitting stage 121A, a second transmitting stage 121B, a third transmitting stage 121C and a fourth transmitting stage 121D. Figure 10 As shown in FIG, the transmitting stages 121A to 121D are connected as a full bridge.

[0111] Transmit module 121 is connected to bus 40, more precisely to a first bus core 41 for CAN_H or CAN-XL_H and a second bus core 42 for CAN_L or CAN-XL_L. Each of transmit stages 121A to 121D is connected to bus 40.

[0112] A voltage supply is provided via at least one terminal 43 for supplying electrical energy, in particular the 3.3V CAN supply voltage, to the first and second bus lines 41 and 42. Connection to ground, or CAN_GND, is achieved via a terminal 44. The first and second bus lines 41 and 42 are terminated by a terminating resistor 49. This terminating resistor 49 is connected to the full bridge as an external load resistor. Resistor 49 is connected to the bridge branch between the terminals for the bus lines 41 and 42.

[0113] Figure 10The first transmission stage 121A has an anti-polarity circuit D_A and a parallel circuit 121A1, in which the first to nth current stages are connected in parallel, where n is a natural number > 1. In addition, there is a control circuit T_A. The first current stage has a transistor TM_CH1 with a diode connected in parallel. The parallel-connected diode is parasitically generated by the transistor TM_CH1. The nth current stage has a transistor TM_CHn with a diode connected in parallel. The parallel-connected diode is parasitically generated by the transistor TM_CHn. The optional components present in the parallel circuit 121A1, but not in the Figure 10 The second to n-1th current stages shown in FIG are designed in the same manner as described for transistor TM_CH1 or transistor TM_CHn. Transistors TM_CH1 to TM_CHn are each CMOS transistors, for example, PMOS transistors. Specifically, each of transistors TM_CH1 to TM_CHn is a PMOS switching transistor with a high voltage withstand of approximately 60V to 80V. The abbreviation "CMOS" denotes a semiconductor component in which both p-channel and n-channel MOSFETs are used on a common substrate. The abbreviation CMOS stands for "Complementary Metal-Oxide Semiconductor," which translates to "Complementary Metal Oxide Semiconductor." The abbreviation "MOSFET" stands for Metal Oxide Field Effect Transistor. A control circuit T_A controls transistors TM_CH1 to TM_CHn of the first to nth current stages of transmit stage 121A according to the transmit signal TxD and the set operating modes SIC and FAST_TX of transmit module 121.

[0114] The first reverse polarity circuit D_A comprises a diode D1, a first transistor TR1, a second transistor TR2, a resistor R1 and optionally a capacitor C1. The diode D1 is parasitically generated by the transistor TR1. The transistor TR2 has its own parasitic diode, which Figure 10Transistors TR1 and TR2 are PMOS transistors. The anode of diode D1 is connected to the drain terminal of the first transistor TR1 and to the supply voltage VCC at terminal 43. The cathode of diode D1 is connected to the source terminal of the first transistor TR1 and to the source terminal of the second transistor TR2. The gate terminal of the first transistor TR1 is connected to the drain terminal of the second transistor TR2, to the terminal of resistor R1, and to the terminal of the optional capacitor C1. Another terminal of resistor R1 is connected to ground, in particular terminal 44 (GND). In addition, another terminal of optional capacitor C1 is connected to ground, in particular terminal 44 (GND). The gate terminal of the second transistor TR2 is connected to the supply voltage VCC at terminal 43. Therefore, the drain terminal of the first transistor TR1 and the gate terminal of the second transistor TR2 are connected to terminal 43 and, therefore, to the supply voltage VCC. Diode D1 can be conductive during operation and is short-circuited, in other words, bridged, by transistors TR1, TR2, and resistor R1. The transistor TR1 forms a bridgeable diode with the diode D1 , which is formed by the parasitic body-drain diode of the transistor TR1 . The function of the reverse polarity circuit D_A is described in more detail below.

[0115] Figure 10 The second transmission stage 121B has a reverse polarity diode D_B and a parallel circuit 121B1 in which the first to nth current stages are connected in parallel, where n is a natural number > 1. In addition, there is a control circuit T_B. The first current stage has a transistor TM_CL1 with a diode connected in parallel. The parallel-connected diode is parasitically generated by the transistor TM_CL1. The nth current stage has a transistor TM_CLn with a diode connected in parallel. The parallel-connected diode is parasitically generated by the transistor TM_CLn. The optional, but not present, diodes in the parallel circuit 121B1 are Figure 10 The second to n-1th current stages shown in FIG are designed in the same manner as described for transistor TM_CL1 or transistor TM_CLn. Transistors TM_CL1 to TM_CLn are each CMOS transistors, for example, NMOS transistors. Specifically, each of transistors TM_CH1 to TM_CHn is an NMOS switching transistor with a high voltage resistance of approximately 60V to 80V. The control circuit T_B controls the transistors TM_CL1 to TM_CLn of the first to nth current stages of the transmit stage 121B according to the transmit signal TxD and the set operating modes SIC and FAST_TX of the transmit module 121.

[0116] Figure 10The third transmission stage 121C has a polarity reversing circuit D_C and a parallel circuit 121C1 in which the first to nth current stages are connected in parallel, where n is a natural number > 1. In addition, there is a control circuit T_C. The first current stage has a transistor TC_CL1 with a diode connected in parallel. The diode connected in parallel is parasitically generated by the transistor TC_CL1. The nth current stage has a transistor TC_CLn with a diode connected in parallel. The diode connected in parallel is parasitically generated by the transistor TC_CLn. The optional components present in the parallel circuit 121C1, but not in the Figure 10 The second to n-1th current stages shown in FIG are designed in the same manner as described for transistor TC_CL1 or transistor TC_CLn. Transistors TC_CL1 to TC_CLn are each CMOS transistors, for example, PMOS transistors. Specifically, each of transistors TC_CL1 to TC_CLn is a PMOS switching transistor with a high voltage resistance of approximately 60V to 80V. The control circuit T_C controls transistors TC_CL1 to TC_CLn of the first to nth current stages of transmit stage 121C according to the transmit signal TxD and the set operating modes SIC and FAST_TX of transmit module 121.

[0117] The second reverse polarity circuit D_C has a diode D2, a first transistor TR3, a second transistor TR4, a resistor R2 and optionally a capacitor C2. The diode D2 is parasitically generated by the transistor TR3. The transistor TR4 has its own parasitic diode, which Figure 10 Transistors TR3 and TR4 are PMOS transistors. The anode of diode D2 is connected to the drain terminal of the first transistor TR3 and to the supply voltage VCC at terminal 43. The cathode of diode D2 is connected to the source terminal of the first transistor TR3 and to the source terminal of the second transistor TR4. The gate terminal of the first transistor TR3 is connected to the drain terminal of the second transistor TR4, to the terminal of resistor R2, and to the terminal of an optional capacitor C2. Another terminal of resistor R2 is connected to ground, in particular terminal 44 (GND). In addition, another terminal of capacitor C2 is connected to ground, in particular terminal 44 (GND). The gate terminal of the second transistor TR4 is connected to the supply voltage VCC at terminal 43. Therefore, the drain terminal of the first transistor TR3 and the gate terminal of the second transistor TR4 are connected to terminal 43 and, therefore, to the supply voltage VCC. Diode D2 can be conductive during operation and is short-circuited, in other words, bridged, by transistors TR3, TR4, and resistor R2. The transistor TR3 forms a bridgeable diode with the diode D2 , which is formed by the parasitic body-drain diode of the transistor TR3 . The function of the reverse polarity circuit D_C is described in more detail below.

[0118] Figure 10 The fourth transmission stage 121D has a reverse polarity diode D_D and a parallel circuit 121D1 in which the first to nth current stages are connected in parallel, where n is a natural number > 1. In addition, there is a control circuit T_D. The first current stage has a transistor TC_CH1 with a diode connected in parallel. The parallel-connected diode is parasitically generated by the transistor TC_CH1. The nth current stage has a transistor TC_CHn with a diode connected in parallel. The parallel-connected diode is parasitically generated by the transistor TC_CHn. The optional components present in the parallel circuit 121D1, but not in the Figure 10 The second to n-1th current stages shown in FIG are designed in the same manner as described for transistor TC_CH1 or transistor TC_CHn. Transistors TC_CH1 to TC_CHn are each CMOS transistors, for example, NMOS transistors. Specifically, each of transistors TC_CH1 to TC_CHn is an NMOS switching transistor with a high voltage resistance of approximately 60V to 80V. The control circuit T_D controls transistors TC_CH1 to TC_CHn of the first to nth current stages of the transmit stage 121D according to the transmit signal TxD and the set operating modes SIC and FAST_TX of the transmit module 121.

[0119] The current levels 1 to n of each of the transmission stages 121A to 121D are Figure 11 In the embodiment of the present invention, the current levels S1 to Sn are also referred to as current levels S1 to Sn. The number n can be selected arbitrarily. In particular, the number n and therefore the number of levels or current levels can be selected between 1 and 60. Alternatively, however, a number greater or less than 60 can be selected for n.

[0120] Each of the reversing diodes D_B and D_D protects the associated transmitter stage 121B and 121D from positive feedback to terminal 43 (CAN supply) and negative feedback to terminal 43 (CAN_GND). Each of the reversing diodes D_B and D_D can also be referred to as a blocking diode. Each of the reversing diodes D_B and D_D can be a pn-based diode, which is a parasitic pn junction of a (silicon) transistor that is permanently wired, so that the transistor cannot be controlled and the diode cannot be short-circuited / bridged. In particular, the forward voltage of each of the reversing diodes D_B and D_D is approximately 0.7 V.

[0121] Each of the polarity reversing circuits D_A, D_C protects the associated transmitting stage 121A, 121C from positive feedback to the terminal 43 (CAN supply) and negative feedback to the terminal 44 (CAN_GND). Each of the polarity reversing circuits D_A, D_C can also be referred to as a blocking circuit.

[0122] As mentioned, the gate terminal of the first transistor TR1 is connected to ground, in particular to the terminal 44 (GND), via the resistor R1. If the voltage of the source terminals of the transistors TR1 and TR2 increases, in particular due to a power supply of VCC_min=3.0V, the channel connected in parallel to the diode D1, i.e., the channel through the transistor TR1, can become conductive. This reduces the forward voltage of the diode D1. With a power supply of VCC_min=3.0V, a voltage according to Figure 7 or Figure 9 level.

[0123] Just as with the reverse polarity diodes D_B and D_D, backfeed protection is also achieved with the reverse polarity circuit D_A. As described, transistor TR2 is a PMOS transistor. If at least a threshold voltage lower than the potential at the source terminal of transistor TR2 is applied to its gate terminal, which is connected to terminal 43, transistor TR2 is turned on. If the voltage at the cathode of diode D1 (which is equal to the potential of the source terminal of the second transistor TR2) increases and exceeds the voltage VCC at terminal 43 by approximately the transistor threshold voltage, transistor TR2 can be turned on, the voltage at the gate of transistor TR1 increases, and transistor TR1 is turned off. Thus, parasitic diode D1 is effective. This provides backfeed protection.

[0124] For this purpose, the transistors TR1 and TR2 are designed such that the on-resistance of the second transistor TR2 is much smaller than the resistance of the resistor R1. <R1。

[0125] Optionally, the gate-source paths of the transistors TR1 , TR2 are filtered, in particular using an RC filter formed by a resistor R1 and a capacitor C1 . This makes the polarity reversal circuit D_A robust against pulse-like interferences, in particular DPI, ISO pulses, and the like.

[0126] As mentioned, the gate terminal of the first transistor TR3 is connected to ground, in particular to the terminal 44 (GND), via the resistor R2. If the voltage of the source terminals of the transistors TR3 and TR4 increases, in particular due to a power supply of VCC_min=3.0V, the channel connected in parallel to the diode D2, i.e., the channel through the transistor TR3, can be turned on. This reduces the forward voltage of the diode D2. With a power supply of VCC_min=3.0V, a voltage according to Figure 7 or Figure 9 level.

[0127] Just as with the reverse polarity diodes D_B and D_D, backfeed protection is also achieved with the reverse polarity circuit D_C. As described, transistor TR4 is a PMOS transistor. If at least a threshold voltage lower than the potential at the source terminal of transistor TR4 is applied to its gate terminal, which is connected to terminal 43, transistor TR4 is turned on. If the voltage at the cathode of diode D2 (which is equal to the potential of the source terminal of the second transistor TR4) increases and exceeds the voltage VCC at terminal 43 by approximately the transistor threshold voltage, transistor TR4 can be turned on, the voltage at the gate of transistor TR3 increases, and transistor TR3 is turned off. Thus, parasitic diode D2 is effective. This provides backfeed protection.

[0128] For this purpose, the transistors TR3 and TR4 are designed such that the on-resistance value of the second transistor TR4 is much smaller than the resistance value of the resistor R3. This then applies: Ron_TR4< <R2。

[0129] Optionally, the gate-source paths of transistors TR3, TR4 can be filtered, in particular using an RC filter formed by resistor R2 and capacitor C2. This makes the polarity reversal circuit D_C robust against pulse-like interference, in particular DPI, ISO pulses, and the like.

[0130] Each of the parallel circuits 121A1, 121B1, 121C1, and 121D1, more precisely the associated control circuits T_A, T_B, T_C, and T_D, sets the current value for the associated transmission stage 121A, 121B, 121C, and 121D according to the operating mode (SLOW or SIC, FAST_TX) of the transmission module 121 and the transmission signal TxD. The current value of each transmission stage 121A, 121B, 121C, and 121D can thus be set according to the operating mode (SLOW or SIC, FAST_TX) of the transmission module 121 and the transmission signal TxD. Figure 11 and Figure 12 and Tables 2 and 3 describe this in more detail.

[0131] In transmit module 121, transmit stage 121A is connected between terminal 43 for supply voltage and terminal 41 (CANH) for signal CAN_H, and, with respect to polarity reversal circuit D_A, between terminal 43 for supply voltage VCC and terminal 44 (CAN_GND) for ground. Transmit stage 121C is connected between terminal 43 for supply voltage and terminal 42 (CANL), and, with respect to polarity reversal circuit D_C, between terminal 43 for supply voltage VCC and terminal 44 (CAN_GND) for ground. Transmit stage 121D is connected between terminal 41 (CANH) for signal CAN_H and terminal 43 (CAN_GND) for ground. Transmit stage 121B is connected between terminal 42 (CANL) for signal CAN_L and terminal 43 (CAN_GND) for ground. Thus, in transmit module 121, transmit stage 121A is connected to the CANH path, while transmit stage 121D is connected to the CANH path. On the one hand, the transmission stage 121C is connected to the CAN1 path, and on the other hand, the transmission stage 121B is connected to the CAN1 path.

[0132] Therefore, the transmitter module 121 in the CANH path and the CANL path is composed of a specific number of parallel circuits 121A1, 121B1, 121C1, and 121D1 of current levels. A single current level is implemented by a parallel circuit composed of CMOS switches and their parasitic diodes, as described above. In the CANH path and the CANL path, the parallel circuits of all current levels are connected in series with the reverse polarity circuits D_A and D_C or the reverse polarity diodes D_B and D_D, as described above.

[0133] According to Table 2 below, Figure 10 The operating principle of the circuit is shown in FIG. 1 as a function of the operating mode of transmit module 121 and bus states 401 (dom), 403 (sic), 402 (rec) in SIC operating mode (arbitration phase 451), and L0 and L1 in data phase 452. Table 2 shows the standardized or required impedance of transmit module 121 as a function of the state of transmit module 121 or the resulting bus state on bus 40 and the differential voltage VDIFF on bus 40 in volts (V).

[0134]

[0135] Table 2: Normalized impedance of the transistors of the transmission stage 121 as a function of the transmission state or bus state

[0136] If the impedance is “infinite”, the transmission module 121 or the corresponding transmission stage 121A, 121B, 121C, 121D is switched off or made non-conductive.

[0137] Will Figure 10 Each parallel circuit 121A1, 121B1, 121C1, 121D1 is divided into n parts or n current levels, which allows a time-graded and controlled switching process between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 in the data phase 452. Figure 11 As indicated, the resistance values ​​of n current stages, in particular the parameters of the transistors, are set for this purpose.

[0138] Figure 11 An example of a current level for each switching stage or current stage S1 to S12 is shown. In the example shown, twelve current stages S1, S2 to S6 to S12 are used for each of the parallel circuits 121A1, 121B1, 121C1, 121D1. Therefore, n=12 applies.

[0139] The value of current I ( Figure 11 The vertical axis in the figure) or the values ​​of I1, I2, I6, I12, etc. are set by selecting the resistance values ​​or transistor parameters of the corresponding current levels S1 to S12. Figure 11 The horizontal axis in FIG) thus has different resistance values ​​or transistor parameters.

[0140] To generate bus states 401, 402, 403 in arbitration phase (SIC operating mode) 451 or bus states L0, L1 in data phase 452, the individual current stages S1 to S12 are switched on or off in a time-staggered manner using the CMOS transistors of current stages S1 to S12. As a result, a corresponding current I flows in the CANH path or CANL path, to which upstream transmitting stages 121A, 121B, 121C, 121D are connected.

[0141] Generally speaking, it is advantageous to design the staggering of each switching stage or current stage S1 to S12 and the parameters of the resistors, in particular the transistors, so that the shape of the differential signal VDIFF follows a Gaussian error function, thereby analytically generating the lowest radiation.

[0142] For the transition from state 402 (implicit) to state 401 (explicit) (which corresponds to Figure 5The rising edge of the differential voltage VDIFF is used to gradually increase the current in the CANH path and the CANL path by switching on the transistors of the parallel circuits 121A1, 121B1, 121C1, and 121D1 at different times, so as to generate a dominant level on the bus 40. The transition from state 401 (dominant) to state 402 (recessive) (which corresponds to Figure 5 The falling edge of the differential voltage VDIFF is achieved by switching off the transistors of the parallel circuits 121A1, 121B1, 121C1, and 121D1 in a time-staggered manner, thereby gradually reducing the current in the CANH and CANL paths. During state 401 (dominant), the total current flows, which is the sum of the currents I1 to I12 or I1 to In of all current stages S1 to Sn. Here, all current stages S1 to Sn or transistors of the parallel circuits 121A1, 121B1, 121C1, and 121D1 are turned on, and the total current used to generate the dominant level of the nominal VDIFF = 2 V flows through the bus resistor or terminating resistor 49.

[0143] As mentioned above, the current levels of the current stages S1 to S12 are set and selected in time by switching the transistors of the transmitting module 121, thereby enabling the bus signals CAN_H and CAN_L to be aligned with each other when transitioning between the states 401 and 402, thereby achieving the desired state. Figure 7 or according to Figure 4 The structure of the transmitting module 121 enables the current levels of the parallel circuits 121A1, 121B1, 121C1, and 121D1 to be switched on in a staggered manner. Figure 7 or Figure 9 or Figure 4 The signal shapes of CAN_H and CAN_L are aligned as required. The signal curves for CAN_H and CAN_L can be shaped in a targeted manner. In general, the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 in the data phase 452 can be formed according to the presetting.

[0144] The resistances of the individual current levels S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1, more precisely the design of the transistors of these current levels and thus the respective proportion of these current levels in the total current can be selected in different ways in order to achieve the lowest possible radiation, in particular low radiation of the transmitting module 121. It is advantageous for low radiation if a small amount of current I (high resistance value) is switched on or off at the beginning and end of the switching process between the bus states 401, 402 and a large amount of current (low resistance value) is switched on or off in the middle of the switching process. Therefore, it is very advantageous if Figure 11 The settings of the currents of the current levels S1 to S12 are shown in FIG.

[0145] Compared to an implementation using identical resistors, in particular transistors, in the current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1, Figure 10 The configuration avoids a current increase during the switch-off period, during the transition from state 401 (dominant) to state 402 (recessive).

[0146] The temporal staggering of the switching on and off of the individual current steps S1 to S12 The time steps are in the range of approximately 2 ns. Such small steps or steps for time grading result in low common-mode interference and have minimal negative effects on radiation. The voltage steps set by the resistors or resistor stages of current stages S1, S2 to S6 to S12 are kept constant, while the time grading is varied to achieve the smoothest possible behavior (according to the Gaussian error function) during the switching process. Furthermore, varying the time steps or time steps prevents the appearance of narrow frequency lines in the radiation spectrum.

[0147] Alternatively, the stepped steps (staggered steps) can be implemented with fixed time steps and varying voltage steps.

[0148] The illustrated structure of the transmit module 121 allows for symmetrical switching of the bus signals CAN_H and CAN_L in the case of steep switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 in the data phase 452 ( Figure 7 or Figure 9 or Figure 4 ).

[0149] On the one hand, due to the use of fast CMOS switches or CMOS transistors, the illustrated design of transmit module 121 enables significantly steeper switching edges between bus states 401, 402, 403 in arbitration phase (SIC operating mode) 451, or between bus states L0, L1 in data phase 452. On the other hand, the symmetry of the time profiles of bus signals CAN_H and CAN_L, necessary for complying with radiation limit values, is achieved during the switching process. The characteristic curves are adjusted (matched) by the selection or use of resistors, or more precisely, transistors, of parallel circuits 121A1, 121B1, 121C1, 121D1.

[0150] The parallel-connected current-stage CMOS transistors of the respective transmission stage 121A, 121B, 121C, 121D are operated as switches, ie, with a maximum voltage between the gate and source terminals.

[0151] Dominant state 401 (dom) is determined by adjusting (matching) transistors TM_CH1 to TM_CHn (transmitting stage 121A) and transistors TM_CL1 to TM_CLn (transmitting stage 121B). Here and in the following text, the term "adjustment" may refer to an active trimming step. Another possible embodiment of "adjustment" is to match the resistor values ​​as closely as possible, which is typically done without any adjustment or trimming steps.

[0152] The sic state (sic) is determined by adjusting (matching) transistors TM_CH1 to TM_CHn (transmitting stage 121A) and transistors TC_CL1 to TC_CLn (transmitting stage 121C), and adjusting (matching) transistors TC_CH1 to TC_CHn (transmitting stage 121D) and transistors TM_CL1 to TM_CLn (transmitting stage 121B).

[0153] In operating mode XL-Fast, state L0 is determined by adjusting (matching) transistors TM_CH1 to TM_CHn (transmitting stage 121A) and transistors TM_CL1 to TM_CLn (transmitting stage 121B). State L1 is determined by adjusting (matching) transistors TC_CL1 to TC_CLn (transmitting stage 121C) and transistors TC_CH1 to TC_CHn (transmitting stage 121D).

[0154] Figure 12 Shows a Figure 101 is a special example of the configuration of the transmitting stage 121B. Thus, the transmitting stage 121B in the parallel circuit 121B1 has three current stages S_I, S_II, and S_III. The first current stage S_I has a transistor TM_CL1. The second current stage S_II has a transistor TM_CL2. The third current stage S_III has a transistor TM_CL3.

[0155] For the following pair Figure 10 According to Figure 11 or Figure 12 The description of the circuit configuration assumes that each of the transmission stages 121A, 121C, 121D has a corresponding parallel circuit 121A1, 121C1, 121D1 in which it belongs. Figure 12 The three current levels S_I, S_II, S_III of the example.

[0156] Table 3 below shows the values ​​of the transmission stages 121A / 121B and 121C, 121D. Figure 12 The three transistors TM_CL1, TM_CL2, TM_CL3 and Figure 10 The corresponding transistors of the transmitting stages 121A, 121C, and 121D are controlled.

[0157]

[0158]

[0159] Table 3: Required impedance according to the transmit state

[0160] In this way, the required steeper edges can be generated at the bus signals CAN_H and CAN_L using transmit module 121 and emission limit values ​​can be observed.

[0161] Alternatively, more than three current stages can be used in the respective transmission stages 121A, 121B, 121C, 121D as described above.

[0162] Figure 13 The transmitting module 1210 according to the second embodiment is shown. The transmitting module 1210 is constructed in many parts in the same manner as the transmitting module 121 according to the first embodiment. Therefore, only the differences from the first embodiment are described below.

[0163] Unlike the first embodiment, the transmit module 1210 according to this embodiment includes a polarity reversal circuit D_AC and transmit stages 121A0, 121B, 121C0, and 121D. Transmit stages 121A0, 121B, 121C0, and 121D are connected to form a full bridge. A terminating resistor 49 is connected to the bridge branch between the connections for bus cores 41 and 42.

[0164] The polarity reversing circuit D_AC serves as a common polarity reversing circuit for the transmitting stages 121A0 and 121C0. Figure 10 Therefore, for the reverse polarity circuit D_AC, please refer to Figure 10 Description of the reverse polarity circuit D_A.

[0165] Compared with the sending module 121 of the previous embodiment, the sending module 1210 of this embodiment provides a size of about 0.04mm 2 If silicon is used as the semiconductor, for example, approximately 0.04 mm can be saved. 2 silicon area.

[0166] Therefore, the sending module 1210 of this embodiment can be more Figure 10 The sending module 121 of this embodiment is more resource-saving and more cost-effective to manufacture and operate. Figure 10 The sending module 121 requires less space.

[0167] Figure 14 The transmitting module 1211 according to the third embodiment is shown. The transmitting module 1211 is constructed in many parts in the same manner as the transmitting module 121 according to the first embodiment. Therefore, only the differences from the first embodiment are described below.

[0168] Different from the first embodiment, Figure 14 The transmitting module 1211 has four transmitting stages 121A5, 121B5, 121C5, 121D5 and four current mirror circuits 121A7, 121B7, 121C7, 121D7, instead of Figure 10 Transmitting stages 121A1, 121B1, 121C1, 121D1 and parallel circuits 121A1, 121B1, 121C1, 121D1.

[0169] The first transmission stage 121A5 has an inverting polarity circuit D_A connected in series with a current mirror circuit 121A7. The inverting polarity circuit D_A is as described above. Figure 10 Constructed and arranged as described.

[0170] Current mirror circuit 121A7 has at least one current mirror formed by transistors TM_CH and TM_CHs and at least one current sink I_A1. Up to n current mirrors can be connected in parallel. Transistors TM_CH and TM_CHs are CMOS transistors, in particular PMOS transistors.

[0171] Current sink I_A1 is connected to or coupled to the drain terminal of transistor TM_CHs and the gate terminals of transistors TM_CH and TM_CHs. Furthermore, current sink I_A1 is connected at its other terminals to ground, in particular terminal 44. Transistors TM_CH and TM_CHs are each connected to one another at their gate terminals and their source terminals. Furthermore, with respect to reverse polarity circuit D_A, the source terminals of transistors TR1 and TR2 and the cathode of diode D1 are connected to the gate and source terminals of transistors TM_CH and TM_CHs.

[0172] Second transmission stage 121B5 includes a reverse polarity diode D_B connected in series with a current mirror circuit 121B7. Current mirror circuit 121B7 includes at least one current mirror formed by transistors TM_CL and TM_CLs, and at least one current source I_B1. Up to n current mirrors can be connected in parallel. Transistors TM_CL and TM_CLs are CMOS transistors, particularly NMOS transistors.

[0173] Current source I_B1 is connected to or coupled to the drain terminal of transistor TM_CLs and the gate terminals of transistors TM_CL and TM_CLs. Furthermore, current source I_B1 is connected at its other terminals to a bus voltage supply, in particular terminal 43. Transistors TM_CL and TM_CLs are each connected to one another at their gate terminals and their source terminals. Furthermore, the cathode of reverse polarity diode D_B is connected to the drain terminal of transistor TM_CL.

[0174] The third transmission stage 121C5 has an inverting polarity circuit D_C connected in series with the current mirror circuit 121C7. The inverting polarity circuit D_C is as described above. Figure 10 Constructed and arranged as described.

[0175] The current mirror circuit 121C7 includes at least one current mirror formed by transistors TC_CL and TC_CLs and at least one current sink I_C1. Up to n current mirrors can be connected in parallel. Transistors TC_CL and TM_CLs are CMOS transistors, in particular PMOS transistors.

[0176] Current sink I_C1 is connected to or coupled to the drain terminal of transistor TC_CLs and the gate terminals of transistors TC_CL, TC_CLs. Furthermore, current sink I_C1 is connected at its other terminals to ground, in particular terminal 44. Transistors TC_CL, TC_CLs are each connected to one another at their gate terminals and their source terminals. Furthermore, with respect to reverse polarity circuit D_C, the source terminals of transistors TR3, TR4 and the cathode of diode D2 are connected to the gate and source terminals of transistors TC_CL, TC_CLs.

[0177] Fourth transmission stage 121D5 includes a reverse polarity diode D_D connected in series with a current mirror circuit 121D7. Current mirror circuit 121D7 includes at least one current mirror formed by transistors TC_CH and TC_CHs, and at least one current source I_D1. Up to n current mirrors can be connected in parallel. Transistors TC_CH and TC_CHs are CMOS transistors, particularly NMOS transistors.

[0178] Current source I_D1 is connected to or coupled to the drain terminal of transistor TC_CHs and the gate terminals of transistors TC_CH and TC_CHs. Furthermore, current source I_D1 is connected at its other terminals to a bus voltage supply, in particular terminal 43. Transistors TC_CH and TC_CHs are each connected to one another at their gate terminals and their source terminals. Furthermore, the cathode of reverse polarity diode D_D is connected to the drain terminal of transistor TC_CH.

[0179] Transmitting stages 121A5 , 121B5 , 121C5 , 121D5 are connected to form a full bridge. A terminating resistor 49 is connected in the bridge branch between the connections for bus cores 41 , 42 .

[0180] The sending stages 121A5, 121B5, 121C5, and 121D5 can be as described above. Figure 10 The transmission stages 121A1, 121B1, 121C1, 121D1 are operated as described. In this case, the current sources I_B1, I_D1 and the current sinks I_A1, I_C1 can be controlled according to an EMC-compliant evaluation form in order to produce the transmission states and bus states according to the aforementioned Table 1 or the impedances according to the aforementioned Table 2. The EMC-compliant evaluation form produces, for example, a current profile in and / or at the outputs of the transmission stages 121A5, 121B5, 121C5, 121D5 over time t, as shown in FIG. Figure 11 As shown in FIG. 1 for current levels S1 to S12 and described above.

[0181] In this way, it is also possible to use the transmission module 1211 with a power supply of VCC_min=3.0V to generate a signal in accordance with Figure 7 or Figure 9 level.

[0182] Figure 15 A sending module 1212 according to a fourth embodiment is shown. Figure 15 The sending module 1212 is in multiple parts with Figure 14 Therefore, only the differences from the first embodiment will be described below.

[0183] Different from Figure 14 Transmitting module 1211 of this embodiment includes transmitting module 1212 having a polarity reversal circuit D_AC and transmitting stages 121A6, 121B5, 121C6, and 121D5. Transmitting stage 121A6 does not have a polarity reversal circuit and is therefore identical to current mirror circuit 121A7. Transmitting stage 121C6 does not have a polarity reversal circuit and is therefore identical to current mirror circuit 121C7.

[0184] Transmitting stages 121A6 , 121B5 , 121C6 , 121D5 are connected to form a full bridge. A terminating resistor 49 is connected to the bridge branch between the connections for bus cores 41 , 42 .

[0185] The polarity reversing circuit D_AC serves as a common polarity reversing circuit for the transmitting stages 121A6 and 121C6. Figure 10 Therefore, for the reverse polarity circuit D_AC, please refer to Figure 10 Description of the reverse polarity circuit D_A.

[0186] Compared to Figure 14 The sending module 1211 of this embodiment provides a sending module 1212 of about 0.04mm according to the size design. 2 If silicon is used as the semiconductor, for example, approximately 0.04 mm can be saved. 2 silicon area.

[0187] Therefore, the sending module 1212 of this embodiment can be more Figure 14 The sending module 1211 of this embodiment is more resource-saving and more cost-effective to manufacture and operate. Figure 14 The sending module 1211 requires less location space.

[0188] All previously described embodiments and modifications thereof of transmit modules 121, 1210, 1211, 1212, transmit / receive devices 12, 22, subscriber stations 10, 20, 30, bus system 1, and the methods implemented therein according to the first and second exemplary embodiments can be used individually or in all possible combinations. In addition, the following modifications are particularly conceivable.

[0189] The bus system 1 according to the first and second embodiments described above is described as a bus system based on the CAN protocol. However, as an alternative, the bus system 1 according to the first and / or second embodiments can be another communication network in which signals are transmitted as differential signals. It is advantageous, but not mandatory, for the bus system 1 to ensure exclusive, conflict-free access to the bus 40 for the user stations 10, 20, and 30, at least for a specific period of time.

[0190] The bus system 1 according to the exemplary embodiment and its modifications is in particular a CAN bus system, a CAN-HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system. However, the bus system 1 can also be another communication network in which signals are transmitted serially as differential signals via the bus.

[0191] Thus, the functionality of the exemplary embodiments described above can be used, for example, in a transceiver 12 , 22 which can be operated in a CAN bus system, a CAN-HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system.

[0192] It is possible to at least temporarily not use the dominant and recessive bus states for the two bus states 401 , 402 , but instead use a first bus state and a second bus state, both of which are activated. An example of such a bus system is the CAN XL bus system.

[0193] The number and arrangement of subscriber stations 10, 20, 30 in bus system 1 according to the first and second exemplary embodiments and their modifications are arbitrary. In particular, only subscriber station 10 or only subscriber station 30 is present in bus system 1 of the first or second exemplary embodiment.

Claims

1. A sending module (121; 1210; 1211; 1212) for sending a differential signal in a serial bus system (1), the sending module comprising: a first transmission stage (121A; 121A0; 121A5; 121A6) for generating at least one transmission current (I1 to In; IA1) for a first signal (CAN_H) to be transmitted on a bus (40) of the bus system (1); a second transmission stage (121B; 121B5) for generating at least one transmission current (I1 to In; IB1) ​​for a second signal (CAN_L) to be transmitted to the bus (40) as a differential signal with respect to the first signal (CAN_H); a third transmitting stage (121C; 121C0; 121C5; 121C6) for generating at least one transmitting current (I1 to In; IC1) for the first signal (CAN_H); and a fourth transmitting stage (121D; 121D5) for generating at least one transmitting current (I1 to In; ID1) for the second signal (CAN_L), in, The first to fourth transmission stages are connected to form a full bridge, in which the first and fourth transmission stages (121A, 121D; 121A0, 121D; 121A5, 121D5; 121A6, 121D5) are connected in series, and the third and second transmission stages (121C, 121B; 121C0, 121B; 121C5, 121B5; 121C6, 121B5) are connected in series, wherein each of the transmission stages comprises at least two transistors (TM_CH1, TM_CHn; TM_CH, TM_CHs; TM_CL1, TM_CLn; TM_CL, TM_CLs; TC_CL1, TC_CLn; TC_CL, TC_CLs; TC_CH1, TC_CHn; TC_CH, TC_CHs) for generating the at least one transmission current (I1 to In; IA1; IB1, IC1; ID1), and The first transmission stage and the third transmission stage are connected to a connection (43) for bus voltage supply via reverse polarity diodes (D1; D2) for protection against positive feedback into the connection (43) for bus voltage supply and negative feedback from a connection (44) for ground.

2. The sending module (121; 1210; 1211; 1212) according to claim 1, in, The output terminals (41, 42) of the full bridge are provided for connection to a terminal resistor (49) of the bus (40).

3. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, in, The reverse polarity diode (D1; D2) is a switchable reverse polarity diode (D1; D2) that can be bridged or short-circuited.

4. The sending module (1210; 1212) according to any one of the preceding claims, in, The first and third transmitting stages (121A0, 121C0; 121A6, 121C6) are connected to a connection (43) for a bus voltage supply via the same reverse polarity diode (D1).

5. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, in, The reverse polarity diode (D1; D2) is arranged in a reverse polarity circuit (D_A; D_C; D_AC), which further comprises a first transistor (TR1; TR3), a second transistor (TR2; TR4) and a resistor (R1; R2), and The second transistor (TR2; TR4) has an on-resistance value that is much smaller than the resistance value of the resistor (R1; R2).

6. The sending module (121; 1210; 1211; 1212) according to claim 5, in, The drain terminal of the first transistor (TR1; TR3) is connected to the anode of the reverse polarity diode (D1; D2), wherein the source terminals of the first and second transistors (TR1, TR2; TR3, TR4) are connected to the cathodes of the reverse polarity diodes (D1; D2), wherein the gate terminal of the first transistor (TR1; TR3) is connected to the drain terminal of the second transistor (TR2; TR4) and to the terminal (44) for ground via the resistor (R1; R2), and The gate terminal of the second transistor (TR2; TR4) is connected to a terminal (43) for a bus voltage supply.

7. The sending module (121; 1210; 1211; 1212) according to claim 5 or 6, in, The path from the gate terminal to the source terminal of the first transistor (TR1; TR3) has a filter (R1, C1; R2, C2) for protection against pulse-like interference.

8. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, in, The second and fourth transmission stages (121B, 121D; 121B5, 121D5) each have a reverse polarity diode (D_B; D_D) for protection against positive feedback into the connection (43) for bus voltage supply and negative feedback from the connection (44) for ground, and The reverse polarity diodes (D_B; D_D) of the second transmitting stage (121B; 121B0) and the fourth transmitting stage (121D; 121D0) are respectively pn-based reverse polarity diodes (D_B; D_D), which are parasitic components of the transistor and are fixedly wired so that the reverse polarity diodes (D_B; D_D) cannot be bridged or short-circuited.

9. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, in, The reverse polarity diode (D1; D_B; D2; D_D) is designed to set a bus intermediate voltage (Vcm) of approximately 1.9 V when the transmitting module (121; 1210) is operated at a supply voltage of approximately 3.3 V.

10. A transmitting module (121; 1210; 1211; 1212) according to any of the preceding claims, further comprising a control circuit (T_A; T_B; T_C; T_D) for controlling the switchable components of the first to fourth transmitting stages in accordance with a digital transmitting signal (TxD) and in accordance with an operating mode (SIC; FAST_TX) set for the transmitting module (121; 1210; 1211; 1212).

11. The sending module (121; 1210) according to claim 10, in, The control circuit (T_A; T_B; T_C; T_D) is designed to switch at least two current levels (S1 to Sn) of the transmission stage (121A; 121A0; 121B; 121C; 121C0; 121D) in a temporally graded and controlled manner.

12. The sending module (1211; 1212) according to any one of the preceding claims, in, Each of the transmitting stages (121A5; 121A6; 121B5; 121C5; 121C6; 121D5) has a current mirror consisting of two transistors (TM_CH1, TM_CHn; TM_CH, TM_CHs; TM_CL, TM_CLs; TC_CL, TC_CLs; TC_CH, TC_CHs) for generating the at least one transmitting current (IA1; IB1, IC1; ID1).

13. The sending module (121; 1210) according to any one of claims 1 to 11, in, Each of the transmission stages (121A; 121A0; 121B; 121C; 121C0; 121D) has at least two current stages (S1 to Sn) connected in parallel, wherein each of the at least two current stages (S1 to Sn) comprises a transistor (TM_CH1, TM_CHn; TM_CL1, TM_CLn; TC_CL1, TC_CLn; TC_CH1, TC_CHn) for generating at least one transmission current (I1 to In; IA1; IB1, IC1; ID1), wherein at least two transistors have different parameters, and The number n of the at least two current levels ( S1 to Sn) is the same for each of the first to fourth transmitting stages, wherein n is a natural number greater than 1.

14. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, in, At least two transistors (TM_CH1, TM_CHn; TM_CH, TM_CHs; TM_CL1, TM_CLn; TM_CL, TM_CLs; TC_CL1, TC_CLn; TC_CL, TC_CLs; TC_CH1, TC_CHn; TC_CH, TC_CHs) used to generate the at least one transmission current (I1 to In; IA1; IB1, IC1; ID1) are CMOS transistors.

15. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, in, The CMOS transistors of the first transmitting stage (121A; 121A0; 121A5; 121A6) are PMOS transistors, Wherein, the CMOS transistors of the second transmitting stage (121B; 121B5) are NMOS transistors, The CMOS transistors of the third transmitting stage (121C; 121C0; 121C5; 121C6) are PMOS transistors, and The CMOS transistors of the fourth transmitting stage (121D; 121D5) are NMOS transistors.

16. A transmitting / receiving device (12; 22) for a subscriber station (20) of a serial bus system (1), the transmitting / receiving device comprising: A transmitting module (121; 1210; 1211; 1212) according to any one of the preceding claims; and A receiving module (122) is provided for receiving a signal from the bus (40).

17. A subscriber station (10; 20; 30) for a serial bus system (1), the subscriber station comprising: The transmitting / receiving device (12; 22) according to claim 16; and A communication control device (11; 21) is used to control the communication in the bus system (1) and to generate a digital transmission signal (TxD) for actuating the first to fourth transmission stages.

18. The user station (10; 20; 30) according to claim 17, in, The user station (10; 20; 30) is designed for communication in a bus system (1), in which exclusive, conflict-free access to a bus (40) of the bus system (1) is ensured at least temporarily for the user station (10, 20, 30).

19. A method for transmitting differential signals in a serial bus system (1), wherein: The method is implemented using a sending module (121; 1210; 1211; 1212), and comprises the following steps: generating, by means of a first transmission stage (121A; 121A0; 121A5; 121A6), at least one transmission current (I1 to In; IA1) for a first signal (CAN_H) to be transmitted on a bus (40) of the bus system (1), generating, by means of a second transmission stage (121B; 121B5), at least one transmission current (I1 to In; IB1) ​​for a second signal (CAN_L) which is to be transmitted on the bus (40) as a differential signal with respect to the first signal (CAN_H), generating at least one transmission current (I1 to In; IC1) for the first signal (CAN_H) by means of a third transmission stage (121C; 121C0; 121C5; 121C6), and generating at least one transmission current (I1 to In; ID1) for the second signal (CAN_L) by means of a fourth transmission stage (121D; 121D5), wherein the first to fourth transmission stages are connected to form a full bridge, in which the first and fourth transmission stages (121A, 121D; 121A0, 121D; 121A5, 121D5; 121A6, 121D5) are connected in series, and the third and second transmission stages (121C, 121B; 121C0, 121B; 121C5, 121B5; 121C6, 121B5) are connected in series, wherein each of the transmission stages comprises at least two transistors (TM_CH1, TM_CHn; TM_CH, TM_CHs; TM_CL1, TM_CLn; TM_CL, TM_CLs; TC_CL1, TC_CLn; TC_CL, TC_CLs; TC_CH1, TC_CHn; TC_CH, TC_CHs) for generating the at least one transmission current (I1 to In; IA1; IB1, IC1; ID1), and The first and third transmission stages are connected to a connection (43) for a bus voltage supply via reverse polarity diodes (D1; D2) for protection against positive feedback into the connection (43) for the bus voltage supply and negative feedback from a connection (44) for ground.

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