Semiconductor device and preparation method thereof, and gate drive circuit

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and a gate drive circuit, the semiconductor device comprises a drain electrode, an active layer, a first dielectric layer, a second dielectric layer, a source electrode and a first modulation part, and the active layer is arranged on one side of the drain electrode in the thickness direction; the first dielectric layer is arranged on one side, deviating from the drain, of the active layer; the second dielectric layer is arranged on the side, away from the drain electrode, of the first dielectric layer, and the second dielectric layer and the first dielectric layer are insulated and spaced; the source electrode is arranged on the side, away from the drain electrode, of the second dielectric layer, and the source electrode and the second dielectric layer are insulated and spaced; the first modulation part is electrically connected with the second dielectric layer, and the first modulation part is arranged on the side, away from the drain electrode, of the second dielectric layer; wherein a first insulating layer is further arranged on the side, away from the drain electrode, of the active layer, the first dielectric layer covers the active layer and the first insulating layer, the first dielectric layer close to the active layer is reused as a grid electrode, and the first dielectric layer away from the active layer and the second dielectric layer form a storage capacitor.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device, a preparation method thereof, and a gate drive circuit. Background Art

[0002] Semiconductor devices are widely used in high-frequency and high-voltage scenarios due to their advantages such as fast response speed, small size, and low power consumption. They use their high-speed switching capabilities to perform tasks such as logical operations and data transmission.

[0003] Currently, the switching performance of semiconductor devices still needs to be further optimized. Summary of the Invention

[0004] The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and a gate drive circuit, which can achieve rapid shutdown of the semiconductor device and improve the reliability of the device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, which includes a drain, an active layer, a first dielectric layer, a second dielectric layer, a source, and a first modulation unit, wherein the active layer is arranged on one side of the drain in the thickness direction; the first dielectric layer is arranged on the side of the active layer facing away from the drain; the second dielectric layer is arranged on the side of the first dielectric layer facing away from the drain, and the second dielectric layer and the first dielectric layer are insulated and spaced apart; the source is arranged on the side of the second dielectric layer facing away from the drain, the source and the second dielectric layer are in ohmic contact with the active layer; the first modulation unit is electrically connected to the second dielectric layer, the first modulation unit is arranged on the side of the second dielectric layer facing away from the drain, and the first modulation unit is used to connect to an external potential; wherein a first insulating layer is further provided on the side of the active layer facing away from the drain, the first dielectric layer covers the active layer and the first insulating layer, the first dielectric layer close to the active layer is reused as a gate, and the first dielectric layer and the second dielectric layer away from the active layer form a storage capacitor.

[0006] In some optional embodiments, the first modulation portion includes a polysilicon material, a doping type of the first modulation portion is the same as a doping type of the first dielectric layer, and the first modulation portion is insulated and spaced apart from the source.

[0007] In some optional embodiments, the semiconductor device also includes a second modulation portion, which is arranged on a side of the second dielectric layer away from the drain and is insulated from the second dielectric layer. The second modulation portion includes polysilicon material, and the doping type of the second modulation portion is the same as the doping type of the first dielectric layer.

[0008] In some optional embodiments, the orthographic projection of the second modulation portion on the active layer does not overlap with the orthographic projection of the source electrode on the active layer, and the orthographic projection of the second modulation portion on the active layer is connected to or partially overlaps with the orthographic projection of the first dielectric layer on the active layer.

[0009] In some optional embodiments, the semiconductor device also includes a voltage-stabilizing structure having an opposite doping type to that of the first dielectric layer. The voltage-stabilizing structure is arranged on a side of the active layer away from the drain. The voltage-stabilizing structure is insulated and spaced apart from the active layer. A first dielectric layer is formed on both sides of the voltage-stabilizing structure along the first direction.

[0010] In some optional embodiments, the semiconductor device further includes a first interconnection electrically connected to the source, and along the first direction, the orthographic projection of the first interconnection on the active layer and the orthographic projection of the gate on the active layer are located on both sides of the orthographic projection of the voltage stabilizing structure on the active layer.

[0011] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device provided by any embodiment of the first aspect, and the preparation method includes:

[0012] forming a first insulating dielectric material layer on one side of the active layer, and patterning the first insulating dielectric material layer to obtain a first insulating layer;

[0013] forming a first dielectric layer on one side of the first insulating layer;

[0014] forming a second insulating layer on a side of the first dielectric layer away from the active layer, and forming a second dielectric layer on one side of the second insulating layer;

[0015] The second dielectric layer is patterned to obtain a first via hole, and a first modulation portion is formed in the first via hole.

[0016] In some optional embodiments, the preparation method further comprises:

[0017] Performing patterning on the first dielectric layer to obtain a second via hole, and forming a voltage stabilizing structure in the second via hole; or,

[0018] A first mask is provided on the first dielectric layer, and P-type ion implantation is performed on the first dielectric layer not covered by the first mask to form a voltage stabilizing structure.

[0019] In a third aspect, an embodiment of the present application provides a gate drive circuit, which is used to control the on or off of a semiconductor device. The gate drive circuit includes:

[0020] An input module, configured to provide a first voltage or a second voltage;

[0021] a first resistor, wherein a first end of the first resistor is connected to an output end of the input module;

[0022] a first capacitor, wherein a first electrode of the first capacitor is connected to the second end of the first resistor, and a second electrode of the first capacitor is connected to the gate of the semiconductor device;

[0023] A second resistor, wherein a first end of the second resistor is connected to the output end of the input module, and a second end of the second resistor is connected to the gate of the semiconductor device.

[0024] In some optional embodiments, the gate drive circuit further includes a voltage stabilizing module, which includes two Zener diodes connected in reverse series, one end of the voltage stabilizing module is connected to the second electrode of the first capacitor and the other end is connected to the source of the semiconductor device.

[0025] The semiconductor device provided in an embodiment of the present application has a first dielectric layer integrated above the active layer. The first dielectric layer is separated from the active layer by a first insulating layer, and the first dielectric layer can serve as a gate to control the on and off of the semiconductor device. The semiconductor device also has a second dielectric layer insulated above the first dielectric layer. The second dielectric layer can cooperate with the first dielectric layer to form a storage capacitor, so that the potential of the first dielectric layer can change instantaneously in response to changes in the potential of the second dielectric layer, thereby achieving rapid shutdown of the semiconductor device. The semiconductor device also integrates a first modulation unit electrically connected to the second dielectric layer. The first modulation unit is connected to an external potential to change the potential of the second dielectric layer and the first dielectric layer to achieve device switching control. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 This is a schematic structural diagram of a semiconductor device according to some embodiments of the present application;

[0028] Figure 2 A schematic diagram of a layout of a semiconductor device according to some embodiments of the present application;

[0029] Figures 3 to 9 Schematic diagram of the manufacturing process of semiconductor devices according to some embodiments of the present application;

[0030] Figure 10 This is a connection diagram of the gate drive circuit of some embodiments of the present application.

[0031] The drawings are not necessarily drawn to scale.

[0032] The specific marking information in the accompanying drawings is as follows:

[0033] 110, drain; 120, source;

[0034] 200, active layer;

[0035] 310, first dielectric layer; 320, second dielectric layer;

[0036] 410, first insulating layer; 420, second insulating layer; 430, passivation layer;

[0037] 510, first modulation unit; 520, second modulation unit;

[0038] 600, voltage stabilizing structure; 610, first interconnection portion;

[0039] 700, photoresist;

[0040] 01. Input module; 02. First resistor; 03. First capacitor; 04. Second resistor; 05. Voltage regulator module;

[0041] Thickness direction Z. DETAILED DESCRIPTION

[0042] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0044] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0045] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0047] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0048] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0049] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0050] Semiconductor devices represented by Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) are widely used in high-frequency and high-voltage scenarios due to their advantages such as fast response speed, small size, and low power consumption. They use their high-speed switching capabilities to perform tasks such as logical operations and data transmission.

[0051] Specifically, using a bridge circuit as an example, to prevent shoot-through caused by simultaneous conduction of the upper and lower bridge switching semiconductor devices, it is necessary to wait for a dead time after one device is turned off before turning the other on. During this dead time, the load current must flow through the freewheeling diode, resulting in additional conduction losses. Therefore, semiconductor devices with slower turn-off speeds extend the dead time of the bridge circuit, exacerbating dead time losses and reducing system efficiency.

[0052] Moreover, in a bridge circuit, when device A is turned off, the rapidly changing voltage in the bridge arm may cause the gate voltage of device A to rise instantaneously, causing device A to be turned on for a short time unexpectedly, or even turned on at the same time as device B, resulting in a short circuit.

[0053] Therefore, it is necessary to optimize the switching performance of semiconductor devices to meet the usage scenarios that require fast switching, such as bridge circuits.

[0054] To solve the problems of the prior art, the present invention provides a semiconductor device and a method for manufacturing the same, as well as a gate drive circuit, which can shorten the turn-off time of the semiconductor device.

[0055] Please see below Figure 1 and Figure 2 , Figure 1 This is a schematic structural diagram of a semiconductor device according to some embodiments of the present application; Figure 2 Schematic diagram of the layout of the semiconductor device according to some embodiments of the present application.

[0056] In a first aspect, an embodiment of the present application provides a semiconductor device, which includes a drain 110, an active layer 200, a first dielectric layer 310, a second dielectric layer 320, and a source 120, wherein the active layer 200 is arranged on one side of the drain 110 in the thickness direction; the first dielectric layer 310 is arranged on the side of the active layer 200 away from the drain 110; the second dielectric layer 320 is arranged on the side of the first dielectric layer 310 away from the drain 110, and the second dielectric layer 320 is insulated from the first dielectric layer 310; the source 120 is provided. 20 is arranged on the side of the second dielectric layer 320 away from the drain electrode 110, the source electrode 120 and the second dielectric layer 320 are insulated and spaced apart, and the source electrode 120 is in ohmic contact with the active layer 200; wherein, a first insulating layer 410 is further provided on the side of the active layer 200 away from the drain electrode 110, the first dielectric layer 310 covers the active layer 200 and the first insulating layer 410, the first dielectric layer 310 close to the active layer 200 is reused as a gate, and the first dielectric layer 310 and the second dielectric layer 320 away from the active layer 200 form a storage capacitor.

[0057] It can be understood that the first dielectric layer 310 and the second dielectric layer 320 are conductive layers. Optionally, the first dielectric layer 310 and the second dielectric layer 320 are made of the same material, or the first dielectric layer 310 and the second dielectric layer 320 are made of different materials.

[0058] Exemplarily, the first dielectric layer 310 is made of polysilicon material so that the first dielectric layer 310 can be reused as the plate of the storage capacitor and the gate of the semiconductor device, and the low defect density at the interface between polysilicon and oxide can improve the leakage current of the semiconductor device at the gate oxide dielectric.

[0059] Exemplarily, the second dielectric layer 320 is made of polysilicon material.

[0060] Specifically, a second insulating layer 420 is provided between the first dielectric layer 310 and the second dielectric layer 320 to achieve an insulating gap between the two electrodes of the storage capacitor.

[0061] It can be understood that a passivation layer 430 is further formed between the second dielectric layer 320 and the source electrode 120 to achieve an insulating gap between the storage capacitor and the source electrode 120 .

[0062] Thus, the semiconductor device is integrated with a storage capacitor and a gate above the active layer 200 , and the gate potential can change instantaneously in response to the potential change of the second dielectric layer 320 , thereby increasing the speed of the shutdown signal being transmitted to the gate.

[0063] In addition, due to the presence of the storage capacitor, a higher external potential is required to drive the semiconductor device to turn on after the capacitor is charged. The voltage drop during the transition from on to off of the external potential becomes larger. When the driving potential remains unchanged, the voltage drop of the semiconductor device increases, causing the off voltage of the semiconductor device to become more negative, thereby increasing the shutdown speed and improving the safety of the semiconductor device.

[0064] Moreover, since the turn-off voltage of the semiconductor device becomes more negative, the voltage of one of the devices in the bridge circuit after being raised is further reduced, thereby reducing the probability of the device being accidentally turned on, thereby avoiding the occurrence of a direct short circuit caused by the upper and lower tubes being turned on at the same time.

[0065] The semiconductor device provided in the embodiment of the first aspect of the present application is also integrated with a first modulation part 510 for connecting to an external potential. The first modulation part 510 is electrically connected to the second dielectric layer 320 and is arranged on the side of the second dielectric layer 320 away from the drain 110.

[0066] Therefore, the first modulation unit 510 is provided between the external potential and the storage capacitor to form a resistor, so as to suppress a shoot-through short circuit phenomenon that may occur in the bridge circuit.

[0067] According to some embodiments of the first aspect of the present application, the first modulation portion 510 includes a polysilicon material, and the first modulation portion 510 is insulated and spaced apart from the source 120 .

[0068] Optionally, the doping type of the first modulation portion 510 is the same as the doping type of the first dielectric layer 310. Exemplarily, the first modulation portion 510 is N-type doped.

[0069] Optionally, the doping type of the first modulation portion 510 is different from the doping type of the first dielectric layer 310 .

[0070] Therefore, the processing of the first modulation portion 510 is facilitated, and the interface quality between the first modulation portion 510 and the oxide insulator in the semiconductor device is improved to improve leakage current or other defects that may occur in the device.

[0071] According to some embodiments of the first aspect of the present application, the semiconductor device further includes a second modulation portion 520 , which is disposed on a side of the second dielectric layer 320 away from the drain 110 and is insulated from the second dielectric layer 320 .

[0072] Specifically, the second modulation section 520 is electrically connected to the first modulation section 510 and the gate. That is, the second modulation section 520 is connected in parallel to both sides of the first modulation section 510 and the storage capacitor.

[0073] Optionally, the second modulation portion 520 is made of the same material as the first modulation portion 510 .

[0074] Further optionally, the second modulation portion 520 includes polysilicon material.

[0075] Further optionally, the doping type of the second modulation portion 520 is the same as the doping type of the first dielectric layer 310 .

[0076] Optionally, the resistance of the second modulation part 520 is greater than the resistance of the first modulation part 510 to avoid a short circuit at the second modulation part 520 .

[0077] Further optionally, the resistance of the second modulation unit 520 is R2, the resistance of the first modulation unit 510 is R1, R2 ≥ mR1, where m ≥ 5. Thus, the effect of the second modulation unit 520 on consuming the charge in the storage capacitor is accelerated.

[0078] Further optionally, m≥10.

[0079] Optionally, the source 120 of the semiconductor device comprises polysilicon material, and the doping type of the source 120 is the same as the doping type of the second modulation portion 520. Thus, the electrically interconnected source 120 and the second modulation portion 520 can be fabricated simultaneously, reducing the difficulty of fabricating the semiconductor device.

[0080] Thus, the second modulation unit 520 can form a resistor. After the semiconductor device is turned off, the charge stored in the storage capacitor can be discharged through the circuit formed by the storage capacitor, the first modulation unit 510 and the second modulation unit 520 to achieve negative voltage shutdown when the semiconductor device is turned on next time.

[0081] According to some embodiments of the first aspect of the present application, the orthographic projection of the second modulation portion 520 on the active layer 200 does not overlap with the orthographic projection of the source electrode 120 on the active layer 200, and the orthographic projection of the second modulation portion 520 on the active layer 200 is connected to or partially overlaps with the orthographic projection of the first dielectric layer 310 on the active layer 200.

[0082] Optionally, the orthographic projection of the second modulation portion 520 on the active layer 200 is connected to or partially overlaps with the orthographic projection of the first modulation portion 510 on the active layer 200 .

[0083] Optionally, the orthographic projection of the second modulation portion 520 on the active layer 200 is spaced apart from the orthographic projection of the first modulation portion 510 on the active layer 200 , and the second modulation portion 520 and the first modulation portion 510 are electrically connected via interconnecting metal or other structures.

[0084] Thus, the second modulation unit 520 is conveniently electrically connected to the electrode on the same side of the storage capacitor and the gate through a via or other structure.

[0085] According to some embodiments of the first aspect of the present application, the semiconductor device further includes a voltage-stabilizing structure 600 having an opposite doping type to the first dielectric layer 310. The voltage-stabilizing structure 600 is disposed on a side of the active layer 200 facing away from the drain 110. The voltage-stabilizing structure 600 is insulated and spaced apart from the active layer 200. Along the first direction, the first dielectric layer 310 is formed on both sides of the voltage-stabilizing structure 600.

[0086] Optionally, one voltage stabilizing structure 600 is provided. Exemplarily, the voltage stabilizing structure 600 includes P-type doped polysilicon, and two Zener diodes connected in reverse series can be formed on both sides of the voltage stabilizing structure 600 along the first direction.

[0087] Optionally, a plurality of voltage stabilizing structures 600 are provided.

[0088] Therefore, by setting a voltage stabilizing structure 600 of opposite doping type in the first dielectric layer 310, at least two diodes connected in series and with opposite current directions can be formed, which can improve the gate threshold voltage drift phenomenon of the semiconductor device and reduce the probability of overvoltage breakdown of the gate oxide layer.

[0089] According to some embodiments of the first aspect of the present application, the semiconductor device also includes a first interconnection 610 electrically connected to the source 120. Along the first direction, the orthographic projection of the first interconnection 610 on the active layer 200 and the orthographic projection of the gate on the active layer 200 are located on both sides of the orthographic projection of the voltage stabilizing structure 600 on the active layer 200.

[0090] Thus, the voltage stabilizing structure 600 is electrically connected to the source 120 through the first interconnect 610. By integrating the voltage stabilizing structure 600 in the semiconductor device, the voltage stabilizing structure 600 can be placed close to the gate-source pins, shortening the protection path and avoiding the introduction of additional inductance.

[0091] In a second aspect, the present application provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device provided by any embodiment of the first aspect. The process diagram of the preparation method can be found in Figures 3 to 9 , the preparation method comprises:

[0092] S100 , forming a first insulating dielectric material layer on one side of the active layer 200 , and patterning the first insulating dielectric material layer to obtain a first insulating layer 410 ;

[0093] S200 , forming a first dielectric layer 310 on one side of the first insulating layer 410 ;

[0094] S300 , forming a second insulating layer 420 on a side of the first dielectric layer 310 away from the active layer 200 , and forming a second dielectric layer 320 on one side of the second insulating layer 420 ;

[0095] S400 , patterning the second dielectric layer 320 to obtain a first via hole, and forming a first modulation portion 510 in the first via hole.

[0096] Optionally, in step S400 , a photolithography process is performed on the second dielectric layer 320 to perform patterning.

[0097] According to some embodiments of the second aspect of the present application, the preparation method further includes:

[0098] S510A: Patterning the first dielectric layer 310 to obtain a second via hole, and forming a voltage-stabilizing structure 600 in the second via hole.

[0099] Optionally, in step S510A, a photolithography process is performed on the first dielectric layer 310 to perform patterning. Figure 6 After covering the area to be retained with photoresist 700, photolithography is performed to obtain a second via hole.

[0100] According to some embodiments of the second aspect of the present application, the preparation method further includes:

[0101] S510B, setting a first mask on the first dielectric layer 310 , and performing P-type ion implantation on the first dielectric layer 310 not covered by the first mask to form a voltage stabilizing structure 600 .

[0102] In a third aspect, the present invention provides a gate drive circuit, which is used to control the on or off of a semiconductor device. For a connection diagram of the gate drive circuit, please refer to Figure 10 , the gate drive circuit includes:

[0103] Input module 01, used to provide a first voltage or a second voltage;

[0104] A first resistor 02, wherein a first end of the first resistor 02 is connected to an output end of the input module 01;

[0105] a first capacitor 03 , wherein a first electrode of the first capacitor 03 is connected to the second end of the first resistor 02 , and a second electrode of the first capacitor 03 is connected to the gate of the semiconductor device;

[0106] The second resistor 04 has a first end connected to the output end of the input module 01 , and a second end connected to the gate of the semiconductor device.

[0107] Thus, by providing the first resistor 02 and the first capacitor 03 in series between the input module 01 and the gate, when the semiconductor device needs to be turned on, the first voltage passes through the first resistor 02 to charge the first capacitor 03. After the first capacitor 03 is charged, the semiconductor device turns on in response to the first voltage. When the semiconductor device needs to be turned off, the second voltage passes through the first resistor 02 to reach the first electrode of the first capacitor 03. The second electrode of the first capacitor 03 changes instantaneously in response to the voltage change of the first electrode, so that the second voltage can reach the gate of the semiconductor device more quickly to turn it off.

[0108] Furthermore, due to losses in the transmission of the first voltage to the gate of the semiconductor device, the gate of the semiconductor device can receive a voltage signal less than the second voltage when the voltage drops across the first capacitor 03 are the same, further improving the reliability of the semiconductor device. The gate drive circuit also includes a second resistor 04 connected in parallel between the first resistor 02 and the first capacitor 03. The second resistor 04 can be used to discharge the first capacitor 03, allowing the semiconductor device to achieve a rapid shutdown effect the next time it is driven.

[0109] In combination with the semiconductor device provided in any embodiment of the first aspect, it can be understood that the gate drive circuit provided in the embodiment of the third aspect of the present application can be directly integrated with the semiconductor device to further reduce the switching loss of the semiconductor device.

[0110] According to some embodiments of the third aspect of the present application, the gate drive circuit further includes a voltage stabilizing module 05 , one end of the voltage stabilizing module 05 is connected to the second electrode of the first capacitor 03 and the other end is connected to the source 120 of the semiconductor device.

[0111] Optionally, the voltage stabilizing module 05 includes two Zener diodes connected in reverse series.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: drain; an active layer, disposed on one side of the drain electrode in a thickness direction; a first dielectric layer, disposed on a side of the active layer away from the drain electrode; a second dielectric layer, disposed on a side of the first dielectric layer away from the drain electrode, the second dielectric layer being insulated and spaced apart from the first dielectric layer; a source electrode, disposed on a side of the second dielectric layer away from the drain electrode, the source electrode being insulated and spaced apart from the second dielectric layer, and being in ohmic contact with the active layer; a first modulation portion electrically connected to the second dielectric layer, the first modulation portion being disposed on a side of the second dielectric layer away from the drain electrode, and being configured to connect to an external potential; In which, a first insulating layer is also provided on the side of the active layer away from the drain, the first dielectric layer covers the active layer and the first insulating layer, the first dielectric layer close to the active layer is reused as a gate, and the first dielectric layer and the second dielectric layer away from the active layer form a storage capacitor.

2. The semiconductor device according to claim 1, wherein The first modulation portion comprises polysilicon material, the doping type of the first modulation portion is the same as the doping type of the first dielectric layer, and the first modulation portion is insulated and spaced apart from the source.

3. The semiconductor device according to claim 1, wherein The semiconductor device also includes a second modulation part, which is arranged on a side of the second dielectric layer away from the drain and is insulated from the second dielectric layer. The second modulation part includes polysilicon material, and the doping type of the second modulation part is the same as the doping type of the first dielectric layer.

4. The semiconductor device according to claim 3, wherein The orthographic projection of the second modulation portion on the active layer does not overlap with the orthographic projection of the source electrode on the active layer, and the orthographic projection of the second modulation portion on the active layer is connected to or partially overlaps with the orthographic projection of the first dielectric layer on the active layer.

5. The semiconductor device according to claim 1, wherein The semiconductor device also includes a voltage-stabilizing structure with an opposite doping type to that of the first dielectric layer. The voltage-stabilizing structure is arranged on a side of the active layer away from the drain. The voltage-stabilizing structure is insulated and spaced apart from the active layer. Along the first direction, the first dielectric layer is formed on both sides of the voltage-stabilizing structure.

6. The semiconductor device according to claim 5, wherein The semiconductor device also includes a first interconnection electrically connected to the source. Along the first direction, the orthographic projection of the first interconnection on the active layer and the orthographic projection of the gate on the active layer are located on both sides of the orthographic projection of the voltage stabilizing structure on the active layer.

7. A method for preparing a semiconductor device, for preparing the semiconductor device according to any one of claims 1 to 6, characterized in that: The preparation method comprises: forming a first insulating dielectric material layer on one side of the active layer, and patterning the first insulating dielectric material layer to obtain a first insulating layer; forming a first dielectric layer on one side of the first insulating layer; forming a second insulating layer on a side of the first dielectric layer away from the active layer, and forming a second dielectric layer on one side of the second insulating layer; The second dielectric layer is patterned to obtain a first via hole, and a first modulation portion is formed in the first via hole.

8. The method for preparing a semiconductor device according to claim 7, wherein: The preparation method further comprises: Performing patterning on the first dielectric layer to obtain a second via hole, and forming a voltage stabilizing structure in the second via hole; or, A first mask is provided on the first dielectric layer, and P-type ion implantation is performed on the first dielectric layer not covered by the first mask to form a voltage stabilizing structure.

9. A gate drive circuit for controlling the on or off of a semiconductor device, characterized in that: include: An input module, configured to provide a first voltage or a second voltage; a first resistor, wherein a first end of the first resistor is connected to an output end of the input module; a first capacitor, wherein a first electrode of the first capacitor is connected to the second end of the first resistor, and a second electrode of the first capacitor is connected to the gate of the semiconductor device; A second resistor, wherein a first end of the second resistor is connected to the output end of the input module, and a second end of the second resistor is connected to the gate of the semiconductor device.

10. The gate driving circuit according to claim 9, wherein: The gate drive circuit further includes a voltage stabilizing module, which includes two Zener diodes connected in reverse series. One end of the voltage stabilizing module is connected to the second electrode of the first capacitor and the other end is connected to the source of the semiconductor device.

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