Semiconductor device

Abstract

A semiconductor device includes a substrate and a first block on the substrate. The first block includes a first source / drain pattern, a second source / drain pattern, and a third source / drain pattern between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern, the second source / drain pattern, and the third source / drain pattern being spaced apart in a first direction parallel to an upper surface of the substrate. The first lower power line is on the lower portion of the substrate, and the second lower power line is spaced apart from the first lower power line in a first direction, the first and second lower power lines extending in the first direction. A first back surface via is in the substrate connecting the first lower power line and the first source / drain pattern. A second rear surface via is in the substrate connecting the second lower power line and the second source / drain pattern. A third rear surface via is in the substrate, connected to the third source / drain pattern, and extends in a second direction perpendicular to the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the patent application filed on March 20, 2024, Korean Patent Application No.

[0003] 10-2024-0038287, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The present disclosure herein relates to semiconductor devices, and more particularly, to semiconductor devices including field effect transistors. Background Art

[0005] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOSFETs). As the size and design rules of semiconductor devices gradually decrease, the scaling down of MOSFETs is gradually accelerating. When MOSFETs are scaled down, the operating characteristics of the semiconductor device may deteriorate. Therefore, various methods are being studied to overcome the limitations caused by the high integration density of semiconductor devices and to form semiconductor devices with improved performance. Summary of the Invention

[0006] The present disclosure provides a semiconductor device having improved electrical characteristics and reliability.

[0007] An embodiment of the inventive concept provides a semiconductor device including a substrate and a first block on the substrate, wherein the first block includes a first source / drain pattern, a second source / drain pattern, and a third source / drain pattern between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern, the second source / drain pattern, and the third source / drain pattern being spaced apart from each other in a first direction parallel to an upper surface of the substrate; a first lower power line and a second lower power line, the first lower power line being located on a lower portion of the substrate, the second lower power line being located on a lower portion of the substrate, A first rear surface via is located in the substrate and connects the first lower power line to the first source / drain pattern; a second rear surface via is located in the substrate and connects the second lower power line to the second source / drain pattern; and a third rear surface via is located in the substrate and connected to the third source / drain pattern, and the third rear surface via extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction.

[0008] In an embodiment of the present invention, a semiconductor device includes: a channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; a first source / drain pattern and a second source / drain pattern respectively connected to opposite sides of the channel pattern and spaced apart from each other in a first direction; a gate electrode located on the channel pattern and including a plurality of internal electrodes located between the plurality of semiconductor patterns; a first rear surface via connected to the first source / drain pattern; a second rear surface via connected to the second source / drain pattern; a lower power line located below at least one of the first rear surface via and the second rear surface via and connected to at least one of the first rear surface via and the second rear surface via; an interlayer insulating layer located on the first source / drain pattern and the second source / drain pattern and in contact with upper surfaces of the first source / drain pattern and the second source / drain pattern; and a first insulating pattern located between the first rear surface via and the second rear surface via.

[0009] In an embodiment of the present inventive concept, a semiconductor device includes an insulating substrate and a first block and a second block on the insulating substrate, wherein the first block includes: a first source / drain pattern, a second source / drain pattern, and a third source / drain pattern between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern, the second source / drain pattern, and the third source / drain pattern being spaced apart from each other in a first direction parallel to an upper surface of the insulating substrate; a first lower power line and a second lower power line, the first lower power line being located on a lower portion of the insulating substrate, the second lower power line being spaced apart from the first lower power line in the first direction, the first lower power line and the second lower power line extending in the first direction; and a first rear surface via member located on the insulating substrate. and connecting the first lower power line and the first source / drain pattern; a second rear surface via, which is located in the insulating substrate and connects the second lower power line and the second source / drain pattern; and a third rear surface via, which is located in the insulating substrate and connected to the third source / drain pattern, the second block includes: a channel pattern, which includes a plurality of semiconductor patterns stacked and spaced apart from each other; and a fourth source / drain pattern and a fifth source / drain pattern, respectively connected to opposite sides of the channel pattern and spaced apart from each other in the first direction, and the third rear surface via extends in a second direction parallel to the upper surface of the insulating substrate and perpendicular to the first direction to be connected to any one of the fourth source / drain pattern and the fifth source / drain pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0011] Figure 1 is a plan view for describing a semiconductor device according to an embodiment of the inventive concept;

[0012] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D and Figure 2E It is along Figure 1 corresponding cross-sectional views taken along lines AA', BB', CC', DD' and EE';

[0013] Figure 3A is a schematic diagram showing the arrangement of Figure 1 A perspective view of a transistor in a region R1;

[0014] Figure 3B yes Figure 2A An enlarged view of block A1;

[0015] Figure 4 is a schematic diagram showing the arrangement of Figure 1 A perspective view of the transistor in the region R2;

[0016] Figure 5 is a schematic diagram showing the arrangement of Figure 1 A perspective view of the transistor in the region R3;

[0017] Figure 6 is a schematic diagram showing the arrangement of Figure 1 A perspective view of the connections of transistors in regions R1, R2, and R3;

[0018] Figure 7 is a schematic diagram showing the arrangement of Figure 1 A perspective view of transistors in region R4;

[0019] Figure 8 is a schematic diagram showing the arrangement of Figure 1 A perspective view of transistors in region R5;

[0020] as well as

[0021] 9A to 9H is a cross-sectional view for describing a method of fabricating a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0022] Hereinafter, a semiconductor device according to the inventive concept will be described with reference to the accompanying drawings.

[0023] Figure 1 is a plan view for describing a semiconductor device according to an embodiment of the inventive concept. Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D and Figure 2E It is along Figure 1 Corresponding cross-sectional views taken along lines AA', BB', CC', DD' and EE'. Figure 3A is a schematic diagram showing the arrangement of Figure 1 A three-dimensional diagram of the transistor in region R1. Figure 3B yes Figure 2A An enlarged view of block A1. Figure 4 is a schematic diagram showing the arrangement of Figure 1 A three-dimensional diagram of the transistor in region R2. Figure 5 is a schematic diagram showing the arrangement of Figure 1 A three-dimensional diagram of the transistor in region R3.

[0024] Figure 6 is a schematic diagram showing the arrangement of Figure 1 A perspective view of the connections of transistors in regions R1, R2, and R3. Figure 7 is a schematic diagram showing the arrangement of Figure 1 A three-dimensional diagram of the transistor in region R4. Figure 8 is a schematic diagram showing the arrangement of Figure 1 A three-dimensional diagram of the transistor in region R5.

[0025] Reference Figure 1 , a plurality of blocks provided on the substrate 105 may be provided. Each of the blocks includes at least one transistor. As used herein, the term "block" refers to a unit of a collection in which corresponding transistors perform a specific function. For example, as described later, a block may include a power gate block PGB, a switch block SWB, an operation block OPB, etc. (see Figure 6 ). The power gating block PGB can control the power supply to a specific block inside the semiconductor device. In addition, the power gating block PGB can be connected to the switch block SWB to supply or block power to a specific block as needed. The switch block SWB may include a switching transistor. The switching transistor can control the flow of current to switch the "on" and "off" states of the electrical signal. For example, when a voltage of at least a threshold voltage is applied to the control terminal (e.g., a gate), the switching transistor may have an "on" state. The operation block may include a logic unit in which transistors constituting a logic circuit for performing a specific function are provided. The logic unit may represent a logic element (e.g., an AND gate, an OR gate, an XOR gate, an XNOR gate, an inverter, etc.) that performs a specific function.

[0026] For example, the substrate 105 may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may extend in a first direction D1.

[0027] The substrate 105 may include a first region R1, a second region R2, a third region R3, a fourth region R4, and a fifth region R5. Each of the first to fifth regions R1 to R5 may be located in any one of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2. For example, the first region R1 may be located in the first PMOSFET region PR1, the second region R2 may be located in the second PMOSFET region PR2, the third region R3 may be located in the second PMOSFET region PR2, the fourth region R4 may be located in the first NMOSFET region NR1, and the fifth region R5 may be located in the second NMOSFET region NR2. The above placement relationship is an example, and the first to fifth regions R1 to R5 may be located differently in the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2.

[0028] In this specification, the configuration of the transistor provided in the first PMOSFET region PR1 may be structurally identical or similar to the configuration of the transistor provided in the second PMOSFET region PR2. In addition, the configuration of the transistor provided in the first NMOSFET region NR1 may be structurally identical or similar to the configuration of the transistor provided in the second NMOSFET region NR2.

[0029] For ease of description, reference will be made to Figure 2A The common parts in describing the PMOSFETs on the first PMOSFET region PR1 and the second PMOSFET region PR2 will be described, and reference will be made to Figure 2D Common portions in describing the NMOSFETs on the first NMOSFET region NR1 and the second NMOSFET region NR2 are described.

[0030] Reference Figure 1 、 Figure 2A and Figure 2DThe first and second insulating patterns AP1 and AP2 may be defined by a trench TR formed on the substrate 105. The first insulating pattern AP1 may be disposed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second insulating pattern AP2 may be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. The first and second insulating patterns AP1 and AP2 may extend in the first direction D1. The first and second insulating patterns AP1 and AP2 may be vertical protrusions that are part of the substrate 105. An element isolation film ST may be located in the trench TR (e.g., may fill the trench TR). The element isolation film ST may be located on the sidewalls of each of the first and second insulating patterns AP1 and AP2 (e.g., may cover the sidewalls of each of the first and second insulating patterns AP1 and AP2). For example, the element isolation film ST may include a silicon oxide film. The first and second insulating patterns AP1 and AP2 (and therefore the substrate 105 that may include the first and second insulating patterns AP1 and AP2) may include at least any one of silicon nitride, silicon oxide, and silicon carbide.

[0031] An etch stop layer (ESL) may be disposed on each of the first insulating pattern AP1 and the second insulating pattern AP2. For example, the etch stop layer (ESL) may include silicon doped with oxygen (O), carbon (C), or a combination thereof. The etch stop layer (ESL) may have a single crystal structure. The concentration of impurities (oxygen, carbon, or a combination thereof) in the etch stop layer (ESL) may be approximately 0.5 at% to approximately 2 at%. In some embodiments, the etch stop layer (ESL) may be omitted.

[0032] Each of the first and second channel patterns CH1 and CH2 may include sequentially stacked first, second, and third semiconductor patterns SP1, SP2, and SP3. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (ie, a third direction D3).

[0033] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon. Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be a nanosheet.

[0034] like Figure 2AAs shown in FIG, a plurality of first conductive source / drain patterns SDA may be disposed on the first insulating pattern AP1. A plurality of first recesses RS1 may be formed on the first insulating pattern AP1. The first conductive source / drain patterns SDA may be disposed in each of the first recesses RS1. The first conductive source / drain patterns SDA may be first conductive (e.g., p-type) impurity regions. The first channel pattern CH1 may be interposed between the pair of first conductive source / drain patterns SDA. In other words, the stacked first to third semiconductor patterns SP1, SP2, and SP3 may connect (e.g., electrically connect) the pair of first conductive source / drain patterns SDA.

[0035] like Figure 2D As shown in FIG, a plurality of second conductive source / drain patterns SDB may be disposed on the second insulating pattern AP2. A plurality of second recesses RS2 may be formed on the second insulating pattern AP2. The second conductive source / drain patterns SDB may be disposed in the second recesses RS2, respectively. The second conductive source / drain patterns SDB may be second conductive (e.g., n-type) impurity regions. The second channel pattern CH2 may be interposed between the pair of second conductive source / drain patterns SDB. In other words, the stacked first to third semiconductor patterns SP1, SP2, and SP3 may connect (e.g., electrically connect) the pair of second conductive source / drain patterns SDB.

[0036] like Figure 2AAs shown in FIG, each of the first conductive source / drain patterns SDA may include a buffer layer BFL and a main layer MAL on the buffer layer BFL. The buffer layer BFL may cover the inner sidewalls of the first recess RS1. The main layer MAL may fill the remaining area of ​​the first recess RS1 except for the buffer layer BFL. The volume of the main layer MAL may be greater than that of the buffer layer BFL. The buffer layer BFL and the main layer MAL may each include silicon germanium (SiGe). Specifically, the buffer layer BFL may include germanium (Ge) at a relatively low concentration. According to another embodiment of the present inventive concept, the buffer layer BFL may include only silicon (Si) in addition to germanium (Ge). The buffer layer BFL may include germanium (Ge) at a concentration of 0 to approximately 30 at %. The main layer MAL may include germanium (Ge) at a relatively high concentration. For example, the main layer MAL may include germanium (Ge) at a concentration of approximately 30 at % to approximately 70 at %. The concentration of germanium (Ge) in the main layer MAL may increase in the third direction D3. For example, the lower portion of the main layer MAL adjacent to the buffer layer BFL may have a germanium (Ge) concentration of approximately 40 at%, but the upper portion of the main layer MAL may have a germanium (Ge) concentration of approximately 60 at%. Each of the buffer layer BFL and the main layer MAL may include impurities (e.g., boron, gallium, or indium) such that the first conductive source / drain pattern SDA is p-type. The impurity concentration of the main layer MAL may be greater than the impurity concentration of the buffer layer BFL. The buffer layer BFL may protect the main layer MAL during a process, to be described later, in which the sacrificial layer is replaced with the first to third internal electrodes PO1, PO2, and PO3 of the gate electrode GE. In other words, the buffer layer BFL may prevent the etching material used to remove the sacrificial layer from penetrating into the main layer MAL and etching the main layer MAL.

[0037] Reference Figure 2D Each of the second conductive source / drain patterns SDB may include silicon (Si). The second conductive source / drain patterns SDB may further include impurities (eg, phosphorus, arsenic, or antimony) such that the second conductive source / drain patterns SDB are n-type.

[0038] According to an embodiment of the present invention, Figure 2A and Figure 2D As shown in FIG, the first conductive source / drain pattern SDA and the second conductive source / drain pattern SDB may each include a concave bottom surface BOS. The concave bottom surface BOS may be concave in the third direction D3. According to some embodiments, the first conductive source / drain pattern SDA and the second conductive source / drain pattern SDB may each not have a concave bottom surface BOS. For example, some of the first conductive source / drain pattern SDA and the second conductive source / drain pattern SDB may have a convex bottom surface.

[0039] like Figure 1 、 Figure 2A and Figure 2D As shown in the figure, a gate electrode GE may be provided that extends across the first channel pattern CH1 and the second channel pattern CH2 in the second direction D2. The gate electrode GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. The gate electrode GE may include a first internal electrode PO1 interposed between the etch stop layer ESL and the first semiconductor pattern SP1, a second internal electrode PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third internal electrode PO3 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an external electrode PO4 on the third semiconductor pattern SP3. According to this embodiment, the etch stop layer ESL may be interposed between the first internal electrode PO1 and the substrate 105. A gate insulating film GI may be interposed between the first internal electrode PO1 and the etch stop layer ESL. The transistor according to this embodiment may be a three-dimensional field effect transistor (e.g., an MBCFET or a GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0040] like Figure 1 As shown in , the gate cutting pattern CT can be set on the boundary of the cell. The gate cutting pattern CT can separate adjacent gate electrodes GE. The gate cutting pattern CT can separate adjacent isolation structures DB. The gate cutting pattern CT can include an insulating material such as a silicon oxide film, a silicon nitride film, or a combination thereof.

[0041] like Figure 2A and Figure 2D As shown in , a pair of gate spacers GS may be respectively provided on opposite (e.g., two) sidewalls of the outer electrode PO4 of the gate electrode GE. The gate spacer GS may extend along the gate electrode GE in the second direction D2. The upper surface of the gate spacer GS may be higher than the upper surface of the gate electrode GE. The upper surface of the gate spacer GS may be coplanar with the upper surface of the first interlayer insulating film 110 to be described later. The gate spacer GS may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacer GS may include a multilayer composed of at least two of SiCN, SiCON, and SiN.

[0042] The gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE in the second direction D2. The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer insulating film 110 and the second interlayer insulating film 120 to be described later. Specifically, the gate capping pattern GP may include at least one of SiON, SiCN, SiCON, and SiN.

[0043] The gate insulating film GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating film GI may cover the upper surface, bottom surface, and both sidewalls of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating film GI may cover the upper surface of the element isolation film ST below the gate electrode GE. The gate insulating film GI may be interposed between the first internal electrode PO1 and the etch stop layer ESL.

[0044] According to an embodiment of the present invention, the gate insulating film GI may include a silicon oxide film, a silicon oxynitride film, and / or a high dielectric constant film. The high dielectric constant film may include a material having a higher dielectric constant than the silicon oxide film. For example, the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0045] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating film GI so as to be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. The target threshold voltage of the transistor can be achieved by controlling the thickness and composition of the first metal pattern. For example, the first to third internal electrodes PO1, PO2, and PO3 of the gate electrode GE may be composed of the first metal pattern including the work function metal.

[0046] The first metal pattern may include a metal nitride film. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), and combinations thereof, and nitrogen (N). Furthermore, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal films.

[0047] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), and combinations thereof. For example, the external electrode PO4 of the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern.

[0048] like Figure 2D and Figure 2EAs shown in FIG, the internal spacer IP may be disposed on the first NMOSFET region NR1 and the second NMOSFET region NR2. In other words, the internal spacer IP may be disposed on the second insulating pattern AP2. The internal spacers IP may be interposed between the first to third internal electrodes PO1, PO2, and PO3 of the gate electrode GE and the second conductive source / drain pattern SDB, respectively. The internal spacers IP may be in direct contact with the second conductive source / drain pattern SDB. Each of the first to third internal electrodes PO1, PO2, and PO3 of the gate electrode GE may be separated from the second conductive source / drain pattern SDB by the internal spacers IP.

[0049] like Figure 2A and Figure 2D As shown in FIG, a first interlayer insulating film 110 may be provided on the substrate 105. The first interlayer insulating film 110 may cover the gate spacer GS and the first and second conductive source / drain patterns SDA and SDB. The first interlayer insulating film 110 may be in contact with an upper surface of each of the first and second conductive source / drain patterns SDA and SDB.

[0050] The upper surface of the first interlayer insulating film 110 may be substantially coplanar with the upper surface of the gate capping pattern GP and the upper surface of the gate spacer GS. The second interlayer insulating film 120 covering the gate capping pattern GP may be disposed on the first interlayer insulating film 110. The third interlayer insulating film 130 may be disposed on the second interlayer insulating film 120. The fourth interlayer insulating film 140 may be disposed on the third interlayer insulating film 130. For example, the first to fourth interlayer insulating films 110 to 140 may include silicon oxide films.

[0051] Active contacts AC may be provided in the first and second interlayer insulating films 110 and 120 (e.g., penetrating the first and second interlayer insulating films 110 and 120) to electrically connect to the first and second conductive source / drain patterns SDA and SDB, respectively. Each of the active contacts AC may be provided adjacent to one side of the gate electrode GE. When viewed in a plane (e.g., in a plan view), the active contacts AC may have a stripe shape (e.g., a rectangle) extending in the second direction D2.

[0052] The active contact AC may be a self-aligned contact. In other words, the active contact AC may be self-aligned and formed using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may at least partially cover the sidewalls of the gate spacer GS (i.e., may cover at least a portion of the sidewalls of the gate spacer GS). Although not shown, the active contact AC may partially cover the upper surface of the gate capping pattern GP.

[0053] A metal-semiconductor compound layer SC, such as a silicide layer, may be interposed between the active contact AC and the first conductive source / drain pattern SDA, and between the active contact AC and the second conductive source / drain pattern SDB. The active contact AC may be electrically connected to the first conductive source / drain pattern SDA and the second conductive source / drain pattern SDB through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0054] A gate contact GC may be provided in the second interlayer insulating film 120 and the gate capping pattern GP (e.g., penetrating the second interlayer insulating film 120 and the gate capping pattern GP) to be electrically connected to the gate electrode GE, respectively. The gate contact GC may be freely provided on the gate electrode GE without being restricted in its position.

[0055] like Figure 2D As shown in , the upper portion of the active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP can be lower than the bottom surface of the gate contact GC. In other words, due to the upper insulating pattern UIP, the upper surface of the active contact AC adjacent to the gate contact GC can be lower than the bottom surface of the gate contact GC. Therefore, the gate contact GC can be prevented from contacting the active contact AC adjacent to it to generate a short circuit. For example, the upper insulating pattern UIP may include a silicon-based insulating material (e.g., a silicon oxide film, a silicon nitride film, or a silicon oxynitride film).

[0056] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal film / metal nitride film. The metal film may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one of a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a nickel nitride (NiN) film, a cobalt nitride (CoN) film, and a platinum nitride (PtN) film.

[0057] The first upper metal layer M1 may be disposed in the third interlayer insulating film 130. The first upper metal layer M1 may include first lines M1_I. The first lines M1_I of the first upper metal layer M1 may extend parallel to each other in the first direction D1.

[0058] According to an embodiment of the present inventive concept, a power line for supplying power to a semiconductor device may be located in the form of a lower power line VPR in a lower insulating layer 107 disposed on a lower portion of the substrate 105 (e.g., buried in the lower insulating layer 107 disposed on the lower portion of the substrate 105). In some embodiments, the lower insulating layer 107 may be referred to herein as a "second insulating pattern." The lower insulating layer 107 may include an insulating material such as silicon oxide. Therefore, the power line may be omitted from the first upper metal layer M1. The first line M1_I for transmitting a signal may be disposed in the first upper metal layer M1.

[0059] The first upper metal layer M1 may further include a first via VI1. The first vias VI1 may be disposed below the first wires M1_I of the first upper metal layer M1. The active contact AC and the first wires M1_I of the first upper metal layer M1 may be electrically connected to each other via the first vias VI1. The gate contact GC and the first wires M1_I of the first upper metal layer M1 may be electrically connected to each other via the first vias VI1.

[0060] The first wire M1_I of the first upper metal layer M1 and the first via VI1 below the first wire M1_I can be formed in separate processes. In other words, the first wire M1_I of the first upper metal layer M1 and the first via VI1 can be formed in a single damascene process. The semiconductor device according to this embodiment can be formed using a process with a thickness of less than approximately 20 nanometers (nm).

[0061] The second upper metal layer M2 may be disposed in the fourth interlayer insulating film 140. The second upper metal layer M2 may include a plurality of second lines M2_I. Each of the second lines M2_I of the second upper metal layer M2 may have a linear or bar shape extending in the second direction D2. In other words, the second lines M2_I may extend parallel to each other in the second direction D2.

[0062] The second upper metal layer M2 may further include second vias VI2 disposed below the second wires M2_I, respectively. The first wires M1_I of the first upper metal layer M1 and the second wires M2_I of the second upper metal layer M2 may be electrically connected to each other via the second vias VI2. For example, the second wires M2_I of the second upper metal layer M2 and the second vias VI2 below the second wires M2_I may be formed together in a dual damascene process.

[0063] The first wire M1_I of the first upper metal layer M1 and the second wire M2_I of the second upper metal layer M2 may include the same material or different materials. For example, the first wire M1_I of the first upper metal layer M1 and the second wire M2_I of the second upper metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. Although not shown, additional metal layers (e.g., a third upper metal layer, a fourth upper metal layer, a fifth upper metal layer, etc.) may be provided stacked on the fourth interlayer insulating film 140. Each of the stacked metal layers may include wires for routing between cells.

[0064] A rear surface via BV may be provided in the substrate 105 (e.g., penetrating the substrate 105) to extend vertically to the first conductive source / drain pattern SDA and the second conductive source / drain pattern SDB. The rear surface via BV may include a rear surface via contact BVC and a rear surface via line BVL. The rear surface via contact BVC represents a portion of the rear surface via BV that is in direct contact with the first conductive source / drain pattern SDA and the second conductive source / drain pattern SDB. The rear surface via contact BVC may be provided on the rear surface via line BVL. The rear surface via contact BVC may be integrally connected to the rear surface via line BVL. The rear surface via contact BVC may have a shape that protrudes from the rear surface via line BVL in the third direction D3. The width of the rear surface via line BVL in the first direction D1 may be greater than the width of the rear surface via contact BVC in the first direction D1. The width of the back surface via line BVL in the second direction D2 may be greater than the width of the back surface via contact BVC in the second direction D2. The back surface via contact BVC may have a cylindrical form. The back surface via line BVL may have a linear or bar (e.g., rectangular) form.

[0065] A liner may be interposed between each of the back surface vias BVL and the substrate 105. The back surface via BV may include at least one metal selected from the group consisting of tungsten, molybdenum, ruthenium, cobalt, aluminum, copper, and combinations thereof. The liner may include a silicon-based insulating material (e.g., SiO, SiN, SiOC, or SiOCN). Each of the first conductive source / drain pattern SDA and the second conductive source / drain pattern SDB, which are adjacent to each other in the first direction D1 (e.g., along the first direction D1), may be vertically electrically connected to the back surface via BV. The insulating material of the substrate 105 may be interposed between adjacent back surface vias BV (specifically, adjacent back surface vias BVL) to electrically separate each other. In this specification, the insulating material of the substrate 105 between adjacent back surface vias BVL may be referred to as an insulating pattern.

[0066] The lower power lines VPR may be disposed below the substrate 105 (and / or in / on the lower portion of the substrate 105). The lower power lines VPR may extend parallel to each other (e.g., primarily / longitudinally) in a first direction D1. The lower power lines VPR may vertically overlap the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2. The lower power lines VPR may include at least one selected from the group consisting of copper, molybdenum, tungsten, ruthenium, and combinations thereof. The bottom surface of each of the lower power lines VPR may be coplanar with the bottom surface of the substrate 105.

[0067] The power transmission network layer (PDN) may be disposed on the bottom surface of the substrate 105. The PDN layer may include a plurality of lower lines electrically connected to the lower power lines VPR. For example, the PDN layer may include a network of lines for applying a source voltage or a drain voltage to the lower power lines VPR. A portion of the back surface via line (BVL) may be in direct contact with the lower power lines VPR.

[0068] Reference Figure 1 、 Figure 2A 、 Figure 3A and Figure 3B The power gating block PGB may be disposed in the first region R1. Side blocks SB having different functions may be disposed on both sides of the power gating block PGB. The power gating block PGB may include at least one of sub-power gating blocks A1, A2, and A3.

[0069] like Figure 3B As shown in FIG, each of the power gating sub-blocks A1, A2, and A3 may include three source / drain patterns SD adjacent to each other in a first direction D1 (e.g., along the first direction D1). The power gating sub-blocks (e.g., A2 and A3) disposed adjacent to each other may share one source / drain pattern SD. The three source / drain patterns SD may include a first source / drain pattern SD1, a second source / drain pattern SD2, and a third source / drain pattern SD3 interposed between the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0070] The back surface vias BV may include a first back surface via BV1, a second back surface via BV2, and a third back surface via BV3. The first back surface via BV1, the second back surface via BV2, and the third back surface via BV3 may penetrate the substrate 105 to be connected (e.g., electrically connected) to the first source / drain pattern SD1, the second source / drain pattern SD2, and the third source / drain pattern SD3, respectively.

[0071] The lower power line VPR may include a first lower power line VPR1 and a second lower power line VPR2 spaced apart from each other in the first direction D1. The first lower power line VPR1 and the second lower power line VPR2 may not contact each other. The first rear surface via BV1 may be electrically connected to the first lower power line VPR1 and in contact with the first lower power line VPR1. The second rear surface via BV2 may be electrically connected to the second lower power line VPR2 and in contact with the second lower power line VPR2. The third rear surface via BV3 may extend (e.g., mainly / longitudinally) farther in the second direction D2 than the first rear surface via BV1 and the second rear surface via BV2. Specifically, the rear surface via line BVL of the third rear surface via BV3 may extend farther than the rear surface via line BVL of the first rear surface via BV1 and the rear surface via line BVL of the second rear surface via BV2. Specifically, the width of the back surface via line BVL of the third back surface via BV3 in the second direction D2 may be greater than the width of the back surface via line BVL of the first back surface via BV1 and the width of the back surface via line BVL of the second back surface via BV2 in the second direction D2.

[0072] A first voltage may be transmitted to the first lower power line VPR1, so that the first power may be transmitted to the third source / drain pattern SD3 through the first rear surface via BV1, the first source / drain pattern SD1, and the channel pattern CH. A second voltage may be applied to the second lower power line VPR2, so that the second power may flow to the third source / drain pattern SD3 through the second rear surface via BV2, the second source / drain pattern SD2, and the channel pattern CH. A third voltage, which is the sum of the first voltage and the second voltage, may be transmitted to the third source / drain pattern SD3, so that the third power may be transmitted to another block connected to the third rear surface via BV3 through the third rear surface via BV3.

[0073] Reference Figure 1 、 Figure 2B 、 Figure 4 and Figure 6 The switch block SWB, the operation block OPB, and the side block SB may be disposed in the second region R2. The side block SB may be placed on one side of the switch block SWB, and the operation block OPB may be placed on the other (e.g., opposite) side of the switch block SWB. An isolation structure DB may be provided between the switch block SWB and the operation block OPB, and between the switch block SWB and the side block SB. Each of the isolation structures DB may insulate between the switch block SWB and the operation block OPB, and between the switch block SWB and the side block SB.

[0074] The switching block SWB may include a switching transistor SWT. The rear surface via BV may further include a fourth rear surface via BV4 and a fifth rear surface via BV5. The fourth rear surface via BV4 and the fifth rear surface via BV5 may be respectively connected to a fourth source / drain pattern SD4 and a fifth source / drain pattern SD5 provided on opposite (e.g., two) sides of the channel pattern CH of the switching transistor SWT. The lower power line VPR may further include a third lower power line VPR3 and a fourth lower power line VPR4 spaced apart from each other in the first direction D1. The third lower power line VPR3 and the fourth lower power line VPR4 may not be in contact with each other. The fourth rear surface via BV4 and the third lower power line VPR3 may be electrically connected to each other and in contact with each other. The fifth rear surface via BV5 and the fourth lower power line VPR4 may be electrically connected to each other and in contact with each other.

[0075] The operation block OPB may include transistors that constitute a logic circuit. The operation transistors may include a sixth source / drain pattern SD6 disposed on one side of the channel pattern CH and a seventh source / drain pattern SD7 disposed on the other side of the channel pattern CH. A rear surface via BV may be disposed on the lower portion of either the sixth source / drain pattern SD6 or the seventh source / drain pattern SD7, and an active contact AC may be disposed on the upper portion of the other of the sixth source / drain pattern SD6 and the seventh source / drain pattern SD7. For example, the rear surface via BV may be disposed on the lower portion of the sixth source / drain pattern SD6 and may be connected to and in contact with the fourth lower power line VPR4. The active contact AC may be disposed on the upper portion of the seventh source / drain pattern SD7 and in contact with the upper portion of the seventh source / drain pattern SD7. The third power transmitted from the third rear surface via BV3 of the power gating block PGB may be supplied as a source voltage to the transistors of the operation block OPB via the switch block SWB.

[0076] Reference Figure 1 、 Figure 2C 、 Figure 5 and Figure 6 , the operation block OPB may be disposed in the third region R3. The operation block OPB may receive power transmitted from the first sub-power gating block A1 and the second sub-power gating block A2 of the power gating block PGB to operate (see Figure 1 、 Figure 3A and Figure 6 ).

[0077] For example, a back surface via line BVL connected to the back surface via BV of the second sub-power gating block A2 may contact a back surface via contact BVC of a transistor of the operation block OPB. That is, the back surface via BV of the transistor connected to the second sub-power gating block A2 may share a back surface via line BVL with the back surface via BV of the transistor connected to the operation block OPB. A source voltage may be applied to two adjacent operation transistors in the operation block OPB through the shared back surface via contact BVC.

[0078] Reference Figure 1 、 Figure 2D and Figure 7 , the operation block OPB' can be set in the fourth region R4.

[0079] The operation block OPB' may include a pair of adjacent transistors and an isolation structure DB disposed between the pair of adjacent transistors. An active contact AC may be connected to one source / drain pattern SD of each of the adjacent transistors, and a rear surface via BV may be connected to the other source / drain pattern SD of each of the adjacent transistors. The rear surface vias BV of the adjacent transistors may contact a common lower power line VPR to receive the same power.

[0080] Reference Figure 1 、 Figure 2E and Figure 8 , different operation blocks OPB1 and OPB2 can be set in the fifth region R5.

[0081] The first operation block OPB1 and the second operation block OPB2 may each include a transistor, and an isolation structure DB may be interposed between the first operation block OPB1 and the second operation block OPB2. An active contact AC may be connected to one source / drain pattern SD of each of the transistors of the first operation block OPB1 and the transistors of the second operation block OPB2, and a rear surface via BV may be connected to another source / drain pattern SD of each of the transistors of the first operation block OPB1 and the transistors of the second operation block OPB2. The rear surface vias BV of the transistors of the first operation block OPB1 and the rear surface vias BV of the transistors of the second operation block OPB2 may be connected to different lower power lines VPR, respectively. Different lower power lines VPR may supply different power to the first operation block OPB1 and the second operation block OPB2, respectively.

[0082] According to the present invention, each of the adjacent source / drain patterns can be in contact with the rear surface via on its lower portion and connected (e.g., electrically connected) to the rear surface via on its lower portion. In addition, the active contact may not be provided on the upper portion of the source / drain pattern connected to the rear surface via. As a result, transmitting power without passing through the first metal layer and the second metal layer can be advantageous in terms of space utilization of the design line and can be desirable in terms of resistance reduction. Connecting the rear surface via to each of the adjacent source / drain patterns can increase the density of the rear surface vias in the same area, and inserting an insulating material between adjacent source / drain patterns can block / prevent current from flowing directly between adjacent source / drain patterns.

[0083] In addition, the middle source / drain pattern placed among the three consecutive source / drain patterns can be supplied with power (e.g., power 1 and power 2) by being connected to the rear surface vias of the source / drain patterns placed on both sides thereof, and can be supplied with power as a sum (power 1 + power 2) greater than power 1 or power 2 by extending the rear surface vias to another block. In this case, when the power gating block is connected to the switch block, at least the target power can be transmitted to the operation block connected to the switch block. According to some embodiments, the middle source / drain pattern placed among the three consecutive source / drain patterns can be supplied with power (e.g., power 1 and -power 2) by being connected to the rear surface vias of the source / drain patterns placed on both sides thereof, and can be supplied with power as a sum (power 1 - power 2) less than power 1 or -power 2 by extending the rear surface vias to another block.

[0084] 9A to 9H is a cross-sectional view for describing a method for fabricating a semiconductor device according to an embodiment of the inventive concept. 9A to 9H It is along Figure 1 A cross-sectional view taken along line AA'.

[0085] Reference Figure 9A A semiconductor substrate 100 including first and second PMOSFET regions PR1 and PR2 and first and second NMOSFET regions NR1 and NR2 may be provided. For example, the semiconductor substrate 100 may be a silicon wafer. An etch stop layer ESL may be formed on the semiconductor substrate 100. The etch stop layer ESL may be formed to have an etch selectivity with respect to the semiconductor substrate 100 (i.e., silicon (Si)). According to some embodiments, the formation of the etch stop layer ESL may be omitted.

[0086] Semiconductor layers and sacrificial layers stacked alternately may be formed on the etch stop layer ESL. For example, the semiconductor layers may include silicon (Si), and the sacrificial layers may include silicon germanium (SiGe).

[0087] A mask pattern may be formed on the first and second PMOSFET regions PR1 and PR2 and the first and second NMOSFET regions NR1 and NR2 of the semiconductor substrate 100, respectively. The mask pattern may have a line or stripe shape extending in the first direction D1. The trench TR defining the active pattern PAP may be formed by performing a patterning process using the mask pattern as an etching mask (see FIG. Figure 1 ). An active pattern PAP may be formed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2 and each of the first NMOSFET region NR1 and the second NMOSFET region NR2. Thus, a stacked pattern may be formed by simultaneously patterning the semiconductor layer and the sacrificial layer. An element isolation film may be formed to fill the trench. The stacked pattern may be exposed on the element isolation film.

[0088] A sacrificial pattern intersecting the stacked pattern may be formed on the semiconductor substrate 100. A pair of gate spacers GS may be formed on both sidewalls of each of the sacrificial patterns. Next, a first recess RS1 and a second recess RS2 may be formed. First to third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent first recesses RS1 may be formed from a semiconductor layer. First to third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent second recesses RS2 may be formed from a semiconductor layer. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1 may constitute a first channel pattern CH1. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2 may constitute a second channel pattern CH2.

[0089] First conductive source / drain patterns SDA may be formed in the first recesses RS1. A buffer layer BFL may be formed by performing a first selective epitaxial growth (SEG) process, and a main layer MAL may be formed by performing a second SEG process. Second conductive source / drain patterns SDB may be formed in the second recesses RS2. The second conductive source / drain patterns SDB may be formed by performing a selective epitaxial growth (SEG) process using the inner sidewalls of the second recesses RS2 as a seed layer.

[0090] A first interlayer insulating film 110 may be formed covering the first conductive source / drain pattern SDA and the second conductive source / drain pattern SDB. The sacrificial pattern may be removed to expose the first and second channel patterns CH1 and CH2. The sacrificial film may be removed to ensure an empty space between the first to third semiconductor patterns SP1, SP2, and SP3. A gate insulating film GI may be conformally formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. A gate electrode GE may be formed on the gate insulating film GI. A gate capping pattern GP may be formed on the gate electrode GE.

[0091] Cutting holes and isolation holes can be formed by performing an etching process in the space where the sacrificial pattern is removed. Cutting holes can be formed between adjacent gate spacers GS. Isolation holes can be formed on opposite (e.g., two) sides of a cell. The isolation holes can penetrate the gate capping pattern GP, ​​the gate electrode GE, and the element isolation film ST to extend into the semiconductor substrate 100. The isolation holes can extend to the upper portion of the semiconductor substrate 100. The gate cutting pattern CT and the isolation structure DB can be formed by filling each of the cutting hole and the isolation hole with an insulating material. As another example, the gate cutting pattern CT and the isolation structure DB can be formed simultaneously by filling the cutting hole and the isolation hole with an insulating material. According to some embodiments, after filling the cutting hole with an insulating material, the isolation hole can be formed. For example, the gate cutting pattern CT and the isolation structure DB can be formed in different processes.

[0092] A second interlayer insulating film 120 may be formed on the first interlayer insulating film 110. An active contact AC may be formed to penetrate the first and second interlayer insulating films 110, 120 to electrically connect to at least one of the first and second conductive source / drain patterns SDA, SDB. A gate contact GC may be formed to penetrate the second interlayer insulating film 120 and the gate capping pattern GP to electrically connect to the gate electrode GE. A third interlayer insulating film 130 may be formed on the active contact AC and the gate contact GC. A first upper metal layer M1 may be formed in the third interlayer insulating film 130. A fourth interlayer insulating film 140 may be formed on the third interlayer insulating film 130. A second upper metal layer M2 may be formed in the fourth interlayer insulating film 140.

[0093] Reference Figure 9B After completing a back end of line (BEOL) process, the bottom surface of the semiconductor substrate 100 may be exposed by flipping the semiconductor substrate 100. At least a portion of the exposed semiconductor substrate 100 may be removed.

[0094] According to an embodiment of the present inventive concept, removing the semiconductor substrate 100 may include reducing the thickness of the semiconductor substrate 100 by performing a process to planarize the bottom surface of the semiconductor substrate 100 and performing an etching process to selectively remove silicon (Si) from the semiconductor substrate 100. For example, the etching process may be performed until the etch stop layer (ESL) is exposed. The removal of the semiconductor substrate 100 may slightly remove the lower portions of the first and second conductive source / drain patterns SDA and SDB. Consequently, a recessed bottom (BOS) may be formed on the lower portions of the first and second conductive source / drain patterns SDA and SDB. Removing the semiconductor substrate 100 may form a rear surface trench in the region where the active pattern PAP is located.

[0095] Reference Figure 9C , a substrate 105 can be formed by filling the removed region of the semiconductor substrate 100 with an insulating material. The substrate 105 may therefore be referred to herein as an "insulating substrate." The substrate 105 may include a silicon-based insulating layer. The first insulating pattern AP1 and the second insulating pattern AP2 filling the rear surface trench may be formed simultaneously.

[0096] Reference Figure 9D The back surface via hole BVH can be formed by performing a photolithography process and an anisotropic etching process on the substrate 105. The back surface via hole BVH may include a back surface contact hole BCH located in at least a portion of (e.g., penetrating at least a portion of) the first and second conductive source / drain patterns SDA and SDB, and a back surface line hole BLH located in (e.g., penetrating) the substrate 105 connected thereto. The back surface via hole BVH may expose the first and second conductive source / drain patterns SDA and SDB. After patterning, the substrate 105 may remain vertically overlapped with the gate electrode GE and the isolation structure DB. A liner may be formed on the inner sidewalls of each of the back surface via holes BVH.

[0097] Reference Figure 9E , the first lower metal layer ML1 may be formed by filling the back surface via hole BVH with metal. The first lower metal layer ML1 may fill the back surface via hole BVH and may cover the upper surface of the substrate 105.

[0098] Reference Figure 9F The first lower metal layer ML1 may be patterned through a planarization process to form a plurality of back surface vias BV (eg, a damascene process). The plurality of back surface vias BV may be separated from each other and electrically insulated from each other by the substrate 105.

[0099] Reference Figure 9G , a lower insulating layer 107 may be formed and patterned using a photolithography process, etc. As a result of the patterning, the lower insulating layer 107 may expose some (but not all) of the plurality of rear surface vias BV and cover the other rear surface vias BV.

[0100] Reference Figure 9H , a lower power line VPR may be formed. The lower power line VPR may be connected to at least one of the back surface vias BV. Forming the lower power line VPR may include forming a second lower metal layer and patterning the second lower metal layer (eg, a damascene process).

[0101] Return to reference Figure 2A A power transmission network layer PDN may be formed on the lower power line VPR. The power transmission network layer PDN may be formed to apply a source voltage or a drain voltage to the lower power line VPR.

[0102] According to the present invention, in a transistor that transmits power, a first rear surface via and a second rear surface via can be respectively connected (e.g., electrically connected) to a first source / drain pattern and a second source / drain pattern connected (e.g., electrically connected) to a channel pattern along a first direction, and a channel pattern is located between the first rear surface via and the second rear surface via. The first rear surface via can be connected (e.g., electrically connected) to a first rear surface power line that vertically overlaps with the first source / drain pattern. The second rear surface via can extend in a second direction perpendicular to the first direction to directly connect to a lower power line that does not vertically overlap with the second source / drain pattern or a third source / drain pattern of another transistor (e.g., contact with a lower power line that does not vertically overlap with the second source / drain pattern). Transmitting power without passing through an active contact or upper line provided on the source / drain pattern can be advantageous in terms of space utilization of the design line and can reduce resistance due to a reduced power path. As a result, the electrical characteristics and reliability of the semiconductor device can be improved.

[0103] Although the embodiments of the present inventive concept have been described, it is to be understood that the present inventive concept should not be limited to these embodiments, but a person skilled in the art may make various changes and modifications within the scope of the present inventive concept as claimed above.

Claims

1. A semiconductor device comprising: substrate; as well as a first block, which is located on the substrate, The first block includes: a first source / drain pattern, a second source / drain pattern, and a third source / drain pattern between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern, the second source / drain pattern, and the third source / drain pattern being spaced apart from each other in a first direction parallel to an upper surface of the substrate; a first lower power line and a second lower power line, the first lower power line being located on a lower portion of the substrate, the second lower power line being spaced apart from the first lower power line in the first direction, the first lower power line and the second lower power line extending in the first direction; a first rear surface via located in the substrate and connecting the first lower power line and the first source / drain pattern; a second rear surface via located in the substrate and connecting the second lower power line and the second source / drain pattern; and a third rear surface via located in the substrate and connected to the third source / drain pattern, and The third rear surface via extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein The first rear surface via, the second rear surface via, and the third rear surface via include: a first rear surface via contact, a second rear surface via contact, and a third rear surface via contact respectively contacting the first source / drain pattern, the second source / drain pattern, and the third source / drain pattern; and a first rear surface via line, a second rear surface via line, and a third rear surface via line respectively located on the first rear surface via contact, the second rear surface via contact, and the third rear surface via contact, and The width of the third rear surface via line in the second direction is greater than the width of the first rear surface via line in the second direction and the width of the second rear surface via line in the second direction.

3. The semiconductor device according to claim 1 , further comprising a third lower power line spaced apart from at least one of the first lower power line and the second lower power line in the second direction, in, The third lower power line is connected to the third rear surface via.

4. The semiconductor device according to claim 3, wherein The third lower power line extends in parallel with the at least one of the first lower power line and the second lower power line in the first direction.

5. The semiconductor device according to claim 3 , further comprising a second block connected to the first block, in, The second block includes: a fourth source / drain pattern and a fifth source / drain pattern spaced apart from each other in the first direction; a fourth lower power line located on a lower portion of the substrate and spaced apart from the third lower power line in the first direction; a fourth rear surface via member located in the substrate and connecting the third lower power line and the fourth source / drain pattern; and A fifth rear surface via is located in the substrate and connects the fourth lower power line and the fifth source / drain pattern. 6 . The semiconductor device according to claim 5 , further comprising isolation structures spaced apart from each other in the first direction, and the fourth source / drain pattern and the fifth source / drain pattern are located between the isolation structures.

7. The semiconductor device according to claim 5, further comprising a third block connected to the second block, in, The third block includes: a sixth source / drain pattern and a seventh source / drain pattern spaced apart from each other in the first direction; a sixth rear surface via member located in the substrate and connecting the fourth lower power line and a lower side of the sixth source / drain pattern; and An active contact is located on an upper side of the seventh source / drain pattern.

8. The semiconductor device according to claim 3, in, the first lower power line being configured to have a first voltage applied thereto, wherein the second lower power line is configured to have a second voltage applied thereto, and The third lower power line is configured to have the sum of the first voltage and the second voltage transmitted thereto.

9. The semiconductor device according to claim 1 , further comprising a second block connected to the first block, in, The third rear surface via member includes a first rear surface via contact member, a second rear surface via contact member, and a rear surface via line located on the first rear surface via contact member and the second rear surface via contact member. wherein the second block includes a fourth source / drain pattern and a fifth source / drain pattern spaced apart from each other in the first direction, wherein the first rear surface via contact contacts the third source / drain pattern, and The second rear surface via contact is in contact with any one of the fourth source / drain pattern and the fifth source / drain pattern.

10. The semiconductor device according to claim 1, wherein The substrate is an insulating substrate.

11. The semiconductor device according to claim 10, wherein The substrate includes at least one of silicon nitride, silicon oxide, and silicon carbide.

12. The semiconductor device according to claim 1, further comprising a power transmission network layer below the substrate, in, The power transmission network layer is configured to apply a source voltage or a drain voltage to the first lower power line and the second lower power line.

13. A semiconductor device comprising: a channel pattern comprising a plurality of semiconductor patterns stacked and spaced apart from each other; first and second source / drain patterns respectively connected to opposite sides of the channel pattern and spaced apart from each other in a first direction; a gate electrode located on the channel pattern and including a plurality of inner electrodes respectively located between the plurality of semiconductor patterns; a first rear surface via connected to the first source / drain pattern; a second rear surface via connected to the second source / drain pattern; a lower power line located below and connected to at least one of the first rear surface via and the second rear surface via; an interlayer insulating layer located on the first source / drain pattern and the second source / drain pattern and contacting upper surfaces of the first source / drain pattern and the second source / drain pattern; as well as A first insulating pattern is located between the first rear surface via and the second rear surface via.

14. The semiconductor device according to claim 13, wherein The first insulating pattern includes at least one of silicon nitride, silicon oxide, and silicon carbide.

15. The semiconductor device according to claim 13, wherein The first insulating pattern vertically overlaps the gate electrode.

16. The semiconductor device according to claim 13, further comprising: a first isolation structure located on a side surface of the first source / drain pattern; as well as a second isolation structure located on a side surface of the second source / drain pattern, The first isolation structure and the second isolation structure are spaced apart from each other, and the first rear surface via and the second rear surface via are located between the first isolation structure and the second isolation structure.

17. The semiconductor device according to claim 13, in, The first rear surface via is spaced apart from the lower power line, wherein the second rear surface via contacts the lower power line, and The first rear surface via extends further than the second rear surface via in a second direction perpendicular to the first direction.

18. The semiconductor device according to claim 13, in, The lower power line is one of a plurality of lower power lines, The plurality of lower power lines each include a first lower power line and a second lower power line, wherein the first rear surface via is connected to the first lower power line, wherein the second rear surface via is connected to the second lower power line, and The semiconductor device further includes a second insulating pattern located between the first lower power line and the second lower power line.

19. The semiconductor device according to claim 13, further comprising an etch stop layer between the first insulating pattern and the channel pattern, in, The etch stop layer includes silicon doped with oxygen, carbon, or a combination thereof.

20. A semiconductor device comprising: insulating substrate; as well as The first block and the second block on the insulating substrate, The first block includes: a first source / drain pattern, a second source / drain pattern, and a third source / drain pattern between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern, the second source / drain pattern, and the third source / drain pattern being spaced apart from each other in a first direction parallel to an upper surface of the insulating substrate; a first lower power line and a second lower power line, the first lower power line being located on a lower portion of the insulating substrate, the second lower power line being spaced apart from the first lower power line in the first direction, the first lower power line and the second lower power line extending in the first direction; a first rear surface via located in the insulating substrate and connecting the first lower power line and the first source / drain pattern; a second rear surface via located in the insulating substrate and connecting the second lower power line and the second source / drain pattern; and a third rear surface via located in the insulating substrate and connected to the third source / drain pattern, The second block includes: a channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; and fourth and fifth source / drain patterns respectively connected to opposite sides of the channel pattern and spaced apart from each other in the first direction, and The third rear surface via extends in a second direction parallel to the upper surface of the insulating substrate and perpendicular to the first direction to be connected to any one of the fourth source / drain pattern and the fifth source / drain pattern.

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