Large-area micro single crystal array processing method

Abstract

The invention discloses a large-area micro single crystal array processing method, which is realized through large-area micro single crystal array processing equipment, and the equipment comprises an alignment system, an alignment platform, a display device, a control device, a sample table and an operation device, the method comprises the following steps: S1, processing an array silicon column template through photoetching and etching; s2, dropwise adding an organic semiconductor solution on the array silicon column template; and S3, controlling the alignment system and the alignment platform through software to align the silicon column and the substrate and then press the silicon column and the substrate, and completing self-assembly of the micro-single crystal array on the sample table so as to complete preparation of the micro-single crystal array. According to the preparation method disclosed by the invention, by adopting large-area micro single crystal array processing equipment, accurate alignment of the silicon column and the substrate is realized, and large-area consistency of the single crystal array is ensured.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of array processing technology, and in particular to a method for processing a large-area micro single crystal array. Background Art

[0002] In fields such as optoelectronic devices and flexible electronics, large-area micro-single crystal arrays have attracted much attention due to their excellent electrical and optical performance and high consistency. With the rapid development of technologies in these fields, the demand for large-area micro-single crystal array fabrication technology is becoming increasingly urgent, and related processing methods have become a research hotspot.

[0003] Traditional processing methods have many limitations in the preparation of large-area micro-single crystal arrays. For example, the micro-imprinting method can form an array by filling the solution with micro-nanostructures through mold imprinting, but the mold production cost is high, the precision requirements are stringent, and it is easy to wear. The inkjet printing method is easy to diffuse on the substrate, resulting in poor pattern accuracy, and the nozzle is also prone to clogging, affecting processing stability. The liquid phase dip coating method is easy to operate and suitable for large areas, but the crystal growth direction and size are difficult to accurately control, affecting the quality and performance of the array. These traditional methods are difficult to meet the current demand for large-area, high-precision micro-single crystal arrays. Summary of the Invention

[0004] The present invention provides a large-area micro single crystal array processing method to solve the problem of difficulty in large-area processing in organic liquid phase processing.

[0005] An embodiment of the present invention provides a method for processing a large-area micro-single crystal array. The method is implemented using a large-area micro-single crystal array processing device, the device comprising: an alignment system, an alignment platform, a display device, a control device, a sample stage, and an operating device; the method comprises: S1, processing the array silicon pillar template by photolithography and etching; S2, dropping the organic semiconductor solution onto the array silicon pillar template; S3. The alignment system and the alignment platform are controlled by software to align the silicon pillars and the substrate and then press them, and the self-assembly of the micro single crystal array is completed on the sample stage, thereby completing the preparation of the micro single crystal array.

[0006] Optionally, the S1 specifically includes: The N-type doped single crystal silicon wafer is subjected to photolithography and etching to produce an array silicon pillar template.

[0007] Optionally, the silicon pillars in the array silicon pillar template have a width of 2-5 μm, a spacing of 5-10 μm, and a height of 12-18 μm.

[0008] Optionally, the volume of the organic semiconductor solution droplet is 5-15 μL, the solvent is chloroform or toluene, and the concentration is 1-10 mg / ml.

[0009] Optionally, the alignment system is a dual CCD alignment system, and the alignment platform is a six-degree-of-freedom high-precision alignment platform.

[0010] Optionally, the alignment system objective lens axis distance varies within a range of ±10 mm, and images of the two fields of view are presented separately or simultaneously on a display device.

[0011] Optionally, the substrate material includes at least one of silicon wafer, silicon dioxide, quartz and sapphire.

[0012] Beneficial effects of the present invention: The present invention utilizes large-area micro-single crystal array processing equipment that enables precise alignment of silicon pillars and substrates, ensuring uniformity across a large area of ​​the single crystal array. This equipment can also be used to assemble organic semiconductor materials, offering a simple, low-cost production process and enabling large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A flowchart of a large-area micro single crystal array processing method provided by an embodiment of the present invention; Figure 2 A physical diagram of a large-area micro single crystal array processing device provided by an embodiment of the present invention; Figure 3 SEM image of the array silicon pillar template provided by an embodiment of the present invention; Figure 4 A structural diagram of a dual CCD alignment system provided in an embodiment of the present invention; Figure 5 A structural diagram of a workpiece stage system provided in an embodiment of the present invention; Figure 6 This is the morphology of an organic semiconductor single crystal array obtained by optical microscopy; Figure 7 The SEM morphology of the organic semiconductor single crystal array; Figure 8 SAED pattern of organic semiconductor single crystal array; Figure 9 This is the morphology of organic semiconductor on quartz; Figure 10 This is the morphology of organic semiconductor on silicon dioxide; Figure 11 This is the morphology of organic semiconductor on sapphire. DETAILED DESCRIPTION

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures. Example

[0015] Figure 1 A flow chart of a large-area micro-single crystal array processing method provided in an embodiment of the present invention is implemented by a large-area micro-single crystal array processing device, which includes: an alignment system, an alignment platform, a display device, a control device, a sample stage and an operating device.

[0016] As an example, the physical picture of the device can be found in Figure 2 The alignment system is a dual CCD alignment system; the alignment platform is a six-degree-of-freedom high-precision alignment platform that can control X, Y, Z, θ X ,θ Y ,θ Z The alignment system has an objective lens axis distance variation range of ±10 mm, and displays images of two fields of view separately or simultaneously on a display device.

[0017] The display device may be a computer interface, the control device may be pre-set control software, and the operating device may be a keyboard.

[0018] Furthermore, the preparation method comprises the following steps: S1. Processing an array silicon pillar template through photolithography and etching.

[0019] Specifically, the above S1 includes the following steps: A four-inch N-type doped single-crystal silicon wafer with exposed single-sided polished crystal surface is photolithographically and etched to produce an array silicon pillar template with a width of 2-5μm, a spacing of 5-10μm, and a height of 12-18μm.

[0020] See also Figure 3 , Figure 3 This is the SEM image of the array silicon pillar template, which is a characterization of the morphology of the array silicon pillar template processed by photolithography and etching.

[0021] S2. Add the organic chiral semiconductor solution dropwise onto the array silicon pillar template.

[0022] The volume of the organic semiconductor solution droplet is 5-15 μL, the solvent is chloroform or toluene, and the concentration is 1-10 mg / ml.

[0023] S3. The alignment system and the alignment platform are controlled by software to align the silicon pillars and the substrate and then press them, and the self-assembly of the micro single crystal array is completed on the sample stage, thereby completing the preparation of the micro single crystal array.

[0024] In this embodiment, the size of the substrate is adapted to the size of the silicon pillars.

[0025] Figure 4 This is a structural diagram of a dual CCD alignment system provided by an embodiment of the present invention. The alignment system is used to determine the offset between the silicon pillar and the substrate. The control software controls the six-degree-of-freedom high-precision alignment platform (controllable X, Y, Z, θ) according to the offset. X ,θ Y ,θ Z ) movement to achieve precise alignment of the silicon pillars and the substrate, thereby ensuring large-area uniformity of the single crystal array.

[0026] Figure 5 The workpiece stage system structure diagram provided in the embodiment of the present invention regulates the sample preparation temperature by controlling the temperature of the heating plate, thereby controlling the morphology of the micro single crystal and meeting the requirements of different devices for micro single crystals.

[0027] The substrate material in this embodiment may include various materials, such as silicon wafer, silicon dioxide, quartz, sapphire, etc.

[0028] See further Figure 6-11 , Figure 6 This is an optical microscope morphology image of an organic semiconductor single crystal array. From the image, it can be seen that the organic semiconductor single crystal array has a complete morphology and is neatly arranged.

[0029] Figure 7 This is the SEM morphology of the organic semiconductor single crystal array. From the figure, it can be seen that the organic semiconductor single crystal array has a complete morphology and is neatly arranged.

[0030] Figure 8 This is the SAED pattern of an organic semiconductor single crystal array. From the regularly arranged diffraction points in the figure, it can be seen that the prepared organic semiconductor array is a single crystal array, not a polycrystalline array.

[0031] Figure 9 This is a morphology diagram of organic semiconductors on quartz. From the figure, it can be seen that the organic semiconductor array has a complete morphology and is neatly arranged.

[0032] Figure 10 This is a morphology diagram of organic semiconductors on silicon dioxide. From the figure, it can be seen that the organic semiconductor array has a complete morphology and is neatly arranged.

[0033] Figure 11 This is the morphology of organic semiconductors on sapphire. From the figure, we can see that the organic semiconductor array has a complete morphology and is neatly arranged.

[0034] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for processing a large-area micro single crystal array, characterized in that: The method is implemented by a large-area micro single crystal array processing device, which includes: an alignment system, an alignment platform, a display device, a control device, a sample stage, and an operating device; the method includes: S1, processing the array silicon pillar template by photolithography and etching; S2, dropping the organic semiconductor solution onto the array silicon pillar template; S3. The alignment system and the alignment platform are controlled by software to align the silicon pillars and the substrate and then press them, and the self-assembly of the micro single crystal array is completed on the sample stage, thereby completing the preparation of the micro single crystal array.

2. The method according to claim 1, characterized in that Said S1 specifically includes: The N-type doped single crystal silicon wafer is subjected to photolithography and etching to produce an array silicon pillar template.

3. The method according to claim 2, characterized in that The silicon pillars in the array silicon pillar template have a width of 2-5 μm, a spacing of 5-10 μm, and a height of 12-18 μm.

4. The method according to claim 1, wherein The volume of the organic semiconductor solution droplet is 5-15 μL, the solvent is chloroform or toluene, and the concentration is 1-10 mg / ml.

5. The method according to claim 1, wherein The alignment system is a dual CCD alignment system, and the alignment platform is a six-degree-of-freedom high-precision alignment platform.

6. The method according to claim 1, wherein The alignment system objective lens axis distance varies within a range of ±10 mm, and images of two viewing fields are presented separately or simultaneously on a display device.

7. The method according to claim 1, characterized in that The substrate material includes at least one of silicon wafer, silicon dioxide, quartz and sapphire.

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