Techniques for capturing signal from logic circuit at logic analyzer

Abstract

An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store a value of the signal selected by the multiplexer circuit. A method for capturing a signal within an integrated circuit is provided. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in a logic analyzer circuit in the integrated circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims priority to U.S. patent application 18 / 122,238, filed on March 16, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to electronic integrated circuits, and more particularly, to circuits and methods for capturing signals from logic circuits in the integrated circuit at a logic analyzer circuit. Background Art

[0003] In the field of electronics, various electronic design automation (EDA) tools are useful for automating the process of designing and manufacturing integrated circuits, multi-chip modules, circuit boards, and the like. In particular, electronic design automation tools are useful in the design of configurations of standard integrated circuits, custom integrated circuits, and programmable integrated circuits. A programmable integrated circuit can be programmed by a customer to produce a custom circuit design for the integrated circuit. After a programmable integrated circuit (IC) has been programmed with the custom circuit design and is operating within a working system, it is important to be able to debug the IC, for example, by capturing the values ​​of signal traces within the custom circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a diagram illustrating an example of an integrated circuit including a logic analyzer circuit.

[0005] Figure 2 is a flow chart illustrating an example of a compile operation for a circuit design of a programmable integrated circuit (IC).

[0006] Figure 3 is a diagram illustrating an example of an input interface to a logic analyzer circuit including a multiplexer circuit controlled by a register circuit.

[0007] Figure 4 is a diagram illustrating an example of an input interface to a logic analyzer circuit including a multiplexer circuit controlled by a configuration memory circuit.

[0008] Figure 5 is a diagram illustrating an example of an input interface to a logic analyzer circuit including a multiplexer circuit in a peripheral area of ​​an IC.

[0009] Figure 6 Examples of programmable integrated circuits (ICs) that may include the circuits disclosed herein are illustrated. DETAILED DESCRIPTION

[0010] This disclosure discusses integrated circuit devices, including programmable (configurable) integrated circuits, such as field programmable gate arrays (FPGAs). As discussed herein, integrated circuits (ICs) can include hard logic and / or soft logic. As used herein, "hard logic" generally refers to circuits in an integrated circuit device that are not programmable by an end user. Circuits in an integrated circuit device (e.g., a programmable IC) that are programmable by an end user are referred to as "soft logic."

[0011] In a typical custom circuit design for a programmable integrated circuit, the user's goal is a custom circuit design with high value, and the custom circuit design of the high value always has a very high cost of use. When the circuit design of a programmable integrated circuit (also referred to as a custom circuit design herein) needs to be debugged, a challenge arises. Adding debug functionality to the circuit design generally requires utilizing the soft logic resources in the programmable integrated circuit. Typically, the user must either transplant the circuit design to a larger programmable integrated circuit to provide enough soft logic for debugging functionality, or make a design compromise by trading the functionality of the circuit design for debug functionality. Reassembling, retiming, and recompiling the debug-enabled circuit design increases the time to market for the circuit design. When adding debug functionality to the circuit design of a programmable integrated circuit, another problem that often arises is that the change in the overall system behavior of the circuit design caused by adding debug functionality can make any errors in the circuit design disappear. For users attempting to debug the circuit design of a programmable integrated circuit (IC), another significant limitation is the high throughput (e.g., tens of gigabits per second) required to capture the signal traces within the circuit design.

[0012] Integrated circuits (ICs) may include embedded logic analyzer circuitry that uses embedded memory in the IC that operates at the same frequency as the signals being monitored in the IC to provide a matching bandwidth that ensures the signals can be captured. If the embedded memory offers very limited storage capacity, the user may have to compromise between the number of signals captured and the number of samples of the captured signals. This compromise results in the user either capturing the desired signals but not enough for the IC operation period required to fully understand the problem, or capturing enough for the IC operation period but not enough for the signals required to understand why a logic circuit in the circuit design is misbehaving.

[0013] Embedded logic analyzer circuitry is typically implemented using soft logic resources within programmable ICs. The soft logic resources used for embedded logic analyzer circuitry cannot be used in custom circuit designs for programmable ICs. Furthermore, introducing an embedded logic analyzer circuit into a circuit design using soft logic requires extensive layout and routing changes to the circuit design, which often fail to maintain signal timing. These changes in signal timing can alter the failure scenarios or sequences within the circuit design that the user is attempting to debug. Routing internal signals to the output pads of the programmable IC consumes additional valuable device resources, which can limit the number of internal signals that can be analyzed simultaneously.

[0014] According to some examples disclosed herein, a highly optimized embedded logic analyzer circuit is provided in hard logic within a programmable integrated circuit (IC) for debugging a circuit design of the programmable IC. The programmable IC may further include a hardware interface coupled between the embedded logic analyzer circuit and soft logic, the soft logic implementing the circuit design debugged by the embedded logic analyzer circuit. The hardware interface may be controlled by software available to a user. The hardware interface may expose a signal input interface of the embedded logic analyzer circuit to the soft logic implementing the circuit design of the programmable IC. Signals generated by the circuit design during various stages of compilation may be routed to the signal input interface of the embedded logic analyzer circuit via the hardware interface. The signals generated by the circuit design may be routed to the embedded logic analyzer circuit, for example, via a multiplexer circuit implemented in hard logic or soft logic and formed as part of the hardware interface. The hardware interface allows a user to select signals to be provided to the embedded logic analyzer circuit using a single compilation effort and fast runtime switching.

[0015] Throughout the specification and in the claims, the term "connected" means a direct electrical connection between the circuits being connected, without any intervening devices. The term "coupled" means a direct electrical connection between the circuits or an indirect electrical connection through one or more passive or active intervening devices. The term "circuit" may mean one or more passive and / or active electronic components arranged to cooperate with each other to provide a desired functionality.

[0016] One or more specific examples are described below. In order to provide a concise description of these examples, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Furthermore, it should be appreciated that such development work can be complex and time-consuming, but for those of ordinary skill having the benefit of this disclosure, it will remain a routine task of design, fabrication, and manufacturing.

[0017] Figure 1 is a diagram illustrating an example of an integrated circuit 100 including a logic analyzer circuit. Integrated circuit (IC) 100 may be any type of integrated circuit (IC), such as a programmable integrated circuit (IC), a microprocessor or central processing unit (CPU), a graphics processing unit (GPU), an application-specific IC, a memory IC, etc. Programmable ICs include any integrated circuit that can be programmed to execute a custom circuit design, including programmable logic arrays (PLAs), programmable array logic (PALs), field programmable gate arrays (FPGAs), and programmable logic devices (PLDs).

[0018] Integrated circuit (IC) 100 includes core logic region 102 and peripheral region 118. Peripheral region 118 includes logic analyzer circuits 104 and 124. IC 100 may also include additional logic analyzer circuits. Core logic region 102 includes 16 logic circuit blocks 106, bidirectional horizontal routing channels 108, and bidirectional vertical routing channels 109-111. Although Figure 1 16 blocks 106 and 4 routing channels 108-111 are shown in FIG1 , but it should be understood that IC 100 and other ICs having logic analyzer circuits can have any number of logic circuit blocks and any number of routing channels. Each of the routing channels can include conductors (wires) for routing signals, buffer circuits, and / or multiplexer circuits. In addition to routing channels external to block 106, IC 100 also includes routing channels within block 106. As an example, block 106 can include programmable logic circuits, digital signal processing (DSP) circuits, memory circuits (e.g., static random access memory or SRAM), microprocessors, etc. The programmable logic circuits in one or more of blocks 106 can include, for example, adaptive logic modules, lookup tables, registers, programmable logic array blocks, etc. Routing channels 108-111 can include, for example, programmable interconnects, network-on-chip (NOC) routing interconnects, fixed interconnects, etc.

[0019] Logic analyzer circuits 104 and 124 can capture signals generated by circuits in block 106 (or other blocks in IC 100) and transmit these captured signals to host computer system 114 via channels 116 and 136, respectively. Logic analyzer circuits 104 and 124 can capture signals generated by circuits in block 106 (or other blocks in IC 100) and transmit these captured signals to host computer system 114 via channels 116 and 136, respectively. Figure 1 , including signals originating from logic circuits in smaller blocks within block 106. Signals captured by one or both of logic analyzer circuits 104 and 124 are also referred to herein as monitor signals.

[0020] Logic analyzer circuits 104 and 124 may capture signals from logic circuits in block 106, group these captured signals with source clock signal timing information, and transmit these captured signals to host computer system 114 for storage and debugging (e.g., signal trace reconstruction by post-processing software). Logic analyzer circuits 104 and 124 may be used to debug signal data packets by monitoring debug signal byte lane values, creating packets containing new data values ​​and source clock timing information, and transmitting these packets to host computer system 114 for storage and debugging.

[0021] The logic analyzer circuits 104 and 124 can support multiple modes of operation, including, for example, a continuous drain mode and a separate buffer mode. In the continuous drain mode, the logic analyzer circuits 104 and 124 can continuously attempt to drain data from signals captured from block 106 downstream to a central trace aggregator (e.g., in IC 100 or host computer system 114) when a downstream trace path is available. If data is not intended to be drained downstream, the separate buffers in one or both of the logic analyzer circuits 104 and / or 124 can operate in two modes, including a stop-on-full mode and a circular buffer mode. The logic analyzer circuits 104 and 124 can support separate buffer modes with configurable start and stop signal trace storage, including a manual method using a configurable status register and hardware triggers.

[0022] The logic analyzer circuits 104 and 124 may also provide a watermarking capability to indicate to the host computer system 114 when the storage of signals captured from block 106 has reached a programmable threshold. The logic analyzer circuits 104 and 124 may also store separate byte lanes in separate output streams, or may combine multiple byte lanes into a single output stream. In some implementations, the logic analyzer circuits 104 and 124 may, for example, store only new data values ​​for a per-bit mask of data compression stored upon change, which reduces the occurrence of new data values ​​stored by the grouping logic in the logic analyzer circuits. The logic analyzer circuits 104 and 124 may also have a byte-wide event identifier that uses Boolean logic blocks (BLBs) to further qualify data storage (e.g., based on logic state) and drive a trigger sequencer event input for signals captured from block 106.

[0023] Logic analyzer circuits 104 and 124 may also provide intellectual property (IP) clock counter circuitry per packet stream of signals captured from block 106 for detecting source IP clock gating and frequency variations. One or both of logic analyzer circuits 104 and 124 may include a timestamp counter unit (TSCU) that combines an always-on timer (ART) with a local fast counter to generate timestamps. The TSCU in one or both of logic analyzer circuits 104 and 124 may generate timestamps indicating the time at which signals captured from logic circuits in block 106 were received. One or both of logic analyzer circuits 104 and 124 may transmit the timestamps to host computer system 114. When one or more externally driven trigger input signals are asserted, one or both of logic analyzer circuits 104 and 124 may generate additional trigger packets that mark the trigger position in the signal trace stream from block 106. These trigger packets may also be transmitted to host computer system 114.

[0024] In embodiments where IC 100 is a programmable IC, block 106 may include programmable logic circuitry (e.g., soft logic such as adaptive logic modules, lookup tables, programmable logic array blocks, etc.), DSP blocks, microprocessor circuitry including hard or soft logic, hard IP blocks, input / output interfaces (e.g., serializer / deserializer circuitry), and / or memory blocks. Logic analyzer circuits 104 and 124 may capture signals generated by circuitry in any of the programmable logic circuitry (e.g., adaptive logic modules, lookup tables, programmable logic array blocks), DSP blocks, microprocessor circuitry, hard IP blocks, input / output interfaces (e.g., serializer / deserializer circuitry), network-on-chip (NOC) routing, and / or memory blocks (e.g., SRAM) in IC 100. Signals may be transmitted from these circuits and blocks to logic analyzer circuits 104 and 124 via routing channels 108-112 and 132. Routing channels 108-112 and 132 may include programmable routing interconnects and conductors that may be programmed as disclosed below.

[0025] Logic analyzer circuits 104 and 124 can be implemented using non-programmable logic circuitry (i.e., hard logic). By implementing logic analyzer circuits 104 and 124 using hard logic in programmable IC 100, a user can debug the circuit design of programmable IC 100 without negatively impacting or changing the circuit design's utilization of soft logic resources in IC 100. As a result, the user can maximize the utilization of the soft logic in block 106 by the circuit design. Implementing logic analyzer circuit 104 using hard logic avoids compile and fit iterations of the circuit design of programmable IC 100 and significantly reduces the turnaround time of the user's debug cycle for the circuit design. Because debug logic circuitry is not added to the soft logic in block 106 to perform debugging or signal capture of the circuit design, signals generated by the circuit design can be captured by logic analyzer circuits 104 and 124 without changing the timing or state of the circuit design. As a result, the user can debug scenarios in the circuit design that are sensitive to changes in erroneous system behavior. No additional external terminals and soft logic resources of IC 100 are required to enable user logic debug functions using the signals captured by logic analyzer circuits 104 and 124 .

[0026] Horizontal routing channel 108 is coupled to logic analyzer circuit 104 via bidirectional routing channel 112. Horizontal routing channel 108 is coupled to logic analyzer circuit 124 via bidirectional routing channel 136. Horizontal routing channel 108 is also coupled to each of vertical routing channels 109, 110, and 111. Each of routing channels 108-111 can be coupled to logic circuits in adjacent blocks 106 via local routing channels, which include conductors / wires and interconnects for routing signals. Routing channels 108-112 can be programmed to route signals from any one or more logic circuits in any one or more blocks 106 to logic analyzer circuits 104 and / or 124 (e.g., during test mode or during normal system operation). Furthermore, routing channels 108-112 can be programmed to route signals from logic analyzer circuits 104 and / or 124 to any one or more logic circuits in any one or more blocks 106. A software program (eg, running on host computer system 114 ) may implement an algorithm that couples selected debug nodes in block 106 to an interface coupled to logic analyzer circuits 104 and / or 124 via routing channels 108 - 112 .

[0027] Embedding logic analyzer circuits 104 and 124 in IC 100 allows logic analyzer circuits 104 and 124 to capture signals both before and after one or more trigger conditions. These signals may include, for example, an acquisition clock signal, a data input signal, a trigger condition for a source input, and a storage qualification condition for the source input. Logic analyzer circuits 104 and 124 capture and store logic signals (e.g., from the logic circuit in block 106) and export these logic signals for viewing on host computer system 114. Using electronic design automation (EDA) software tools running on host computer system 114, a user can specify, for example, the signals of IC 100 to be monitored, one or more trigger conditions, a total number of samples of the signals to be stored, a number of samples of the signals to be captured after the occurrence of the trigger condition(s), and a system clock signal. Signals are continuously stored in memory within logic analyzer circuits 104 and 124. Once the trigger condition(s) occur, additional signal samples are captured, if desired, in addition to those captured before the trigger condition(s). The EDA tool directs logic analyzer circuits 104 and 124 to export data from memory for display on host computer system 114. Trigger condition(s) and sample count can be changed without recompiling the IC or the host. Logic analyzer circuits 104 and 124 can be controlled via one or more external terminals of the IC (e.g., a JTAG port). Input and output signals of logic analyzer circuits 104 and 124 are routed to and from host computer system 114 through one or more external terminals using input and output buffer circuits in IC 100.

[0028] In embodiments where IC 100 is a programmable IC, routing between monitored internal nodes generating signals in IC 100 (e.g., in block 106) and logic analyzer circuits 104 and 124 may be performed at various stages throughout the compilation of the circuit design of programmable IC 100. A user may decide at which compilation stage of the circuit design the signals are routed to logic analyzer circuits 104 and 124. Figure 2201 is a flowchart illustrating an example of a compilation operation for a circuit design of a programmable IC. After a circuit designer has input a circuit design for a programmable IC using an EDA tool and a register transfer level (RTL) file for the circuit design has been generated, analysis and elaboration can be performed using the RTL file in operation 201 to simulate the functionality of the circuit design. The analysis and elaboration performed in operation 201 may include timing analysis of the circuit design using timing constraints. If the functionality of the circuit design is incomplete or incorrect, the circuit designer can use the EDA tool to make changes to the circuit design and generate new RTL files.

[0029] For example, the circuit designer can create routes (i.e., couplings) between selected internal nodes that generate signals to be monitored and captured in IC 100 and logic analyzer circuits 104 and 124 during or after analysis and processing operation 201 and before synthesis. Advantages of creating these routes during or after operation 201 and before synthesis include providing maximum signal visibility and providing signal names that are close to those used in the RTL file. Disadvantages of creating these routes during or after operation 201 include requiring a full compilation of the circuit design and possible changes to the timing of the circuit design.

[0030] After the functional operation of the circuit design has been determined to be satisfactory, a logic synthesis and optimization tool (e.g., part of an EDA tool) may generate a gate-level netlist for the circuit design during synthesis operation 202. The logic synthesis and optimization tool may optimize the circuit design by appropriately selecting hardware to implement different logic functions in the circuit design based on constraint data and circuit design data input by the circuit designer using the EDA tool.

[0031] For example, the circuit designer may create routes (i.e., couplings) between selected internal nodes that generate signals to be monitored and captured in IC 100 and logic analyzer circuits 104 and 124 before, during, or after synthesis operation 202. Advantages of creating these routes during or after synthesis operation 202 include providing the ability to observe the state of the gate-level netlist generated during synthesis operation 202, reducing the analysis and processing performed in operation 201, and potentially reducing the time to perform synthesis operation 202. Disadvantages of creating these routes during or after synthesis operation 202 include providing a limited number of signal names that match the signal names used in the RTL file and causing timing changes in the circuit design.

[0032] After synthesis operation 202, the circuit designer may use a place and route tool (e.g., part of an EDA tool) to perform a place and route operation 203. The place and route tool may be used to determine where to place each gate of the gate-level netlist generated during operation 202 within the programmable IC. Place and route operation 203 creates an orderly and efficient implementation of the circuit design for any target integrated circuit (e.g., a given programmable integrated circuit such as a field programmable gate array (FPGA)).

[0033] For example, the circuit designer can create routes (i.e., couplings) between selected internal nodes that generate signals to be monitored and captured in IC 100 and logic analyzer circuits 104 and 124 during or after placement and routing operation 203. Advantages of creating these routes during or after placement and routing operation 203 include providing the ability to observe the state of the compiled circuit design generated during placement and routing operation 203, preserving the timing of the circuit design, and reducing compilation time. Disadvantages of creating these routes during or after placement and routing operation 203 include providing a limited number of signal names that match the signal names used in the RTL file.

[0034] In operation 204, the EDA tool performs assembly of the placed and routed circuit design generated in operation 203 to generate a complete or partial device configuration file. The configuration file may include, for example, a mask-level layout description of an integrated circuit or configuration data for programming a programmable IC.

[0035] EDA tools may provide a user interface that allows circuit designers to make decisions about Figure 2 The user interface may include a project setup file, an automation script, and a graphical user interface. Using the user interface, the circuit designer may select signal names based on a compilation phase (e.g., one or more of operations 201-203). The circuit designer may define the coupling between the nodes that generate the signals to be monitored and captured and the input ports of the logic analyzer circuits 104 and 124. In some embodiments, the coupling between the nodes that generate the signals to be monitored and captured and the input ports of the logic analyzer circuits 104 and 124 may be performed during partial reconfiguration of the programmable logic IC.

[0036] Logic analyzer circuits 104 and 124 each have a signal input interface that is insensitive to delay. The EDA tool can add an equal number of registers along each signal path from the signal source (i.e., node) to the signal input interface of each logic analyzer circuit 104 and 124. The registers are added to meet the timing requirements based on the clock signal input to the logic analyzer circuits 104 and 124. The number of registers added to each signal path is selected based on the timing requirements of the signal path. The EDA tool can provide a user interface to allow the circuit designer to specify how to tolerate delay differences. Based on input from the circuit designer, the EDA tool can insert the necessary number of registers into the signal path, which number is not equal in all signal paths to the logic analyzer circuits 104 and 124. The EDA tool operating on the host computer system 114 can include a logic analyzer control and analysis tool that applies one or more trigger conditions and visualizes the captured data based on the delay differences between the signal paths.

[0037] If IC 100 is a programmable IC, IC 100 can be fully or partially configured to couple logic analyzer circuits 104 and 124 to nodes being monitored in the circuit design. If the system under debug needs to be restarted, the full configuration of IC 100 is used to configure the programmable IC with an image of the circuit design, including the coupling to logic analyzer circuits 104 and 124. If the system under debug needs to maintain the current system state, the partial device configuration can be used to configure the programmable IC with only the coupling to logic analyzer circuits 104 and 124. In some implementations, during configuration or partial reconfiguration of programmable IC 100, logic analyzer circuits 104 and 124 can capture signals from the monitored nodes in the circuit in block 106.

[0038] The host computer system 114 can run a logic analyzer tool that the circuit designer can use to configure trigger conditions and storage conditions for the logic analyzer circuits 104 and 124 to access and store signals from monitored nodes and / or circuits in the block 106. The logic analyzer tool can also be configured to display captured signal data in various user interfaces, such as waveforms, listings, and decode information. The logic analyzer tool is typically connected to the chip via an on-chip debug communication channel and / or attached probe hardware / cable (in the Figure 1 The logic analyzer circuits 104 and 124 exchange data with each other.

[0039] In some implementations, the input interfaces to logic analyzer circuits 104 and 124 through channels 112 and 132, respectively, may have a limited width that does not allow all of the signals being monitored in IC 100 to be simultaneously communicated to logic analyzer circuits 104 and 124. In these implementations, the input interfaces to logic analyzer circuits 104 and 124 may include one or more multiplexer circuits that can be configured and reconfigured to provide the states of different sets of monitored signals from block 106 to logic analyzer circuits 104 and 124 at different times. The multiplexer circuits allow logic analyzer circuits 104 and 124 to obtain the states of many more signals than the input interfaces can communicate to logic analyzer circuits 104 and 124 at any one time.

[0040] Figure 3 is a diagram illustrating an example of an input interface to logic analyzer circuit 304 including a multiplexer circuit controlled by a register circuit. Figure 3 The logic analyzer circuit 304 may be, for example, Figure 1 Either of the logic analyzer circuits 104 or 124 . Figure 3 The input interface of the IC 100 includes three parallel selection circuits 301, 302 and 303 located in the IC 100 (for example, in block 106). The three selection circuits 301-303 are arranged in parallel. Figure 3 It should be understood that the input interface to the logic analyzer circuit 304 may have any number of selection circuits having circuit blocks that select circuits 301 - 303 .

[0041] Each of the selection circuits 301-303 includes logic circuits 31 and 32 (e.g., user logic circuits in a programmable IC), three register circuits 33-35, and three multiplexer circuits 36-38. In a programmable IC, the logic circuits 31-32 include programmable logic circuits, such as adaptive logic modules, programmable logic array blocks, lookup tables, and the like. In some implementations of the programmable logic IC, the multiplexers 36-38 in each of the selection circuits 301-303 may be implemented by combinatorial programmable logic circuits in block 106 (e.g., a programmable logic block), such as lookup table (LUT) circuits.

[0042] The following description of circuits 31-38 applies to each of the selection circuits 301-303. Logic circuit 31 provides two output logic signals to the data input of multiplexer circuit 36, and logic circuit 32 provides two output logic signals to the data input of multiplexer circuit 37. For the purpose of debugging the circuit design of IC 100, the output logic signals of logic circuits 31-32 provided to multiplexer circuits 36-37 are signals that can be monitored and stored in logic analyzer circuit 304. The selected output signal of multiplexer circuits 36-37 is provided to the data input of multiplexer circuit 38.

[0043] The outputs of register circuits 33-34 are coupled to select inputs of multiplexer circuits 36-37, respectively. The values ​​of the output signals stored in register circuits 33-34 control the selection of multiplexer circuits 36-37, respectively. That is, the values ​​of the output signals stored in register circuits 33-34 determine which of the output logic signals of logic circuits 31-32 are provided to the data input of multiplexer circuit 38 via multiplexer circuits 36-37.

[0044] The value of the output signal stored in register circuit 35 controls the selection of multiplexer circuit 38. That is, the value of the output signal stored in register circuit 35 determines which of the output signals of multiplexer circuits 36-37 are provided to the input of logic analyzer circuit 304 through multiplexer circuit 38.

[0045] Logic analyzer circuit 304 receives the value of the monitored signal from logic circuit 31 or 32 in each of selection circuits 301-303. Thus, logic analyzer circuit 304 receives the values ​​of three monitored signals from the three selection circuits 301-303 at any given time. The value of one or more of the output signals stored in one or more of register circuits 33-35 in any of selection circuits 301-303 can be changed at any time to reconfigure multiplexer circuits 36-38 in that selection circuit to provide a different value of the logic signal from one of logic circuits 31-32 to logic analyzer circuit 304. The values ​​of the output signals stored in register circuits 33-35 can be changed, for example, by a logic analyzer tool in host computer system 114.

[0046] Thus, by changing the selection of one or more of the multiplexer circuits 36-38, the selection circuits 301-303 can be reconfigured at any time to provide different sets of values ​​for monitored signals from the logic circuits 31-32 to the logic analyzer circuit 304. As a result, the selection circuits 301-303 can be configured and reconfigured to select a much larger number of monitored signals that are provided in groups to the logic analyzer circuit 304 at different times. The monitored signals are selected in groups, and each group of monitored signals is transmitted to the logic analyzer circuit 304 at a different time. For example, the selection circuits 301-303 may transmit a first group of monitored signals to the logic analyzer circuit 304 in a first time interval, and the selection circuits 301-303 may transmit a second group of monitored signals to the logic analyzer circuit 304 in a second time interval that follows the first time interval. If IC 100 has enough selection circuits 301-303, each group of signals can include, for example, hundreds or thousands of monitored signals.

[0047] Figure 4 is a diagram illustrating an example of an input interface to logic analyzer circuit 404 including a multiplexer circuit controlled by a memory circuit. Figure 4 The logic analyzer circuit 404 may be, for example, Figure 1 Either of the logic analyzer circuits 104 or 124 . Figure 4 The input interface of IC 100 includes three parallel selection circuits 401, 402, and 403 located in IC 100. In an embodiment where IC 100 is a programmable IC, selection circuits 401, 402, and 403 may include, for example, multiplexers in a programmable routing channel, such as routing channels 108-112 and / or 132. Figure 4 Only three selection circuits 401 - 403 are shown in FIG. 4 . It should be understood that the input interface to the logic analyzer circuit 404 may have any number of selection circuits having circuit modules selecting circuits 401 - 403 and / or 301 - 303 .

[0048] Each of the selection circuits 401-403 includes logic circuits 41 and 42 (e.g., user logic circuits in a programmable IC), three memory circuits 43-45, and three multiplexer circuits 46-48. In a programmable IC, the logic circuits 41-42 include programmable logic circuits, such as adaptive logic modules, lookup tables, or programmable logic array blocks, the memory circuits 43-45 are configuration memory circuits (e.g., configurable random access memory (RAM)) that store configuration data for configuring the IC 100, and the multiplexer circuits 46-48 are in programmable routing channels in the routing structure, such as channels 108-112 and 132 in the IC 100.

[0049] The following description of circuits 41-48 applies to each of the selection circuits 401-403. Logic circuit 41 provides two output logic signals to the data input of multiplexer circuit 46, and logic circuit 42 provides two output logic signals to the data input of multiplexer circuit 47. For the purpose of debugging the circuit design of IC 100, the output logic signals of logic circuits 41-42 provided to multiplexer circuits 46-47 are signals that can be monitored and stored in logic analyzer circuit 404. The output signals of multiplexer circuits 46-47 are provided to the data input of multiplexer circuit 48.

[0050] The outputs of memory circuits 43-44 are coupled to select inputs of multiplexer circuits 46-47, respectively. The values ​​of the signals stored in memory circuits 43-44 control the selection of multiplexer circuits 46-47, respectively. That is, the values ​​of the signals stored in memory circuits 43-44 determine which of the output logic signals of logic circuits 41-42 are provided to the data input of multiplexer circuit 48 via multiplexer circuits 46-47.

[0051] The value of the signal stored in memory circuit 45 controls the selection of multiplexer circuit 48. That is, the value of the signal stored in memory circuit 45 determines which of the output signals of multiplexer circuits 46-47 are provided to the input of logic analyzer circuit 404 through multiplexer circuit 48.

[0052] exist Figure 4In the example shown in FIG. 4 , logic analyzer circuit 404 receives the value of a monitored signal from logic circuit 41 or 42 in each of selection circuits 401-403. Thus, logic analyzer circuit 404 receives the values ​​of three monitored signals from the three selection circuits 401-403 at any given moment. The values ​​of one or more of the signals stored in one or more of memory circuits 43-45 in any of selection circuits 401-403 can be changed at any time to reconfigure multiplexer circuits 46-48 in that selection circuit to provide a different value of a signal from one of logic circuits 41-42 to logic analyzer circuit 404. The values ​​of the signals stored in memory circuits 43-45 can be configured at runtime using partial reconfiguration of the programmable IC without affecting the state of the circuit design programmed into the programmable IC.

[0053] Thus, by changing the selection of one or more of the multiplexer circuits 46-48, the selection circuits 401-403 can be reconfigured at any time (e.g., using partial reconfiguration) to provide different sets of values ​​for the monitored signals from the logic circuits 41-42 to the logic analyzer circuit 404. As a result, the selection circuits 401-403 can be configured and reconfigured to select a much larger number of monitored signals that are provided in groups to the logic analyzer circuit 404 at different times. The monitored signals are selected in groups, and each group of monitored signals is transmitted to the logic analyzer circuit 404 at a different time. For example, the selection circuits 401-403 may transmit a first group of monitored signals to the logic analyzer circuit 404 in a first time interval, and the selection circuits 401-403 may transmit a second group of monitored signals to the logic analyzer circuit 404 in a second time interval that follows the first time interval. If the IC 100 has enough selection circuits 401-403, each group of signals can include, for example, hundreds or thousands of monitored signals.

[0054] Figure 5 is a diagram illustrating an example of an input interface to the logic analyzer circuit 507 included in the multiplexer circuit in the peripheral area of ​​the IC 100 . Figure 5 The logic analyzer circuit 507 may be, for example, Figure 1 Either of the logic analyzer circuits 104 or 124 . Figure 5 Three regions 501, 502, and 503 (eg, blocks 106) of IC 100 are illustrated, each including logic circuits 51, 52, and 53. The three logic circuits 51-53 are Figure 55. It is shown here only as an example. It should be understood that logic analyzer circuit 507 can receive signals from any number of logic circuits. In a programmable IC, logic circuits 51-53 include programmable logic circuits such as adaptive logic modules, lookup tables, programmable logic array blocks, etc.

[0055] Circuit block 504, located in a peripheral area of ​​IC 100, includes multiplexer circuit 505, register circuit 506, and logic analyzer circuit 507. The output logic signal of each of logic circuits 51, 52, and 53 is provided to a different data input of multiplexer circuit 505. Thus, multiplexer circuit 505 receives at least three signals from at least three different logic circuits 51-53 at three or more data inputs.

[0056] Register circuit 506 stores the output signal that is provided to the select input of multiplexer circuit 505. The value of the output signal stored in register circuit 506 controls the selection of multiplexer circuit 505. That is, the value of the output signal stored in register circuit 506 determines which of the signals received from logic circuits 51-53 are provided to the input of logic analyzer circuit 507. In some implementations, multiplexer circuit 505 can be configured to simultaneously provide two or more signals from logic circuits 51-53 (and possibly other logic circuits) to logic analyzer circuit 507.

[0057] The value of the output signal stored in register circuit 506 can be changed using a tool by latching a different value into register circuit 506 via a debug communication channel (such as a Joint Test Action Group (JTAG) channel). The value of the output signal stored in register circuit 506 can be changed at any time to change the selection of multiplexer circuit 505, thereby providing a different monitored signal value (or multiple different monitored signal values) from logic circuits 51-53 to logic analyzer circuit 507. As a result, multiplexer circuit 505 can be configured and reconfigured to select a much larger number of monitored signals to be provided to logic analyzer circuit 507 at different times. Each monitored signal or group of monitored signals is selected by multiplexer circuit 505 and transmitted to logic analyzer circuit 507 at a different time. For example, if multiplexer circuit 505 has enough inputs coupled to as many logic circuits, each group of signals can include hundreds or thousands of monitored signals.

[0058] In some implementations, references herein to Figure 3-5 Two or more of the disclosed input interfaces may be used in a single channel within an IC that provides the monitored signal to logic analyzer circuits 104 and 124. Figure 3-5 Any combination of the disclosed input interfaces may be deployed in a single IC to implement grouping of signals to be monitored (e.g., signal width) and desired user signal selection using logic analyzer circuits 104 and 124. Figure 3-5 Any one or more of the disclosed input interfaces may be used to provide monitored signals to a logic analyzer circuit implemented in soft logic in a programmable IC.

[0059] Figure 6 An example of a programmable integrated circuit (IC) 600 is illustrated, which may include the circuits disclosed herein. For example, the programmable IC 600 may be a Figure 1 Public IC 100. Figure 6 As shown in FIG, a programmable integrated circuit (IC) 600 includes a two-dimensional array of configurable (programmable) functional circuit blocks, including a configurable logic array block (LAB) 610 and other functional circuit blocks, such as a random access memory (RAM) block 630 and a digital signal processing (DSP) block 620. Functional blocks such as LAB 610 may include smaller programmable logic circuits (e.g., logic elements, logic blocks, or adaptive logic modules) that receive input signals and perform customized functions on the input signals to produce output signals. In some implementations, LAB 610 may be or include Figure 3-5 logic circuit. Figure 6 The configurable functional circuit blocks shown in can be organized into sectors, or can each include multiple sectors of programmable logic circuitry.

[0060] In addition, the programmable IC 600 may have input / output elements (IOEs) 602 for driving signals out of the programmable IC 600 and for receiving signals from other devices. The input / output elements 602 may include parallel input / output circuit modules, serial data transceiver circuit modules, differential receiver and transmitter circuit modules, or other circuit modules for connecting one integrated circuit to another integrated circuit. As shown, the input / output elements 602 may be located around the periphery of the chip. If desired, the programmable IC 600 may have input / output elements 602 arranged in different ways. For example, the input / output elements 602 may form one or more columns, rows, or islands of input / output elements, which may be located anywhere on the programmable IC 600.

[0061] The programmable IC 600 may also include programmable interconnect circuit modules in the form of vertical routing channels 640 (i.e., interconnects formed along the vertical axis of the programmable IC 600) and horizontal routing channels 650 (i.e., interconnects formed along the horizontal axis of the programmable IC 600), each routing channel including at least one conductor to route at least one signal.

[0062] Note that except Figure 6 In addition to the topology of interconnecting circuit modules depicted in FIG, other routing topologies can be used. For example, in the case of a three-dimensional integrated circuit, the routing topology can include wires running diagonally or running horizontally and vertically along different parts of their extent, as well as wires running perpendicular to the plane of the device. The driver for the wire can be located at a point different from one end of the wire.

[0063] In addition, it should be understood that the Figure 1-5 The disclosed embodiments can be implemented in any integrated circuit or electronic system. If desired, the functional blocks of such an integrated circuit can be arranged in more levels or layers, where multiple functional blocks are interconnected to form larger blocks. Other device arrangements can use functional blocks that are not arranged in rows and columns.

[0064] Programmable IC 600 may include programmable memory elements. The memory elements may be loaded with configuration data using input / output elements (IOEs) 602. Once loaded, the memory elements each provide corresponding static control signals that control the operation of the associated configurable functional block (e.g., LAB 610, DSP block 620, RAM block 630, or input / output element 602).

[0065] In a typical scenario, the output of the loaded memory element is applied to the gate of a metal oxide semiconductor field effect transistor (MOSFET) in a functional block to turn certain transistors on or off and thereby configure the logic in the functional block including the routing path. Programmable logic circuit elements that can be controlled in this manner include multiplexers (e.g., multiplexers used to form routing paths in interconnect circuits), lookup tables, logic arrays, AND, OR, XOR, NAND, and NOR logic gates, pass gates, and the like.

[0066] Programmable memory elements can be organized in a configuration memory array with rows and columns. Data registers spanning all columns and address registers spanning all rows can receive configuration data. Configuration data can be transferred to the data registers. When the appropriate address register is active, the data registers write the configuration data to the configuration memory bits for the row specified by the address register.

[0067] In some embodiments, programmable IC 600 may include configuration memory organized in sectors, whereby a sector may include configuration RAM bits that specify the functions and / or interconnections of subcomponents and wires in or through that sector. Each sector may include independent data and address registers.

[0068] Figure 6 The programmable IC is merely one example of an IC that can be used with the embodiments disclosed herein. The embodiments disclosed herein can be used with any suitable integrated circuit or system. For example, the embodiments disclosed herein can be used with various types of devices, such as processor integrated circuits, central processing units, memory integrated circuits, graphics processing unit integrated circuits, application specific standard products (ASSPs), application specific integrated circuits (ASICs), and programmable logic integrated circuits. Examples of programmable logic integrated circuits include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), to name a few.

[0069] The integrated circuits disclosed in one or more embodiments herein may be part of a data processing system that includes one or more of the following components: a processor; a memory; an input / output circuit module; and peripheral devices. The data processing system may be used in a variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other suitable application. The integrated circuits may be used to perform a variety of different logic functions.

[0070] Typically, the software and data for performing any of the functions disclosed herein can be stored in a non-transitory computer-readable storage medium. A non-transitory computer-readable storage medium is a tangible computer-readable storage medium that stores data and software for access at a later time, in contrast to a medium (e.g., wire) that only transmits propagating electrical signals. Software code may sometimes be referred to as software, data, program instructions, instructions, or code. A non-transitory computer-readable storage medium may, for example, include a computer memory chip, a non-volatile memory such as a non-volatile random access memory (NVRAM), one or more hard drives (e.g., a magnetic drive or solid-state drive), one or more removable flash drives or other removable media, a compact disc (CD), a digital versatile disc (DVD), a Blu-ray disc (BD), other optical media, and a floppy disk, a magnetic tape, or any other suitable memory or (one or more) storage device.

[0071] Additional examples are now disclosed. Example 1 is an integrated circuit comprising: a logic circuit; a logic analyzer circuit; and a first multiplexer circuit, the first multiplexer circuit configurable to provide the value of a first signal selected from a first one of the logic circuits to the logic analyzer circuit, wherein the logic analyzer circuit is configured to store the value of the first signal selected by the first multiplexer circuit.

[0072] In Example 2, the integrated circuit of Example 1 can optionally include, wherein the logic analyzer circuit is implemented in hard logic, and the integrated circuit is a programmable integrated circuit.

[0073] In Example 3, the integrated circuit of any of Examples 1-2 may optionally include, wherein the logic analyzer circuit is configured to provide the value of the first signal from the first logic circuit in the logic circuit external to the integrated circuit.

[0074] In Example 4, the integrated circuit of any one of Examples 1-3 may optionally include, wherein the first multiplexer circuit is reconfigurable to provide the value of a second signal selected from a second logic circuit of the logic circuits to the logic analyzer circuit, and the logic analyzer circuit is configured to store the value of the second signal.

[0075] In Example 5, the integrated circuit of any one of Examples 1-4 further includes: a second multiplexer circuit configured to select a value of a second signal from a second logic circuit of the logic circuits; and a third multiplexer circuit configured to provide the value of a selected one of the first signal selected by the first multiplexer circuit or the second signal selected by the second multiplexer circuit to the logic analyzer circuit.

[0076] In Example 6, the integrated circuit of any one of Examples 1-5 may optionally include, wherein the logic analyzer circuit is configured to generate a trigger packet in response to a trigger input signal, the trigger packet marking a trigger position in a signal trace stream from the logic circuit.

[0077] In Example 7, the integrated circuit of any of Examples 1-6 may optionally include that the first multiplexer circuit is in one of: a lookup table circuit, a routing channel of the integrated circuit configurable to route signals from the logic circuit, or a peripheral area of ​​the integrated circuit.

[0078] In Example 8, the integrated circuit of any of Examples 1-6 may optionally include, wherein the logic analyzer circuit is configured to generate a timestamp indicating a time when the value of the first signal is received at the logic analyzer circuit.

[0079] In Example 9, the integrated circuit of any one of Examples 1-8 may optionally include, wherein the logic analyzer circuit supports a continuous drain mode and an independent buffer mode.

[0080] Example 10 is a method for capturing a signal within an integrated circuit, the method comprising: providing a first logic signal from a first logic circuit to a first multiplexer circuit; providing a second logic signal from a second logic circuit to the first multiplexer circuit; selecting one of the first logic signal or the second logic signal as a first selection signal using the first multiplexer circuit, wherein the first logic circuit and the second logic circuit and the first multiplexer circuit are in the integrated circuit; and storing a value of the first selection signal in a logic analyzer circuit in the integrated circuit.

[0081] In Example 11, the method of Example 10 may optionally include, wherein the first multiplexer circuit selects one of the first logic signal or the second logic signal as the first selection signal, and the logic analyzer circuit stores the value of the first selection signal after analyzing and processing the circuit design of the integrated circuit.

[0082] In Example 12, the method of any of Examples 10-11 may optionally include, wherein the first multiplexer circuit selects one of the first logic signal or the second logic signal as the first selection signal, and the logic analyzer circuit stores the value of the first selection signal after synthesizing the circuit design into the integrated circuit.

[0083] In Example 13, the method of any of Examples 10-12 may optionally include, wherein the first multiplexer circuit selects one of the first logic signal or the second logic signal as the first selection signal, and the logic analyzer circuit stores the value of the first selection signal after placing and routing the circuit design to the integrated circuit.

[0084] In Example 14, the method of any of Examples 10-13 further includes: providing a third logic signal from a third logic circuit to a second multiplexer circuit; providing a fourth logic signal from a fourth logic circuit to the second multiplexer circuit; and selecting one of the third logic signal or the fourth logic signal as a second selection signal using the second multiplexer circuit.

[0085] In Example 15, the method of Example 14 further includes: selecting the first selection signal or the second selection signal as a third selection signal using a third multiplexer circuit; and storing a value of the third selection signal in the logic analyzer circuit.

[0086] In Example 16, the method of any of Examples 10-15 may optionally include, wherein using the first multiplexer circuit to select one of the first logic signal or the second logic signal as the first selection signal further includes using the first multiplexer circuit to select the first logic signal as the first selection signal during a first time interval, and using the first multiplexer circuit to select the second logic signal as the first selection signal during a second time interval after the first time interval.

[0087] In Example 17, the method of any of Examples 10-16 may optionally include, wherein storing the value of the first selection signal in the logic analyzer circuit further comprises storing the value of the first selection signal in the logic analyzer circuit in response to a trigger condition.

[0088] Example 18 is a programmable integrated circuit comprising: a first logic circuit and a second logic circuit; a multiplexer circuit, the multiplexer circuit being configurable to provide a value of an output signal of a selected one of the first logic circuit or the second logic circuit in a selected signal; and a logic analyzer circuit configured to store the selected signal, wherein the logic analyzer circuit is implemented by hard logic.

[0089] In Example 19, the programmable integrated circuit of Example 18 may optionally include, wherein the multiplexer circuit is in a routing channel of the programmable integrated circuit, the routing channel being configurable to route signals from the first logic circuit and the second logic circuit.

[0090] In Example 20, the programmable integrated circuit of any of Examples 18-19 may optionally include, wherein the logic analyzer circuit groups the captured signals received from the first logic circuit and the second logic circuit with source clock signal timing information of the captured signals.

[0091] The foregoing description of examples has been presented for illustrative purposes. The foregoing description is not intended to be exhaustive or limiting to the examples disclosed herein. In some examples, features of the examples may be employed without corresponding use of other features as described. Many modifications, substitutions, and variations are possible in light of the above teachings.

Claims

1. An integrated circuit comprising: Logic circuits; Logic analyzer circuit; as well as a first multiplexer circuit configurable to provide a value of a first signal selected from a first one of the logic circuits to the logic analyzer circuit, wherein the logic analyzer circuit is configured to store the value of the first signal selected by the first multiplexer circuit.

2. The integrated circuit according to claim 1, wherein: The logic analyzer circuit is implemented in hard logic and the integrated circuit is a programmable integrated circuit.

3. The integrated circuit according to any one of claims 1 to 2, wherein: The logic analyzer circuit is configured to provide the value of the first signal from the first logic circuit among the logic circuits external to the integrated circuit.

4. The integrated circuit according to any one of claims 1 to 3, wherein: The first multiplexer circuit is reconfigurable to provide a value of a second signal selected from a second one of the logic circuits to the logic analyzer circuit, and the logic analyzer circuit is configured to store the value of the second signal.

5. The integrated circuit according to any one of claims 1 to 4, further comprising: a second multiplexer circuit configurable to select a value of a second signal from a second one of the logic circuits; as well as A third multiplexer circuit is configurable to provide a value of a selected one of the first signal selected by the first multiplexer circuit or the second signal selected by the second multiplexer circuit to the logic analyzer circuit.

6. The integrated circuit according to any one of claims 1 to 5, wherein: The logic analyzer circuit is configured to generate a trigger packet in response to a trigger input signal, the trigger packet marking a trigger position in a stream of signal traces from the logic circuit.

7. The integrated circuit according to any one of claims 1 to 6, wherein: The first multiplexer circuit is in one of: a lookup table circuit, a routing channel of the integrated circuit configurable to route signals from the logic circuit, or a peripheral area of ​​the integrated circuit.

8. The integrated circuit according to any one of claims 1 to 6, wherein: The logic analyzer circuit is configured to generate a timestamp indicating a time when the value of the first signal was received at the logic analyzer circuit.

9. The integrated circuit according to any one of claims 1 to 8, wherein: The logic analyzer circuit supports continuous drain mode and independent buffer mode.

10. A method for capturing a signal within an integrated circuit, the method comprising: providing a first logic signal from the first logic circuit to the first multiplexer circuit; providing a second logic signal from a second logic circuit to the first multiplexer circuit; selecting one of the first logic signal or the second logic signal as a first selection signal using the first multiplexer circuit, wherein the first logic circuit and the second logic circuit and the first multiplexer circuit are in the integrated circuit; as well as The value of the first select signal is stored in a logic analyzer circuit in the integrated circuit.

11. The method according to claim 10, wherein: The first multiplexer circuit selects one of the first logic signal or the second logic signal as the first selection signal, and the logic analyzer circuit stores the value of the first selection signal after analyzing and processing a circuit design of the integrated circuit.

12. The method according to any one of claims 10-11, wherein The first multiplexer circuit selects one of the first logic signal or the second logic signal as the first select signal, and the logic analyzer circuit stores the value of the first select signal after synthesizing a circuit design into the integrated circuit.

13. The method according to any one of claims 10 to 12, wherein: The first multiplexer circuit selects one of the first logic signal or the second logic signal as the first select signal, and the logic analyzer circuit stores the value of the first select signal after placing and routing a circuit design to the integrated circuit.

14. The method according to any one of claims 10 to 13, further comprising: providing a third logic signal from the third logic circuit to the second multiplexer circuit; providing a fourth logic signal from a fourth logic circuit to the second multiplexer circuit; as well as The second multiplexer circuit is used to select one of the third logic signal or the fourth logic signal as a second selection signal.

15. The method according to claim 14, further comprising: using a third multiplexer circuit to select either the first selection signal or the second selection signal as a third selection signal; as well as The value of the third select signal is stored in the logic analyzer circuit.

16. The method according to any one of claims 10 to 15, wherein: Using the first multiplexer circuit to select one of the first logic signal or the second logic signal as the first selection signal also includes using the first multiplexer circuit to select the first logic signal as the first selection signal during a first time interval, and using the first multiplexer circuit to select the second logic signal as the first selection signal during a second time interval after the first time interval.

17. The method according to any one of claims 10 to 16, wherein: Storing the value of the first select signal in the logic analyzer circuit further includes storing the value of the first select signal in the logic analyzer circuit in response to a trigger condition.

18. A programmable integrated circuit comprising: a first logic circuit and a second logic circuit; a multiplexer circuit configurable to provide in a selected signal a value of an output signal of a selected one of the first logic circuit or the second logic circuit; as well as A logic analyzer circuit is configured to store a value of the selected signal, wherein the logic analyzer circuit is implemented in hard logic.

19. The programmable integrated circuit according to claim 18, wherein: The multiplexer circuit is in a routing channel of the programmable integrated circuit, the routing channel being configurable to route signals from the first logic circuit and the second logic circuit.

20. The programmable integrated circuit according to any one of claims 18 to 19, wherein: The logic analyzer circuit groups captured signals received from the first logic circuit and the second logic circuit with source clock signal timing information of the captured signals.

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