Chip and preparation method thereof

Abstract

The invention provides a chip, which comprises a chip substrate, and regularly arranged recesses are formed on at least one surface of the chip substrate; and the recess sequentially comprises a first geometric structure and a second geometric structure which are communicated with each other in the direction from the surface of the chip substrate to the center part. According to the chip provided by the embodiment of the invention, the recesses which are regularly arranged are formed in the substrate, and each recess sequentially comprises a first geometric structure and a second geometric structure which are communicated with each other in the direction from the surface of the chip substrate to the center part; according to the sunken morphology structure, during biochemical reaction in the detection process (such as nucleic acid sequencing), substance exchange and diffusion are carried out on a reaction reagent liquid phase and active molecules on the surface of the reaction reagent liquid phase, the reaction is promoted, and better detection signals (including signal brightness and signal-to-noise ratio) and more accurate detection results are obtained.

Description

Technical Field

[0001] The present invention relates to the field of biotechnology, and in particular to a chip and a preparation method thereof. Background Art

[0002] Chips used in biomolecule detection platforms integrate biochemical analysis processes onto the chip surface based on the principle of specific interactions between biomolecules, enabling high-throughput and rapid detection of DNA, RNA, peptides, proteins, and other biological components. Biochips offer advantages such as high throughput, miniaturization, and automated detection. They are widely used in fields such as gene sequencing, protein detection, and small biomolecule detection (such as carbohydrates). They provide viable technical solutions for nucleic acid sequence analysis, drug screening, and large-scale biological sample testing.

[0003] The chip surface can be formed into biomolecule detection sites through geometric structures of specific shapes. By forming a patterned arrangement of sites, it is easier to control the density of the chip surface geometric structure and enable the simultaneous detection of a variety of test samples, thereby improving detection throughput. Setting the chip surface as a patterned surface with a regular arrangement of geometric structures helps to increase the chip's arrangement density and improve surface utilization.

[0004] Nucleic acid sequencing on chip surfaces is widely used. Research has found that the chip structure, which serves as both the carrier for sequencing and the device that initiates the sequencing reaction, influences various parameters that reflect the sequencing results, and thus the accuracy of the results. Designing an appropriate chip micro-nanostructure to improve sequencing stability and accuracy has become a major concern for those skilled in the field. Summary of the Invention

[0005] The inventors have discovered that in chip-based nucleic acid sequencing methods, the shape and size of the chip surface geometric structure, including the vertical height, horizontal size, depth, and shape of the geometric structure (e.g., whether the geometric structure is narrow at the top and wide at the bottom, wide at the top and narrow at the bottom, or uniformly wide at the top and narrow at the bottom), can affect the stability and accuracy of the sequencing results. This influence is reflected in sequencing metrics or parameters obtained during the sequencing process, such as the stability of the clonal clusters obtained after amplification of nucleic acid molecules within the geometric structure, the signal brightness captured during the sequencing process, parameters of the quality of the sequencing sequence (reads) such as Q30, the sample multi-tag resolution rate, and the alignment rate of the sequencing results with the reference genome.

[0006] In view of this, the present invention provides a chip and a preparation method thereof that are beneficial to improving sequencing quality by designing the shape and size of the chip's geometric structure.

[0007] A first aspect of the present invention provides a patterned chip, comprising a chip substrate, wherein regularly arranged depressions are formed on at least one surface of the chip substrate;

[0008] The recess includes a first geometric structure and a second geometric structure that are interconnected in sequence from the surface of the chip substrate toward the center;

[0009] The first geometric structure has a depth c in a direction perpendicular to the chip surface of 0 to 100 μm, a maximum dimension a in a direction horizontal to the chip surface of 10 nm to 100 μm, and a maximum dimension b in a horizontal direction away from the chip surface of 10 nm to 100 μm; an angle α between a sidewall of the first geometric structure and the horizontal direction of the side away from the chip surface of 10 nm to 170°;

[0010] The depth e of the second geometric structure in a direction perpendicular to the chip surface is 0 to 100 μm, and the maximum dimension d in a horizontal direction away from the chip surface is 0 to 100 μm; the depth c and the depth e are not both 0.

[0011] By forming regularly arranged recessed structures on a substrate, the present invention improves sequencing stability and accuracy. Furthermore, the regularly arranged recessed structures increase their density on the chip, improving detection throughput. Furthermore, the regularly arranged recessed structures can be used to locate the detection sites corresponding to the recessed structures, facilitating the simultaneous detection of multiple nucleic acid molecules on the same chip surface and reducing detection costs.

[0012] As a possible implementation manner, the recess includes a first geometric structure and a second geometric structure that are interconnected in sequence from the surface of the chip substrate toward the center.

[0013] As a possible embodiment, the depth c of the first geometric structure in the direction perpendicular to the surface is 0 to 100 μm, the maximum dimension a in the direction horizontal to the surface is 10 nm to 100 μm, and the maximum dimension b in the horizontal direction away from the surface is 10 nm to 100 μm; the angle α between the side wall of the first geometric structure and the horizontal direction away from the chip surface is 10 to 170°.

[0014] As a possible embodiment, the depth c of the first geometric structure in the direction perpendicular to the chip surface is 0 to 100 μm, the maximum dimension a in the horizontal direction of the chip surface is 10 nm to 100 μm, and the maximum dimension b in the horizontal direction away from the chip surface is 10 nm to 100 μm; the angle α between the side wall of the first geometric structure and the horizontal direction of the side away from the chip surface is 10 to 170°.

[0015] As a possible implementation, the depth e of the second geometric structure in the direction perpendicular to the chip surface is 0-100 μm, and the maximum dimension d in the horizontal direction away from the chip surface is 0-100 μm; the depth c and depth e are not 0 at the same time.

[0016] As a possible implementation, the angle α satisfies the following relationship: 10≤α<90°.

[0017] As a possible implementation manner, the maximum dimension a is greater than the maximum dimension b, and the maximum dimension b is equal to the maximum dimension d. In this case, the shape of the recess is similar to a trumpet shape.

[0018] As a possible implementation manner, when the shape of the depression is similar to a trumpet shape, the depth c is 50 nm to 50 μm.

[0019] As a possible implementation, the maximum dimension a is greater than the maximum dimension b, the maximum dimension b is greater than the maximum dimension d, and the maximum dimension d is not 0; in this case, the shape of the depression is similar to a truncated cone, that is, a cone-like shape with a flat bottom at the top.

[0020] As a possible implementation manner, when the shape of the depression is similar to a truncated cone, the depth c is 50 nm to 50 μm.

[0021] As a possible implementation manner, when the shape of the recess is similar to a truncated cone, the ratio of the depth c to the depth e is 1:1000 to 1000:1;

[0022] As a possible implementation manner, the maximum dimension a is greater than the maximum dimension b, and the maximum dimension d is equal to 0; in this case, the shape of the recess is similar to a cone.

[0023] As a possible implementation manner, when the shape of the depression is similar to a cone, the depth c is 50 nm to 50 μm;

[0024] As a possible implementation, when the shape of the recess is similar to a cone, the depth e is 0.

[0025] As a possible implementation manner, the distance f between adjacent recesses is 10 nm to 100 μm. In the present application, the distance between adjacent recesses is the distance between the centers of the recesses.

[0026] As a possible implementation, the surface has at least one array unit, and the array unit has regularly arranged recesses.

[0027] As a possible implementation manner, the array unit is one or more of a square array unit, a rectangular array unit, and a honeycomb array unit.

[0028] As a possible implementation manner, the chip further includes a first cover plate combined with a surface of one side of the chip substrate where a recess is provided, and the first cover plate is made of a material with a light transmittance greater than or equal to 95%.

[0029] As a possible implementation manner, the surface of the first cover plate facing the chip substrate is a flat surface.

[0030] As a possible implementation manner, a surface of the first cover plate facing the chip substrate is provided with a regularly arranged geometric structure, and the geometric structure of the first cover plate is the same as or different from the recess of the chip substrate.

[0031] As a possible implementation manner, the chip substrate has regularly arranged geometric structures on both surfaces.

[0032] As a possible implementation, the chip includes a first cover plate and a second cover plate respectively bonded to two side surfaces of the chip substrate, and the first cover plate and the second cover plate are made of a material with a light transmittance greater than or equal to 95%.

[0033] As a possible implementation manner, both surfaces of the first cover plate and the second cover plate are flat surfaces.

[0034] As a possible implementation manner, the first cover plate is a cover plate with a geometric structure provided on a surface thereof, and the geometric structure of the first cover plate is arranged opposite to the recess of the chip substrate, and both surfaces of the second cover plate are flat surfaces.

[0035] As a possible implementation manner, the first cover plate and the second cover plate are both cover plates with geometric structures disposed on their surfaces, and the geometric structures on the first cover plate and the second cover plate are respectively disposed opposite to the recesses on the two surfaces of the chip substrate.

[0036] As a possible implementation manner, the chip includes a polymer layer, and the polymer layer is disposed on the surface of the recess.

[0037] As a possible implementation, the polymer layer is formed of a polymer containing a first functional group, wherein the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group, and an azide group.

[0038] As a possible implementation manner, the polymer layer is bonded to the surface of the chip substrate and / or the cover plate via coupling molecules.

[0039] As a possible embodiment, the molecular formula of the coupling molecule is as follows: X a Si(Y b)M c Z,

[0040] Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 alkoxy;

[0041] Y is selected from C 1-10 alkyl;

[0042] M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ;

[0043] Z is selected from the following groups: unsubstituted or substituted: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl;

[0044] The a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50.

[0045] As a possible implementation manner, the chip further includes a first film layer disposed between the chip substrate and / or the cover plate and the polymer layer, and the material of the first film layer is different from the material of the surface to which it is bonded.

[0046] As a possible implementation manner, the first film layer is selected from one or more of a metal film, a metal oxide film and an inorganic oxide film.

[0047] As a possible implementation manner, the material of the first film layer is at least one of Au, Al and SiO2.

[0048] As a possible implementation manner, the thickness of the first film layer is 10 to 1000 nm.

[0049] As a possible embodiment, an adhesive layer is arranged between the chip base and the cover plate, and the adhesive layer has a channel arranged in the length direction of the chip, the recess is arranged on the chip base in the area where the channel is located and / or the geometric structure is arranged on the cover plate surface in the area where the channel is located, and the shape and / or arrangement of the recess or geometric structure in different channels on the same surface are the same or different.

[0050] A second aspect of the present invention provides a method for preparing a chip, comprising the following steps:

[0051] a) forming regularly arranged depressions on at least one surface of the substrate;

[0052] The recess includes a first geometric structure and a second geometric structure that are interconnected in sequence from the surface of the chip substrate toward the center;

[0053] The first geometric structure has a depth c in a direction perpendicular to the chip surface of 0 to 100 μm, a maximum dimension a in a direction horizontal to the chip surface of 10 nm to 100 μm, and a maximum dimension b in a horizontal direction away from the chip surface of 10 nm to 100 μm; an angle α between a sidewall of the first geometric structure and the horizontal direction of the side away from the chip surface of 10 nm to 170°;

[0054] The second geometric structure has a depth e in a direction perpendicular to the chip surface of 0 to 100 μm, and a maximum dimension d in a horizontal direction away from the chip surface of 0 to 100 μm;

[0055] The depth c and the depth e are not 0 at the same time.

[0056] As a possible implementation manner, the substrate is a chip base and / or a cover plate.

[0057] As a possible implementation, the method further includes:

[0058] b) forming a polymer layer on the depressions.

[0059] As a possible implementation, the b) includes:

[0060] attaching a polymer containing a first functional group to the surface where the geometric structure is located;

[0061] The polymer is polished to remove the polymer outside the area where the geometric structure is located, and a polymer layer is formed on the geometric structure.

[0062] As a possible implementation manner, the polishing is chemical polishing and / or mechanical polishing.

[0063] As a possible implementation, the method further includes: before step a), or after step a) and before step b), preparing a first film layer on the surface where the depression is located, wherein the first film layer and the substrate are made of different materials.

[0064] As a possible implementation manner, the first film layer is selected from one or more of a metal film, a metal oxide film and an inorganic oxide film.

[0065] As a possible implementation manner, the material of the first film layer is at least one of Au, Al and SiO2.

[0066] As a possible implementation manner, the thickness of the first film layer is 10 to 1000 nm.

[0067] As a possible implementation manner, the substrate includes at least a chip base, and the method further includes:

[0068] Adhesive material is used to combine the cover plate on the surface of the chip substrate on one side where the geometric structure is arranged, and the adhesive material forms a channel in the length direction of the chip.

[0069] As a possible implementation manner, the chip is the chip described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 is a schematic cross-sectional view of a chip substrate having a cylindrical recessed structure provided by an embodiment of the present invention;

[0071] Figure 2 1 is a schematic plan view of a chip substrate having a cylindrical recessed structure provided by an embodiment of the present invention;

[0072] Figure 3 This is a physical cross-sectional view of a chip substrate having a cylindrical recessed structure provided by an embodiment of the present invention;

[0073] Figure 4 This is a physical plan view of a chip substrate having a cylindrical recessed structure provided by an embodiment of the present invention;

[0074] Figure 5 A schematic diagram of the structure of the depression on the chip surface provided in an embodiment of the present application;

[0075] Figure 6 A schematic structural diagram of a first type of distance between adjacent recesses on a chip surface provided in an embodiment of the present application;

[0076] Figure 7 A schematic structural diagram of the distance between the second type of adjacent recesses on the chip surface provided in an embodiment of the present application;

[0077] Figure 8 Schematic cross-section of the chip substrate of the first structure;

[0078] Figure 9 This is a physical picture of the first type of chip structure;

[0079] Figure 10 Schematic cross-section of the second structural chip substrate;

[0080] Figure 11 This is a physical picture of the second structure chip;

[0081] Figure 12 Schematic cross-section of the chip substrate with the third structure;

[0082] Figure 13 This is a physical picture of the third type of chip structure;

[0083] Figure 14 Schematic cross-section of the fourth chip substrate structure;

[0084] Figure 15 This is a physical picture of the fourth type of chip structure;

[0085] Figure 16 Schematic cross-section of the fifth chip structure substrate;

[0086] Figure 17 This is a physical picture of the fifth structure chip;

[0087] Figure 18 This is a schematic diagram of a chip structure in which a surface of a chip substrate provided by an embodiment of the present invention has a geometric structure;

[0088] Figure 19 This is a schematic diagram of another chip structure in which one surface of a chip substrate has a geometric structure provided by an embodiment of the present invention;

[0089] Figure 20 This is a schematic diagram of a chip structure in which two surfaces of a chip substrate provided by an embodiment of the present invention have geometric structures;

[0090] Figure 21 This is a schematic diagram of another chip structure in which both surfaces of a chip substrate provided by an embodiment of the present invention have geometric structures;

[0091] Figure 22 This is a schematic diagram of another chip structure in which both surfaces of the chip substrate provided by an embodiment of the present invention have geometric structures;

[0092] Figure 23 Statistical graphs of fluorescence brightness after nucleic acid amplification on biochips with different concave shapes provided in Examples 1 to 5 of the present invention;

[0093] Figure 24 It is a statistical graph of Q30, output ratio, resolution rate and matching rate of the biochips with different depression shapes provided in Examples 1 to 5 of the present invention. DETAILED DESCRIPTION

[0094] The present invention provides a patterned biochip and a method for preparing the same. Those skilled in the art can refer to the disclosure herein and appropriately modify the process parameters to achieve the desired results. It is particularly important to note that all similar substitutions and modifications apparent to those skilled in the art are considered encompassed by the present invention. The methods and applications of the present invention have been described using preferred embodiments. It is apparent that those skilled in the art can modify, alter, and combine the methods and applications herein to implement and apply the technology of the present invention without departing from the disclosure, spirit, and scope of the present invention.

[0095] In an embodiment of the present application, a chip is provided, comprising a chip substrate, the chip substrate being used to carry a sample to be tested, such as a nucleic acid molecule to be tested, and to provide a reaction site or detection site for the sample to be tested. In an embodiment of the present application, at least one surface of the chip substrate is formed with a depression, and therefore, the chip can also be referred to as a patterned chip. In some embodiments, by encapsulating the chip, a fluid pathway containing a reaction area can be formed, and therefore, the chip having the depression is also referred to as a flow chamber or flow cell.

[0096] In the embodiments of the present application, the chip substrate has good stability and chemical inertness, so that after the sample to be tested, such as a nucleic acid molecule, is fixed on the surface of the chip substrate, the physical and chemical properties and structure of the sample to be tested are not changed by the material of the chip substrate. Taking the sample to be tested as a nucleic acid molecule as an example, the structure of the sample to be tested includes but is not limited to the composition of the nucleic acid molecule, the spatial conformation of the nucleic acid molecule, the two-dimensional structure, and even the three-dimensional structure. In some specific implementations, the material of the chip substrate is made of but is not limited to: glass; quartz; silicon-based materials such as silicon dioxide, polycrystalline silicon, and single crystal silicon; polymers such as hexamethyldisilazane (HMDS), polyethylene (PE), and polypropylene (PP); and metals such as aluminum. It can be one of these materials or a composite substrate material composed of two or more. It should be understood that when the chip substrate is composed of multiple materials, its composition includes at least the following two situations. In one embodiment, two or more materials are mixed to form a mixed material, and the chip substrate is prepared using the mixed material as the raw material. In this case, the chip substrate is displayed as a single material layer. Preferably, considering the processability of the chip substrate and the performance of the obtained product, it is preferred to select materials with similar or similar materials to mix and prepare the chip substrate. For example, a mixture containing silicon dioxide and polysilicon is used to prepare the chip substrate, and a mixture containing polyethylene (PE) and polypropylene (PP) is used to prepare the chip substrate, and so on. In another embodiment, two or more materials of different materials are selected to prepare a composite layer containing at least two layer structures as the chip substrate. Each layer structure can be made of a material of the same material, or it can be made by compounding two or more materials of different materials with reference to the previous embodiment. Multiple layer structures can be arranged according to a certain structure, such as forming a stacked structure, and so on.

[0097] The embodiments of the present application do not impose any special restrictions on the size of the chip substrate, and the design can be based on the requirements. In some embodiments, for the convenience of processing, a regularly arranged geometric structure is formed on a large-area wafer, and then the wafer is cut to obtain a chip substrate of the required size. There is no restriction on the size specifications of the wafer structure, for example, it can be 6 inches, 8 inches, 12 inches, and other specifications.

[0098] The chip substrate provided in the embodiment of the present application has a geometric structure. In the embodiment of the present application, the shape of the geometric structure on the surface of the chip substrate is a depression formed inwardly on the surface of the chip substrate, that is, a depression structure is formed on the substrate. For example, taking the geometric structure as a depression structure with a width at the top and a narrowness at the bottom as an example, the cross-sectional schematic diagram and the planar schematic diagram of the chip substrate are respectively as follows: Figure 1 and Figure 2 As shown, 11 is a depression with a wide top and a narrow bottom, 12 is a chip base; the physical cross-sectional view and the physical plan view are shown in FIG. Figure 3 and Figure 4 shown.

[0099] In the embodiment of the present application, the recess is provided on at least one surface of the chip substrate.

[0100] In one embodiment, the depression of the chip substrate is formed on a surface of the chip substrate. In this case, the material of the chip substrate can be selected from the materials listed above, for example, glass; quartz; silicon-based materials, such as silicon dioxide, polycrystalline silicon, single crystal silicon, etc.; polymers, such as hexamethyldisilazane (HMDS), polyethylene (PE), polypropylene (PP), etc.; metals, such as aluminum, etc. The chip substrate can be composed of one of them, or it can be made of a composite material composed of two or more of the above materials. In some embodiments, the chip substrate can be set as a single layer, and the single-layer chip substrate can be made of one material or a mixture of multiple materials; the chip substrate can also be set as a stacked structure, and the layers constituting the stacked structure can be made of the same material or a mixture of multiple materials. The depression is set in the surface layer of the stacked structure and can penetrate the surface and sink to at least one other layer of the stacked structure.

[0101] In another embodiment, the chip substrate has recesses formed on both surfaces of the chip substrate. The resulting chip substrate provides two surfaces for biochemical reactions and / or detection of the sample to be tested, such as nucleic acid sequencing, which helps improve the throughput of the biochemical reactions and / or detection. In some embodiments, the chip substrate is a single layer. When the detection of the sample to be tested requires the use of photoelectric signals, such as when the chip is used to sequence nucleic acid molecules, the transmittance of the single layer chip substrate is less than 70%, or the thickness of the single layer chip substrate is 500 μm or greater. This allows the imaging device to collect optical signals from the two surfaces of the chip substrate (especially the geometric structure) while reducing interference between the optical signals on the two surfaces. The single layer chip substrate can be made of opaque materials, such as silicon-based materials such as silicon dioxide, polycrystalline silicon, single crystal silicon, etc.; or metals such as aluminum. The single layer chip substrate can also be made of a mixture of multiple materials, with the transmittance of the film layer formed by the mixture being less than 70%, or the thickness of the film layer formed by the mixture being 500 μm or greater. For example, a silicon-based material is mixed with other substrates in an appropriate ratio to obtain a chip substrate. In another embodiment, the chip substrate is a laminated structure, which includes at least one laminate with a transmittance of less than 70% or a thickness of 500μm or more, and is used to reduce the mutual interference of optical signals generated by the two surfaces of the chip substrate (especially the geometric structure). Exemplarily, the chip substrate is a laminated structure including two laminates. In one case, one laminate is a laminate with a transmittance greater than 95%, and the other laminate is a laminate with a transmittance less than 70%; the geometric structures are respectively provided on the opposite surfaces of the two laminates. In another case, both laminates are laminates with a transmittance less than 70%; the geometric structures are respectively provided on the opposite surfaces of the two laminates. In yet another case, both laminates are laminates with a transmittance greater than 95%, and the total thickness of the two laminates is 500μm or more; the geometric structures are respectively provided on the opposite surfaces of the two laminates.

[0102] In the embodiment of the present application, the depression has an irregular shape.

[0103] See also Figures 5 to 17 , the present application embodiment provides a schematic diagram of the structure of the depression on the chip surface. Figure 5The depression includes, in sequence, a first geometric structure A and a second geometric structure B, interconnected in the direction from the chip substrate surface toward the center. Here, the direction from the chip substrate surface toward the center can also be understood as a top-to-bottom direction, i.e., a hole is opened from one surface of the chip substrate and extends toward the other surface of the chip substrate without penetrating the other surface, thereby forming a depression. As shown in the figure, the first geometric structure A has a depth c in the direction perpendicular to the chip surface, a maximum dimension a in the horizontal direction of the chip surface, and a maximum dimension b in the horizontal direction away from the chip surface. The sidewalls of the first geometric structure form an angle α with the horizontal direction away from the chip surface. The second geometric structure B has a depth e in the direction perpendicular to the chip surface and a maximum dimension d in the horizontal direction away from the chip surface. In the embodiment of the present application, the maximum dimension of the chip surface in the horizontal direction can be understood as the maximum distance of all distances formed by any two points on the edge of the recess in the cross-section formed by the recess on the chip surface; similarly, the maximum dimension b of the first geometric structure A in the horizontal direction away from the chip surface can be understood as the maximum distance of all distances formed by any two points on the edge of the recess in the common surface of the first geometric structure A and the second geometric structure B; the maximum dimension d of the second geometric structure B in the horizontal direction away from the chip surface can be understood as the maximum distance of all distances formed by any two points on the edge of the bottom surface of the recess.

[0104] In the embodiment of the present application, the size of the recess can meet the detection needs of biological molecules. Specifically, the depth c of the first geometric structure A in the direction perpendicular to the chip surface is 0 to 100 μm, the maximum dimension a in the horizontal direction of the chip surface is 10 nm to 100 μm, and the maximum dimension b in the horizontal direction away from the chip surface is 10 nm to 100 μm; the angle α between the side wall of the first geometric structure and the horizontal direction of the side away from the chip surface is 10 to 170°.

[0105] In some embodiments, the depth c is preferably 10 nm to 100 μm, more preferably 50 nm to 50 μm, more preferably 100 nm to 10 μm, more preferably 150 nm to 5 μm, and most preferably 200 nm to 3 μm. The maximum dimension a is preferably 50 nm to 50 μm, more preferably 100 nm to 10 μm, more preferably 150 nm to 5 μm, and most preferably 200 nm to 3 μm. The maximum dimension b is preferably 50 nm to 50 μm, more preferably 100 nm to 10 μm, more preferably 150 nm to 5 μm, and most preferably 200 nm to 3 μm.

[0106] In one implementation scenario, Figure 5 、 Figure 12As shown, when α is less than 90°C, the cross-sectional area of ​​the first geometric structure A located on the surface of the chip substrate is larger than the cross-sectional area located inside the chip substrate, and the first geometric structure A presents a structure that is wide at the top and narrow at the bottom. In an embodiment of the present application, when the depression has a morphological structure that is wide at the top and narrow at the bottom, during the biochemical reaction in the detection process (such as nucleic acid sequencing), the liquid phase of the reaction reagent exchanges substances and diffuses with the active molecules on its surface, thereby promoting the reaction and obtaining a better detection signal (including signal brightness, signal-to-noise ratio) and a more accurate detection result. Experimental results show that this structure has better sequencing results (including Q30 ratio, alignment rate, error rate, splitting rate, output ratio, and sequencing brightness, etc.). In some embodiments, such as Figure 5 As shown, the angle α preferably satisfies the following relationship: 10≤α<90°, more preferably 20-80°, more preferably 30-70°, and most preferably 40-60°. In another embodiment, as Figure 16 As shown, when α>90°C, the first geometric structure A presents a structure that is narrow at the top and wide at the bottom. In another embodiment, as Figure 14 As shown, when α=90°C, the first geometric structure A is a cylindrical structure.

[0107] In the embodiment of the present application, the depth e of the second geometric structure in the direction perpendicular to the chip surface is 0-100 μm, preferably 10 nm-100 μm, more preferably 50 nm-50 μm, more preferably 100 nm-10 μm, more preferably 150 nm-5 μm, and most preferably 200 nm-3 μm. The maximum dimension d is 0-100 μm, preferably 10 nm-100 μm, more preferably 50 nm-50 μm, more preferably 100 nm-10 μm, more preferably 150 nm-5 μm, and most preferably 200 nm-3 μm.

[0108] In the embodiment of the present application, the ratio of the maximum dimension b to the maximum dimension d is preferably 1:10 to 1000:1, more preferably 1:5 to 500:1, and most preferably 1:1 to 100:1.

[0109] In the embodiments of the present application, depth c and depth e are not both zero. In some embodiments, the ratio of depth c to depth e is preferably in the range of 1:1000 to 1000:1, more preferably 1:500 to 500:1, more preferably 1:100 to 100:1, more preferably 1:50 to 50:1, further preferably 1:10 to 10:1, and most preferably 1:5 to 5:1. In some embodiments, one of depth c and depth e is zero. When depth c is zero, the recessed structure is the second geometric structure B; when depth e is zero, the recessed structure is the first geometric structure A.

[0110] In the embodiment of the present application, the distance f between adjacent recesses can be divided into two situations according to the shape of the recess cross section. In one implementation, when the recess cross section is a symmetrical figure, the distance f between adjacent recesses is the distance between the centers of two adjacent recesses, that is, the distance from the center of one recess to the center of the adjacent recess, such as Figure 6 In another embodiment, when the depression is an irregular shape, the distance between the same positions in two cross sections formed by adjacent depressions on the same horizontal plane is as follows: Figure 7 In some embodiments, the distance f between adjacent recesses is preferably 10 nm to 100 μm, more preferably 50 nm to 50 μm, further preferably 100 nm to 10 μm, more preferably 200 nm to 5 μm, and most preferably 300 nm to 3 μm.

[0111] In the embodiment of the present application, depressions of different structures can be obtained by adjusting the above parameters.

[0112] In some implementations of the present application, by adjusting the above parameters, a depression that is wider at the top and narrower at the bottom is obtained on the surface of the chip substrate.

[0113] Specifically, in one embodiment, when the maximum dimension a of the concave is greater than the maximum dimension b, and the maximum dimension b is equal to the maximum dimension d, the angle α is less than 90°. In this case, a concave with a trumpet-shaped structure can be obtained, such as Figures 5 to 9 In some embodiments, for the depression of the trumpet-shaped structure, the first geometric structure and the second geometric structure are both symmetrical geometric structures, and the symmetry axes of the first geometric structure and the second geometric structure coincide. Figure 8 and Figure 9 , Figure 8 Schematic diagram of a longitudinal cross-section of a chip substrate of the first structure, wherein 71 is the chip substrate, 72 is the recess, A is the first geometric structure and B is the second geometric structure; Figure 9 This is a physical picture of the first type of chip structure, where A is a longitudinal cross-sectional view and B is a top view.

[0114] When the depression is a trumpet-shaped structure, the depth c is preferably 150 nm to 5 μm, more preferably 200 nm to 3 μm, and most preferably 250 nm to 1 μm. The maximum dimension a is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The maximum dimension b is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The angle α preferably satisfies the following relationship: 10 ≤ α < 90°, more preferably 20 to 85°, more preferably 30 to 80°, most preferably 40 to 80°, and even more preferably 60 to 80°. The depth e is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The maximum dimension d is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm.

[0115] In another embodiment, the maximum dimension a of the depression is greater than the maximum dimension b, the maximum dimension b is greater than the maximum dimension d, the maximum dimension d is not 0, and the angle α is less than 90°. For this embodiment, it can also be understood that the first geometric structure of the depression is a geometric structure in which the inner diameter gradually decreases with increasing depth, and the depth e of the second geometric structure is 0; it can also be understood that the depth c of the first geometric structure of the depression is 0, and the second geometric structure is a geometric structure in which the inner diameter gradually decreases with increasing depth. In some embodiments, the first geometric structure and the second geometric structure of the depression are both symmetrical geometric structures, and the axes of symmetry of the first geometric structure and the second geometric structure coincide. Exemplarily, the depression is a depression of a flat-bottomed conical structure (an inverted truncated cone structure), see Figure 10 and Figure 11 . Figure 10 Schematic diagram of a longitudinal cross-section of a chip substrate of the second structure, wherein 91 is the chip substrate and 92 is the recess; Figure 11This is a physical picture of the second structure chip, where A is a longitudinal cross-sectional view and B is a top view. When the depression is a flat-bottomed conical structure, the depth c is preferably 150nm~5μm, more preferably 200nm~3μm, and most preferably 250nm~1μm. The maximum dimension a is preferably 100nm~5μm, more preferably 150nm~3μm, and most preferably 200nm~1μm. The maximum dimension b is preferably 100nm~5μm, more preferably 150nm~3μm, and most preferably 200nm~1μm. The angle α preferably satisfies the following relationship: 10≤α<90°, more preferably 20~80°, more preferably 30~70°, and most preferably 40~60°. The depth e is preferably 100nm~5μm, more preferably 150nm~3μm, and most preferably 200nm~1μm. The maximum dimension d is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. Specifically, when the depression has a flat-bottomed conical structure, the value of the maximum dimension b can be ignored, and the ratio of the maximum dimension a to the maximum dimension d can be defined by the total depth, i.e., the sum of the depth c and the depth e, and the angle α. In some specific implementations, the sum of the depth c and the depth e is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm.

[0116] In another embodiment, the maximum dimension a of the depression is greater than the maximum dimension b, and the maximum dimension d is 0. For this embodiment, it can also be understood that the first geometric structure of the depression is a geometric structure in which the inner diameter gradually decreases with increasing depth until it is 0, and the depth e of the second geometric structure is 0; it can also be understood that the depth c of the first geometric structure of the depression is 0, and the second geometric structure is a geometric structure in which the inner diameter gradually decreases with increasing depth until it is 0. In some embodiments, the first geometric structure and the second geometric structure of the depression are both symmetrical geometric structures, and the symmetry axes of the first geometric structure and the second geometric structure coincide. For example, the depression is a depression of a conical structure, see Figure 12 and Figure 13 .in, Figure 12 1 is a schematic longitudinal cross-sectional view of a chip substrate of the third structure, wherein 111 is the chip substrate and 112 is a recess; Figure 13 This is a physical picture of the third structural chip, where A is a longitudinal cross-sectional view and B is a top view.

[0117] When the depression is a conical structure, the depth c is preferably 150 nm to 5 μm, more preferably 200 nm to 3 μm, and most preferably 250 nm to 1 μm. The maximum dimension a is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The maximum dimension b is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The angle α preferably satisfies the following relationship: 10 ≤ α < 90°, more preferably 20 to 80°, more preferably 30 to 70°, and most preferably 40 to 60°. The depth e is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. Specifically, when the depression is a conical structure, the value of the maximum dimension b can be ignored, and the maximum dimension a is defined by the total depth, i.e., the sum of the depth c and the depth e, and the angle α. In some specific implementations, the sum of the depth c and the depth e is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm.

[0118] In the implementation of the present application, in addition to the above-mentioned depressions with a wide top and narrow bottom feature, the surface of the chip substrate may also include depressions with a narrow top and wide bottom feature or with consistent top and bottom features.

[0119] In one embodiment, the maximum dimension a of the depression is equal to the maximum dimension b and equal to the maximum dimension d. In this case, the angle α is 90°, which can be considered as a depression of a cylindrical structure. For this embodiment, it can also be understood that the first geometric structure of the depression is a geometric structure with a constant inner diameter, and the depth e of the second geometric structure is 0; it can also be understood that the depth c of the first geometric structure of the depression is 0, and the second geometric structure is a geometric structure with a constant inner diameter. In some embodiments, the first geometric structure and the second geometric structure of the depression are both symmetrical geometric structures, and the symmetry axes of the first geometric structure and the second geometric structure coincide. Figure 14 and Figure 15 , Figure 14 13 is a schematic cross-sectional view of a chip substrate of a fourth structure, wherein 131 is the chip substrate and 132 is a recess; Figure 15 This is a physical picture of the fourth structural chip, where A is a longitudinal cross-sectional view and B is a top view.

[0120] When the depression has a cylindrical structure, the depth c is preferably 150 nm to 5 μm, more preferably 200 nm to 3 μm, and most preferably 250 nm to 1 μm. The maximum dimension a is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The maximum dimension b is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The depth e is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. Specifically, when the depression has a cylindrical structure, the value of the maximum dimension b can be ignored, and its morphology can be defined by the total depth, that is, the sum of the depth c and the depth e. In some specific implementations, the sum of the depth c and the depth e is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm.

[0121] In one embodiment, the maximum dimension a of the depression is smaller than the maximum dimension b, and the maximum dimension b is smaller than the maximum dimension d. In this case, the angle α is greater than 90°, which can be considered as a pear-shaped depression. For this embodiment, it can also be understood that the first geometric structure of the depression is a geometric structure in which the inner diameter gradually increases with increasing depth, and the depth e of the second geometric structure is 0; it can also be understood that the depth c of the first geometric structure of the depression is 0, and the second geometric structure is a geometric structure in which the inner diameter gradually increases with increasing depth. In some embodiments, the first geometric structure and the second geometric structure of the depression are both symmetrical geometric structures, and the symmetry axes of the first geometric structure and the second geometric structure coincide. Figure 16 and Figure 17 , Figure 16 15 is a schematic cross-sectional view of a chip substrate of the fifth structure, wherein 151 is the chip substrate and 152 is the recess; Figure 17 This is a physical picture of the fifth structure chip, A is a longitudinal cross-sectional view, and B is a top view.

[0122] When the depression is pear-shaped, the depth c is preferably 150 nm to 5 μm, more preferably 200 nm to 3 μm, and most preferably 250 nm to 1 μm. The maximum dimension a is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The maximum dimension b is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. The angle α preferably satisfies the following relationship: 90 < α ≤ 170°, more preferably 95 to 160°, more preferably 100 to 150°, and most preferably 110 to 140°. The depth e is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm. Specifically, when the depression is cylindrical, the maximum dimension b can be ignored, and its morphology can be defined by the total depth, i.e., the sum of the depth c and the depth e, and the angle α. In some specific implementations, the sum of the depth c and the depth e is preferably 100 nm to 5 μm, more preferably 150 nm to 3 μm, and most preferably 200 nm to 1 μm.

[0123] Compared with the structure with the same width at the top and bottom or narrow at the top and wide at the bottom (such as Figures 14 to 17 As shown), micro-nano structures with a wide top and narrow bottom (such as Figures 5 to 13 As shown in the figure, it is beneficial for the biochip to exchange and diffuse substances between the liquid phase of the reaction reagent and the active molecules on the surface of the micro-nanostructure during the biochemical reaction in the detection process (such as nucleic acid sequencing), thereby promoting the reaction and obtaining better detection signals (including signal brightness and signal-to-noise ratio) and more accurate detection results.

[0124] In some specific implementations, the depression on the chip substrate surface may be one of the above structures or a combination of multiple structures, preferably including at least a depression that is wide at the top and narrow at the bottom, that is, a conical, flat-bottomed conical or trumpet-shaped depression.

[0125] In some embodiments, the recesses are arranged in a regular pattern on the surface of the chip substrate. This can be understood as the recesses being arranged in a certain regular pattern to form a pattern with a certain shape. In some embodiments, the surface comprises at least one array unit, wherein the array unit comprises recesses arranged in a regular pattern. Specifically, the array unit is a square array unit, i.e., the pattern formed by the collection of multiple recesses is a square. Exemplarily, the recesses are arranged in rows and columns, with the distance between adjacent rows being equal to the distance between adjacent columns, and the collection of multiple recesses includes the same number of rows and columns. The array unit is a rectangular array unit, i.e., the pattern formed by the collection of multiple recesses is a rectangle. Exemplarily, the recesses are arranged in rows and columns, with the distance between adjacent rows being equal to the distance between adjacent columns, and the collection of multiple recesses includes different numbers of rows and columns. The array unit is a honeycomb array unit, i.e., the pattern formed by the collection of multiple recesses is a honeycomb pattern, i.e., the recesses are arranged in a certain regular pattern, and the collection of these recesses forms a honeycomb pattern. Of course, the same surface may contain two or more of the following: square array units, rectangular array units, and honeycomb array units. In one embodiment, the same surface of the chip substrate may include one or more recessed sets, with the recesses in each set arranged according to the same pattern. In another embodiment, the same surface of the chip substrate may include one or more recessed sets, with the recesses in at least one set arranged differently from the recesses in another set. In other words, the same chip substrate may include a combination of multiple arrangements, such as splicing or nesting.

[0126] In some implementations, the chip may further include an encapsulation layer disposed on the chip substrate, the encapsulation layer being configured to encapsulate the recessed surface of the chip substrate to protect the chip substrate and form a reaction region for solution circulation.

[0127] In one embodiment, the chip includes a first cover plate bonded to a recessed surface of the chip substrate. The first cover plate is made of a material with a light transmittance greater than or equal to 95%, allowing light to pass through the first cover plate and reach the recessed surface of the chip substrate. The material of the first cover plate can be the same as or different from that of the chip substrate, and this application does not specifically limit this. Exemplary materials for the cover plate include glass, quartz, polymer film, and the like.

[0128] In some embodiments, as Figure 18 and Figure 19 As shown, the chip substrate 82 has a recess formed on one surface of the chip substrate 82, and a first cover plate 81 is bonded to the side surface of the chip substrate 82 where the recess is located to achieve chip packaging. The first cover plate 81 can be a patterned material or a non-patterned material.

[0129] In one embodiment, Figure 18As shown, the first cover plate 81 is a conventional cover plate without recesses, meaning both surfaces of the cover plate are untreated, flat surfaces. In this case, the surface of the first cover plate 81 facing the chip substrate 82 is flat. In one embodiment, an adhesive layer 83 is provided between the first cover plate 81 and the chip substrate 82 for bonding the first cover plate 81 and the chip substrate 82. The adhesive layer 83 has channels extending along the length of the chip, and recesses are provided on the surface of the chip substrate 82 in the areas where the channels are located. The shapes and / or arrangements of the recesses in different channels on the same surface may be the same or different.

[0130] In other embodiments, Figure 19 As shown, the first cover plate 91 is a cover plate with regularly arranged recesses on one side surface, and the recesses of the first cover plate 91 are arranged opposite to the recesses of the chip substrate 92, that is, the surface of the first cover plate 91 facing the chip substrate 92 is provided with recesses with a regular arrangement. In this case, a chip has two surfaces that can be sequenced, thereby improving the sequencing throughput. In this embodiment, the recesses of the first cover plate 91 and the recesses of the chip substrate 92 can be the same or different. In order to save space, they are not described here. In one embodiment, an adhesive layer 93 is provided between the first cover plate 91 and the chip substrate 92 for bonding the first cover plate 91 and the chip substrate 92, and the adhesive layer 93 has a channel provided in the longitudinal direction of the chip, and the recesses are provided on the surfaces of the chip substrate 92 and the first cover plate 91 in the area where the channel is located, and the shape and / or arrangement of the recesses in different channels on the same surface are the same or different.

[0131] In another embodiment, the chip substrate has regularly arranged depressions on both surfaces, and the arrangement of the depressions on the two surfaces may be the same or different. For the arrangement of the depressions on the two surfaces of the chip substrate, refer to the above, and in order to save space, it will not be repeated here. At this time, the transmittance of the chip substrate is less than 70% or the thickness of the chip substrate is 500μm or more, so that when the imaging device collects optical signals from the two surfaces (especially the depressions) of the chip substrate, the interference between the optical signals on the two surfaces is reduced. In this embodiment, a cover plate is combined with at least one side surface of the depression of the chip substrate to realize the packaging of the chip. In some embodiments, the chip includes a first cover plate and a second cover plate respectively combined with the two side surfaces of the chip substrate, wherein the material of the first cover plate and the second cover plate is a material with a transmittance greater than or equal to 95%, so that light can pass through the first cover plate and the second cover plate respectively to reach the two surfaces of the chip substrate where the depressions are set.

[0132] In some embodiments, the cover plate is a common cover plate without a recess, that is, both surfaces of the cover plate are untreated flat surfaces. Figure 20As shown, a first cover plate 101 and a second cover plate 104 are respectively bonded to the side surfaces of the recess of the chip substrate 102. The first cover plate 101 and the second cover plate 104 are ordinary cover plates without recesses, that is, the first cover plate 101 and the second cover plate 104 have two flat surfaces. In one embodiment, an adhesive layer 103 is provided between the first cover plate 101 and the chip substrate 102, and between the second cover plate 104 and the chip substrate 102, for bonding the first cover plate 101 and the chip substrate 102, and the second cover plate 104 and the chip substrate 102. The adhesive layer 103 has a channel provided along the length of the chip. The recess is provided on the surface of the chip substrate 102 in the area where the channel is located. The shape and / or arrangement of the recesses in different channels on the same surface may be the same or different.

[0133] In some embodiments, the first cover plate and / or the second cover plate is a cover plate with a recess provided on one side surface.

[0134] In one embodiment, Figure 21 As shown, a first cover plate 111 and a second cover plate 114 are respectively bonded to the two sides of the recessed surface of the chip substrate 112. The first cover plate 111 is a cover plate with a recess, and the recess of the first cover plate 111 is arranged opposite the recess of the chip substrate 112. The second cover plate is a conventional cover plate without a recess, and both surfaces of the second cover plate 114 are flat. It should be understood that the recess of the first cover plate 111 and the recess of the chip substrate 112 can be the same or different. In one embodiment, an adhesive layer 113 is provided between the first cover plate 111 and the chip substrate 112, and between the second cover plate 114 and the chip substrate 112, for bonding the first cover plate 111 and the chip substrate 112, and the second cover plate 114 and the chip substrate 112. The adhesive layer 113 has a channel extending along the length of the chip. The recesses are provided on the surfaces of the chip substrate 112 and the first cover plate 111 in the area where the channel is located. The shape and / or arrangement of the recesses in different channels on the same surface can be the same or different.

[0135] In one embodiment, Figure 22As shown, a first cover plate 121 and a second cover plate 124 are respectively combined on both side surfaces of the recess of the chip substrate 122. Both cover plates are provided with recesses, and the recesses of the cover plates are arranged opposite to the recesses of the chip substrate 122, forming a structure similar to a double-chip stack. It should be understood that the recess of each cover plate can be the same as or different from the recess of the chip substrate; the recesses of the two cover plates can be the same as or different. In one embodiment, an adhesive layer 123 is provided between the first cover plate 121 and the chip substrate 122 and between the second cover plate 124 and the chip substrate 122, for bonding the first cover plate 121 and the chip substrate 122 and the second cover plate 124 and the chip substrate 122. The adhesive layer 123 has a channel provided in the length direction of the chip, and the recesses are provided on the surfaces of the chip substrate 122, the first cover plate 121 and the second cover plate 122 in the area where the channel is located. The shape and / or arrangement of the recesses in different channels on the same surface are the same or different.

[0136] When the chip is used for sequencing, the above embodiment provides regularly arranged depressions on the surface of the cover plate facing the chip substrate, thereby increasing the number of reaction and / or detection sites for nucleic acid molecules on the chip surface, thereby facilitating increased sequencing throughput. It should be understood that when the cover plate is provided with regularly arranged depressions to increase the number of reaction and / or detection sites for nucleic acid molecules on the chip surface, thereby facilitating increased sequencing throughput, the cover plate also functions as a chip substrate and may also be referred to as a chip substrate.

[0137] In some embodiments, the chip includes a polymer layer, and the polymer layer is disposed on the surface of the recess. Since at least one surface of the chip substrate is provided with a recess, the polymer layer is at least disposed on the surface of the chip substrate having the recess. When both surfaces of the chip substrate have recesses, polymer layers are disposed on both surfaces. Accordingly, when the cover plate includes a first cover plate and a second cover plate and one surface of the cover plate is provided with a recess, the polymer layer is also disposed on the surface of the cover plate where the recess is disposed. In this embodiment, the surface of the recess includes the sidewalls and the bottom surface of the recess. When the recess has no bottom surface, such as when the recess is a conical structure, the surface of the recess is the wall surface of the recess. In this case, the polymer layer is disposed on the bottom surface of the recessed structure.

[0138] The polymer layer provides a capture site or detection site for the analysis and / or detection of nucleic acid molecules by combining with nucleic acid probes, antigen-antibodies, nucleic acid-protein complexes and other nucleic acid molecule connectors. Precisely because of this, the embodiment of the present application sets the shape, size and arrangement of the depressions so that the nucleic acid molecules are fixed on the surface of the chip with a certain arrangement density and arrangement. Even if the nucleic acid molecules form detection or analysis sites with a certain density and arrangement, it is beneficial to later obtain and locate the information generated by the nucleic acid molecules during the reaction and / or detection process, which helps to improve the stability of the detection results of the nucleic acid molecules.

[0139] In some embodiments, the polymer layer is formed by a polymer containing a first functional group, and the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group, and an azide group. These functional groups are chemically reactive or adsorptive functional groups that can react with other reactive functional groups to achieve binding to nucleic acid molecules or nucleic acid molecule linkers such as nucleic acid probes, antigen antibodies, and nucleic acid-protein complexes. That is, illustratively, the polymer constituting the polymer layer can be polyethylene glycol, polypropylene, polyacrylic acid, polymethyl methacrylate, etc., but is not limited thereto. The embodiment of the present application forms a polymer on the concave surface of the chip, which can optimize the environment of the chip sequencing reaction. Specifically, the formed polymer layer has high transparency and low optical background in the visible light band of 400nm-700nm.

[0140] The present application has no particular limitation on the thickness of the polymer layer, as long as it can fix nucleic acid molecules or nucleic acid molecule linkers.

[0141] In this implementation, since the chip substrate and / or cover plate material is relatively weakly reactive, in some embodiments, the polymer layer is bonded to the surface of the chip substrate and / or cover plate via a coupling molecule. In one embodiment, the molecular formula of the coupling molecule is as follows: a Si(Y b )M c Z, X, and Z serve as reactive groups and are used to connect the chip substrate and the functional groups of the polymer, respectively.

[0142] Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 Alkoxy, exemplary, such as Cl, CH3O-, CH3CH2O-, etc.; Y is selected from C 1-10 Alkyl, such as CH3-, CH3CH2-, etc.; M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ; Z is selected from the following groups: unsubstituted or substituted: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl; C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20Aryl, 5-20 membered heteroaryl, at least one R a Replacement, R a Each is independently selected from halogen, nitro, ester, amino, carboxyl, hydroxyl, azide, and epoxy; a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50.

[0143] Exemplarily, the coupling molecule can be at least one of the following structures:

[0144]

[0145] Wherein, X is a halogen, illustratively, X is F, Cl, Br or I;

[0146] R b is -CH3, -C2H5, -C3H7 or -C4H9;

[0147] n1 is an integer selected from 2-10, and exemplary n1 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0148] n2 is an integer selected from 2 to 10, and exemplary n2 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0149] n3 is an integer selected from 2-10, and exemplary n3 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0150] n4 is an integer selected from 2 to 10, and exemplary n2 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0151] n5 is an integer selected from 2 to 10, and exemplary n2 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0152] n6 is an integer selected from 2 to 10, and exemplary n2 is 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0153] n7 is an integer selected from 1-10, and exemplary n2 is 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0154] n8 is an integer selected from 5 to 10, and exemplary, n2 is 5, 6, 7, 8, 9 or 10;

[0155] n9 is an integer selected from 1-10, and exemplary n2 is 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10;

[0156] n10 is an integer selected from 1-10. Exemplarily, n2 is 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10.

[0157] In some embodiments, the chip further includes a first film layer disposed between the chip substrate and / or cover plate and the polymer layer. Specifically, the first film layer is optionally disposed on the surface of the chip substrate having a depression and the cover plate having a depression, and its material is different from the material of the surface to which it is bonded, so as to reduce surface defects of the chip substrate and / or cover plate and improve the uniformity of the chip surface. In addition, during the chip preparation process, considering the feasibility of the process, it is preferred to react on the entire surface of the chip substrate and / or cover plate to generate a polymer layer; then the polymer layer on the surface of the chip substrate and / or cover plate is processed to retain only the polymer formed in the depression to meet the need for detecting the optical signal generated by the nucleic acid molecule reaction. In some embodiments, the polymer is connected within the depression by a selective modification process. In some embodiments, the polymer outside the depression is removed by a polishing process. At this time, the degree of the polishing reaction can be indicated by disposing a first film layer on the surface of the chip substrate and / or cover plate, and by detecting the physical and chemical properties of the first film layer, thereby determining the polishing end point.

[0158] In this embodiment, the first film layer includes, but is not limited to, a metal film, such as an Al film, an Au film, etc.; a metal oxide film, such as an Al2O3 film, etc.; an inorganic oxide film, such as a SiO2 film, etc., and can be one or more of these, preferably one or more of an Al film, an Al2O3 film, and a SiO2 film. For example, when a SiO2 film is used as the first film layer, the SiO2 film can stabilize the surface properties of the chip, specifically by preventing raw materials and reagents introduced during reaction and / or testing from reacting with the chip substrate and generating bubbles. Furthermore, SiO2 can improve the bonding strength of the polymer and reduce the risk of the polymer layer falling off the chip surface.

[0159] In some embodiments, the thickness of the first film layer is 10 to 1000 nm, preferably 15 to 800 nm, more preferably 20 to 500 nm, and most preferably 20 to 200 nm. Within this thickness range, the first film layer can achieve the aforementioned effects. If the thickness is too thick, such as when the first film layer is greater than 1500 nm, the brightness of bases collected from the depressions during sequencing on a chip with the first film layer will be lower than that of a chip without the first film layer, thereby affecting the interpretation of the sequencing signal. Exemplarily, the thickness of the first film layer can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 250nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm and the like.

[0160] In some embodiments, the chip substrate and cover plate are bonded together using an adhesive material, and the adhesive material is hollowed out to form a channel structure, providing a reaction area for the chip substrate. The adhesive material can be adhesive, double-sided tape, or a light-curable material such as UV adhesive. Considering the impact of reagents during the sequencing process, the adhesive material is selected to be stable and non-invasive to the nucleic acid molecules and the reagents used in the sequencing process. Exemplary adhesive materials include, but are not limited to, UV-curable adhesives, heat-curable adhesives, and pressure-sensitive adhesives.

[0161] In some embodiments, the chip has at least one channel extending along its length, such as one or more channels formed between the chip substrate and the encapsulation layer, to facilitate liquid flow. Specifically, recesses are provided on the chip substrate surface in the region where the channels are located, and solutions flowing through the channels react with nucleic acid molecules immobilized in the recesses. It should be understood that the shapes and / or arrangements of the recesses in different channels may be the same or different.

[0162] The chip provided in the present application improves sequencing stability and accuracy by forming regularly arranged depressions on the substrate. Furthermore, the regularly arranged depressions increase the density of the depressions on the chip, thereby increasing detection throughput. Furthermore, the regularly arranged depressions can be used to locate the detection sites corresponding to the depressions, thereby facilitating the simultaneous detection of multiple nucleic acid molecules on the same chip surface.

[0163] The chip provided in the embodiments of the present application can be manufactured by the following method, but is not limited thereto.

[0164] Accordingly, the present invention also provides a method for preparing a chip, comprising the following steps:

[0165] a) forming regularly arranged depressions on at least one surface of the substrate;

[0166] The recess includes a first geometric structure and a second geometric structure that are interconnected in sequence from the surface of the chip substrate toward the center;

[0167] The first geometric structure has a depth c in a direction perpendicular to the chip surface of 0 to 100 μm, a maximum dimension a in a direction horizontal to the chip surface of 10 nm to 100 μm, and a maximum dimension b in a horizontal direction away from the chip surface of 10 nm to 100 μm; an angle α between a sidewall of the first geometric structure and the horizontal direction of the side away from the chip surface of 10 to 170°;

[0168] The second geometric structure has a depth e in a direction perpendicular to the chip surface of 0 to 100 μm, and a maximum dimension d in a horizontal direction away from the chip surface of 0 to 100 μm;

[0169] The depth c and the depth e are not 0 at the same time.

[0170] In step a), the substrate is the target substrate in which the recess is to be provided, and includes at least a chip substrate. In some embodiments, the target substrate in which the recess is to be provided is a chip substrate. In some embodiments, the target substrate in which the recess is to be provided is a cover plate, in which case the substrate is the cover plate. In some embodiments, the target substrate in which the recess is to be provided includes a chip substrate and a cover plate, in which case the substrate includes the chip substrate and the cover plate. The material of the substrate can refer to the material selection of the chip substrate and the cover plate above, and will not be repeated here.

[0171] In the embodiment of the present application, regularly arranged depressions are prepared on the surface of the substrate. The shape, size parameters and arrangement rules of the depressions are as described above and will not be repeated in this application.

[0172] In the embodiment of the present application, regularly arranged depressions can be prepared on the surface of the substrate by using photolithography technology, nanoimprint technology, screen printing technology, etc.

[0173] Exemplarily, the preparation of depressions using photolithography technology includes the following steps: cleaning and drying the substrate, coating it with photoresist, exposing and developing it, and then etching it to obtain regularly arranged depressions, that is, directly obtaining a pattern. It may also include the following steps: coating photoresist on another substrate, exposing and developing it, and then etching it to obtain regularly arranged depressions, and transferring the depressions to a target substrate to form a pattern. The embodiments of the present application have no special restrictions on the reagents and methods of photolithography, wherein the etching method can be dry etching, such as plasma etching, electron beam etching, laser etching, etc., or wet etching, such as acid-base etching, redox etching, etc.

[0174] Exemplarily, the preparation of depressions using nanoimprinting technology may include the following steps: preparing a template of the desired pattern, coating a photoresist on a substrate, pressing the template onto the surface of the photoresist, and transferring the pattern to the photoresist by applying pressure to obtain depressions arranged in a regular pattern, that is, directly obtaining a pattern. It may also include the following steps: preparing a template of the desired pattern on a substrate, coating a photoresist on a second substrate, pressing the template onto the surface of the photoresist, and transferring the pattern to the photoresist by applying pressure to obtain depressions arranged in a regular pattern after the photoresist is cured, and then transferring the depressions to the chip substrate by etching to form a pattern. The embodiments of the present application have no special restrictions on the reagents, methods, etc. of the nanoimprinting technology, wherein the etching method may be dry etching, such as plasma etching, electron beam etching, laser etching, etc., or wet etching, such as acid-base etching, redox etching, etc.

[0175] Exemplarily, the preparation of depressions using screen printing technology specifically includes the following steps: obtaining regularly arranged depressions on the chip substrate by screen printing, that is, directly obtaining a pattern. It may also include the following steps: obtaining regularly arranged depressions on the substrate by screen printing, and then transferring the depressions to the chip substrate by etching to form a pattern. The embodiments of the present application have no special restrictions on the reagents, methods, etc. of the screen printing technology, wherein the etching method can be dry etching, such as plasma etching, electron beam etching, laser etching, etc., or wet etching, such as acid-base etching, redox etching, etc.

[0176] In some implementations, the pattern can be prepared by one of the above methods, or by a combination of two or more methods. After the depression is obtained, it can be post-processed to obtain the final patterned surface. In some specific implementations, post-processing includes but is not limited to enhancement treatment, such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating, etc.; or removal treatment, such as plasma ashing, solution etching, dry oxidation, etc. The embodiments of the present application do not have any special restrictions on the specific process parameters of the above-mentioned treatment, and those skilled in the art can select according to their needs.

[0177] In some implementations, the chip manufacturing method further includes: preparing a first film layer on the surface where the chip base is recessed, wherein the first film layer and the substrate are made of different materials. The parameters and materials of the first film layer and the substrate are as described above and are not further described here. In some embodiments, the first film layer is selected from one or more of a metal film, a metal oxide film, and an inorganic oxide film. In some embodiments, the material of the first film layer is at least one of Au, Al, and SiO2. In some embodiments, the thickness of the first film layer is 10 to 1000 nm.

[0178] In the embodiments of the present application, a first film layer can be formed on a substrate by deposition and then used to prepare the recess; alternatively, the first film layer can be deposited after the recess is formed on the chip base substrate. That is, the first film layer can be prepared before or after step a). The embodiments of the present application are not particularly limited to the deposition method, and can be physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, or oxidation treatment.

[0179] In some specific implementations, after the regularly arranged depressions are formed, the following steps are further included:

[0180] b) forming a polymer layer within the recesses.

[0181] After regularly arranged depressions are formed on a substrate, the surface is modified to provide capture or detection sites.

[0182] In some embodiments, the chip substrate is preferably pretreated before forming the polymer layer. In some specific implementations, the pretreatment includes cleaning and plasma activation. Cleaning can be solution cleaning, and plasma activation is performed after cleaning. In some specific implementations, the gas used for plasma activation includes but is not limited to air, nitrogen, argon, hydrogen, carbon tetrafluoride, etc., and can be a mixture of one or more of these gases. In some specific implementations, the power of plasma activation is 10W to 2kW.

[0183] In one embodiment, the recess is a recess formed on the surface of the chip substrate and / or the cover plate. In this case, b) includes:

[0184] connecting a polymer containing a first functional group to the surface where the depression is located;

[0185] The polymer is polished to remove the polymer except for the area where the depression is located, and a polymer layer is formed on the depression.

[0186] It should be understood that this embodiment includes the case where the polymer is connected to the surface where the depression is located via a coupling molecule. In this way, the polymer outside the depression can be removed, reducing nonspecific adsorption on the chip surface.

[0187] In an embodiment of the present application, the polymer is polished to remove the polymer outside the area where the depression is located, wherein the removal method is not particularly limited, including but not limited to solution cleaning, chemical polishing, mechanical polishing, chemical mechanical polishing and other methods. Among them, solution cleaning specifically uses a reagent that can dissolve and remove polymer molecules, such as acid, alkali, solvent, surfactant, etc. to remove polymer molecules outside the depression. Preferably, the solution cleaning is carried out under ultrasonic conditions, or the solution cleaning is carried out by flushing. In some embodiments, the polymer is removed by polishing. The polishing can be chemical polishing based on chemical reaction removal, mechanical polishing based on mechanical removal, or a combination of the above two polishing methods. The embodiment of the present application can use chemical polishing reagents, for example, it can be a reagent including one or more of acid, alkali, organic solvent, and surfactant for polishing, or mechanical polishing can be used, for example, polishing is carried out using one or more reagents such as diamond, silica sol, calcium carbonate, cerium oxide, zirconium oxide, etc. as polishing agents.

[0188] In the technical solution provided in the present application, when the substrate is processed by polishing, the chip base is preferably a structure including a substrate and a first film layer. At this time, the first film layer can be used as a polishing end point indicator to indicate the polishing end point, which is beneficial to control the degree of surface polishing and obtain a chip with a stable and uniform surface, which is more conducive to the stability of detection.

[0189] In another embodiment, the depressions are protrusions formed on the surface of the chip substrate and / or cover plate. In this case, a) includes attaching a polymer containing a first functional group to the surface of the substrate. Then, the substrate with the polymer formed on the surface is patterned to form regularly arranged depressions on the surface.

[0190] In the above two embodiments, in some examples, the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group, and an azide group.

[0191] In the above two embodiments, in some embodiments, the substrate is treated with coupling molecules to form coupling molecules on the surface of the substrate to be treated or the surface where the depression is located, and the polymer is modified on the coupling molecules to form a polymer layer. Before coupling molecules on the surface of the chip substrate, the chip substrate is preferably pretreated. In some specific implementations, the pretreatment includes cleaning and plasma activation. Cleaning can be solution cleaning, and plasma activation is performed after cleaning. In some specific implementations, the gases used for plasma activation include but are not limited to air, nitrogen, argon, hydrogen, carbon tetrafluoride, etc., and can be a mixed gas of one or more thereof. In some specific implementations, the power of plasma activation is 10W to 2kW. After pretreatment, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition, magnetron sputtering, solution method, spin coating, spray coating, etc. can be used to combine the coupling molecules to provide active sites for the fixation of the polymer.

[0192] The molecular formula of the coupling molecule is as follows: X a Si(Y b )M c Z, X, and Z serve as reactive groups and are used to connect the chip substrate and the functional groups of the polymer, respectively.

[0193] Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 Alkoxy, exemplary, such as Cl, CH3O-, CH3CH2O-, etc.; Y is selected from C 1-10 Alkyl, such as CH3-, CH3CH2-, etc.; M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ; Z is selected from the following groups: unsubstituted or substituted: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl; C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl, at least one R a Replacement, R aEach is independently selected from halogen, nitro, ester, amino, carboxyl, hydroxyl, azide, and epoxy; a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50.

[0194] In some possible implementations, the polymer and the coupling molecule can be connected by solution method, spin coating, screen printing, spray coating, etc. In some specific implementations, the temperature for modifying the polymer on the coupling molecule to form a polymer layer is 25-100° C. and the time is 1 hour to 48 hours.

[0195] In some embodiments, after the polymer layer is formed, the polymer and coupling molecules on the periphery of the depression are removed by post-processing to reduce the non-specific adsorption on the surface of the biochip. The embodiments of the present application have no special restrictions on the removal method, including but not limited to solution cleaning, chemical polishing, mechanical polishing, chemical mechanical polishing and other methods. Among them, solution cleaning specifically adopts a reagent that can dissolve and remove the coupling molecules, such as acid, alkali, solvent, surfactant, etc. to remove the coupling molecules on the periphery of the depression, preferably the solution cleaning is carried out under ultrasonic conditions, or the solution cleaning is carried out by flushing. In some embodiments, the coupling molecules are removed by polishing, and the polishing can be chemical polishing based on chemical reaction removal, mechanical polishing based on mechanical removal, or a combination of the above two polishings. The embodiments of the present application can use chemical polishing reagents, for example, it can be a reagent including one or more of acid, alkali, organic solvent, and surfactant for polishing, or mechanical polishing can be used, for example, polishing is carried out using one or more reagents such as diamond, silica sol, calcium carbonate, cerium oxide, zirconium oxide, etc. as polishing agents.

[0196] Similarly, when the chip substrate is processed by polishing, the chip substrate is preferably a structure including a chip substrate and a first film layer. At this time, the first film layer can be used as a polishing end point indicator to indicate the polishing end point, which is beneficial to control the degree of surface polishing, thereby making the surface polishing and coupling molecule modification uniform, obtaining a chip with a stable and uniform surface, which is more conducive to the stability of detection.

[0197] In some specific implementations, the chip preparation method further includes modifying capture molecules or detection molecules on the polymer layer, such as nucleic acid probes, antigen antibodies, and nucleic acid-protein complexes. The embodiments of the present application do not specifically limit the modification method of the capture molecules or detection molecules. For example, they can be modified by chemical coupling, including hydroxyl-carboxyl coupling, amino-carboxyl coupling, thiol-thiol coupling, click chemistry coupling, etc. In some specific implementations, the capture molecules or detection molecules can be modified after post-treatment, or after the polymer layer is formed, and then the excess polymer, capture molecules or detection molecules are removed by post-treatment.

[0198] In the embodiments of the present application, the chip includes a chip substrate, at least the chip substrate being prepared by the above-described method. In some specific implementations, the prepared chip substrate is further packaged so that depressions on the chip substrate form one or more flow channels to achieve a liquid flow function, enabling the switching of different reagents during the detection process and the flow reaction on the chip, while also withstanding multiple cycles of reagent flushing.

[0199] In some specific implementations, the encapsulation material can be bonded to the chip substrate using methods including, but not limited to, thermal bonding, laser bonding, and chemical or physical bonding. Chemical or physical bonding can employ UV-curable adhesives, heat-curable adhesives, and pressure-sensitive adhesives. In some specific implementations, the encapsulation layer can be a cover plate with a recess, which can be the same or different from the recess in the chip substrate; or it can be a plain cover plate.

[0200] In one embodiment, Figure 18 As shown, the first cover plate is a common cover plate without a recess, i.e., both surfaces of the first cover plate are untreated, flat surfaces. The first cover plate is bonded to the recessed surface of the chip substrate, and during the bonding process, a fluid channel is formed along the length of the recessed surface of the chip, allowing fluid to flow through the recessed surface.

[0201] In one embodiment, Figure 19 As shown, the first cover plate has regularly spaced depressions on one side, and the depressions in the first cover plate are positioned opposite the depressions in the chip substrate. The side of the first cover plate with the bonding structure is aligned with the side of the chip substrate with the depressions. During the alignment process, fluid channels are formed along the length of the surface with the depressions, allowing fluid to flow through the depressions. In this embodiment, the depressions in the first cover plate and the depressions in the chip substrate can be the same or different. To save space, they will not be further described here.

[0202] In one embodiment, Figure 20 As shown, a first cover plate and a second cover plate are respectively attached to the two side surfaces of the chip base recess. The first and second cover plates are ordinary cover plates without recesses, that is, both surfaces of the first and second cover plates are flat. The first and second cover plates are respectively attached to the two surfaces of the chip base with recesses. During the attachment process, a fluid channel is formed along the length of the recessed surface of the chip, allowing fluid to flow through the recess.

[0203] In one embodiment, Figure 21As shown, a first cover plate and a second cover plate are respectively bonded to the two side surfaces of the chip substrate recess. The first cover plate is a cover plate with a recess, and the recess of the first cover plate is arranged opposite the recess of the chip substrate. The second cover plate is a conventional cover plate without a recess, and both surfaces of the second cover plate are flat. In this case, the side of the first cover plate with the bonding structure is bonded to the surface of the chip substrate with the recess. The second cover plate is bonded to the other surface of the chip substrate with the recess. During the bonding process, fluid channels are formed along the length of the recessed surface of the chip, allowing fluid to flow through the recess. It should be understood that the recess of the first cover plate and the recess of the chip substrate can be the same or different.

[0204] In one embodiment, Figure 22 As shown, a first cover plate and a second cover plate are respectively bonded to the two side surfaces of the chip substrate recess. Both cover plates are recessed, and the recesses of the cover plates are arranged opposite to the recesses of the chip substrate, forming a structure similar to a dual-chip stack. At this time, the side of the first cover plate with the bonding structure is relatively bonded to one surface of the chip substrate with the recess, and the side of the second cover plate with the bonding structure is relatively bonded to the other surface of the chip substrate with the recess. During the bonding process, fluid channels are formed along the length direction of the surface with the recess, allowing fluid to flow through the recess. It should be understood that the recess of each cover plate can be the same as or different from the recess of the chip substrate; the recesses of the two cover plates can be the same or different.

[0205] When the cover plate is a cover plate with a recess, the cover plate can be prepared by the above method. The material of the cover plate can be the same as or different from the material of the chip substrate, including but not limited to glass; quartz; silicon-based materials such as silicon dioxide, polycrystalline silicon, single crystal silicon, etc.; polymers such as HMDS, PE, PP, etc. Depending on the situation, please refer to the description of the chip above. In some specific implementations, encapsulation can be performed between any steps of forming the coupling molecule, forming the polymer layer, post-processing, modifying the detection molecule or the capture molecule, as long as it does not affect the subsequent processing.

[0206] In some embodiments, the above steps are performed on a wafer-like chip substrate to improve production efficiency. Therefore, before packaging, the chip can be cut to obtain chips of a desired size.

[0207] After obtaining the biochip, gene sequencing can be performed on the biochip, which can improve the detection throughput and the stability and reliability of the sequencing structure.

[0208] Specifically, by amplifying the fixed nucleic acid molecules in the chip depression to form an amplification cluster containing 10-100,000 copies of DNA molecules, the amplification cluster is then sequenced. Since the depression confines the amplification cluster to a certain space, the amplification cluster can present a shape, density, and brightness that meet the detection requirements, thereby improving the stability and reliability of the detection flux and sequencing structure. Not only that, by confining the amplification cluster in the depression of the chip provided in the embodiment of the present application, the stability of the amplification cluster during the sequencing process can be improved, so that it can withstand liquid environments including acidic reagents, alkaline reagents, organic solvents, a wide reaction temperature of 4°C-90°C, more than 100 solution washes, etc., and can maintain good stability in this environment; moreover, using the depression as a sequencing site will not only not affect the biochemical functions of biomolecules such as polymerases and amplification enzymes, but also reduce the adsorption of fluorescent dyes and nucleic acid molecules.

[0209] In this embodiment, the method for amplifying the immobilized nucleic acid molecules in the chip recess is not strictly limited, and surface chain polymerase chain reaction (PCR) amplification such as bridge amplification, template walking amplification, etc., or rolling circle amplification can be used, but is not limited thereto.

[0210] The patterned biochip and its preparation method provided by the present application are further described below with reference to the examples.

[0211] Example 1

[0212] This embodiment provides a patterned biochip, which includes a silicon chip substrate, on which depressions arranged in a honeycomb pattern are formed, that is, the depressions are arranged in rows and columns, the depressions in two adjacent rows are not located in the same column, and the depressions in the alternate rows are located in the same column; the depressions in two adjacent columns are not located in the same row, and the depressions in the alternate columns are located in the same row, and the depressions are pear-shaped structures, such as Figure 16 As shown, it can be considered that the depression comprises a symmetrical first geometric structure A, whose bottom diameter in the horizontal direction of the chip surface is smaller than the bottom diameter b in the horizontal direction away from the chip surface, resulting in a shape that is narrow at the top and wide at the bottom. The pear-shaped depression's depth c perpendicular to the chip surface, bottom diameter a in the horizontal direction of the chip surface, bottom diameter b in the horizontal direction away from the chip surface, angle α between the sidewall and the horizontal direction away from the chip surface, and spacing f between adjacent depressions (i.e., center-to-center) are shown in Table 1, which lists the dimensional parameters of the depressions in the biochips provided in Examples 1-5.

[0213] A silane molecular film layer with amino functional groups and a polymer layer are sequentially formed on the surface of each depression;

[0214] The surface of the silicon chip substrate is packaged with a cover plate whose surface is not treated.

[0215] The preparation process is as follows: first, a patterned adhesive layer is formed on the surface of a silicon chip substrate by nanoimprinting, the chip substrate is etched according to the pattern, and after removing the adhesive layer, regularly arranged depressions are formed on the silicon chip substrate; after forming a chip substrate with a pattern, a silane molecular film layer with amino functional groups is formed in the depressions, and then the polymer is fixed on the chip substrate by amino-carboxyl condensation; polishing is performed to remove the biological macromolecule layer, small molecule layer and part of the silicon dioxide film outside the truncated cone-shaped depressions; the polished chip substrate is cut and cleaned, and encapsulated with a cover plate with an untreated surface to obtain a biochip.

[0216] Example 2

[0217] The difference from Example 1 is that the depression is a cylindrical depression, such as Figure 14 As shown, it can be considered that the depression comprises a symmetrical second geometric structure B, with its bottom diameter horizontally on the chip surface equal to its bottom diameter d horizontally away from the chip surface, and a shape with equal width at the top and bottom. The depth e of the cylindrical depression perpendicular to the chip surface, the bottom diameter d horizontally away from the chip surface, the angle α between the sidewall and the horizontal direction away from the chip surface, and the spacing f between adjacent depressions (i.e., center-to-center) are shown in Table 1, which lists the dimensional parameters of the depressions in the biochips provided in Examples 1-5.

[0218] Example 3

[0219] The difference from Example 1 is that the depression is a nearly conical depression, see Figure 12 It can be considered that the depression comprises a symmetrical first geometric structure A, with its bottom diameter a horizontally on the chip surface being larger than its bottom diameter b horizontally away from the chip surface, resulting in a shape that is wider at the top and narrower at the bottom. The depth c of the nearly conical depression perpendicular to the chip surface, the bottom diameter a horizontally on the chip surface, the bottom diameter b horizontally away from the chip surface, the angle α between the sidewall and the horizontal direction away from the chip surface, and the spacing f between adjacent depressions (i.e., center-to-center) are shown in Table 1, which lists the dimensional parameters of the depressions in the biochips provided in Examples 1-5.

[0220] Example 4

[0221] The difference from Example 1 is that it includes a silicon chip substrate, on which depressions arranged in a honeycomb pattern are formed, that is, the depressions are arranged in rows and columns, the depressions of two adjacent rows are not located in the same column, and the depressions of alternate rows are located in the same column; the depressions of two adjacent columns are not located in the same row, and the depressions of alternate columns are located in the same row, and the depressions are a trumpet-shaped structure, such as Figure 5As shown. The depressions, in the direction from the chip base surface toward the center, include interconnected truncated cone-shaped depressions A and cylindrical depressions B. The truncated cone-shaped depression A is a symmetrical structure, with its bottom diameter a in the horizontal direction of the chip surface being greater than its bottom diameter b in the horizontal direction away from the chip surface, presenting a shape that is wide at the top and narrow at the bottom. The cylindrical depression B is a symmetrical structure, with its bottom diameter d equal to its bottom diameter b, presenting a shape that is uniformly wide and narrow at the top and bottom. The depth c of the truncated cone-shaped depression A in the direction perpendicular to the chip surface, the bottom diameter a in the horizontal direction of the chip surface, the bottom diameter b in the horizontal direction away from the chip surface, the angle α between the sidewall and the horizontal direction away from the chip surface, the depth e of the truncated cone-shaped depression B in the direction perpendicular to the chip surface, the bottom diameter d in the horizontal direction away from the chip surface, and the spacing f between adjacent depressions (i.e., center to center) are shown in Table 1, which lists the dimensional parameters of the depressions in the biochips provided in Examples 1 to 5.

[0222] Example 5

[0223] The difference from Example 1 is that the depression is a flat-bottomed conical depression, see Figure 10 It can be considered that the depression comprises a symmetrical first geometric structure A, with its bottom diameter a horizontally on the chip surface being larger than its bottom diameter b horizontally away from the chip surface, resulting in a shape that is wider at the top and narrower at the bottom. The flat-bottomed conical depression's depth c perpendicular to the chip surface, bottom diameter a horizontally on the chip surface, bottom diameter b horizontally away from the chip surface, angle α between the sidewall and the horizontal direction away from the chip surface, and spacing f between adjacent depressions (i.e., center-to-center) are listed in Table 1, which lists the dimensional parameters of the depressions in the biochips provided in Examples 1-5.

[0224] Table 1 Dimensional parameters of the depressions in the biochips provided in Examples 1 to 5

[0225] Example a(nm) b(nm) c(nm) d(nm) e(nm) f(nm) α(°) 1 250 400 500 \ 0 750 100 2 \ \ 0 400 500 750 90 3 400 5 500 \ 0 750 68 4 400 250 200 250 300 750 70 5 400 250 500 \ 0 750 80

[0226] Test Example 1

[0227] Amplification and sequencing were performed in the biochips prepared in Examples 1 to 5, respectively, and the process was as follows:

[0228] Probes are introduced into the biochips provided in Examples 1 to 5, and the probes are fixed in the micropores via polymers; a nucleic acid library (nucleic acid sample to be tested) is introduced and surface amplification is performed to form replicated amplification clusters in the micropores;

[0229] Add the nucleic acid substrate ATCG with a fluorescent group and polymerase to carry out base extension reaction, collect the impact signal of each base extension reaction, and determine the base type involved in each round of base extension reaction through image analysis to determine the sequence of the nucleic acid library.

[0230] The brightness of ATCG in the fluorescence images collected by the chips provided in Examples 1 to 5 was statistically analyzed, and the results were as follows: Figure 23 As shown, the results show that when the biochip with a micro-nano structure that is wide at the top and narrow at the bottom (Examples 3 to 5) is used for sequencing, ATCG has higher brightness in the fluorescent image and the nucleic acid library has a higher copy number in the depression than the biochip with a micro-nano structure that is equal in width at the top and bottom (Example 2) or narrow at the top and wide at the bottom (Example 1).

[0231] The Q30, output ratio, resolution rate and alignment rate of the chip amplification process provided in Examples 1 to 5 were statistically analyzed. The results are as follows: Figure 23 shown.

[0232] Among them, Q30 refers to the percentage of bases with Q values ​​greater than or equal to 30 among all bases, and the calculation formula of Q value is: Q = -10log 10 P, where P is the error rate. Q30 can also be understood as the percentage of bases with a base recognition error rate lower than 0.1% to the total number of sequenced bases. Q30 reflects the quality of sequencing. The higher the value, the better the sequencing quality.

[0233] The output ratio refers to the proportion of valid reads that pass the filtering criteria among the total reads that can generate signals and are recognized and read by the algorithm;

[0234] The splitting rate refers to the percentage of nucleic acid molecules that can be matched to each labeled sample in the total number of nucleic acid molecules in the mixed sample when multiple samples are mixed and sequenced;

[0235] The alignment rate refers to the percentage of sequenced sequences that align with the sample standard sequence.

[0236] Figure 24 The results show that the biochips with micro-nano structures that are wide at the top and narrow at the bottom (Examples 3 to 5) have better sequencing results than the biochips with micro-nano structures that are equal in width at the top and bottom (Example 2) or narrow at the top and wide at the bottom (Example 1).

[0237] The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip, characterized in that: The chip substrate comprises a chip substrate, wherein regularly arranged depressions are formed on at least one surface of the chip substrate; The recess includes a first geometric structure and a second geometric structure that are interconnected in sequence from the surface of the chip substrate toward the center; The first geometric structure has a depth c in a direction perpendicular to the chip surface of 0 to 100 μm, a maximum dimension a in a direction horizontal to the chip surface of 10 nm to 100 μm, and a maximum dimension b in a horizontal direction away from the chip surface of 10 nm to 100 μm; an angle α between a sidewall of the first geometric structure and the horizontal direction of the side away from the chip surface of 10 nm to 170°; The depth e of the second geometric structure in a direction perpendicular to the chip surface is 0 to 100 μm, and the maximum dimension d in a horizontal direction away from the chip surface is 0 to 100 μm; the depth c and the depth e are not both 0.

2. The chip according to claim 1, characterized in that The angle α satisfies the following relationship: 10≤α<90°.

3. The chip according to claim 2, characterized in that The maximum dimension a is greater than the maximum dimension b, and the maximum dimension b is equal to the maximum dimension d; Optionally, the depth c is 50 nm to 50 μm; Alternatively, the maximum size a is greater than the maximum size b, the maximum size b is greater than the maximum size d, and the maximum size d is not 0; Optionally, the depth c is 50 nm to 50 μm; Optionally, the ratio of the depth c to the depth e is 1:1000 to 1000:1; Alternatively, the maximum size a is greater than the maximum size b, and the maximum size d is equal to 0; Optionally, the depth c is 50 nm to 50 μm; Optionally, the depth e is 0.

4. The chip according to any one of claims 1 to 3, characterized in that: The distance f between adjacent recesses is 10 nm to 100 μm.

5. The chip according to any one of claims 1 to 4, characterized in that: The surface has at least one array unit, and the array unit has regularly arranged depressions; Optionally, the array unit is one or more of a square array unit, a rectangular array unit and a honeycomb array unit.

6. The chip according to any one of claims 1 to 5, characterized in that: The chip further includes a first cover plate combined with a surface of one side of the chip substrate where a recess is provided, wherein the first cover plate is made of a material with a light transmittance greater than or equal to 95%; Optionally, the surface of the first cover plate facing the chip substrate is a flat surface; or A surface of the first cover plate facing the chip substrate is provided with a regularly arranged geometric structure, and the geometric structure of the first cover plate is the same as or different from the recess of the chip substrate; Optionally, the chip substrate has regularly arranged depressions on both surfaces; Optionally, the chip includes a first cover plate and a second cover plate respectively bonded to both side surfaces of the chip substrate, and the first cover plate and the second cover plate are made of a material with a light transmittance greater than or equal to 95%; Optionally, both surfaces of the first cover plate and the second cover plate are flat surfaces; or The first cover plate is a cover plate with a geometric structure on its surface, and the geometric structure of the first cover plate is arranged opposite to the recess of the chip base, and both surfaces of the second cover plate are flat surfaces; or The first cover plate and the second cover plate are both cover plates with geometric structures arranged on their surfaces, and the geometric structures on the first cover plate and the second cover plate are respectively arranged opposite to the depressions on the two surfaces of the chip substrate.

7. The chip according to any one of claims 1 to 6, characterized in that: The chip includes a polymer layer, and the polymer layer is arranged on the surface of the recess; Optionally, the polymer layer is formed of a polymer containing a first functional group, wherein the first functional group is selected from one or more of a thiol group, an aldehyde group, a hydroxyl group, a carboxyl group, an amino group, an alkenyl group, an alkynyl group, and an azide group; Optionally, the polymer layer is bonded to the surface of the chip substrate and / or the cover plate via coupling molecules; Optionally, the molecular formula of the coupling molecule is as follows: X a Si(Y b )M c Z, Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 alkoxy; Y is selected from C 1-10 alkyl; M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ; Z is selected from the following groups: unsubstituted or substituted: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl; a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50; Optionally, the chip further comprises a first film layer provided between the chip substrate and / or the cover plate and the polymer layer, wherein the material of the first film layer is different from the material of the surface to which it is bonded; Optionally, the first film layer is selected from one or more of a metal film, a metal oxide film and an inorganic oxide film; Optionally, the material of the first film layer is at least one of Au, Al and SiO2; Optionally, the thickness of the first film layer is 10 to 1000 nm; Optionally, an adhesive layer is provided between the chip base and the cover plate, and the adhesive layer has a channel provided in the length direction of the chip, the recess is provided on the chip base in the area where the channel is located and / or the geometric structure is provided on the cover plate surface in the area where the channel is located, and the shapes and / or arrangements of the recesses or geometric structures in different channels on the same surface are the same or different.

8. A method for preparing a chip, characterized in that: The following steps are involved: a) forming regularly arranged depressions on at least one surface of the substrate; The recess includes a first geometric structure and a second geometric structure that are interconnected in sequence from the surface of the chip substrate toward the center; The first geometric structure has a depth c in a direction perpendicular to the chip surface of 0 to 100 μm, a maximum dimension a in a direction horizontal to the chip surface of 10 nm to 100 μm, and a maximum dimension b in a horizontal direction away from the chip surface of 10 nm to 100 μm; an angle α between a sidewall of the first geometric structure and the horizontal direction of the side away from the chip surface of 10 nm to 170°; The second geometric structure has a depth e in a direction perpendicular to the chip surface of 0 to 100 μm, and a maximum dimension d in a horizontal direction away from the chip surface of 0 to 100 μm; The depth c and the depth e are not 0 at the same time.

9. The preparation method according to claim 8, characterized in that The substrate is a chip base and / or a cover plate; Optionally, the method further includes: b) forming a polymer layer on the recess; Optionally, the b) includes: connecting a polymer containing a first functional group to the surface where the depression is located; polishing the polymer to remove the polymer outside the area where the depression is located, thereby forming a polymer layer on the depression; Optionally, the polishing is chemical polishing and / or mechanical polishing; Optionally, the molecular formula of the coupling molecule is as follows: X a Si(Y b )M c Z, Wherein, X is H, F, Cl, Br, I, C 1-6 Alkyl, C 1-6 Haloalkyl or C 1-6 alkoxy; Y is selected from C 1-10 alkyl; M c Selected from C 1-50 Alkylene, -(OCH2CH2) c -、-(CH(OH)CH2-) c ; Z is selected from the following groups: unsubstituted or substituted: amino, carboxyl, hydroxyl, azido, C 1-20 Alkyl, C 2-20 Alkenyl, C 2-20 Alkynyl, C 3-20 Cycloalkyl, 3-20 membered heterocyclic group, C 6-20 Aryl, 5-20 membered heteroaryl; a, b, and c are all integers, and their values ​​satisfy: 0≤a≤3, 0≤b≤3, and a+b=3; 1≤c≤50; Optionally, the method further comprises: before step a), or after step a) and before step b), preparing a first film layer on the surface where the depression is located, wherein the first film layer and the substrate are made of different materials; Optionally, the first film layer is selected from one or more of a metal film, a metal oxide film and an inorganic oxide film; Optionally, the material of the first film layer is at least one of Au, Al and SiO2; Optionally, the thickness of the first film layer is 10 to 1000 nm; Optionally, the substrate includes at least a chip base, and the method further includes: Adhesive material is used to combine the cover plate on the surface of the chip substrate on one side where the recess is set, and the adhesive material forms a channel in the length direction of the chip.

10. The preparation method according to claim 8 or 9, characterized in that: The chip is the chip according to any one of claims 1 to 7.

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