Chip aging test system and aging test method

Abstract

The invention discloses a chip aging test system and an aging test method. The chip aging test system comprises a chip set to be tested and an aging test device, the chip set to be tested comprises a red light chip, a green light chip and a blue light chip; the aging test device comprises a high-temperature test box body, a data acquisition module and a control module; the chip set to be tested is arranged in the aging test device and is connected with the power supply of the high-temperature test box body, the data acquisition module and the control module respectively; the data acquisition module is arranged in the high-temperature test box body and is used for acquiring aging data of the to-be-tested chipset, and the control module is used for controlling the temperature of the high-temperature test box body and on-off of a power supply. According to the invention, the reliability of the aging test is improved by simulating a heat accumulation environment during actual work.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip aging test system and an aging test method. Background Art

[0002] Conventional aging technology for RGB LEDs is based on the principle of accelerated life testing. It applies electrical and thermal stresses to screen for early failures and ensure product reliability. Typically, LED chips are placed in a high-temperature environment of 85°C to 125°C and continuously energized at a rated current of 20mA to 50mA for 48 to 168 hours. This accelerates the thermal degradation of the LED chip and packaging materials, and observes for light decay, color drift, or even dead LEDs. However, testing each LED chip individually consumes significant time and raw materials, significantly reducing production efficiency, especially in large-scale production. Furthermore, testing individual LED chips individually fails to expose them to the heat accumulation experienced in actual cluster operation, resulting in low reliability in aging tests. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a chip aging test system and aging test method, which can improve the reliability of the aging test by simulating the heat accumulation environment during actual operation.

[0004] In order to solve the above problems, the present invention discloses a chip aging test system, including a chipset to be tested and an aging test device;

[0005] The chipset to be tested includes a red light chip, a green light chip and a blue light chip;

[0006] The aging test device includes a high-temperature test chamber, a data acquisition module and a control module; the chipset to be tested is arranged in the aging test device and is respectively connected to the power supply, data acquisition module and control module of the high-temperature test chamber; the data acquisition module is arranged in the high-temperature test chamber and is used to collect aging data of the chipset to be tested, and the control module is used to control the temperature of the high-temperature test chamber and the on / off of the power supply.

[0007] As an improvement of the above technical solution, the high-temperature test box is provided with a power supply, a PWM driver, and an aging board, and multiple chip groups to be tested are arranged on the aging board. The aging board is connected to the power supply, the PWM driver is connected to the power supply, and the control module is connected to the power supply and the PWM driver.

[0008] As an improvement of the above technical solution, the chip group to be tested includes a lamp cup, a red light chip, a green light chip, a blue light chip, welding wires and a packaging glue layer. The red light chip welding area, the green light chip welding area and the blue light chip welding area are spaced apart on the lamp cup. The red light chip, the green light chip and the blue light chip are electrically connected to the red light chip welding area, the green light chip welding area and the blue light chip welding area respectively through welding wires; the packaging glue layer covers the red light chip, the green light chip and the blue light chip.

[0009] As an improvement to the above technical solution, a plurality of chipsets to be tested are arranged on the aging board at intervals, and the chipsets to be tested are connected to the power supply.

[0010] As an improvement of the above technical solution, the aging data includes luminous flux, luminous intensity, spectral characteristics, color temperature, color rendering index, forward voltage test, reverse voltage test and leakage current.

[0011] Accordingly, the present invention also discloses a chip aging test method, comprising the following steps:

[0012] Provide multiple chipsets to be tested;

[0013] Placing the plurality of chipsets to be tested and aged in the aging test device and connecting the aging test device to a power supply;

[0014] Start the aging test device through the control module to control the high temperature test box to a preset temperature;

[0015] Starting the power supply through the control module, lighting the aging chipset to be tested under the aging current; the ratio of the aging current to the rated current is (1-1.5):1;

[0016] The aging condition of the aging chipset to be tested is recorded by a data acquisition module.

[0017] As an improvement to the above technical solution, after lighting up the chips of the chipset to be tested and aged, aging data of the chipset to be tested and aged is recorded at preset intervals to determine whether the chipset to be tested and aged is invalid; if so, the power is turned off to stop aging; if not, the aging trend of the chipset to be tested and aged is analyzed and aging is continued;

[0018] The aging data for judging the aging trend includes one or more of luminous flux, luminous intensity, wavelength, forward voltage, and reverse voltage.

[0019] As an improvement to the above technical solution, the following method is adopted to light up the chipset to be tested and aged: the red chip, the green chip and the blue chip in the chipset to be tested and aged are simultaneously lit up under the aging current.

[0020] As an improvement to the above technical solution, the following method is adopted to light up the chipset to be tested and aged: the red chip, the green chip and the blue chip in the chipset to be tested and aged are sequentially lit up under an aging current.

[0021] As an improvement to the above technical solution, the following method is used to light up the chipset to be tested and aged: multiple chipsets to be tested and aged are connected to a aging power supply and a PWM driver; and the red light chip, green light chip, and blue light chip in the chipset to be tested and aged are lit under a PWM dynamic dimming program and an aging current.

[0022] The implementation of the present invention has the following beneficial effects:

[0023] The present invention's chipset under test includes a red chip, a green chip, and a blue chip. These chips are packaged together within the same chipset, generating collective heat to simulate real-world heat dissipation conditions. This allows for more efficient and comprehensive exposure to heat-sensitive defects such as light decay and color shift. A control module controls the temperature and power supply of the high-temperature test chamber, enabling intelligent testing based on the different chip usage states and aging test methods. This eliminates the need for repeated manual adjustment of the chamber's parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a chipset to be tested provided by an embodiment of the present invention;

[0025] Figure 2 It is a flow chart of a chip aging test method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0027] The present invention provides a chip aging test system, comprising a chipset to be tested and an aging test device;

[0028] The chipset to be tested includes a red light chip, a green light chip and a blue light chip;

[0029] The aging test device includes a high-temperature test chamber, a data acquisition module and a control module; the chipset to be tested is arranged in the aging test device and is respectively connected to the power supply, data acquisition module and control module of the high-temperature test chamber; the data acquisition module is arranged in the high-temperature test chamber and is used to collect aging data of the chipset to be tested, and the control module is used to control the temperature of the high-temperature test chamber and the on / off of the power supply.

[0030] The present invention's chipset under test includes a red chip, a green chip, and a blue chip. These chips are packaged together within the same chipset, generating collective heat to simulate real-world heat dissipation conditions. This allows for more efficient and comprehensive exposure to heat-sensitive defects such as light decay and color shift. A control module controls the temperature and power supply of the high-temperature test chamber, enabling intelligent testing based on the different chip usage states and aging test methods. This eliminates the need for repeated manual adjustment of the chamber's parameters.

[0031] In one embodiment, the high-temperature test box is provided with a power supply, a PWM driver, and an aging board, and multiple chipsets to be tested are arranged on the aging board, the aging board is connected to the power supply, the PWM driver is connected to the power supply, and the control module is connected to the power supply and the PWM driver.

[0032] In one embodiment, Figure 1 As shown, the chipset to be tested includes a lamp cup 1, a red light chip 21, a green light chip 22, a blue light chip 23, welding wires 3 and an encapsulation adhesive layer (not shown in the figure). The red light chip welding area 11, the green light chip welding area 12 and the blue light chip welding area 13 are spaced apart on the lamp cup 1. The red light chip 21, the green light chip 22 and the blue light chip 23 are electrically connected to the red light chip welding area 11, the green light chip welding area 12 and the blue light chip welding area 13 respectively through the welding wires 3; the encapsulation adhesive layer covers the red light chip 21, the green light chip 22 and the blue light chip 23.

[0033] Compared to conventional packaging and testing of a single chip, the present invention packages the red light chip 21, green light chip 22, and blue light chip 23 on the same lamp cup 1 for aging testing, which can compress the test time by dozens of times and significantly improve the efficiency of the aging test. Secondly, the red light chip 21, green light chip 22, and blue light chip 23 are in exactly the same temperature, humidity, power supply, and signal environment, eliminating the errors introduced by equipment fluctuations, making the data more comparable and facilitating the identification of batch defects. In addition, centralized aging can simulate real application scenarios and expose systemic faults that are difficult to detect through individual tests.

[0034] Specifically, a plurality of chipsets to be tested are arranged at intervals on the aging board, and the chipsets to be tested are connected to the power supply. Different types of aging tests are realized by controlling the on and off of the current through a control module.

[0035] Chip aging refers to the process of verifying the chip's reliability, stability, and lifespan by simulating long-term use or extreme environmental conditions. Aging testing can expose potential defects (such as material degradation, packaging failure, and light efficiency degradation) and is a key verification step before mass production or during the R&D phase. Common aging methods are as follows:

[0036] (1) Current accelerated aging method: Continuously light the chip at a current higher than the rated current (such as 1.2 to 1.5 times) to accelerate chip degradation. (2) High temperature and high humidity aging method: 85℃ / 85%RH (high temperature and high humidity) for hundreds to thousands of hours. (3) Temperature cycle aging method: (4) Dimming aging method: long-term operation under high-frequency PWM dimming (such as 1kHz) to simulate actual dimming applications. The chip aging test system of the present invention can implement a variety of different aging methods.

[0037] It is understandable that the aging data includes one or more of luminous flux, luminous intensity, spectral characteristics, color temperature, color rendering index, forward voltage test, reverse voltage test, and leakage current.

[0038] Correspondingly, such as Figure 2 As shown, the present invention also provides a chip aging test method, comprising the following steps:

[0039] S1. Provide multiple chipsets to be tested.

[0040] It is understandable that the plurality of chipsets to be tested are prepared using the following method:

[0041] S11. Dispense glue on the lamp cup or package bracket. Dispensing glue is to precisely apply glue to the lamp cup or package bracket to fix the chip, enhance its performance and ensure long-term stable operation.

[0042] S12. Bond the chip to the lamp cup or package bracket. Bonding is to fix the chip to the lamp cup or package bracket to form a thermal or electrical path, providing conditions for subsequent wire bonding.

[0043] S13. Bake the lamp cup or package bracket after die bonding. During the early stages of die bonding, bubbles or impurities may be generated. Baking can expand and expel these bubbles due to heat, while removing some impurities and improving the purity and density of the packaging material, thereby enhancing the bonding strength and stability between the chip and the packaging material.

[0044] S14. Wire bond the chip to the lamp cup or package bracket. Wire bonding is a key step in the packaging process. One end of the wire is formed into a spherical solder joint through heating and ultrasonic vibration, and then precisely placed on the chip's pad. The metal wire is stretched and formed into a specific arc shape to avoid stress concentration. The other end of the wire is welded to the pin of the lamp cup or package bracket to complete the electrical connection.

[0045] S15, encapsulate the obtained structure with encapsulation glue. Post-encapsulation testing is a key step in ensuring product quality and performance.

[0046] S2. Place the plurality of chipsets to be tested and aged in the aging test device and connect them to a power source.

[0047] S3. Start the aging test device through the control module to control the high-temperature test box to a preset temperature.

[0048] Specifically, the preset temperature can be a constant temperature or a high and low temperature cycle. Optionally, the preset temperature can be 85°C for hundreds to thousands of hours, combined with 85% RH for high temperature and high humidity aging. The preset temperature can be cycled from -40°C to 100°C, with each cycle lasting 1 to 2 hours, repeated hundreds of times, for temperature cycling aging.

[0049] S4. Start the power supply through the control module to light up the aging chipset to be tested under the aging current; the ratio of the aging current to the rated current is (1-1.5):1.

[0050] In one embodiment, the following method is used to illuminate the chipset under test and burn-in: the red, green, and blue chips in the chipset are simultaneously illuminated under a burn-in current. Simultaneous illumination can simulate a white light illumination scenario. The superposition of red, green, and blue light produces white light, making it particularly suitable for applications requiring white light output, such as general lighting and LCD backlighting.

[0051] In one embodiment, the following method is used to illuminate the chipset under test and burn-in: the red, green, and blue chips in the chipset are sequentially illuminated under a burn-in current. This sequential illumination simulates monochromatic light applications and independently detects the attenuation characteristics of each color LED. This is particularly useful in applications requiring a monochromatic display, such as traffic lights, warning lights, and status indicators.

[0052] In one embodiment, the following method is used to illuminate the chipset to be tested and burned in: multiple chipsets to be tested and burned in are connected to a burn-in power supply and a PWM driver; and the red, green, and blue chips in the chipset to be tested and burned in are illuminated using a PWM dynamic dimming program and a burn-in current. Illuminating the red, green, and blue chips under the PWM dynamic dimming program can simulate complex lighting effects. The PWM frequency can range from 100Hz to 1kHz, and the duty cycle can range from 0.1% to 99.9%. This method is particularly suitable for scenes requiring dynamic color changes, such as stage lighting and RGB ambient lighting.

[0053] In one embodiment, the following method is used to light up the chipset to be tested and aged: multiple chipsets to be tested and aged are connected to an aging power supply and a PWM driver; the red light chip, green light chip, and blue light chip in the chipset to be tested and aged are sequentially lit under a PWM dynamic dimming program and an aging current, the aging time is 5 minutes to 10 minutes, the PWM frequency can be 1Hz to 10Hz, and the duty cycle can be 10% to 50%, and flash aging is performed, and then the red light chip, green light chip, and blue light chip in the chipset to be tested and aged are sequentially lit under the aging current.

[0054] S5. Record the aging condition of the aging chipset to be tested through a data acquisition module.

[0055] In one embodiment, after lighting up the chip of the chipset to be tested and aged, the aging data of the chipset to be tested and aged are recorded at preset intervals to determine whether the chipset to be tested and aged has failed; if so, the power is turned off to stop aging; if not, the aging trend of the chipset to be tested and aged is analyzed and aging is continued. It is understandable that by comprehensively analyzing the chip aging data, calculating chip attenuation and chip defects, an in-depth understanding of the performance changes, reliability status, and service life of the display screen can be obtained. These analysis results not only help to evaluate the quality of the display screen, but also provide an important basis for subsequent product improvement and optimization, ensuring that the display screen can operate stably and reliably in various application scenarios. Whether the chipset to be tested and aged has failed can be determined by different aging data. For example, the attenuation of the luminous flux can be obtained by an integrating sphere or a photometer. If the attenuation value of the luminous flux is greater than 30% of the initial value, the chipset to be tested and aged is defined as failed.

[0056] In summary, by adopting the chip aging test system and aging test method provided by the present invention, material costs can be saved by 20% and time costs can be reduced by more than 30%. Accurate aging testing and data analysis can help enterprises better understand the quality status of chips and avoid rework due to raw material quality problems; human resources are optimized. Compared with decentralized aging, which requires a large amount of manpower to monitor and operate on each production line, centralized aging only requires a relatively small number of professional and technical personnel for centralized management; centralized aging has significant advantages through simulation authenticity, especially in thermal management, consistency, mutual interference and other aspects.

[0057] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A chip aging test system, characterized in that: Including chipset to be tested and aging test equipment; The chipset to be tested includes a red light chip, a green light chip and a blue light chip; The aging test device includes a high-temperature test chamber, a data acquisition module and a control module; the chipset to be tested is arranged in the aging test device and is respectively connected to the power supply, data acquisition module and control module of the high-temperature test chamber; the data acquisition module is arranged in the high-temperature test chamber and is used to collect aging data of the chipset to be tested, and the control module is used to control the temperature of the high-temperature test chamber and the on / off of the power supply.

2. The chip aging test system according to claim 1, wherein: The high-temperature test box is equipped with a power supply, a PWM driver, and an aging board. Multiple chip groups to be tested are arranged on the aging board. The aging board is connected to the power supply, the PWM driver is connected to the power supply, and the control module is connected to the power supply and the PWM driver.

3. The chip aging test system according to claim 1, wherein: The chipset to be tested includes a lamp cup, a red light chip, a green light chip, a blue light chip, welding wires and a packaging adhesive layer. The lamp cup is provided with a red light chip welding area, a green light chip welding area and a blue light chip welding area at intervals. The red light chip, green light chip and blue light chip are electrically connected to the red light chip welding area, green light chip welding area and blue light chip welding area respectively through welding wires; the packaging adhesive layer covers the red light chip, green light chip and blue light chip.

4. The chip aging test system according to claim 1, wherein: A plurality of chipsets to be tested are arranged on the aging board at intervals, and the chipsets to be tested are connected to the power supply.

5. The chip aging test system according to claim 1, wherein: The aging data includes one or more of luminous flux, luminous intensity, spectral characteristics, color temperature, color rendering index, forward voltage, reverse voltage, and leakage current.

6. A chip aging test method, characterized in that: The following steps are involved: Provide multiple chipsets to be tested; Placing the plurality of chipsets to be tested and aged in the aging test device and connecting the aging test device to a power supply; Start the aging test device through the control module to control the high temperature test box to a preset temperature; Starting the power supply through the control module, lighting the aging chipset to be tested under the aging current; the ratio of the aging current to the rated current is (1-1.5):1; The aging condition of the aging chipset to be tested is recorded by a data acquisition module.

7. The chip aging test method according to claim 6, wherein: After lighting up the chips of the chipset to be tested and aged, recording the aging data of the chipset to be tested and aged at preset intervals to determine whether the chipset to be tested and aged is invalid; if so, turning off the power supply to stop the aging; if not, analyzing the aging trend of the chipset to be tested and continuing the aging; The aging data for judging the aging trend includes one or more of luminous flux, luminous intensity, wavelength, forward voltage, and reverse voltage.

8. The chip aging test method according to claim 6, wherein: The following method is used to light up the chipset to be tested and aged: a red chip, a green chip and a blue chip in the chipset to be tested and aged are simultaneously lit up under an aging current.

9. The chip aging test method according to claim 6, wherein: The following method is used to light up the chipset to be tested and aged: a red chip, a green chip and a blue chip in the chipset to be tested and aged are sequentially lit up under an aging current.

10. The chip aging test method according to claim 6, wherein: The following method is used to light up the chipset to be tested and aged: multiple chipsets to be tested and aged are connected to an aging power supply and a PWM driver; red chips, green chips and blue chips in the chipset to be tested and aged are lit under a PWM dynamic dimming program and an aging current.

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