Simulation device, simulation method, and non-transitory computer readable medium

Abstract

The invention relates to a simulation apparatus, a simulation method, and a non-transitory computer readable medium. The simulation device comprises a loop instruction sequence detector and an instruction calculation part. The loop instruction sequence detector detects a loop instruction sequence included in a target program and generates a loop instruction sequence detection signal. When generating the loop instruction sequence detection signal, the instruction calculation section executes the loop instruction sequence once and generates a simulation elapsed time required to execute the loop instruction sequence for a predetermined number of times.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2024-049180 filed on March 26, 2024 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a simulation device, a simulation method, and a non-transitory computer-readable medium for storing a program. Background Art

[0004] In recent years, with advances in autonomous driving, electrification, and connectivity technologies, the functionality and performance of in-vehicle electronic control units (ECUs) have continued to improve. At the same time, the scale and complexity of the electronic control software executed on in-vehicle ECUs have also increased. Software operation verification systems using simulation devices have been introduced into the development of in-vehicle software to improve development efficiency. The simulation device used is a development environment for hardware simulation and includes a model of the central processing unit (CPU) used to execute the software. This allows verification of the operation of in-vehicle software even in the early stages of development, when the actual ECU used to execute the software is not yet ready.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0357549

[0007] For example, an example of such a simulation device is disclosed in Patent Document 1. Patent Document 1 discloses a simulation device in which a target program is executed as a core part of a simulation model. Summary of the Invention

[0008] The simulation device sequentially executes the instructions included in the software program to be verified, and as a result, the state of the CPU model changes. The CPU model outputs data (such as a log or state) (hereinafter referred to as an execution log) depending on the processing carried out in response to the executed instructions. Based on the output execution log, it is determined whether the state of the CPU model should be transferred, thereby verifying the operation of the software.

[0009] Software operation is verified by executing the instructions included in the software program. As the software program to be verified becomes longer, the verification operation takes longer. As the scale and complexity of in-vehicle software increase, the use of simulation devices is expected to reduce the time required to verify software operation.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0011] According to one aspect, a simulation device includes a loop instruction sequence detector and an instruction calculation unit. The loop instruction sequence detector detects a loop instruction sequence included in a target program and generates a loop instruction sequence detection signal. When the loop instruction sequence detection signal is generated, the instruction calculation unit executes the loop instruction sequence once and generates a simulation elapsed time required to execute the loop instruction sequence a predetermined number of times.

[0012] According to the present disclosure, the time spent on simulation can be reduced, thereby reducing the time to verify software operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram illustrating a configuration example of a computer that implements the simulation device according to an embodiment of the present disclosure.

[0014] Figure 2 is a block diagram illustrating a configuration example of a simulation device according to the first embodiment.

[0015] Figure 3 is a block diagram illustrating a configuration example of a CPU model according to the first embodiment.

[0016] Figure 4 is a diagram illustrating an example of a delay loop instruction sequence.

[0017] Figure 5 is a diagram illustrating an example of an order in which multiple instructions including a delay loop instruction sequence are executed.

[0018] Figure 6 is a flowchart illustrating an example of the flow of instructions for processing executed by the CPU model according to the first embodiment.

[0019] Figure 7 is a flowchart illustrating an example of the flow of instructions for processing executed by the CPU model according to the first embodiment.

[0020] Figure 8 is a flowchart illustrating an example of the flow of instructions for processing executed by the CPU model according to the first embodiment.

[0021] Figure 9 is a block diagram illustrating a configuration example of a simulation device according to the second embodiment.

[0022] Figure 10 is a block diagram illustrating a configuration example of a CPU model according to the second embodiment.

[0023] Figure 11 is a diagram illustrating an example of a polling loop instruction sequence.

[0024] Figure 12is a diagram illustrating an example of an order in which multiple instructions comprising a polling loop instruction sequence are executed.

[0025] Figure 13 is a flowchart illustrating an example of the flow of instructions for processing executed by the CPU model according to the second embodiment.

[0026] Figure 14 is a flowchart illustrating an example of the flow of instructions for processing executed by the CPU model according to the second embodiment.

[0027] Figure 15 is a block diagram illustrating a configuration example of a CPU model according to the third embodiment.

[0028] Figure 16 is a flowchart illustrating an example of the flow of instructions for processing executed by the CPU model according to the third embodiment. DETAILED DESCRIPTION

[0029] The embodiments will be described in detail below with reference to the accompanying drawings. The same components are denoted by the same reference numerals and will not be described again in this specification and the accompanying drawings. Components may be omitted or simplified for illustration in the accompanying drawings.

[0030] The program can be stored in various types of non-transitory computer-readable media or tangible storage media. Examples of non-transitory computer-readable media and tangible storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other types of memory, compact disc (CD)-ROM, digital versatile disc (DVD), Blu-ray (registered trademark) disc or other optical disc storage device, magnetic cassette, magnetic tape and magnetic disk storage device or other magnetic storage device. The program can be transmitted on various types of temporary computer-readable media or communication media. Examples of temporary computer-readable media and communication media include, but are not limited to, electrical, optical, acoustic or other forms of propagation signals.

[0031] [First embodiment]

[0032] This disclosure will describe simulation devices according to various embodiments, and a computer executes a development environment program to implement the simulation devices according to the embodiments of the present disclosure. Similarly, a computer executes a development environment program to implement the simulation method according to the embodiments of the present disclosure.

[0033] A simulation device realized by using a computer will be described by way of example. Figure 11 is a block diagram illustrating a configuration example of a computer 1 for implementing a simulation device according to various embodiments of the present disclosure. The computer 1 includes a processor 11, an input / output (I / O) interface 12, a hard disk 13, and a bus 14. The processor 11 and the I / O interface 12 can access the hard disk 13 via the bus 14.

[0034] The hard disk 13 stores a development environment program and a software program to be verified (hereinafter referred to as a target program). The development environment program and the target program are input to the I / O interface 12 via various types of temporary or non-temporary computer-readable media and stored in the hard disk 13. The development environment program and the target program may be stored in other types of non-temporary computer-readable media, not limited to the hard disk.

[0035] The processor 11 reads and executes the development environment program from the hard disk 13 via the bus 14. Thus, a simulation device and a simulation method are realized. As described in detail below, the CPU model included in the simulation device executes the target program, thereby verifying the operation of the target program by using the simulation device.

[0036] Figure 2 1 is a block diagram illustrating a configuration example of the simulation device 2 according to the first embodiment. Figure 2 As shown in FIG, the simulation apparatus 2 includes a CPU model 21, a memory model 22, and a simulation controller 23. The CPU model 21 and the memory model 22 are modeled intellectual property (IP) blocks included in a semiconductor device on which a target program operates. The semiconductor device includes a CPU for executing the target program and a memory for storing the target program. The CPU in the semiconductor device is simulated by the CPU model 21, and the memory in the semiconductor device is simulated by the memory model 22.

[0037] The CPU model 21 reads the target program stored in the memory model 22 and executes the instructions included in the target program. The CPU model 21 outputs the simulation elapsed time of executing the instructions included in the target program. The CPU model 21 outputs the execution log in response to the processing carried out by executing the instructions included in the target program.

[0038] The memory model 22 stores the target program. The memory model 22 is connected to the CPU model 21 and stores the execution log output from the CPU model 21.

[0039] The simulation controller 23 is connected to the CPU model 21, and receives a simulation elapsed time of executing instructions included in the target program from the CPU model 21. The simulation controller 23 manages the simulation time based on the simulation elapsed time received from the CPU model 21.

[0040] The CPU model 21 will be described in detail below. Figure 31 is a block diagram illustrating a configuration example of the CPU model 21 according to the first embodiment. Figure 3 As illustrated in FIG. 2 , the CPU model 21 includes an instruction controller 211 , a loop instruction sequence detector 212 , and an instruction calculation section 213 .

[0041] The instruction controller 211 includes a program counter (PC) 2111, an instruction register 2112, and an instruction decoder 2113. The PC 2111 stores a PC value used to extract instructions included in the target program. The instruction register 2112 is used to store the extracted instructions. The instruction controller 211 extracts the next instruction to be executed based on the PC value stored in the PC 2111 and stores the extracted instruction in the instruction register 2112. Each time an instruction is extracted, the PC value is incremented and updated to indicate the address where the next instruction is stored.

[0042] The instruction decoder 2113 is connected to the instruction register 2112. The instruction decoder 2113 decodes the instruction stored in the instruction register 2112 or the instruction included in the target program, thereby generating a decoding result. The decoding result of the instruction is output to the loop instruction sequence detector 212 and the instruction calculation part 213.

[0043] The loop instruction sequence detector 212 includes a delayed loop instruction sequence pattern storage device 2121, a delayed loop execution information storage device 2122, and an instruction comparator 2123. The loop instruction sequence detector 212 can detect a delayed loop instruction sequence included in the target program using the delayed loop instruction sequence pattern storage device 2121, the delayed loop execution information storage device 2122, and the instruction comparator 2123.

[0044] The following describes a loop instruction sequence. Loop processing is used to create the wait state required to transition the CPU state. In loop processing, a predetermined process is repeatedly executed without transitioning the CPU state. In this disclosure, an instruction sequence used in a repeatedly executed process is referred to as a loop instruction sequence. The CPU repeatedly executes the loop instruction sequence, thereby achieving a wait state without transitioning the CPU state.

[0045] An example of a loop instruction sequence may be a delay loop instruction sequence. In the present disclosure, a loop process using a delay loop instruction sequence is referred to as a delay loop. Figure 4 FIG is a diagram illustrating an example of a delay loop instruction sequence. Figure 4 As shown in FIG, the delay loop instruction sequence includes an ldr instruction, a sub instruction, a str instruction, an ldr instruction, a cmp instruction, and a bne instruction. The delay loop instruction sequence is executed in a time sequence from the ldr instruction to the bne instruction.

[0046] The ldr instruction reads a value from memory and stores it in a general-purpose register in the CPU. The sub instruction subtracts two values ​​and stores the result in a general-purpose register in the CPU. The str instruction reads a value from a general-purpose register in the CPU and stores it in memory. The cmp instruction compares two values, setting a flag in the CPU status register to 1 if the two values ​​match, and setting the flag in the CPU status register to 0 if the two values ​​do not match. The bne instruction branches to a predetermined instruction when the flag in the CPU status register is 0.

[0047] The following will describe Figure 4 In the following description, it is assumed that the delay loop instruction sequence is repeated a number of times M. M is a natural number of 2 or greater.

[0048] First, using the ldr instruction, M is read from the memory and stored in a general-purpose register in the CPU. Next, using the sub instruction, 1 is subtracted from M stored in the general-purpose register in the CPU, and the result, M-1, is stored in the general-purpose register in the CPU. Next, using the str instruction, M-1 is read from the general-purpose register in the CPU and stored in the memory.

[0049] Next, the ldr instruction is used again to read M-1 from the memory and store it in a general register in the CPU. Next, the cmp instruction is used to compare M-1 with 0, and a mismatch is obtained, thereby setting the flag of the status register in the CPU to 0. Next, the bne instruction is used, and since the flag of the status register in the CPU is 0, the process branches to the first ldr instruction, and Figure 4 The delay loop instruction sequence is completed once.

[0050] Since the calculation result is decremented by 1 each time the sub instruction is executed, when the delay loop instruction sequence is repeated M times, the calculation result is 0. When the calculation result of the sub instruction is 0, the flag in the status register in the CPU is set to 1 using the cmp instruction. Therefore, the bne instruction prevents processing from branching to the first ldr instruction and exits the loop executing the delay loop instruction sequence. As described above, the delay loop instruction sequence is repeated M times to implement the delay loop.

[0051] Back to Figure 3 , and subsequently, a description will be given of the configuration of the CPU model 21. The delay loop instruction sequence pattern storage device 2121 stores a delay loop instruction sequence pattern that defines a delay loop instruction sequence included in a target program and to be repeatedly executed.

[0052] The delay loop instruction sequence pattern includes information about the type of instructions that configure the delay loop instruction sequence and the order in which the instructions are executed. Figure 4 In the example of , the delay loop instruction sequence pattern includes information indicating that the delay loop instruction sequence is configured by an ldr instruction, a sub instruction, a str instruction, an ldr instruction, a cmp instruction, and a bne instruction and is executed in this order.

[0053] The delay loop execution information storage device 2122 stores delay loop execution information about the delay loop instruction sequence being executed. The delay loop execution information includes information indicating whether the CPU model 21 is executing an instruction in the delay loop instruction sequence, information indicating which instruction in the delay loop instruction sequence is being executed when the delay loop instruction sequence is being executed, and the like.

[0054] The instruction comparator 2123 sequentially compares the instructions included in the target program with the delay loop instruction sequence pattern and generates a delay loop instruction sequence detection signal indicating that the plurality of instructions included in the target program match the delay loop instruction sequence pattern. The delay loop instruction sequence detection signal generated by the instruction comparator 2123 is output to the instruction calculation section 213.

[0055] Specifically, the instruction comparator 2123 sequentially receives the instruction decoding results output from the instruction controller 211. The instruction comparator 2123 receives the delay loop instruction sequence pattern stored in the delay loop instruction sequence pattern storage device 2121. The instruction comparator 2123 sequentially compares the instruction decoding results with the delay loop instruction sequence pattern in the order in which it receives the instruction decoding results.

[0056] When it is detected that the compared instruction matches the first instruction in the delay loop instruction sequence defined in the delay loop instruction sequence pattern, the instruction comparator 2123 generates delay loop execution information and stores it in the delay loop execution information storage device 2122. The delay loop execution information includes information indicating that the delay loop instruction sequence is being executed and information indicating that the first instruction in the delay loop instruction sequence is being executed.

[0057] When the instruction to be compared next is detected to match the second instruction in the delay loop instruction sequence defined in the delay loop instruction sequence pattern, the instruction comparator 2123 updates the delay loop execution information to indicate that the second instruction in the delay loop instruction sequence is being executed. Conversely, when the instruction to be compared next is not detected to match the second instruction in the delay loop instruction sequence defined in the delay loop instruction sequence pattern, the instruction comparator 2123 deletes the delay loop execution information stored in the delay loop execution information storage device 2122.

[0058] As described above, after comparison processing is performed on multiple instructions, when it is detected that the multiple compared instructions match the delay loop instruction sequence defined in the delay loop instruction sequence pattern, the instruction comparator 2123 generates a delay loop instruction sequence detection signal and deletes the delay loop execution information stored in the delay loop execution information storage device 2122.

[0059] For example, in Figure 4 In the delay loop instruction sequence, the instruction comparator 2123 follows Figure 4 The instruction comparator 2123 sequentially receives decoding results of the ldr instruction to the bne instruction. The instruction comparator 2123 generates delayed loop execution information based on the comparison processing result of the first ldr instruction, then sequentially updates the delayed loop execution information based on the comparison processing results of the sub instruction to the cmp instruction, and finally generates a delayed loop instruction sequence detection signal based on the comparison processing result of the bne instruction.

[0060] When the target program includes multiple delay loop instruction sequences, the delay loop instruction sequence pattern storage device 2121 may store multiple delay loop instruction sequence patterns. In this case, for each delay loop instruction sequence, the instruction comparator 2123 compares the instruction with the delay loop instruction sequence pattern, generates delay loop execution information, and generates a delay loop instruction sequence detection signal.

[0061] As described above, the delayed loop instruction sequence is a loop instruction sequence. Therefore, the delayed loop instruction sequence pattern storage device 2121 can be referred to as a loop instruction sequence pattern storage device, which is used to store a loop instruction sequence pattern that defines a loop instruction sequence included in the target program and to be repeatedly executed. The instruction comparator 2123 can sequentially compare the instructions included in the target program with the loop instruction sequence pattern and can generate a loop instruction sequence detection signal indicating that multiple instructions included in the target program match the loop instruction sequence pattern.

[0062] The instruction calculation section 213 includes an instruction execution section 2131 , an elapsed time controller 2132 , and a delay loop instruction sequence elapsed time storage device 2133 .

[0063] The instruction execution section 2131 is connected to the instruction controller 211, and receives an instruction decoding result generated by the instruction decoder 2113. The instruction execution section 2131 executes an instruction included in the target program based on the instruction decoding result.

[0064] The elapsed time controller 2132 generates the simulated elapsed time of executing the instruction included in the target program. For example, the elapsed time controller 2132 obtains information about the number of clock cycles required to execute the instruction from the instruction execution part 2131 and finds the product of the number of clock cycles and the clock period, thereby generating the simulated elapsed time.

[0065] The elapsed time controller 2132 determines when to output the generated simulation elapsed time, and collectively outputs the generated simulation elapsed time to the simulation controller 23 at predetermined intervals. The intervals for outputting the simulation elapsed time can be preset in the simulation apparatus 2. The simulation elapsed time output from the elapsed time controller 2132 is used by the simulation controller 23 to manage the simulation time.

[0066] The delay loop instruction sequence elapsed time storage device 2133 stores the delay loop instruction sequence elapsed time. The delay loop instruction sequence elapsed time is based on the simulation elapsed time required to execute the delay loop instruction sequence once. The delay loop instruction sequence elapsed time can be based on the simulation elapsed time required to execute the delay loop instruction sequence once, and can be the simulation elapsed time required to execute the delay loop instruction sequence once.

[0067] When a delay loop instruction sequence detection signal is generated, the instruction calculation unit 213 may not repeatedly execute the delay loop instruction sequence. Upon receiving the delay loop instruction sequence detection signal, the instruction calculation unit 213 recognizes that the delay loop instruction sequence detection signal is generated by the instruction comparator 2123. When the delay loop instruction sequence detection signal is generated, the instruction execution unit 2131 executes the delay loop instruction sequence once, but does not repeatedly execute the delay loop instruction sequence, that is, does not repeat the remaining M-1 times. The instruction execution unit 2131 obtains M (the number of times the delay loop instruction sequence is repeated) by executing the delay loop instruction sequence once and outputs it to the elapsed time controller 2132.

[0068] When the delay loop instruction sequence detection signal is generated, the elapsed time controller 2132 generates the simulation elapsed time required to repeatedly execute the delay loop instruction sequence M times. Specifically, the elapsed time controller 2132 receives the number of repetitions M from the instruction execution unit 2131. The elapsed time controller 2132 receives the simulation elapsed time required to execute the delay loop instruction sequence once (i.e., the delay loop instruction sequence elapsed time) from the delay loop instruction sequence elapsed time storage device 2133. The elapsed time controller 2132 multiplies the simulation elapsed time required to execute the delay loop instruction sequence once by M to generate the simulation elapsed time required to repeatedly execute the delay loop instruction sequence M times, and outputs the generated simulation elapsed time to the simulation controller 23.

[0069] As described above, each time an instruction is extracted, the PC value is incremented and updated to indicate the address where the next instruction is stored. When the delay loop instruction sequence detection signal is generated, the delay loop instruction sequence is not repeatedly executed. That is, when the instruction execution part 2131 executes the delay loop instruction sequence, a process of branching to the first instruction in the delay loop instruction sequence is usually performed, but the simulation device 2 according to the first embodiment does not perform this process. In other words, the delay loop instruction sequence is not executed, and the PC value is not updated to the address of the branch destination. Therefore, when the delay loop instruction sequence detection signal is generated, the instruction controller 211 does not extract the first instruction in the delay loop instruction sequence, but extracts the next instruction in the delay loop instruction sequence based on the PC value.

[0070] As described above, when the delay loop instruction sequence detection signal is generated, the instruction execution part 2131 executes the delay loop instruction sequence once, and the elapsed time controller 2132 outputs the simulation elapsed time required to execute the delay loop instruction sequence a predetermined number of times (M times) based on the delay loop instruction sequence elapsed time.

[0071] As described above, the delayed loop instruction sequence is a loop instruction sequence. Therefore, the delayed loop instruction sequence elapsed time storage device 2133 can be referred to as a loop instruction sequence elapsed time storage device, which is used to store the loop instruction sequence elapsed time based on the simulated elapsed time required to execute the loop instruction sequence once. When the loop instruction sequence detection signal is generated, the instruction execution unit 2131 can execute the loop instruction sequence once, and the elapsed time controller 2132 can output the simulated elapsed time required to execute the loop instruction sequence a predetermined number of times based on the loop instruction sequence elapsed time.

[0072] The following will refer to Figures 5 to 8 A process of executing instructions included in a target program by the CPU model 21 according to the first embodiment will be described. Figure 5 is a diagram illustrating an example of an order in which multiple instructions including a delay loop instruction sequence are executed. Figures 6 to 8 is a flowchart illustrating an example of the flow of instructions for processing executed by the CPU model 21 according to the first embodiment.

[0073] Figure 5 The diagram shows a plurality of xxx instructions and a plurality of delay loop instruction sequences. Figure 4 The delay loop instruction sequence is executed and the delay loop instruction sequence is repeatedly executed M times (M loops). Figure 5 The instructions are executed in chronological order.

[0074] like Figure 5As shown in FIG, the xxx instruction is executed between time t0 and time t1 and after time t3. The xxx instruction is an instruction other than the instruction in the loop instruction sequence. The CPU model 21 executes the xxx instruction and performs processing for the xxx instruction.

[0075] The period between time t1 and time t3 is a period in which the delay loop instruction sequence is repeatedly executed M times. When the target program is executed on an actual semiconductor device, the delay loop instruction sequence is repeatedly executed throughout the period between time t1 and time t3. However, when the delay loop instruction sequence is detected, the CPU model 21 according to the first embodiment executes the delay loop instruction sequence once between time t1 and time t2, but does not repeatedly execute the delay loop instruction sequence for the remaining M-1 times between time t2 and time t3.

[0076] As described above, the CPU model 21 executes the delay loop instruction sequence and performs processing for the delay loop instruction sequence between time t1 and time t2. In other words, the simulation device 2 executes the instructions included in the target program between time t1 and time t2 to perform simulation. In contrast, the CPU model 21 neither executes the delay loop instruction sequence nor performs processing for the delay loop instruction sequence between time t2 and time t3. In other words, the simulation device 2 does not perform simulation by executing the instructions included in the target program between time t2 and time t3.

[0077] The following will refer to Figures 6 to 8 The detailed description is performed by the CPU model 21 Figure 5 Processing of instructions.

[0078] First, in Figure 5 In the example, xxx instructions are executed sequentially between time t0 and time t1. Figure 6 In step S101, the instruction controller 211 extracts the xxx instruction included in the target program based on the PC value stored in the PC 2111, and stores the extracted xxx instruction in the instruction register 2112. The instruction extraction process is performed so that the PC value is incremented and updated to indicate the address where the next instruction is stored.

[0079] In step S102 , the instruction decoder 2113 decodes the xxx instruction stored in the instruction register 2112 and generates an xxx instruction decoding result, which is output to the loop instruction sequence detector 212 and the instruction calculation section 213 .

[0080] In step S103, the instruction comparator 2123 determines whether the delayed loop instruction sequence is being executed based on the delayed loop execution information. Between time t0 and time t1, no instructions in the loop instruction sequence are included, and no delayed loop execution information is generated. Therefore, the process returns to "No" in step S103 and then proceeds to step S104.

[0081] In step S104, the instruction comparator 2123 compares the xxx instruction decoding result output from the instruction controller 211 with the delay loop instruction sequence pattern and determines whether the delay loop instruction sequence execution process has started. The xxx instruction is not included in the delay loop instruction sequence, and therefore the process proceeds to "No" in step S104 and then proceeds to Figure 7 process.

[0082] exist Figure 7 In step S106 , the instruction execution section 2131 executes the xxx instruction based on the xxx instruction decoding result generated by the instruction decoder 2113 , and performs processing for the xxx instruction.

[0083] In step S107 , the elapsed time controller 2132 generates the simulated elapsed time of executing the xxx instruction.

[0084] In step S108, the elapsed time controller 2132 determines when to output the generated simulation elapsed time to the simulation controller 23. When it is determined that the generated simulation elapsed time is to be output ("Yes" in step S108), the process proceeds to step S109. Conversely, when it is determined that the generated simulation elapsed time is not to be output ("No" in step S108), the elapsed time controller 2132 retains the generated simulation elapsed time to be output at the next timing.

[0085] In step S109, the elapsed time controller 2132 outputs the generated simulation elapsed time to the simulation controller 23. If the simulation elapsed time remains or there is a simulation elapsed time generated at the previous timing, the elapsed time controller 2132 outputs the simulation elapsed time obtained by adding the simulation elapsed time generated at the current timing to the simulation elapsed time generated at the previous timing to the simulation controller 23. In this way, a series of processing for the xxx instruction is completed.

[0086] Next, in Figure 5 The delay loop instruction sequence is executed between time t1 and time t2. Figure 6 In step S101, the instruction controller 211 extracts the ldr instruction included in the target program based on the PC value stored in the PC 2111, and stores the extracted ldr instruction in the instruction register 2112. Figure 5As shown in , the fetched ldr instruction is the first instruction in the delay loop instruction sequence. The instruction fetch process is performed, and thus the PC value is incremented and updated to indicate the address where the next instruction or sub instruction is stored.

[0087] In step S102 , the instruction decoder 2113 decodes the ldr instruction stored in the instruction register 2112 and generates an ldr instruction decoding result, and outputs the ldr instruction decoding result to the loop instruction sequence detector 212 and the instruction calculation part 213 .

[0088] In step S103, the instruction comparator 2123 determines whether the delay loop instruction sequence is being executed based on the delay loop execution information. Since the delay loop execution information is not generated at this time, the process proceeds to "No" in step S103 and then proceeds to step S104.

[0089] In step S104, the instruction comparator 2123 compares the ldr instruction decoding result output from the instruction controller 211 with the delay loop instruction sequence pattern and determines whether the delay loop instruction sequence execution process has started. The ldr instruction is the first instruction included in the delay loop instruction sequence, and therefore the instruction comparator 2123 determines that the delay loop instruction sequence execution process has started ("Yes" in step S104), and the process proceeds to step S105.

[0090] In step S105 , the instruction comparator 2123 generates delay loop execution information. The delay loop execution information includes information indicating that the first ldr instruction in the delay loop instruction sequence is being executed. The instruction comparator 2123 stores the delay loop execution information in the delay loop execution information storage device 2122 .

[0091] exist Figure 7 In step S106 , the instruction execution section 2131 executes the ldr instruction, and performs processing for the ldr instruction based on the ldr instruction decoding result generated by the instruction decoder 2113 .

[0092] In step S107 , the elapsed time controller 2132 generates the simulated elapsed time of executing the ldr instruction.

[0093] The processing in step S108 and step S109 is carried out similarly to the above-mentioned xxx instruction execution processing. In this way, a series of processing for the ldr instruction which is the first instruction in the delay loop instruction sequence is completed.

[0094] After the ldr instruction is executed, the sub instruction is executed. The sub instruction is the second instruction included in the delay loop instruction sequence. Figure 6In step S101, the instruction controller 211 extracts a sub-instruction. In step S102, the instruction decoder 2113 decodes the extracted sub-instruction and generates a sub-instruction decoding result.

[0095] In step S103, the instruction comparator 2123 determines whether the delay loop instruction sequence is being executed based on the delay loop execution information. The delay loop execution information indicating that the delay loop instruction sequence is being executed is stored in the delay loop execution information storage device 2122, and therefore the process proceeds to "Yes" in step S103 and then proceeds to Figure 8 process.

[0096] exist Figure 8 In step S110, the instruction comparator 2123 compares the sub instruction decoding result with the delay loop instruction sequence pattern. Based on the comparison result and the delay loop execution information, the instruction comparator 2123 determines whether the sub instruction is to be executed next in the delay loop instruction sequence. In other words, it is determined here whether the instructions included in the delay loop instruction sequence are being executed in the proper order. The delay loop execution information stored in the delay loop execution information storage device 2122 includes information indicating that the first ldr instruction in the delay loop instruction sequence is being executed, and therefore the instruction comparator 2123 determines that the sub instruction is to be executed next in the delay loop instruction sequence ("Yes" in step S110), and the process proceeds to step S111.

[0097] In step S111, the instruction comparator 2123 compares the sub instruction decoding result with the delay loop instruction sequence pattern and determines whether the delay loop instruction sequence has ended. In other words, it is determined here whether the last instruction included in the delay loop instruction sequence is to be executed. The sub instruction is not the last instruction in the delay loop instruction sequence, and therefore the instruction comparator 2123 determines that the delay loop instruction sequence has not ended ("No" in step S111), and the process proceeds to step S114.

[0098] In step S114, the instruction comparator 2123 updates the delay loop execution information. The instruction comparator 2123 updates the delay loop execution information to information indicating that the second sub instruction in the delay loop instruction sequence is being executed, and stores the updated information in the delay loop execution information storage device 2122. Thereafter, the process proceeds to Figure 7 Implementation Figure 7 and thus completes a series of processing for the sub instruction which is the second instruction in the delay loop instruction sequence.

[0099] The str instruction, ldr instruction, and cmp instruction following the sub instruction are executed similarly to the sub instruction. When the execution process is not carried out in the order of the instructions in the delay loop instruction sequence defined in the delay loop instruction sequence pattern ("No" in step S110), the instruction comparator 2123 determines that the delay loop instruction sequence is not being executed, and deletes the delay loop execution information stored in the delay loop execution information storage device 2122 (step S112).

[0100] The bne instruction, which is the last instruction in the delay loop instruction sequence, is executed similarly to the sub instruction until Figure 8 Step S110. Figure 8 In step S111, instruction comparator 2123 compares the bne instruction decoding result with the delay loop instruction sequence pattern and determines whether the delay loop instruction sequence has ended. The bne instruction is the last instruction in the delay loop instruction sequence, and therefore instruction comparator 2123 determines that the delay loop instruction sequence has ended ("Yes" in step S111), and the process proceeds to step S113.

[0101] In step S113 , the instruction comparator 2123 generates a delay loop instruction sequence detection signal and outputs the generated delay loop instruction sequence detection signal to the instruction calculation unit 213 .

[0102] In step S115 , the instruction comparator 2123 deletes the delayed loop execution information stored in the delayed loop execution information storage device 2122 .

[0103] In step S116, the instruction execution unit 2131 executes the bne instruction and performs processing for the bne instruction based on the bne instruction decoding result and the delay loop instruction sequence detection signal generated by the instruction decoder 2113. The instruction execution unit 2131 receives the delay loop instruction sequence detection signal from the instruction comparator 2123 and recognizes that the delay loop instruction sequence detection signal has been generated. When the delay loop instruction sequence detection signal is generated, the instruction execution unit 2131 performs the same processing as executing the delay loop instruction sequence M times, thereby avoiding repeated execution of the delay loop instruction sequence. In other words, the processing of branching to the first ldr instruction in the delay loop instruction sequence, which is executed in response to the executed bne instruction, is not performed, and the PC value in the PC 2111 is not updated to indicate the address where the first ldr instruction in the delay loop instruction sequence is stored.

[0104] The instruction execution section 2131 outputs M to the elapsed time controller 2132 as the number of repetitions of the delay loop instruction sequence acquired by executing the delay loop instruction sequence once.

[0105] In step S117, the elapsed time controller 2132 generates a simulation elapsed time required to execute the delay loop instruction sequence M times based on the delay loop instruction sequence elapsed time stored in the delay loop instruction sequence elapsed time storage device 2133 and M output from the instruction execution section 2131. The generated simulation elapsed time is output to the simulation controller 23. In this way, Figure 5 The delayed loop instruction sequence execution process is performed between time t1 and time t2.

[0106] As described above, the simulation apparatus 2 according to the first embodiment does not repeatedly execute the delay loop instruction sequence. Figure 5 The delay loop instruction sequence is repeatedly executed M-1 times between time t2 and time t3 according to the program, but the simulation device 2 according to the first embodiment does not repeatedly execute the delay loop instruction sequence M-1 times.

[0107] Finally, in Figure 5 The xxx instruction is executed after time t3 in the instruction controller 211. At time t3, the instruction controller 211 extracts the xxx instruction after the delay loop instruction sequence based on the PC value stored in the PC 2111 (step S101). Subsequent processing is performed similarly to the xxx instruction between time t0 and time t1. Execution includes Figure 5 A series of processing of instructions of the delay loop instruction sequence is carried out in this manner.

[0108] As described above, according to the first embodiment, the loop instruction sequence detector 212 detects a loop instruction sequence included in the target program and generates a loop instruction sequence detection signal. When the loop instruction sequence detection signal is generated, the instruction execution section 2131 executes the loop instruction sequence once. The elapsed time controller 2132 generates a loop instruction sequence that is executed a predetermined number of times (for example, M times). Figure 4 The elapsed time required for simulation of the delay loop instruction sequence.

[0109] As described above, the simulation apparatus 2 according to the first embodiment does not repeatedly execute a loop instruction sequence included in the target program for a predetermined number of times but in which the state of the CPU model 21 does not transition (for example, executing M-1 times of the loop instruction sequence). Figure 4 Therefore, the time for emulation can be further shortened than the time for executing the target program. In other words, the time for software verification operation performed by confirming whether the state of the CPU model 21 is to be transferred can be reduced.

[0110] [Second embodiment]

[0111] A second embodiment will be described. According to the first embodiment, a simulation device for executing a target program including a delay loop instruction sequence as an example of a loop instruction sequence has been described. According to the second embodiment, a simulation device for executing a target program including a polling loop instruction sequence as another example of a loop instruction sequence will be described.

[0112] Figure 9 1 is a block diagram illustrating a configuration example of a simulation device 2a according to the second embodiment. Figure 9 As illustrated in FIG. 2 , the simulation device 2a according to the second embodiment includes a timer model 24 in addition to the components of the simulation device 2 according to the first embodiment. Instead of the CPU model 21, a CPU model 21a is provided.

[0113] A timer is included in the semiconductor device on which the target program operates, and the timer is modeled as the timer model 24. That is, the timer in the semiconductor device is simulated by the timer model 24.

[0114] The timer model 24 is a slave model that operates in response to instructions from the CPU model 21a, which serves as the master model. The timer model 24 has a status flag (F). The timer model 24 starts measuring time in response to instructions from the CPU model 21a and can change the status flag after a preset time has passed. For example, if the status flag is initially 0, it changes from 0 to 1 after a preset time has passed.

[0115] Next, the CPU model 21a will be described. Figure 10 2 is a block diagram illustrating a configuration example of a CPU model 21a according to the second embodiment. Figure 10 As illustrated in FIG, the loop instruction sequence detector 212 and the instruction calculation section 213 in the CPU model 21 according to the first embodiment are replaced by the loop instruction sequence detector 212a and the instruction calculation section 213a in the CPU model 21a according to the second embodiment, respectively.

[0116] The loop instruction sequence detector 212a includes an instruction comparator 2123, a polling loop instruction sequence pattern storage device 2124, and a polling loop execution information storage device 2125. The loop instruction sequence detector 212a according to the second embodiment can detect a polling loop instruction sequence included in a target program using the polling loop instruction sequence pattern storage device 2124, the polling loop execution information storage device 2125, and the instruction comparator 2123.

[0117] The poll loop instruction sequence is an exemplary loop instruction sequence similar to the delay loop instruction sequence. Loop processing using the poll loop instruction sequence is referred to as a poll loop in this disclosure. Figure 11FIG is a diagram illustrating an example of a polling loop instruction sequence. Figure 11 As shown in FIG, the polling loop instruction sequence includes an ldrh instruction, a tst instruction, and a beq instruction. The polling loop instruction sequence is executed in time order from the ldrh instruction to the beq instruction.

[0118] The ldrh instruction reads a value from memory, changes its bit width, and stores the changed value in a general-purpose register in the CPU. The tst instruction checks whether the value is 0. If the value is 0, it sets the flag in the CPU status register to 1, and if the value is not 0, it sets the flag in the CPU status register to 0. The beq instruction branches to a predetermined instruction when the flag in the CPU status register is 1.

[0119] The following describes the use of Figure 11 The operation of the polling loop is implemented by the polling loop instruction sequence. First, the ldrh instruction is used to read the status flag of the slave device and change the bit width of the status flag to store the status flag in the general register in the CPU. Next, the tst instruction is used to confirm whether the value of the status flag is 0. When the status flag of the slave device is 0 in the initial state, the flag of the status register in the CPU is set to 1. Next, the beq instruction is used. Since the flag of the status register in the CPU is 1, the processing branches to the first ldrh instruction, and Figure 11 The polling loop instruction sequence is completed once.

[0120] The polling loop instruction sequence is repeatedly executed until the status flag of the slave device changes from 0 to 1. When the status flag of the slave device changes to 1, the flag of the status register in the CPU is set to 0 using the tst instruction. Consequently, the beq instruction is executed, preventing processing from branching to the first ldrh instruction and exiting the loop executing the polling loop instruction sequence. As described above, the polling loop instruction sequence includes an instruction for confirming the status flag of the slave device, and the polling loop instruction sequence is repeatedly executed until a change in the status flag is confirmed.

[0121] return Figure 10 The configuration of the CPU model 21a will be described later. The polling loop instruction sequence pattern storage device 2124 stores a polling loop instruction sequence pattern that defines a polling loop instruction sequence included in the target program and to be repeatedly executed. As described above, the polling loop instruction sequence is a loop instruction sequence, and therefore the polling loop instruction sequence pattern storage device 2124 can be referred to as a loop instruction sequence pattern storage device for storing a loop instruction sequence pattern that defines a loop instruction sequence included in the target program and to be repeatedly executed.

[0122] The polling loop sequence mode includes information about the types of instructions that configure the polling loop sequence and the order in which the instructions are executed. Figure 11 In the example of FIG. 1 , the polling loop instruction sequence mode includes information indicating that the polling loop instruction sequence is configured by an ldrh instruction, a tst instruction, and a beq instruction and that instructions are executed in this order.

[0123] The polling loop execution information storage device 2125 stores polling loop execution information about the polling loop instruction sequence being executed. The polling loop execution information includes information indicating whether the CPU model 21a is executing an instruction in the polling loop instruction sequence, information indicating which instruction in the polling loop instruction sequence is being executed when the polling loop instruction sequence is being executed, and the like.

[0124] The instruction comparator 2123 sequentially compares the instructions included in the target program with the polling loop instruction sequence pattern and generates a polling loop instruction sequence detection signal indicating that the plurality of instructions included in the target program match the polling loop instruction sequence pattern. The polling loop instruction sequence detection signal generated by the instruction comparator 2123 is output to the instruction calculation section 213a.

[0125] Specifically, the instruction comparator 2123 sequentially receives the instruction decoding results output from the instruction controller 211. The instruction comparator 2123 also receives the polling cycle instruction sequence pattern stored in the polling cycle instruction sequence pattern storage device 2124. The instruction comparator 2123 sequentially compares the instruction decoding results with the polling cycle instruction sequence pattern in the order in which it receives the instruction decoding results.

[0126] When it is detected that the compared instruction matches the first instruction in the polling loop instruction sequence defined in the polling loop instruction sequence pattern, the instruction comparator 2123 generates polling loop execution information and stores it in the polling loop execution information storage device 2125. The polling loop execution information includes information indicating that the polling loop instruction sequence is being executed and information indicating that the first instruction in the polling loop instruction sequence is being executed.

[0127] When the instruction to be compared is detected to match the second instruction in the polling loop instruction sequence defined in the polling loop instruction sequence pattern, the instruction comparator 2123 updates the polling loop execution information to information indicating that the second instruction in the polling loop instruction sequence is being executed. Conversely, when the instruction to be compared is not detected to match the second instruction in the polling loop instruction sequence defined in the polling loop instruction sequence pattern, the instruction comparator 2123 deletes the polling loop execution information stored in the polling loop execution information storage device 2125.

[0128] As described above, when comparison processing is performed on multiple instructions and it is then detected that the compared multiple instructions match the polling loop instruction sequence defined in the polling loop instruction sequence pattern, the instruction comparator 2123 generates a polling loop instruction sequence detection signal and deletes the polling loop execution information stored in the polling loop execution information storage device 2125.

[0129] For example, for Figure 11 The polling loop instruction sequence, the instruction comparator 2123 follows Figure 11 The instruction comparator 2123 continuously receives decoding results of the ldrh instruction to the beq instruction in the order of 1. The instruction comparator 2123 generates polling loop execution information based on the comparison processing result of the first ldrh instruction, then updates the polling loop execution information based on the comparison processing result of the tst instruction, and finally generates a polling loop instruction sequence detection signal based on the comparison processing result of the third beq instruction.

[0130] When the target program includes multiple polling loop instruction sequences, the polling loop instruction sequence pattern storage device 2124 may store multiple polling loop instruction sequence patterns. In this case, for each polling loop instruction sequence, the instruction comparator 2123 compares the instruction with the polling loop instruction sequence pattern, generates polling loop execution information, and generates a polling loop instruction sequence detection signal.

[0131] The instruction calculation section 213 a includes an instruction execution section 2131 , an elapsed time controller 2132 , and a polling loop instruction sequence elapsed time storage device 2134 .

[0132] The polling loop instruction sequence elapsed time storage device 2134 stores the polling loop instruction sequence elapsed time. The polling loop instruction sequence elapsed time is the simulated elapsed time required to execute the polling loop instruction sequence N times. In other words, the polling loop instruction sequence elapsed time is N times the simulated elapsed time required to execute the polling loop instruction sequence once. N is a natural number of 2 or greater. As described above, the polling loop instruction sequence is a cyclic instruction sequence, and therefore the polling loop instruction sequence elapsed time storage device 2134 can be referred to as a cyclic instruction sequence elapsed time storage device, which is used to store the cyclic instruction sequence elapsed time based on the simulated elapsed time required to execute the cyclic instruction sequence once.

[0133] When receiving the polling cycle instruction sequence detection signal, the instruction calculation section 213a confirms that the polling cycle instruction sequence detection signal has been generated by the instruction comparator 2123. When the polling cycle instruction sequence detection signal is generated, the instruction calculation section 213a operates differently depending on whether the status flag of the timer model 24 changes.

[0134] When a polling loop instruction sequence detection signal is generated, the instruction execution unit 2131 executes the polling loop instruction sequence once. If a change in the status flag is not confirmed after executing the instruction to confirm the status flag, the instruction execution unit 2131 generates a control signal for branching to the first instruction in the polling loop instruction sequence and outputs it to the instruction controller 211. In response to the control signal, the instruction controller 211 updates the PC value stored in the PC 2111 to the address indicating the address where the first instruction in the polling loop instruction sequence is stored, and extracts the first instruction in the polling loop instruction sequence based on the updated PC value. The elapsed time controller 2132 generates the simulation elapsed time required to repeatedly execute the polling loop instruction sequence N times based on the polling loop instruction sequence elapsed time stored in the polling loop instruction sequence elapsed time storage device 2134, and outputs it to the simulation controller 23.

[0135] Conversely, if the status flag is confirmed to have changed after executing the instruction for confirming the status flag, the instruction execution section 2131 does not generate a control signal for branching to the first instruction in the polling loop instruction sequence. When no control signal is generated, the process exits the loop for executing the polling loop instruction sequence. In this case, the instruction controller 211 extracts the next instruction in the polling loop instruction sequence based on the PC value stored in PC 2111, rather than extracting the first instruction in the polling loop instruction sequence. The elapsed time controller 2132 does not generate a simulated elapsed time for executing the polling loop instruction sequence.

[0136] As described above, when the polling loop instruction sequence detection signal is generated, the instruction execution section 2131 executes the polling loop instruction sequence once, and the elapsed time controller 2132 outputs the simulated elapsed time required to execute the polling loop instruction sequence a predetermined number of times (N times) based on the polling loop instruction sequence elapsed time. In particular, when a change in the status flag is not confirmed after executing the polling loop instruction sequence once, the instruction execution section 2131 does not execute the polling loop instruction sequence N-1 times, and the elapsed time controller 2132 generates a simulated elapsed time required to repeatedly execute the polling loop instruction sequence N times, which is N times the simulated elapsed time required to execute the polling loop instruction sequence once.

[0137] The following will refer to Figures 12 to 14 A process in which the CPU model 21 a according to the second embodiment executes instructions included in a target program will be described. Figure 12 is a diagram illustrating an example order of executing multiple instructions comprising a polling loop instruction sequence. Figure 13 and Figure 14 is a flowchart illustrating an example of the flow of instruction execution processing of the CPU model 21 a according to the second embodiment.

[0138] Figure 12 The diagram shows a plurality of xxx instructions, aaa instructions and a plurality of polling loop instruction sequences. The aaa instruction is a state flag change instruction used to cause the timer model 24 to change the state flag of the timer model 24 when the state of the timer model 24 transitions. The state flag change instruction is executed before executing the polling loop instruction sequence. Figure 11 The polling loop instruction sequence is executed in chronological order. Figure 12 instructions.

[0139] like Figure 12 As shown in FIG, the xxx instruction is executed between time t0 and time t1, between time t2 and time t3, and after time t9. Figure 5 is similarly executed.

[0140] The polling loop instruction sequence is repeatedly executed between time t3 and time t9. The CPU model 21a implements the polling loop instruction sequence execution process between time t3 and time t4, between time t5 and time t6, and between time t8 and time t9. In other words, the simulation device 2a simulates by executing the instructions included in the target program in each time period. On the contrary, the CPU model 21a does not implement the polling loop instruction sequence execution process between time t4 and time t5, and between time t6 and time t8. In other words, the simulation device 2a does not simulate by executing the instructions included in the target program in each time period.

[0141] Assume that when the target program is executed on an actual semiconductor device, the polling loop instruction sequence is executed N-1 times in each of the periods between time t4 and time t5 and between time t6 and time t8. The polling loop instruction sequence is executed once in each of the periods between time t3 and time t4 and between time t5 and time t6. Therefore, the polling loop instruction sequence is executed N times (N loops) in each of the periods between time t3 and time t5 and between time t5 and time t8.

[0142] The CPU model 21a executes the aaa instruction between time t1 and time t2. It is assumed here that the initial value of the status flag (F) of the timer model 24 is 0, and in response to the aaa instruction, the timer model 24 changes the status flag from 0 to 1 at time t7. Figure 12 In the example of , the CPU model 21 a does not confirm the status flag change between time t3 and time t4 and between time t5 and time t6 , but confirms the status flag change between time t8 and time t9 .

[0143] The following will refer to Figure 13 and Figure 14Detailed description of the CPU model 21a execution Figure 12 Processing of instructions.

[0144] First, in Figure 12 The xxx instruction is executed between time t0 and time t1 in the embodiment. The xxx instruction is executed similarly to the first embodiment.

[0145] Next, in Figure 12 The aaa instruction is executed between time t1 and time t2 in the example. The aaa instruction is executed similarly to the xxx instruction, but the aaa instruction is a status flag change instruction, and the CPU model 21a executes the aaa instruction (status flag change instruction), thereby instructing the timer model 24 to change the status flag. The timer model 24 starts measuring time in response to the status flag change instruction.

[0146] Next, in Figure 12 The xxx instruction is executed between time t2 and time t3 in the embodiment 1. The xxx instruction is executed similarly to the instruction in the first embodiment.

[0147] Next, in Figure 12 The polling loop instruction sequence is executed between time t3 and time t4. Figure 13 In step S101, the instruction controller 211 extracts the ldrh instruction as the first instruction in the polling loop instruction sequence. In step S102, the instruction decoder 2113 decodes the extracted ldrh instruction and generates a ldrh instruction decoding result.

[0148] In step S201, the instruction comparator 2123 determines whether the polling loop instruction sequence is being executed based on the polling loop execution information. The polling loop execution information has not yet been generated, and therefore the process proceeds to "No" in step S201 and then proceeds to step S202.

[0149] In step S202, the instruction comparator 2123 compares the ldrh instruction decoding result output from the instruction controller 211 with the polling loop instruction sequence pattern and determines whether the polling loop instruction sequence execution process has started. The ldrh instruction is the first instruction included in the polling loop instruction sequence, and therefore the instruction comparator 2123 determines that the polling loop instruction sequence execution process has started ("Yes" in step S202), and the process proceeds to step S203.

[0150] In step S203 , the instruction comparator 2123 generates polling loop execution information. The polling loop execution information includes information indicating that the first ldrh instruction in the polling loop instruction sequence is being executed. The instruction comparator 2123 stores the polling loop execution information in the polling loop execution information storage device 2125 .

[0151] In the first embodiment Figure 7 The processing after step S203 is illustrated in the flowchart of . In this way, a series of processing for the ldrh instruction as the first instruction in the polling loop instruction sequence is completed.

[0152] The tst instruction execution process is executed after the ldrh instruction execution process. The tst instruction is the second instruction included in the polling loop instruction sequence. Figure 13 In step S101, the instruction controller 211 extracts the tst instruction. In step S102, the instruction decoder 2113 decodes the extracted tst instruction and generates a tst instruction decoding result.

[0153] In step S201, the instruction comparator 2123 determines whether the polling loop instruction sequence is being executed based on the polling loop execution information. The polling loop execution information indicating that the polling loop instruction sequence is being executed is stored in the polling loop execution information storage device 2125, and therefore the process proceeds to "Yes" in step S201 and then proceeds to Figure 14 process.

[0154] exist Figure 14 In step S204, the instruction comparator 2123 compares the tst instruction decoding result with the polling loop instruction sequence pattern. Based on the comparison result and the polling loop execution information, the instruction comparator 2123 determines whether the tst instruction is to be executed next in the polling loop instruction sequence. In other words, it is determined here whether the instructions included in the polling loop instruction sequence are being executed in the proper order. The polling loop execution information stored in the polling loop execution information storage device 2125 includes information indicating that the first ldrh instruction in the polling loop instruction sequence is being executed, and therefore the instruction comparator 2123 determines that the tst instruction is to be executed next in the polling loop instruction sequence ("Yes" in step S204), and the process proceeds to step S205.

[0155] In step S205, the instruction comparator 2123 compares the tst instruction decoding result with the polling loop instruction sequence pattern and determines whether the polling loop instruction sequence has ended. In other words, it is determined here whether the last instruction included in the polling loop instruction sequence is to be executed. The tst instruction is not the last instruction in the polling loop instruction sequence, and therefore the instruction comparator 2123 determines that the polling loop instruction sequence has not ended ("No" in step S205), and the process continues to step S208.

[0156] In step S208, the instruction comparator 2123 updates the polling loop execution information. The tst instruction is the second instruction included in the polling loop instruction sequence, and therefore the instruction comparator 2123 updates the polling loop execution information to information indicating that the second tst instruction in the polling loop instruction sequence is being executed, and stores the updated information in the polling loop execution information storage device 2125. The process then proceeds to Figure 7 process.

[0157] exist Figure 7 In step S106, it is confirmed that the tst instruction has been executed, and the status flag of the timer model 24 is not changed and remains at the initial value 0. The processing in and after step S107 is carried out, and then a series of processing for the tst instruction as the second instruction in the polling loop instruction sequence is completed.

[0158] When the execution processing is not carried out in accordance with the order of instructions in the polling loop instruction sequence defined in the polling loop instruction sequence mode ("No" in step S204), the instruction comparator 2123 determines that the polling loop instruction sequence is not being executed, and deletes the polling loop execution information stored in the polling loop execution information storage device 2125 (step S206).

[0159] The execution of the beq instruction as the last instruction in the polling loop instruction sequence is the same as Figure 14 The tst instruction of step S204 is similarly executed. In step S205, the instruction comparator 2123 compares the beq instruction decoding result with the polling loop instruction sequence pattern and determines whether the polling loop instruction sequence has ended. The beq instruction is the last instruction in the polling loop instruction sequence, and therefore the instruction comparator 2123 determines that the polling loop instruction sequence has ended ("Yes" in step S205), and the process proceeds to step S207.

[0160] In step S207, the command comparator 2123 generates a polling cycle command sequence detection signal and outputs the generated polling cycle command sequence detection signal to the command calculation section 213a.

[0161] In step S209 , the instruction comparator 2123 deletes the polling loop execution information stored in the polling loop execution information storage device 2125 .

[0162] In step S210 , the instruction execution section 2131 executes the beq instruction based on the beq instruction decoding result generated by the instruction decoder 2113 and the polling loop instruction sequence detection signal.

[0163] In step S211, when processing for the beq instruction is executed, it is determined whether the status flag of the timer model 24 has changed. It is not confirmed that the status flag of the timer model 24 has changed ("No" in step S211), and thus the process proceeds to step S212.

[0164] In step S212, the instruction execution section 2131 generates a control signal for branching to the first instruction in the polling loop instruction sequence. In response to the control signal, the instruction controller 211 updates the PC value stored in the PC 2111 to indicate the address where the ldrh instruction in the polling loop instruction sequence is stored.

[0165] In step S213, the elapsed time controller 2132 generates a simulation elapsed time required to repeatedly execute the polling loop instruction sequence N times based on the polling loop instruction sequence elapsed time, and outputs it to the simulation controller 23. In this way, a series of processes for the beq instruction, which is the last instruction in the polling loop instruction sequence, are completed.

[0166] As mentioned above, in Figure 12 Between time t4 and time t5, the simulation device 2a according to the second embodiment does not repeatedly execute the polling loop instruction sequence. That is, normally, according to the program, the polling loop instruction sequence is repeatedly executed N-1 times, but the simulation device 2a according to the second embodiment does not repeatedly execute the polling loop instruction sequence N-1 times.

[0167] Next, in Figure 12 The polling loop instruction sequence is executed again between time t5 and time t6 in the example. However, the status flag of the timer model 24 remains unchanged, and therefore the polling loop instruction sequence execution process between time t5 and time t6 is the same as the polling loop instruction sequence execution process between time t3 and time t4.

[0168] CPU model 21a in Figure 12 The polling loop instruction sequence execution process is not performed between time t6 and time t8, similar to the period between time t4 and time t5. Therefore, the timer model 24 changes the status flag from 0 to 1 at time t7 when the preset time has elapsed, but the CPU model 21a cannot confirm the change in the status flag between time t6 and time t8.

[0169] Later, in Figure 12 The polling loop instruction sequence is executed again between time t8 and time t9 in the CPU model 21a. The CPU model 21a can confirm that the status flag of the timer model 24 has changed between time t8 and time t9, and thus Figure 14In the processing in and after step S211 , the polling loop instruction sequence execution processing between time t8 and time t9 is different from the polling loop instruction sequence execution processing between time t3 and time t4 .

[0170] In step S211, if it is confirmed that the status flag of the timer model 24 has changed ("Yes" in step S211), the beq instruction execution process is completed, and the process exits the loop of executing the polling loop instruction sequence. In this case, the control signal for branching to the first instruction in the polling loop instruction sequence is not generated, and the PC value stored in PC 2111 is not updated.

[0171] Finally, in Figure 12 Execute the xxx instruction after time t9 in the command controller 211. At time t9, the command controller 211 extracts the xxx instruction after the polling loop instruction sequence based on the PC value stored in the PC 2111 (step S101). Subsequent execution processing is similar to the xxx instruction between time t0 and time t1. Execution includes Figure 12 A series of processing of the instructions of the polling loop instruction sequence is carried out in this manner.

[0172] As described above, according to the second embodiment, the loop instruction sequence detector 212a detects a loop instruction sequence included in the target program and generates a loop instruction sequence detection signal. When the loop instruction sequence detection signal is generated, the instruction execution section 2131 executes the loop instruction sequence once. The elapsed time controller 2132 generates a loop instruction sequence that is executed a predetermined number of times (for example, N times). Figure 11 The simulation elapsed time required for the polling loop instruction sequence).

[0173] As described above, the simulation apparatus 2a according to the second embodiment does not repeatedly execute a loop instruction sequence included in the target program a predetermined number of times but in which the state of the CPU model 21a does not transition (for example, executing N-1 times). Figure 11 Therefore, the simulation device 2a according to the second embodiment can achieve similar effects to the simulation device 2 according to the first embodiment.

[0174] In the second embodiment, an example of the dependent model is the timer model 24, but it is not limited thereto. For example, the memory model 22 having a predetermined state flag can be used as the dependent model.

[0175] [Third embodiment]

[0176] A third embodiment will be described. A target program may include a delay loop instruction sequence and a polling loop instruction sequence. A simulation apparatus for executing a target program including both a delay loop instruction sequence and a polling loop instruction sequence will be described according to the third embodiment.

[0177] The simulation device according to the third embodiment includes a CPU model 21b, a memory model 22, a simulation controller 23, and a timer model 24. That is, the simulation device according to the third embodiment is different from the simulation device according to the embodiment. Figure 9 The simulation device 2a of the second embodiment is different in that a CPU model 21b is provided instead of the CPU model 21a.

[0178] The CPU model 21b will be described below. Figure 15 2 is a block diagram illustrating a configuration example of a CPU model 21b according to the third embodiment. Figure 15 As illustrated in FIG. 2 , the CPU model 21 b according to the third embodiment includes an instruction controller 211 , a loop instruction sequence detector 212 b , and an instruction calculation section 213 b .

[0179] The loop instruction sequence detector 212b includes a delayed loop instruction sequence pattern storage device 2121, a delayed loop execution information storage device 2122, an instruction comparator 2123, a polling loop instruction sequence pattern storage device 2124, and a polling loop execution information storage device 2125. That is, the loop instruction sequence detector 212b according to the third embodiment is configured by combining the loop instruction sequence detector 212 according to the first embodiment and the loop instruction sequence detector 212a according to the second embodiment. Therefore, the loop instruction sequence detector 212b can detect delayed loop instruction sequences and polling loop instruction sequences, and can generate delayed loop instruction sequence detection signals and polling loop instruction sequence detection signals.

[0180] The instruction calculation section 213b includes an instruction execution section 2131, an elapsed time controller 2132, a delayed loop instruction sequence elapsed time storage device 2133, and a polling loop instruction sequence elapsed time storage device 2134. That is, the instruction calculation section 213b according to the third embodiment is configured by combining the instruction calculation section 213 according to the first embodiment and the instruction calculation section 213a according to the second embodiment. Therefore, the elapsed time controller 2132 can generate a simulated elapsed time for each of the delayed loop instruction sequence detection signal and the polling loop instruction sequence detection signal.

[0181] Figure 16 1 is a flowchart illustrating an exemplary flow of instruction execution processing of the CPU model 21b according to the third embodiment. Figure 16 As illustrated in , the flowchart according to the third embodiment includes a step of delaying a loop instruction sequence and a step of polling a loop instruction sequence.

[0182] exist Figure 16In the example, the steps for the delay loop instruction sequence correspond to step S103 of determining whether the delay loop instruction sequence is being executed, step S104 of determining whether the delay loop instruction sequence execution process has started, and step S105 of generating delay loop execution information. Therefore, when the delay loop instruction sequence is being executed, after the processes in steps S101 and S102, the process proceeds from step S103 to step B, and then executes Figure 8 When the delay loop instruction sequence execution process has started, after the processes in steps S101, S102, S103 and S201, the process proceeds to A via steps S104 and S105, and then executes Figure 7 The processing in the flowchart.

[0183] On the contrary, Figure 16 In the example, the steps for the polling loop instruction sequence correspond to step S201 of determining whether the polling loop instruction sequence is being executed, step S202 of determining whether the polling loop instruction sequence execution process has started, and step S203 of generating the polling loop execution information. Therefore, when the polling loop instruction sequence is being executed, after the processing in steps S101, S102, and S103, the processing proceeds from step S201 to step C, and then executes Figure 14 When the polling loop instruction sequence execution process has started, after the processes in steps S101, S102, S103, S201 and S104, the process proceeds to A via steps S202 and S203, and then executes Figure 7 The processing in the flowchart.

[0184] As described above, the simulation device according to the third embodiment can handle both the delay loop instruction sequence and the polling loop instruction sequence. Therefore, the simulation device 2b according to the third embodiment can achieve similar effects to the simulation device 2 according to the first embodiment and the simulation device 2a according to the second embodiment.

Claims

1. A simulation device comprising a CPU model, The CPU models include: An instruction controller, the instruction controller comprising an instruction decoder, the instruction decoder being configured to decode instructions included in the program to be simulated and generate a decoding result; a loop instruction sequence detector, the loop instruction sequence detector comprising a loop instruction sequence pattern storage device and an instruction comparator, the loop instruction sequence pattern storage device being configured to store a loop instruction sequence pattern defining a loop instruction sequence to be repeatedly executed, the instruction comparator being configured to sequentially compare instructions included in the program to be simulated with the loop instruction sequence pattern, and generate a loop instruction sequence detection signal, the loop instruction sequence detection signal indicating that a plurality of instructions included in the program to be simulated match the loop instruction sequence pattern; as well as an instruction calculation section, the instruction calculation section comprising: an instruction execution section configured to execute instructions included in the program to be simulated according to the decoding result; an elapsed time controller configured to output a simulation elapsed time of the instruction execution section executing the instructions included in the program to be simulated; and a loop instruction sequence elapsed time storage device configured to store a loop instruction sequence elapsed time based on a simulation elapsed time required to execute the loop instruction sequence once; and Wherein, when the loop instruction sequence detection signal is generated, The instruction execution portion executes the loop instruction sequence once, and The elapsed time controller generates a simulation elapsed time required to execute the loop instruction sequence a predetermined number of times based on the loop instruction sequence elapsed time.

2. The simulation device according to claim 1, The loop instruction sequence is a delayed loop instruction sequence to be repeatedly executed M times, wherein the loop instruction sequence detection signal is a delayed loop instruction sequence detection signal, in, When the delayed loop instruction sequence detection signal is generated, The instruction execution portion does not execute the delay loop instruction sequence M-1 times, and The elapsed time controller generates a simulated elapsed time required to repeatedly execute the delay loop instruction sequence M times, the simulated elapsed time being M times the simulated elapsed time required to execute the delay loop instruction sequence once, and Wherein M is a natural number of 2 or greater.

3. The simulation device according to claim 2, The instruction controller further includes a program counter configured to store a program counter value used to extract instructions included in the program to be simulated, and in, When the delay loop instruction sequence detection signal is generated, the instruction controller fetches a next instruction in the delay loop instruction sequence according to the program counter value.

4. The simulation device according to claim 2, wherein the loop instruction sequence elapsed time is a delayed loop instruction sequence elapsed time, and The delay loop instruction sequence elapsed time is the simulation elapsed time required to execute the delay loop instruction sequence once.

5. The simulation apparatus according to claim 2, wherein the instruction execution section outputs M to the elapsed time controller as the number of times the delay loop instruction sequence is repeatedly executed obtained by executing the delay loop instruction sequence once.

6. The simulation apparatus according to claim 1, further comprising a slave model having a status flag, wherein the loop instruction sequence is a polling loop instruction sequence including instructions for confirming the status flag, and is repeatedly executed until it is confirmed that the status flag has changed, wherein when the state of the slave model is transferred before executing the polling loop instruction sequence, the instruction execution section executes a state flag change instruction to cause the slave model to change the state flag, and in, When the status flag change is not confirmed after executing the polling loop instruction sequence, The instruction execution portion does not execute the polling loop instruction sequence N-1 times, and The elapsed time controller generates a simulated elapsed time required to repeatedly execute the polling loop instruction sequence N times, the simulated elapsed time being N times the simulated elapsed time required to execute the polling loop instruction sequence once, and Where N is a natural number of 2 or greater.

7. The simulation device according to claim 6, The instruction controller further comprises a program counter configured to store a program counter value used to extract instructions included in the program to be simulated, and in, When the status flag change is not confirmed after executing the polling loop instruction sequence, the instruction controller fetches a first instruction in the polling loop instruction sequence according to the program counter value.

8. The simulation device according to claim 7, wherein: When it is confirmed that the status flag has changed after executing the polling loop instruction sequence, the instruction controller fetches the next instruction in the polling loop instruction sequence according to the program counter value.

9. The simulation device according to claim 6, The loop instruction sequence elapsed time is the polling loop instruction sequence elapsed time, and The polling loop instruction sequence elapsed time is the simulation elapsed time required to execute the polling loop instruction sequence N times.

10. The simulation device according to claim 2, further comprising a slave model having a status flag, wherein the loop instruction sequence mode is a delayed loop instruction sequence mode, wherein the loop instruction sequence pattern storage device is a delayed loop instruction sequence pattern storage device configured to store the delayed loop instruction sequence pattern, The loop instruction sequence elapsed time is the delayed loop instruction sequence elapsed time, wherein the loop instruction sequence elapsed time storage device is a delayed loop instruction sequence elapsed time storage device configured to store the elapsed time of the delayed loop instruction sequence, The cyclic instruction sequence detector further comprises a polling cyclic instruction sequence pattern storage device, wherein the polling cyclic instruction sequence pattern storage device is configured to store a polling cyclic instruction sequence pattern defining a polling cyclic instruction sequence to be repeatedly executed. wherein the instruction comparator outputs a polling cycle instruction sequence detection signal, wherein the polling cycle instruction sequence detection signal indicates that a plurality of instructions included in the program to be simulated match the polling cycle instruction sequence pattern; The instruction calculation part further includes a polling cycle instruction sequence elapsed time storage device, wherein the polling cycle instruction sequence elapsed time storage device is configured to store the polling cycle instruction sequence elapsed time based on the simulation elapsed time required to execute the polling cycle instruction sequence once. wherein the polling loop instruction sequence is a loop instruction sequence including instructions for confirming the status flag, and is repeatedly executed until it is confirmed that the status flag has changed, in, When the state of the slave model is transferred before executing the polling loop instruction sequence, the instruction execution section executes a state flag change instruction to cause the slave model to change the state flag. When the polling cycle instruction sequence detection signal is generated, the instruction execution part executes the polling cycle instruction sequence once. Wherein, when the status flag is not confirmed to have changed after executing the polling loop instruction sequence, The instruction execution portion does not execute the polling loop instruction sequence N-1 times, and The elapsed time controller outputs a simulated elapsed time required to repeatedly execute the polling loop instruction sequence N times, the simulated elapsed time being N times the simulated elapsed time required to execute the polling loop instruction sequence once, and Where N is a natural number of 2 or greater.

11. A simulation method performed by a simulation device, the simulation device comprising a CPU model, the CPU model comprising a loop instruction sequence pattern storage device and a loop instruction sequence elapsed time storage device, the simulation method causing the CPU model to: Decoding instructions included in the program to be simulated and generating a decoding result; storing a loop instruction sequence pattern defining a loop instruction sequence to be repeatedly executed in the loop instruction sequence pattern storage device; Comparing the instructions included in the program to be simulated with the cyclic instruction sequence pattern in sequence and generating a cyclic instruction sequence detection signal, wherein the cyclic instruction sequence detection signal indicates that a plurality of instructions included in the program to be simulated matches the cyclic instruction sequence pattern; Executing instructions included in the program to be simulated according to the decoding result; Outputting the simulation elapsed time of executing the instructions included in the program to be simulated; storing a loop instruction sequence elapsed time based on a simulation elapsed time required to execute the loop instruction sequence once in the loop instruction sequence elapsed time storage device; as well as When the loop instruction sequence detection signal is generated, the loop instruction sequence is executed once, and a simulation elapsed time required to execute the loop instruction sequence a predetermined number of times is output based on the loop instruction sequence elapsed time.

12. The simulation method according to claim 11, The loop instruction sequence is a delayed loop instruction sequence to be repeatedly executed M times, The simulation method further causes the CPU model to not execute the delayed loop instruction sequence M-1 times when the loop instruction sequence detection signal is generated, and outputs a simulation elapsed time required to repeatedly execute the delayed loop instruction sequence M times, where the simulation elapsed time is M times the simulation elapsed time required to execute the delayed loop instruction sequence once. Wherein M is a natural number of 2 or greater.

13. The simulation method according to claim 12, wherein the CPU model further comprises a program counter, wherein the program counter is configured to store a program counter value used to extract instructions included in the program to be simulated, The simulation method further enables the CPU model to extract the next instruction in the delayed loop instruction sequence according to the program counter value when the loop instruction sequence detection signal is generated.

14. The simulation method according to claim 11, The simulation device further comprises a slave model having a status flag, wherein the loop instruction sequence is a polling loop instruction sequence including instructions for confirming the status flag, and is repeatedly executed until it is confirmed that the status flag has changed, The simulation method further enables the CPU model to: When the state of the slave model is transferred before executing the polling loop instruction sequence, executing a state flag change instruction to cause the slave model to change the state flag; and When the change of the status flag is not confirmed after executing the polling loop instruction sequence, the polling loop instruction sequence is not executed N-1 times, and a simulation elapsed time required to repeatedly execute the polling loop instruction sequence N times is output, the simulation elapsed time being N times the simulation elapsed time required to execute the polling loop instruction sequence once; and Where N is a natural number of 2 or greater.

15. The simulation method according to claim 14, The CPU model further includes a program counter configured to store a program counter value used to extract instructions included in the program to be simulated. The simulation method further enables the CPU model to extract the first instruction in the polling loop instruction sequence according to the program counter value when the CPU model does not confirm the change of the status flag after executing the polling loop instruction sequence.

16. A non-transitory computer-readable medium storing a program for causing a simulation device to execute a simulation method, the simulation device comprising a CPU model, the CPU model comprising a loop instruction sequence pattern storage device and a loop instruction sequence elapsed time storage device, the simulation method causing the CPU model to: Decoding instructions included in the program to be simulated and generating a decoding result; storing a loop instruction sequence pattern defining a loop instruction sequence to be repeatedly executed in the loop instruction sequence pattern storage device; Comparing the instructions included in the program to be simulated with the cyclic instruction sequence pattern in sequence and generating a cyclic instruction sequence detection signal, wherein the cyclic instruction sequence detection signal indicates that a plurality of instructions included in the program to be simulated matches the cyclic instruction sequence pattern; Executing instructions included in the program to be simulated according to the decoding result; Outputting the simulation elapsed time of executing the instructions included in the program to be simulated; storing a loop instruction sequence elapsed time based on a simulation elapsed time required to execute the loop instruction sequence once in the loop instruction sequence elapsed time storage device; as well as When the loop instruction sequence detection signal is generated, the loop instruction sequence is executed once, and a simulation elapsed time required to execute the loop instruction sequence a predetermined number of times is output based on the loop instruction sequence elapsed time.

17. The non-transitory computer readable medium of claim 16, wherein the loop instruction sequence is a delayed loop instruction sequence to be repeatedly executed M times, and wherein the simulation method further causes the CPU model to not execute the delayed loop instruction sequence M-1 times when the loop instruction sequence detection signal is generated, and outputs a simulation elapsed time required to repeatedly execute the delayed loop instruction sequence M times, the simulation elapsed time being M times the simulation elapsed time required to execute the delayed loop instruction sequence once; and Wherein M is a natural number of 2 or greater.

18. The non-transitory computer readable medium of claim 17, The CPU model further includes a program counter configured to store a program counter value used to extract instructions included in the program to be simulated. The simulation method further enables the CPU model to extract the next instruction in the delayed loop instruction sequence according to the program counter value when the loop instruction sequence detection signal is generated.

19. The non-transitory computer readable medium of claim 16, The simulation device further comprises a slave model having a status flag, wherein the loop instruction sequence is a polling loop instruction sequence including instructions for confirming the status flag, and is repeatedly executed until it is confirmed that the status flag has changed, The simulation method further enables the CPU model to: When the state of the slave model is transferred before executing the polling loop instruction sequence, executing a state flag change instruction to cause the slave model to change the state flag; and When the change of the status flag is not confirmed after executing the polling loop instruction sequence, the polling loop instruction sequence is not executed N-1 times, and a simulation elapsed time required to repeatedly execute the polling loop instruction sequence N times is output, the simulation elapsed time being N times the simulation elapsed time required to execute the polling loop instruction sequence once; and Where N is a natural number of 2 or greater.

20. The non-transitory computer readable medium of claim 19, The CPU model further includes a program counter configured to store a program counter value used to extract instructions included in the program to be simulated. The simulation method further enables the CPU model to extract the first instruction in the polling loop instruction sequence according to the program counter value when the CPU model does not confirm the change of the status flag after executing the polling loop instruction sequence.

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