Data reading request processing method and computer equipment

Abstract

The invention discloses a data reading request processing method and computer equipment, and relates to the technical field of data storage, and the method comprises the following steps: determining to-be-read data according to a data reading request; comparing the address information of the to-be-read data with a preset variable, and determining whether the to-be-read data is stored in a first preset buffer area; and if the comparison is successful, directly sending the to-be-read data in the first preset buffer area to the host. The problem that resources of a central processing unit are wasted due to the fact that Nand flash memory data need to be read repeatedly when a host read request is processed can be solved. According to the method, the effective data cached in the first preset buffer area can be directly returned to the host under the condition of not carrying out additional operation on the logic-to-physical address mapping table, so that the random reading performance of the solid state disk in a steady state is improved.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a data read request processing method and computer equipment. Background Art

[0002] Random read performance measures an SSD's ability to read scattered, non-contiguous data. Random read performance directly impacts the speed and efficiency of application data processing. Scenarios that require frequent access to small files require an SSD with high random read performance.

[0003] NAND flash memory is a non-volatile memory. When a solid-state drive enters steady state and triggers a GC (Garbage Collection) operation, the garbage collection operation does not modify the L2P (Logical to Physical Mapping) table after reading data from the NAND flash memory into the garbage collection buffer (GC buffer). At this point, if a data read request is received from the host, the corresponding data to be read may have already been read into the buffer. However, processing a data read request currently requires repeated reading of the NAND flash memory. After determining the data to be read in the NAND flash memory, the data is returned to the corresponding buffer and then returned from the buffer to the host. This results in repeated reading of NAND flash data and wastes CPU resources. Summary of the Invention

[0004] In view of this, the present application provides a data read request processing method and computer device to solve the problem of repeated reading of Nand flash memory data when processing host read requests, resulting in waste of central processing unit resources.

[0005] In a first aspect, the present application provides a method for processing a data read request, the method comprising: When receiving a data read request sent by the host, determining the data to be read according to the data read request; Determining address information of the data to be read, and comparing the address information with a preset variable to obtain a comparison result, wherein the preset variable is generated during the process of writing the data into the first preset buffer, and the preset variable is used to determine the data stored in the first preset buffer; If it is determined according to the comparison result that the data to be read is in the first preset buffer, the data to be read in the first preset buffer is sent to the host.

[0006] In a second aspect, the present application provides a data read request processing device, the device comprising: A data determination module is used to determine the data to be read according to the data read request when receiving the data read request sent by the host; an information comparison module, configured to determine address information of the data to be read and compare the address information with a preset variable to obtain a comparison result, wherein the preset variable is generated during the process of writing the data into the first preset buffer, and the preset variable is used to determine the data stored in the first preset buffer; The data sending module is configured to send the data to be read in the first preset buffer to the host if it is determined according to the comparison result that the data to be read is in the first preset buffer.

[0007] In a third aspect, the present application provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the data reading request processing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0008] In a fourth aspect, the present application provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the data reading request processing method of the first aspect or any corresponding embodiment thereof.

[0009] In a fifth aspect, the present application provides a computer program product, comprising computer instructions, which are used to enable a computer to execute the data read request processing method of the above-mentioned first aspect or any corresponding embodiment thereof.

[0010] The present application solves the problem of repeatedly reading Nand flash memory data when processing host read requests, resulting in wasted CPU resources. This method can directly return valid data cached in the first preset buffer to the host without performing additional operations on the logical-to-physical address mapping table, thereby improving the random read performance of the solid-state drive in steady state. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the specific implementation methods of this application or the technical solutions in related technologies, the following is a brief introduction to the drawings required for use in the specific implementation methods or related technical descriptions. Obviously, the drawings described below are some implementation methods of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 is a flow chart of a conventional data read request processing according to an embodiment of the present application; Figure 2 1 is a flow chart of a method for processing a data read request according to an embodiment of the present application; Figure 3 is a flowchart of processing a data read request according to preset variables according to an embodiment of the present application; Figure 4 is a flowchart of another method for processing a data read request according to an embodiment of the present application; Figure 5 is a schematic diagram of page-to-buffer mapping according to an embodiment of the present application; Figure 6 is a schematic diagram of a method for modifying preset parameters according to an embodiment of the present application; Figure 7 is a schematic diagram of processing a garbage collection request according to preset variables according to an embodiment of the present application; Figure 8 is a structural block diagram of a data read request processing device according to an embodiment of the present application; Figure 9 It is a schematic diagram of the hardware structure of the computer device of an embodiment of the present application. DETAILED DESCRIPTION

[0013] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0014] Random read performance is a core metric for measuring a solid-state drive's (SSD) ability to read scattered, non-contiguous data. High random read performance is crucial for scenarios requiring frequent access to small files, such as system bootup, game loading, and database operations. Random read performance is typically measured in IOPS (Input / Output Operations Per Second) and latency (the duration of a single random read operation). Random read performance directly impacts the speed and efficiency of application data processing. A QLC (Quad-Level Cell) drive is a type of solid-state drive. Each cell in a QLC drive represents four states, resulting in a more sensitive voltage threshold. Each layer contains several word lines (WLs). The process of writing data to a QLC drive involves first writing the entire data layer to the Nand flash memory chip. This complete write operation is called the first programming. Afterwards, when programming begins on the word line data corresponding to the upper layer immediately adjacent to the bottom layer, a phenomenon called "write disturbance" occurs. This is because when high programming voltage is applied to the layer 1 cell, the physically adjacent layer 0 cell may be affected by the electric field, causing its stored charge (representing the voltage / data state) to change slightly or drift. To ensure that the layer 0 data is not destroyed by this disturbance, after completing the first programming of layer 1, the original layer 0 data from the previous step needs to be written again in full. This second write operation for layer 0 is called secondary programming. Subsequent programming is analogous to this. Each time the first programming of the current layer data is completed, the data of the previous layer needs to be reprogrammed. Both the first programming and the secondary programming are complete, overwriting rewrites of the entire target layer.

[0015] The QLC hard drive is an ultra-large capacity product that further increases the amount of cached data. During the garbage collection operation, approximately 196M of data will be cached in the garbage collection buffer. The QLC hard drive has a large amount of data in steady state, which is read from the Nand flash memory and placed in the garbage collection buffer. At this time, the probability of the host's data read request hitting the garbage collection buffer is greatly increased. After the current solid-state drive enters steady state and triggers the garbage collection operation, the garbage collection operation will not modify the l2p (Logical to Physical Mapping) table after reading the data into the garbage collection buffer, that is, the same data is stored in both the Nand flash memory and the garbage collection buffer. Even if the data read by the host at this time is stored in the garbage collection buffer, the Nand flash memory needs to be re-read. Currently, the traditional process of processing data read requests is as follows: Figure 1As shown in the figure, upon receiving a host read command, a flash read command is sent to the Nand flash memory, the Nand data is read, and a flash read reply is sent to the buffer. The buffer then sends a host read reply to the host, completing the data reply. The current mechanism for processing data read requests repeatedly reads data from the Nand flash memory, wasting CPU resources.

[0016] Based on the above content, the embodiment of the present application provides a method for processing data read requests, which adds P2B (page-to-Buffer Mapping) technology. Two variables are designed through this technology. These two variables are used to indicate whether the pba (physical block addressing) address corresponding to the lba (logical block address) has been written into the garbage collection buffer in the process of processing data read requests. In addition, in order to prevent the buffer from being released when processing the host's data read and write requests, this embodiment designs a GCbuffer refCount (garbage collection buffer reference count) mechanism to determine whether the buffer can be released through refCount. The method for processing data read requests is as follows: Figure 1 As shown in the figure, upon receiving a host read command, the corresponding data is determined from the buffer data and a host read reply is sent to the host. This allows valid data cached in the garbage collection buffer to be directly returned to the host without any additional operations on the L2P table, significantly improving the random read performance of the QLC hard drive in steady state.

[0017] According to an embodiment of the present application, a data read request processing embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, for example: a computer, a server, etc., and, although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0018] In this embodiment, a method for processing a data read request is provided. Figure 2 Flowchart of a method for processing a data read request according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps: Step S201 : upon receiving a data read request from a host, determining data to be read according to the data read request.

[0019] Specifically, this embodiment is executed by a data management module (DM), which is configured to return to the host the to-be-read data corresponding to the data read request when the solid-state drive receives a data read request from the host.

[0020] Combine Figure 3 To illustrate this embodiment, when the data management module receives a data read request from the host, it parses the request and extracts a logical block address (LBA). LBA is the unit of data exchanged between the host and the solid-state drive, typically 4 KB in size. If the host wants to read or write 400 KB of data, that is, 400 KB / 4 KB = 100 LBAs. Based on the parsed LBA, the data management module can determine the host's data to be read.

[0021] Step S202, determining address information of the data to be read, and comparing the address information with a preset variable to obtain a comparison result, wherein the preset variable is generated during the process of writing data into the first preset buffer, and the preset variable is used to determine the data stored in the first preset buffer.

[0022] Specifically, the data management module queries the logical-to-physical address mapping table and determines the PBA address of the data to be read in the logical-to-physical address mapping table. PBA is the physical address mapping of the storage unit inside the Nand flash memory, which directly corresponds to the actual physical location of the flash memory medium and forms a mapping relationship with the logical block address. The l2p table records the logical-to-physical address mapping relationship and is a key core technology component table of the solid-state drive.

[0023] Each piece of user data lba will be saved in Nand flash memory, and the corresponding Nand flash memory address is pba. The format of pba is as follows: struct {uint32_t logical_lun:5;uint32_t dataframe:2;uint32_t plane:2;uint32_t page:11;uint32_t block:10;uint32_t slun:2;}pba; where logical_lun:5 represents logical unit 5; dataframe:2 represents data frame 2; plane:2 represents logical partition 2; page:11 represents page 11; block:10 represents data block 10; and slun:2 represents sub-logical unit 2. As can be seen from the above, the pba can be used to determine where the current data is stored in the Nand flash memory. This can be determined using the lun-block-plane-page-dataframe multi-level index. Therefore, based on the determined pba address, the address information of the data to be read can be obtained, including address information such as lun (logical unit), block (data block), page (data page), dataframe (data frame), and SPB_ID (Super Block Identity document).

[0024] Preset variables are, for example, variables generated based on page-to-buffer mapping technology. This variable is generated during the process of writing data into the first preset buffer. In the process of processing data read requests, this variable indicates whether the pba corresponding to the lba has been written into the first preset buffer. The first preset buffer is, for example, a garbage collection buffer. The address information is compared with the preset variable. If the address information is consistent with the preset variable, it is determined that the data to be read has been written into the first preset buffer. The above process is as follows: Figure 3 As shown, the logical to physical address mapping table is read to obtain the corresponding physical block address and determine whether the data is stored in the garbage collection buffer.

[0025] Step S203 : If it is determined according to the comparison result that the data to be read is in the first preset buffer, the data to be read in the first preset buffer is sent to the host.

[0026] Specifically, if the data to be read is determined to be in the first preset buffer according to the comparison result, the data management module returns the data to be read in the first preset buffer to the host. For example, if the address information is consistent with the preset variable, it is determined that the data to be read is in the first preset buffer, and the data to be read is returned to the host. Figure 3 As shown, data is moved from the first preset buffer to the host.

[0027] The data read request processing method provided in this embodiment determines the data to be read based on the data read request; compares the address information of the data to be read with a preset variable to determine whether the data to be read is stored in a first preset buffer; and if the comparison is successful, directly sends the data to be read in the first preset buffer to the host. This method can directly return valid data cached in the first preset buffer to the host without performing additional operations on the logical-to-physical address mapping table, thereby improving the random read performance of the solid-state drive in steady state. It also solves the problem of repeatedly reading Nand flash memory data when processing host read requests, which wastes CPU resources.

[0028] In this embodiment, another method for processing data read requests is provided. Figure 4 is a flowchart of another method for processing a data read request according to an embodiment of the present application. Figure 4 As shown, the process includes the following steps: Step S401 : upon receiving a data read request from a host, determining data to be read according to the data read request.

[0029] For details on how to implement this step, see Figure 1 Step S201 of the illustrated embodiment will not be described in detail here.

[0030] Step S402, determining address information of the data to be read, and comparing the address information with a preset variable to obtain a comparison result, wherein the preset variable is generated during the process of writing data into the first preset buffer, and the preset variable is used to determine the data stored in the first preset buffer.

[0031] Specifically, the preset variable includes a first sub-variable and a second sub-variable, and the above step S402 "comparing the address information with the preset variable to obtain a comparison result" includes steps S4021 to S4023.

[0032] Step S4021: Determine the target data block identifier and the first physical block address corresponding to the data to be read according to the address information.

[0033] Step S4022: If the target data block identifier successfully matches the first sub-variable, and the first physical block address successfully matches the second sub-variable, a first comparison result is obtained.

[0034] Step S4023: If the target data block identifier fails to match the first sub-variable, or the first physical block address fails to match the second sub-variable, a second comparison result is obtained.

[0035] Specifically, according to page-to-buffer mapping technology, during garbage collection operations, only one super block (SPB) in each LUN is currently moving data. A super block represents a collection of physical data blocks with the same block number across multiple LUNs. Based on this, this embodiment uses page-to-buffer mapping technology to generate a first sub-variable and a second sub-variable. These two variables are generated during the process of writing data to a first preset buffer. During the process of processing a data read request, these two variables indicate whether the PBA corresponding to the LBA has been written to the first preset buffer, such as the garbage collection buffer. The first and second sub-variables are global variables and are stored in dynamic random access memory.

[0036] The first sub-variable is, for example, uint16_t g_gc_running_spb[lun]. The first sub-variable indicates the super block number in the current logical unit that is undergoing garbage collection and removal. The first sub-variable is updated when the super block is switched. In addition, the conversion relationship between the super block number and the data block number (block_idx) is: SPB_ID = block_idx / plane_num. Figure 5 As shown, SPB0 actually contains 4 blocks, block0–block3. Figure 5 Logical partition 0 / logical partition 1 / logical partition 2 / logical partition 3 can perform read operations in parallel. When garbage collection is performed inside the solid-state drive, these data will be read into the garbage collection buffer at the same time. The super block number is calculated when the solid-state drive is powered on and initialized, and can be directly called later.

[0037] The second sub-variable is for example: uint16_t g_P2B[lun][plane][page_num][data_frame], the second sub-variable represents the specific data frame in the Nand flash memory (such as Figure 5 The data frame 0, data frame 1, etc. in the buffer are read to the address in the buffer. The second subvariable is updated when the data is read from the Nand flash memory to the garbage collection buffer. If the second subvariable is invalid, it means that the data has not been read.

[0038] Combine Figure 5This section describes the principle of determining whether the data to be read is in the first preset buffer based on the first and second subvariables. If the solid-state drive is currently performing a garbage collection operation, and the first subvariable g_gc_running_spb[0] = 0, and the second subvariable g_P2B[0][0][0][0] = buff0, it indicates that the identifier of the super block on lun 0 that is currently performing a garbage collection operation is SPB_ID = 0, and lun0-plane0-page0-df0 has been read to the buff0 position of the first preset buffer.

[0039] At this time, if the host intends to read the data with lba = 100, that is, the data to be read with lba = 100, the solid-state drive will check the logical-to-physical address mapping table and find the corresponding pba. If the address of the data to be read is determined to be lun0-SPB1-plane0-page0-df0 according to pba, SPB1 does not match the first subvariable g_gc_running_spb[0], and it is determined that the data to be read is not in the first preset buffer. If the address of the data to be read is determined to be lun0-SPB0-plane0-page0-df0 according to pba, SPB0 matches the first subvariable g_gc_running_spb[0], and lun0-SPB0-plane0-page0-df0 matches the second subvariable g_P2B[0][0][0][0], it is determined that the data to be read has been read into the first preset buffer.

[0040] The target data block identifier and the first physical block address corresponding to the data to be read are determined based on the address information. The target data block identifier is, for example, a super block number. The first physical block address is, for example, the lun, plane, page, df, and other information corresponding to the data to be read.

[0041] If the target data block identifier successfully matches the first subvariable, for example, if the target data block identifier is SPB0 and the first subvariable is g_gc_running_spb[0], the target data block identifier successfully matches the first subvariable. If the first physical block address successfully matches the second subvariable, for example, if the first physical block address is lun0-plane0-page0-df0 and the second subvariable is g_P2B[0][0][0][0], the first physical block address successfully matches the second subvariable. In this case, the first comparison result is: the address information is the same as the preset variable, and the data to be read is in the first preset buffer.

[0042] If the target data block identifier fails to match the first subvariable, for example, if the target data block identifier is SPB1 and the first subvariable is g_gc_running_spb[0], the target data block identifier fails to match the first subvariable. If the first physical block address fails to match the second subvariable, for example, if the first physical block address is lun1-plane1-page0-df0 and the second subvariable is g_P2B[0][0][0][0], the first physical block address fails to match the second subvariable. In this case, the second comparison result is: the address information is different from the preset variable, and the data to be read is not in the first preset buffer.

[0043] The operation of "comparing the address information with the preset variables to obtain the comparison result" in this embodiment can be dynamically loaded and unloaded in a modular manner during actual operation without affecting the execution of the garbage collection service.

[0044] In this embodiment, a first sub-variable and a second sub-variable are designed to determine whether the data to be read has been written into the first preset buffer without modifying the logical-to-physical address mapping table, and directly return the data to be read in the first preset buffer to the host, thereby improving the random read performance of the solid-state drive.

[0045] Step S403 : If it is determined according to the comparison result that the data to be read is in the first preset buffer, the data to be read in the first preset buffer is sent to the host.

[0046] Specifically, the above step S403 includes: step S4031 to step S4034.

[0047] Step S4031 : If it is determined according to the comparison result that the data to be read is in the first preset buffer, the preset parameter is increased by a preset step length to obtain a first parameter, wherein the preset parameter is used to determine whether to release the first preset buffer.

[0048] Step S4032: Send the data to be read in the first preset buffer to the host.

[0049] Step S4033: When it is determined that the data to be read still exists in the first preset buffer, the preset step length is subtracted from the first parameter to obtain a second parameter.

[0050] Step S4034: when the second parameter is equal to the preset threshold, release the first preset buffer.

[0051] Specifically, the first preset buffer is, for example, a garbage collection buffer. Since the first preset buffer is used not only for garbage collection operations but also for processing data read requests sent by the host, in order to prevent the first preset buffer from being released during the processing of data read requests sent by the host, resulting in errors in processing data read requests, this embodiment adds a garbage collection buffer reference counting mechanism. In units of 4Kb, a refCount attribute is added to the first preset buffer, and refCount is used as a preset parameter. The modification method of refCount is as follows: Figure 6 As shown, when a garbage collection operation first requests a buffer, or when a data read request hits the first preset buffer, refCount++ is executed, which increments the preset parameter by 1. Alternatively, refCount can be incremented by another value based on actual needs. When the data in the first preset buffer is written to the Nand flash memory, or when the data read request is processed, refCount-- is executed, which decrements the preset parameter by 1. Alternatively, refCount can be decremented by another value based on actual needs, ensuring that the incremented value is the same as the decremented value. When refCount reaches 0, the garbage collection buffer is released.

[0052] The preset parameter is, for example, refCount, and the preset step size is, for example, 1. If the data to be read is determined to be in the first preset buffer according to the comparison result, that is, the data read request hits the first preset buffer, the preset parameter is increased by the preset step size to obtain the first parameter, for example, the first parameter is refCount+1. The above process is as follows Figure 3 As shown, it is determined whether the data is stored in the garbage collection buffer. If it is determined that the data is in the GC buffer, refCount++ is executed. The data to be read in the first preset buffer is sent to the host.

[0053] After the data to be read in the first preset buffer is sent to the host, the data to be read may still be stored in the first preset buffer or in other buffers. In order to determine whether the first preset buffer needs to be released, it is necessary to determine whether the data to be read is still stored in the first preset buffer. If the data to be read is still in the first preset buffer, it is determined whether the preset parameters can be released based on the preset parameters; if the data to be read is not in the first preset buffer, the first preset buffer is directly released.

[0054] If it is determined that the data to be read still exists in the first preset buffer, a preset step size is subtracted from the first parameter to obtain a second parameter, for example, refCount + 1 - 1 = refCount. A preset threshold value, for example, 0 or another value that meets practical requirements, is used. If the second parameter is equal to the preset threshold value, for example, refCount = 0, it is determined that the first preset buffer is no longer needed for garbage collection operations and processing data read requests sent by the host, and therefore, the first preset buffer is released.

[0055] The above process is as follows Figure 3 As shown, determine whether the data is stored in the first preset buffer; if the data is not stored in the first preset buffer, release the first preset buffer; if the data is stored in the first preset buffer, execute refCount minus 1 and determine whether refCount is 0 after minus 1, if it is 0, release the first preset buffer, if not 0, end.

[0056] In this embodiment, by setting preset parameters and the method for modifying the preset parameters, the first preset buffer is prevented from being released during the processing of the data read request sent by the host, thereby avoiding errors in processing the data read request or the garbage collection process.

[0057] Step S404: If it is determined according to the comparison result that the data to be read is not in the first preset buffer, a second preset buffer is requested.

[0058] Step S405 , determining the data to be read in the preset memory according to the address information, and writing the data to be read in the preset memory into the second preset buffer.

[0059] Step S406: Send the data to be read in the second preset buffer to the host.

[0060] Specifically, if it is determined based on the comparison result that the data to be read is not in the first preset buffer, the data management module needs to obtain the data to be read from the Nand flash memory and return it to the host, for example: the address information is inconsistent with the preset variable, and it is determined that the data to be read is not in the first preset buffer.

[0061] The data management module applies for a buffer in 4KB units as the second preset buffer zone. After successfully applying for the second preset buffer zone, the data management module generates a read request based on the address information of the data to be read and sends this read request to the Flash Channel Controller (FCC). The FCC is an independent module that directly operates the Nand flash memory. Other modules must complete data reading, writing, and erasing through the FCC.

[0062] The preset memory is, for example, a Nand flash memory. After receiving the read request, the flash memory lane controller determines the data to be read in the preset memory based on the address information in the read request. The flash memory lane controller then sends a read request reply message (readcpl) to the data management module. The read request reply message includes the data to be read from the preset memory. After receiving the read request reply message, the data management module writes the data to be read into a second preset buffer and then sends the data to be read from the second preset buffer to the host.

[0063] like Figure 3 As shown, it is determined whether the data is stored in the garbage collection buffer. If it is determined that the data is not in the buffer, first apply for a second preset buffer, then move the data from the Nand flash memory to the second preset buffer, and then move the data from the second preset buffer to the host.

[0064] As an optional embodiment, the preset variable includes a first sub-variable and a second sub-variable, and the data read request processing method further includes: steps A1 to A5.

[0065] Step A1: upon receiving a garbage collection request, determining a target data block identifier according to the garbage collection request, and setting a first sub-variable according to the target data block identifier.

[0066] Step A2: Apply for a first preset buffer and determine a first target data block according to the target data block identifier.

[0067] Step A3: writing the data in the first target data block into the first preset buffer.

[0068] Step A4: obtaining a preset number of data frames according to the data in the first preset buffer.

[0069] Step A5: Set the second sub-variable according to the data frame, and write the data frame into the second target data block.

[0070] Specifically, the first subvariable is, for example, uint16_t g_gc_running_spb[lun], and the second subvariable is, for example, uint16_t g_P2B[lun][plane][page_num][data_frame].

[0071] This embodiment is implemented through the Write Manager (WM), the Reclaim Block Manager (RBM), and the Flash Memory Lane Controller. The Write Manager receives garbage collection data from the RBM, arranges it in a specific order, and then notifies the Flash Memory Lane Controller to write it to the Nand Flash memory. The Reclaim Block Manager moves the specified Super Block data to a new data block.

[0072] Combine Figure 7 This embodiment is described below. The write controller initiates a garbage collection request, which carries a target data block. The first target data block, for example, is a super block to be reclaimed. Upon receiving the garbage collection request, the reclaim block manager determines the target data block identifier, for example, SPB_ID, based on the garbage collection request. All logical units within the same stripe are updated, and the first subvariable is set based on the target data block identifier, for example, g_gc_running_spb[lun] = SPB_ID.

[0073] The reclaim block manager allocates a garbage collection buffer as the first preset buffer. For example, starting with data page 0 of the first target data block, it polls all luns, first reading page 0 of all luns, then reading page 1 of all luns, and so on. This improves the concurrency of read operations. Within each lun, a buffer of 4 planes is allocated to obtain the first preset buffer.

[0074] After the first preset buffer zone is successfully applied, the recovery block manager determines the first target data block according to the target data block identifier, initiates a read request (read req) for the first target data block to the flash channel controller, and uses the flash channel controller to write the data in the first target data block into the first preset buffer zone. Figure 7 As shown, the RBM executes the following: loop from page0-pageMax; loop from lun0-lunMax; assigns a value to g_gc_running_spb[lun]; requests a GC buffer; reads the page data on the current lun into the buffer; determines whether to read lunMax and pageMax, that is, whether to traverse all luns and pages. If so, it sends a garbage collection request reply to the reclaim block manager. The RBM sends a read request to the FCC, and the FCC returns a read reply to the RBM, confirming that the data in the first target data block has been written to the first preset buffer.

[0075] When the recycling block manager receives the read request reply information returned by the flash channel controller, it determines that the data of the first target data block has been written into the first preset buffer. The recycling block manager obtains a preset number of data frames based on the data in the first preset buffer, for example: polling all planes in the same lun and processing the data frames one by one. The second sub-variable is set according to the data frame, for example: determining that the data address is lun0-SPB0-plane0-page0-df0 according to the data frame, and setting the second sub-variable to g_P2B[0][0][0][0]= buff0. The data frame is sent to the write controller, and the write controller is used to write the data frame into the second target data block. The above process is as follows. Figure 7 As shown, loop from df0-df3; update g_P2B[lun][plane][page_num][data_frame]; determine whether df3 has read the last data frame. The second target data block, for example, is a data block other than the first target data block, such as a new target super block (dest super block). The preset number indicates multiple, and no specific number limit is imposed here.

[0076] In this embodiment, the first and second subvariables are designed and added to the garbage collection process without affecting the garbage collection process. This allows the determination of whether the data to be read has been written to the first preset buffer without modifying the logical-to-physical address mapping table, and the direct return of the data to be read in the first preset buffer to the host, thereby improving the random read performance of the solid-state drive.

[0077] As an optional embodiment, after the above step A5 of "writing the data frame into the second target data block", step B1 and step B2 are further included.

[0078] Step B1, subtracting a preset step length from the third parameter to obtain a fourth parameter, wherein the third parameter is generated by adding a preset step length to the preset parameter after setting the second sub-variable according to the data frame.

[0079] Step B2: when the fourth parameter is equal to the preset threshold, releasing the first preset buffer area.

[0080] Specifically, the preset parameter is, for example, refCount, and the preset step size is, for example, 1. After the recycling block manager sets the second sub-variable according to the data frame, it increases the preset step size by the preset parameter to obtain a third parameter, indicating that a business is currently using the first preset buffer, for example, the third parameter is refCount+1. The above process is as follows Figure 7As shown, the second subvariable g_P2B[lun][plane][page_num][data_frame] is updated, and refCount++ is about to add 1 to the preset parameter.

[0081] The preset threshold is, for example, 0 or another value that meets actual needs. After receiving the write completion command returned by the flash channel controller, the write controller determines that the data frame has been written to the second target data block. The write controller subtracts the preset step size from the third parameter to obtain a fourth parameter, for example, refCount + 1 - 1 = refCount. After receiving the write completion command returned by the flash channel controller, the write controller performs refCount-- on the GC buffer for each dataframe. When refCount reaches 0, the GC buffer is released.

[0082] The write controller determines whether the fourth parameter is equal to the preset threshold. If the fourth parameter is equal to the preset threshold, it determines that the garbage collection operation and the data read request process sent by the host no longer need the first preset buffer, so the first preset buffer is released. Figure 7 As shown, it is determined whether the preset parameter is 0 after being subtracted by 1. If it is determined to be equal to 0, the garbage collection buffer is released.

[0083] In this embodiment, by setting preset parameters and the method for modifying the preset parameters, the first preset buffer is prevented from being released during the processing of the data read request sent by the host, thereby avoiding errors in processing the data read request or the garbage collection process.

[0084] As an optional embodiment, the above step A5 "setting the second sub-variable according to the data frame" includes steps C1 to C4.

[0085] Step C1, obtaining the logical block address corresponding to the data frame; Step C2, obtaining a second physical block address corresponding to the data frame in the metadata according to the logical block address; Step C3, obtaining a third physical block address corresponding to the data frame in the logical-to-physical mapping table according to the logical block address; Step C4: taking the data frame having the same second physical block address as the third physical block address as the target data frame, and setting the second sub-variable according to the target data frame.

[0086] Specifically, because the host is constantly writing data, previously written data may become invalid. For example, if the same LBA is written twice, the data written the first time will be invalid. However, the data remains on the Nand flash memory, but the logical-to-physical address mapping table indicates that the data corresponding to the current LBA has been moved to the new PBA. Therefore, after obtaining a preset number of data frames, the recycling block manager needs to determine whether the LBA corresponding to the data frame is valid. The recycling block manager obtains the logical block address LBA corresponding to each data frame.

[0087] The metadata Meta stores all lba and corresponding pba addresses. The pba in the metadata is recorded as old_pba. Based on the logical block address, the old_pba corresponding to the data frame is obtained from the metadata and used as the second physical block address. The current logical-to-physical address mapping table is read and the pba recorded in the logical-to-physical address mapping table is recorded as new_pba. Based on the logical block address, the new_pba corresponding to the data frame is obtained from the logical-to-physical address mapping table and used as the third physical block address.

[0088] If old_pba equals new_pba, the data corresponding to the data frame is valid; otherwise, it is invalid. Therefore, the reclaim block manager uses the data frame with the same second and third physical block addresses as the target data frame. The data corresponding to the target data frame is valid. The second subvariable is set based on the target data frame.

[0089] In this embodiment, the second physical block address and the third physical block address corresponding to the data frame are obtained, and the second sub-variable is set only according to the data frame having the same second physical block address and the same third physical block address, so as to filter out invalid data frames and ensure that each second sub-variable is valid.

[0090] As an optional embodiment, the above step A5 "writing the data frame into the second target data block" includes: steps D1 to D3.

[0091] Step D1: assembling data frames into first data to be written according to a first preset format.

[0092] Step D2: assembling the first data to be written into second data to be written according to a second preset format.

[0093] Step D3: writing the second data to be written into the second target data block.

[0094] Specifically, the first preset format is, for example, CCB format. The recovery block manager assembles the data frame into the first data to be written according to the first preset format, for example, the recovery block manager assembles the data frame into CCB format to obtain the first data to be written, and sends the first data to be written to the write controller.

[0095] The second preset format is, for example, a PO format. After receiving the first data to be written, the write controller assembles the first data to be written into the second data to be written according to the second preset format. For example, the write controller assembles CCBs into a PO format. Taking 4 planes as an example, 4 CCBs form a PO, and each plane has 1 PO.

[0096] The write controller sends a write command to send the second data to be written to the flash channel controller, and the flash channel controller saves the second data to be written to the second target data block. The second target data block is, for example, a new target super block.

[0097] After the flash channel controller saves the second data to be written to the second target data block, it sends a write reply message to the write controller. Figure 7 As shown, RBM assembles CCB, i.e., the first data to be written, and sends the first data to be written to WM; WM assembles the first data to be written into PO, i.e., the second data to be written, saves it to the flash memory, and sends a write request to FCC. After FCC completes the writing, it returns the write reply information to WM.

[0098] As an optional embodiment, the above step S4021 "determining the target data block identifier and the first physical block address corresponding to the data to be read according to the address information" includes: steps E1 to E4.

[0099] Step E1, determining a third target data block containing data to be read according to the address information; Step E2, using the identifier of the third target data block as the target data block identifier; Step E3, obtaining the logical unit, logical partition, data page, and data frame corresponding to the data to be read from the address information; Step E4: determining a first physical block address according to the logical unit, the logical partition, the data page, and the data frame.

[0100] Specifically, according to the page-to-buffer mapping technology, during garbage collection operations, only one superblock in each lun is performing data movement. The superblock represents a collection of physical data blocks with equal block numbers in several luns.

[0101] The address information is determined based on the PBA address of the data to be read. The PBA address of the data to be read can also be determined based on the address information. The data block corresponding to the data to be read is determined based on the PBA address, and the super block where the data block is located is used as the third target data block of the data to be read. The identifier of the third target data block is used as the target data block identifier. The identifier of the third target data block is, for example, the SPB_ID of the third target data block.

[0102] Obtain the logical unit, logical partition, data page and data frame contained in the address information, and determine the first physical block address based on the logical unit, logical partition, data page and data frame. For example: the logical unit is lun0, the logical partition is plane0, the data page is page0, and the data frame is df0, and the first physical block address is determined to be lun0-plane0-page0-df0.

[0103] In an embodiment of the present application, the target data block identifier and the first physical block address corresponding to the data to be read are determined respectively according to the address information. The target data block identifier and the first physical block address can be used to accurately determine whether the data to be read has been written into the first preset buffer.

[0104] The data read request processing method provided in this embodiment determines the data to be read based on the data read request; compares the address information of the data to be read with a preset variable to determine whether the data to be read is stored in a first preset buffer; and if the comparison is successful, directly sends the data to be read in the first preset buffer to the host. This method can directly return valid data cached in the first preset buffer to the host without performing additional operations on the logical-to-physical address mapping table, thereby improving the random read performance of the solid-state drive in steady state. It also solves the problem of repeatedly reading Nand flash memory data when processing host read requests, which wastes CPU resources.

[0105] As an optional embodiment, when the capacity of the buffer in the SSD is limited, it is necessary to reduce the memory requirements of QLC multiple programming in the memory-constrained SSD. The above step D3 "writing the second to-be-written data into the second target data block" includes steps F1 to F5.

[0106] In step F1, some SLC (Single-Level Cell) physical blocks are reserved inside the solid state drive. Whenever the flash channel controller writes the second data to be written, the data is always written into the SLC physical blocks first.

[0107] In step F2, a smaller memory area is reserved in the solid-state drive as a WL Buffer (Wordline Buffer).

[0108] Step F3: After writing the second data to be written into the SLC physical block, the second data to be written is read from the SLC physical block to the WL Buffer and transmitted to the QLC physical block corresponding to the DIE, where DIE represents a unit capable of independent concurrent operations.

[0109] Step F4: Release the WL Buffer and initiate QLC programming of the corresponding DIE.

[0110] In step F5, the same process is performed on other DIEs in sequence using the WL Buffer, and the QLC programming of all DIEs is completed.

[0111] Specifically, some SLC physical blocks are reserved within the SSD. When the SLC physical blocks are exhausted, a new set of blank SLC physical blocks is allocated. When the flash channel controller writes the second data to be written, it always writes it first to the SLC physical blocks. Furthermore, a smaller memory area is reserved within the SSD: the WL Buffer. This area contains a single DIE concurrent programming unit, such as one WL, which corresponds to four pages.

[0112] After the second data to be written is written to the SLC physical block, it is read from the SLC physical block into the WL Buffer and transferred to the QLC physical block of the corresponding DIE. The WL Buffer is released, and programming of the QLC physical block of the corresponding DIE is initiated. Using this WL Buffer, the same process is performed on other DIEs in sequence. After the QLC programming is completed, the above process is repeated. If all the data in the SLC physical block has been moved to the QLC physical block, the SLC physical block can be released to store data written by the flash channel controller later.

[0113] In this solution, a single WL Buffer is time-shared across multiple DIEs. Data read from the SLC is stored and then transferred to the QLC physical block. The corresponding DIE then releases the buffer, which then performs QLC programming internally. The released WL Buffer can then be used as data transfer for the next DIE to initiate QLC programming. It's important to note that QLC programming takes significantly longer than SLC reads and data transfers from NAND to the WL Buffer or vice versa. Therefore, even with limited WL Buffer time-shared reuse, concurrent programming of the QLC physical blocks of each DIE is guaranteed, thus ensuring performance.

[0114] In an embodiment of the present application, data migration rules and buffer release are optimized so that data writing can be completed while using only less memory, greatly reducing the memory requirements for multiple QLC programming in memory-constrained solid-state drives, thereby reducing costs.

[0115] This embodiment also provides a data read request processing device for implementing the above-mentioned embodiments and preferred embodiments. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0116] This embodiment provides a data read request processing device, such as Figure 8 Shown, including: The data determination module 801 is configured to determine the data to be read according to the data read request when receiving the data read request sent by the host; An information comparison module 802 is configured to determine address information of the data to be read and compare the address information with a preset variable to obtain a comparison result, wherein the preset variable is generated during the process of writing the data into the first preset buffer and is used to determine the data stored in the first preset buffer; The data sending module 803 is configured to send the data to be read in the first preset buffer to the host if it is determined according to the comparison result that the data to be read is in the first preset buffer.

[0117] In some optional embodiments, the device further comprises: A first application module is configured to apply for a second preset buffer if it is determined according to the comparison result that the data to be read is not in the first preset buffer; A first writing module, configured to determine the data to be read in the preset memory according to the address information, and write the data to be read in the preset memory into the second preset buffer; The sending module is used to send the data to be read in the second preset buffer to the host.

[0118] In some optional implementations, the preset variable includes a first sub-variable and a second sub-variable, and the information comparison module 802 includes: a determining unit, configured to determine a target data block identifier and a first physical block address corresponding to the data to be read according to the address information; A first judgment unit is configured to obtain a first comparison result if the target data block identifier successfully matches the first sub-variable and the first physical block address successfully matches the second sub-variable; The second judgment unit is configured to obtain a second comparison result if the target data block identifier fails to match the first sub-variable, or if the first physical block address fails to match the second sub-variable.

[0119] In some optional implementations, the data sending module 803 includes: a first obtaining unit, configured to, if it is determined according to the comparison result that the data to be read is in the first preset buffer, increase the preset parameter by a preset step length to obtain a first parameter, wherein the preset parameter is used to determine whether to release the first preset buffer; A sending unit, configured to send the to-be-read data in the first preset buffer to a host; a second obtaining unit, configured to, when determining that the data to be read still exists in the first preset buffer, subtract a preset step length from the first parameter to obtain a second parameter; The releasing unit is configured to release the first preset buffer when the second parameter is equal to a preset threshold.

[0120] In some optional embodiments, the preset variable includes a first sub-variable and a second sub-variable, and the apparatus further includes: a setting module, configured to, upon receiving a garbage collection request, determine a target data block identifier according to the garbage collection request, and set a first subvariable according to the target data block identifier; A second application module is used to apply for a first preset buffer and determine a first target data block according to the target data block identifier; A second writing module, configured to write the data in the first target data block into a first preset buffer; A first obtaining module is used to obtain a preset number of data frames according to the data in the first preset buffer; The third writing module is used to set the second sub-variable according to the data frame and write the data frame into the second target data block.

[0121] In some optional embodiments, the device further comprises: a second obtaining module, configured to subtract a preset step length from the third parameter to obtain a fourth parameter, wherein the third parameter is generated by increasing the preset step length by the preset parameter after setting the second subvariable according to the data frame; The release module is configured to release the first preset buffer when the fourth parameter is equal to the preset threshold.

[0122] In some optional implementations, the third writing module includes: A first acquiring unit, configured to acquire a logical block address corresponding to a data frame; A second acquiring unit, configured to acquire a second physical block address corresponding to the data frame in the metadata according to the logical block address; A third acquiring unit, configured to acquire a third physical block address corresponding to the data frame in the logical-to-physical mapping table according to the logical block address; The setting unit is configured to take the data frame having the same second physical block address as the third physical block address as the target data frame, and set the second sub-variable according to the target data frame.

[0123] In some optional implementations, the third writing module includes: A first assembling unit, configured to assemble the data frame into first data to be written according to a first preset format; a second assembling unit, configured to assemble the first to-be-written data into second to-be-written data according to a second preset format; The writing unit is configured to write the second data to be written into the second target data block.

[0124] In some optional implementations, the determining unit includes: A first determining submodule, configured to determine a third target data block containing data to be read according to the address information; Setting a submodule, configured to use the identifier of the third target data block as the target data block identifier; An acquisition submodule, configured to acquire the logical unit, logical partition, data page, and data frame corresponding to the data to be read from the address information; The second determining submodule is configured to determine a first physical block address according to the logical unit, the logical partition, the data page, and the data frame.

[0125] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0126] The data read request processing device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0127] The present application also provides a computer device having the above Figure 8 The data read request processing device shown.

[0128] See also Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present application. Figure 9 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 9 A processor 10 is taken as an example.

[0129] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include an integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0130] The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to execute the method shown in the above embodiment.

[0131] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0132] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0133] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0134] The embodiments of the present application also provide a computer-readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0135] Part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes but is not limited to a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0136] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the present application.

Claims

1. A method for processing a data read request, characterized in that: The method comprises: In the case of receiving a data read request sent by the host, determining the data to be read according to the data read request; Determining address information of the data to be read, and comparing the address information with a preset variable to obtain a comparison result, wherein the preset variable is generated during the process of writing the data into the first preset buffer, and the preset variable is used to determine the data stored in the first preset buffer; If it is determined according to the comparison result that the data to be read is in the first preset buffer, the data to be read in the first preset buffer is sent to the host.

2. The method according to claim 1, characterized in that After comparing the address information with the preset variable to obtain a comparison result, the method further includes: If it is determined according to the comparison result that the data to be read is not in the first preset buffer, applying for a second preset buffer; determining the data to be read in a preset memory according to the address information, and writing the data to be read in the preset memory into the second preset buffer; The to-be-read data in the second preset buffer is sent to the host.

3. The method according to claim 1 or 2, characterized in that The preset variable includes a first sub-variable and a second sub-variable, and the address information is compared with the preset variable to obtain a comparison result, including: Determine a target data block identifier and a first physical block address corresponding to the data to be read according to the address information; If the target data block identifier successfully matches the first sub-variable, and the first physical block address successfully matches the second sub-variable, a first comparison result is obtained; If the target data block identifier fails to match the first sub-variable, or if the first physical block address fails to match the second sub-variable, a second comparison result is obtained.

4. The method according to claim 1, wherein If it is determined according to the comparison result that the data to be read is in the first preset buffer, sending the data to be read in the first preset buffer to the host includes: If it is determined according to the comparison result that the data to be read is in the first preset buffer, increasing a preset parameter by a preset step length to obtain a first parameter, wherein the preset parameter is used to determine whether to release the first preset buffer; Sending the to-be-read data in the first preset buffer to the host; When it is determined that the data to be read still exists in the first preset buffer, subtract the preset step length from the first parameter to obtain a second parameter; When the second parameter is equal to a preset threshold, the first preset buffer is released.

5. The method according to claim 1, wherein The preset variable includes a first sub-variable and a second sub-variable, and the method further includes: In the case of receiving a garbage collection request, determining a target data block identifier according to the garbage collection request, and setting the first subvariable according to the target data block identifier; Applying for the first preset buffer, and determining a first target data block according to the target data block identifier; Writing the data in the first target data block into the first preset buffer; Obtaining a preset number of data frames according to the data in the first preset buffer; The second sub-variable is set according to the data frame, and the data frame is written into a second target data block.

6. The method according to claim 5, characterized in that After writing the data frame into the second target data block, the method further includes: subtracting a preset step length from the third parameter to obtain a fourth parameter, wherein the third parameter is generated by increasing the preset step length by the preset parameter after setting the second sub-variable according to the data frame; When the fourth parameter is equal to a preset threshold, the first preset buffer zone is released.

7. The method according to claim 5, characterized in that The step of setting the second sub-variable according to the data frame includes: Obtaining a logical block address corresponding to the data frame; Obtaining a second physical block address corresponding to the data frame in metadata according to the logical block address; Acquire a third physical block address corresponding to the data frame in a logical-to-physical mapping table according to the logical block address; The data frame having the same second physical block address as the third physical block address is used as a target data frame, and the second sub-variable is set according to the target data frame.

8. The method according to claim 5 or 6, characterized in that Writing the data frame into the second target data block comprises: Assembling the data frame into first data to be written according to a first preset format; assembling the first to-be-written data into second to-be-written data according to a second preset format; Write the second data to be written into the second target data block.

9. The method according to claim 3, characterized in that The determining, according to the address information, a target data block identifier and a first physical block address corresponding to the data to be read includes: determining a third target data block containing the data to be read according to the address information; Using the identifier of the third target data block as the target data block identifier; Obtaining the logical unit, logical partition, data page, and data frame corresponding to the data to be read from the address information; The first physical block address is determined according to the logical unit, the logical partition, the data page, and the data frame.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the data read request processing method according to any one of claims 1 to 9 by executing the computer instructions.

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