Cross-chip register access method, device, and storage medium based on target protocol

Abstract

This invention relates to the field of chip design technology, and in particular to a method, device, and storage medium for cross-chip register access based on a target protocol. It involves configuring a set of on-chip interfaces at the adapter layer and establishing a mapping relationship between multiple pins of the on-chip interfaces and multiple fields of the target protocol at the adapter layer. When a cross-chip register access transaction is sent, the higher layer configures the on-chip interfaces of the adapter layer. The adapter layer parses the on-chip interfaces to obtain configuration information, maps the configuration information to fields of a sideband mailbox transaction according to a first mapping relationship, and initiates a sideband request transaction based on the fields of the sideband mailbox transaction through the sideband processing module of the adapter layer. When a sideband completion transaction is received, the adapter layer parses the fields in the sideband completion transaction and maps the fields in the sideband completion transaction to the corresponding pins of the on-chip interface according to a second mapping relationship. This shortens the access time and reduces communication latency and resource consumption.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a method, device and storage medium for cross-chip register access based on a target protocol. Background Technology

[0002] UCIe (Universal Chiplet Interconnect Express) is an in-package interconnect standard designed specifically for chip technology. The UCIe protocol introduces an innovative dual-path communication mechanism in a multi-chip collaborative architecture within a package. Its core architecture consists of a mainband and a sideband. The mainband handles high-performance data transmission, while the sideband serves as an auxiliary channel for control information exchange. To address the need for register access across chips, UCIe constructs a mailbox mechanism through sideband links, enabling indirect access to remote chips. However, the access steps based on the mailbox mechanism are relatively complex. Taking a write operation as an example, the higher layers of the sending chip perform the following configuration through the sideband signals of the FDI (Flit-Aware Die-to-Die Interface): The information to be accessed is configured in the Sideband Mailbox Index register of the Die-to-Die Adapter layer; the write data to be accessed is configured in the Mailbox Data Register of the Adapter layer; the Write / Read trigger field in the Sideband Mailbox Control register is set to 1, and the Sideband Mailbox Control register is continuously polled until the value of the Write / Read trigger field is 0, indicating the end of the mailbox access; the Adapter layer initiates a mailbox access request transaction to the Physical layer; the Physical layer sends it to the receiving chip via the UCIe sideband link; after the receiving end processes it, it returns the mailbox completion transaction to the Physical layer of the sending chip via the UCIe sideband link, and the Physical layer returns it to the Adapter layer. The Adapter layer updates the Write / Read trigger field of the Mailbox Control register to 0 and updates the Sideband Mailbox Status Register. The sending chip's higher layer reads the write / read trigger field value of the sideband mailbox control register as 0 via the sideband signal of the FDI interface, indicating that the mailbox operation was successful. Therefore, a complete sideband access transaction requires the higher layer to access the adapter layer registers at least three times via sideband signals: the mailbox index register, the mailbox data register, and the sideband mailbox control register. A complete sideband access includes the sending and receiving of the sideband request transaction and the sideband completion transaction. The clock frequency of the sideband link is low, and each sideband access consumes a considerable amount of time. Before the mailbox operation ends, the protocol layer or software needs to continuously poll the mailbox control register via the FDI sideband interface, consuming significant resources and time.

[0003] Therefore, there is an urgent need for a cross-core register access method that can shorten access time and reduce resource consumption. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: a cross-core register access method based on a target protocol, the method comprising the following steps:

[0005] S100, Obtain the target protocol, which includes a higher layer and an adapter layer.

[0006] S200, a set of on-chip interfaces are configured in the adapter layer, the on-chip interfaces including multiple pins; the adapter layer interacts with the higher layer through the on-chip interfaces.

[0007] S300, establish a mapping relationship between multiple pins of the on-chip interface and multiple fields of the target protocol at the adapter layer. The mapping relationship includes a first mapping relationship in the transmission direction and a second mapping relationship in the reception direction. The first mapping relationship is used to map the pin signals of the on-chip interface that conform to the on-chip protocol to the fields of the sideband request transaction that conforms to the target protocol. The second mapping relationship is used to map the fields of the sideband completion transaction that conforms to the target protocol to the corresponding pins of the on-chip interface.

[0008] S400, when a cross-chip register access transaction is sent, the higher layer configures the on-chip interface of the adapter layer; the adapter layer parses the on-chip interface to obtain the corresponding configuration information, maps the configuration information to the field of the sideband mailbox transaction according to the first mapping relationship, and initiates the sideband request transaction through the sideband processing module of the adapter layer according to the field of the sideband mailbox transaction.

[0009] S500, when a sideband completion transaction is received, the adapter layer parses the fields in the sideband completion transaction and maps the fields in the sideband completion transaction to the corresponding pins of the on-chip interface according to the second mapping relationship.

[0010] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.

[0011] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0012] The present invention has at least the following beneficial effects:

[0013] This invention provides a cross-chip register access method based on a target protocol. It establishes a mapping relationship between the on-chip interface and the target protocol at the adapter layer by multiplexing the on-chip interface. Through direct configuration of the on-chip interface at higher layers, the adapter layer maps the signals of the on-chip interface to fields of sideband transactions conforming to the target protocol and generates sideband transactions, thereby realizing sideband transaction interaction. By directly constructing the cross-chip communication path through high-level configuration, it bypasses the configuration of mailbox registers, eliminates dependence on dedicated sideband mailbox mechanisms, requires no additional hardware, and maintains full compatibility with the UCIe protocol. Cross-chip data interaction can be completed in a single register access transaction, significantly shortening access time and substantially reducing communication latency and system resource consumption. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A flowchart of a cross-chip register access method based on UCIe is provided for an embodiment of the present invention;

[0016] Figure 2 This is a flowchart illustrating the entire access process in the traditional method, using a UCIe protocol as the target protocol and a read request as an example.

[0017] Figure 3 The flowchart below illustrates the entire access process in the method provided by this invention, taking the UCIe protocol as the target protocol and a read request as an example.

[0018] Figure 4 The following is a timing diagram of the read and write operations on the on-chip interface, taking the APB interface as an example. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0021] Please see Figure 1The document illustrates a flowchart of a UCIe-based cross-chip register access method, which includes the following steps:

[0022] S100, Obtain the target protocol, which includes a higher layer and an adapter layer.

[0023] In one implementation, the target protocol is the UCIe protocol. Other types of inter-chip protocols with mailbox mechanisms also fall within the scope of this invention.

[0024] The target protocol also includes a physical layer. The adapter layer is located between the higher layers and the physical layer.

[0025] In one implementation, when the target protocol is the UCIe protocol, the UCIe protocol includes a higher layer, an adapter layer, and a physical layer. The higher layer, also known as the protocol layer, defines how to use lower-level services to implement specific application requirements. It includes a transaction layer responsible for handling high-level operations such as requests and responses, and supports different protocols and data formats to facilitate interoperability in various application scenarios. The adapter layer is located between the protocol layer and the physical layer. Its main function is to convert different protocols from the protocol layer into a standard format that can be transmitted at the physical layer, and vice versa. The physical layer is directly responsible for the actual signal transmission between chips.

[0026] S200, a set of on-chip interfaces are configured in the adapter layer, the on-chip interfaces including multiple pins; the adapter layer interacts with higher layers through the on-chip interfaces.

[0027] In one implementation, the on-chip interface standard is AMBA APB (Advanced MicrocontrollerBus Architecture - Advanced Peripheral Bus), AHB (Advanced High-performance Bus), AXI (Advanced eXtensible Interface), etc. Other types of standards also fall within the scope of protection of this invention.

[0028] S300, establish a mapping relationship between multiple pins of the on-chip interface and multiple fields of the target protocol at the adapter layer. The mapping relationship includes a first mapping relationship in the transmission direction and a second mapping relationship in the reception direction. The first mapping relationship is used to map the pin signals of the on-chip interface that conform to the on-chip protocol to the fields of the sideband request transaction that conforms to the target protocol. The second mapping relationship is used to map the fields of the sideband completion transaction that conforms to the target protocol to the corresponding pins of the on-chip interface.

[0029] The sideband transaction fields include the Opcode field, BE field, Addr field, and data field. The Opcode field distinguishes the type of a single sideband transaction, indicating whether the current transaction is a read request, write request, or other specific type of command, such as a completion transaction or a message transaction. The BE field, Byte Enable, specifies which bytes are valid during data transmission. The Addr field is the address of the target register or memory accessed by the sideband mailbox, specifying the exact location where data will be read or written. The data field contains the data; in a write request, the data field is the data to be written to the target address; in a read request, the data field may be empty or contain some predefined information; for a read completion transaction, this field contains the data read back from the target address. Sideband transactions including other types of fields also fall within the scope of this invention.

[0030] In one implementation, when the transmission direction is a read operation, the first mapping relationship includes: mapping the address configuration signal of the on-chip interface to the addr field of the sideband request transaction, and mapping the read / write control signal of the on-chip interface to the opcode field of the sideband request transaction.

[0031] In one implementation, when the transmission direction is a write operation, the first mapping relationship includes: the address configuration signal of the on-chip interface is mapped to the addr field of the sideband request transaction, the read / write control signal of the on-chip interface is mapped to the opcode field of the sideband request transaction, the strobe control signal of the on-chip interface is mapped to the BE field of the sideband request transaction, and the write data signal of the on-chip interface is mapped to the data field of the sideband request transaction.

[0032] In one implementation, when the sending direction is a read operation, the second mapping relationship includes: the status field of the sideband completed transaction is mapped to the reply signal of the on-chip interface, and the data field of the sideband completed transaction is mapped to the read data signal of the on-chip interface.

[0033] In one implementation, when a write operation is sent, the second mapping relationship includes mapping the status field of the sideband completion transaction to the reply signal of the on-chip interface.

[0034] It should be noted that mapping relationships for other types of operations also fall within the scope of protection of this invention.

[0035] As an example, when the on-chip interface standard is the APB protocol and the target protocol is the UCIe protocol, the first mapping relationship is as follows: when the transmission direction is a read operation, the PADDR signal of APB is mapped to the addr field, and the PWRITE signal is mapped to the opcode field. When the transmission direction is a write operation, the PADDR signal is mapped to the addr field, the PWRITE signal is mapped to the opcode field, the PSTRB signal is mapped to the BE field, and the PWDATA signal is mapped to the data field. The second mapping relationship is as follows: when the transmission direction is a read operation, the status field is mapped to the PREADY and PSLVERR signals, and the data field is mapped to the PRDATA signal. When the transmission direction is a write operation, the second mapping relationship is as follows: the status field is mapped to the PREADY and PSLVERR signals.

[0036] It should be noted that the adapter layer is responsible for protocol conversion between the target protocol and the chip's internal on-chip interface protocol, converting the data and control signals transmitted between chips into a format that conforms to the local SoC internal bus standard, thereby achieving seamless communication and integration across chips.

[0037] S400, when a cross-chip register access transaction is sent, the higher layer configures the on-chip interface of the adapter layer; the adapter layer parses the on-chip interface to obtain the corresponding configuration information, maps the configuration information to the field of the sideband mailbox transaction according to the first mapping relationship, and initiates the sideband request transaction through the sideband processing module of the adapter layer according to the field of the sideband mailbox transaction.

[0038] In one implementation, when the sideband request transaction is a read request, the configuration information includes signals such as address configuration signals and read / write control signals. When the sideband request transaction is a write request, the configuration information includes signals such as address configuration signals, strobe control signals, read / write control signals, and write data signals. Other signal types in the configuration information also fall within the protection scope of this invention.

[0039] It should be noted that the sideband request transaction is a sideband transaction or a sideband mailbox transaction that conforms to the target protocol.

[0040] S500, when a sideband completion transaction is received, the adapter layer parses the fields in the sideband completion transaction and maps the fields in the sideband completion transaction to the corresponding pins of the on-chip interface according to the second mapping relationship.

[0041] In one implementation, when the transmission direction is a read operation, the fields in the sideband completion transaction include a status field and a data field. When the transmission direction is a write operation, the fields in the sideband completion transaction include a status field. Other signal types in the fields of the sideband completion transaction also fall within the protection scope of this invention.

[0042] It should be noted that, for a better comparison between traditional methods and the method provided by this invention, the following explanation uses a read request with the UCIe protocol as the target protocol to illustrate the entire access process. For traditional methods, please refer to [link to traditional methods]. Figure 2 The specific steps are as follows: Step 1, for the transmitting phase of the transmitting chip: The higher layer of the transmitting chip configures the opcode, BE, address, and other information to be accessed through the sideband signal of the FDI interface into the index register located in the adapter layer of the transmitting chip via the first transmission path 11. At the same time, it configures the write / read trigger field in the control register to 1 through the second transmission path 12; and continuously polls the control register through the fourth transmission path 14 until the value of the write / read trigger field is 0, indicating that the mailbox access has ended. The adapter layer processes the mailbox access information and initiates a mailbox access request transaction to the physical layer of the transmitting chip through the fifth transmission path 15 on the RDI interface. The physical layer transmits the mailbox access request transaction to the physical layer of the receiving chip through the UCIe sideband link 16. Step 2, for the receiving phase of the receiving chip: The physical layer of the receiving chip transmits the mailbox access request transaction to the adapter layer of the receiving chip through the seventh transmission path 17 via the RDI interface. The adapter layer parses the mailbox access request transaction, completes the cross-chip register access, and initiates a mailbox access completion transaction to the physical layer of the receiving chip through the eighth transmission path 18 on the RDI interface. The physical layer transmits the mailbox transaction completion information to the sending chip's physical layer via UCIe sideband link 19. Step three, the sending chip receives the response: The sending chip's physical layer transmits the mailbox transaction completion information to the sending chip's adapter layer via the RDI interface through the tenth transmission path 110. The adapter layer updates the write / read trigger field of the control register to 0 and updates the status register and data register. The higher layer reads the write / read trigger field value of 0 from the sideband signal of the FDI interface, indicating that the mailbox operation was successful. The higher layer of the sending chip reads the status register and data register via the eleventh transmission path 111 from the sideband signal of the FDI interface. It should be noted that when it is a write operation, the data register located in the adapter layer needs to be configured via the third transmission path 13. For the method provided by this invention, please refer to [link to relevant documentation]. Figure 3The specific steps are as follows: Step 1, for the transmitting phase of the transmitting chip: The higher layer of the transmitting chip configures the on-chip interface located in the adapter layer through the first path 1, including the address, data, and read / write operation types for cross-chip register access. The adapter layer processes the on-chip interface configuration information and initiates a mailbox access request to the transmitting chip's physical layer through the second path 2 on the RDI interface. The physical layer transmits the mailbox access request to the receiving chip's physical layer through UCIe sideband link 3. Step 2, for the receiving phase of the receiving chip: The receiving chip's physical layer transmits the mailbox access request to the receiving chip's adapter layer through the fourth path 4 on the RDI interface. The adapter layer parses the mailbox access request transaction, completes the cross-chip register access, and initiates a mailbox access completion transaction to the receiving chip's physical layer through the fifth path 5 on the RDI interface. The physical layer transmits the mailbox completion transaction to the transmitting chip's physical layer through UCIe sideband link 6. Step 3, for the receiving chip's receiving response phase: The transmitting chip's physical layer transmits the mailbox completion transaction to the transmitting chip's adapter layer through the seventh path 7 on the RDI interface. The adapter layer parses the mailbox to complete the transaction and responds to the higher layer via path 8 on the on-chip interface with the cross-chip register access result. From a protocol layer or software perspective, traditional mailbox register configuration schemes require at least three register configuration transactions before generating a sideband access transaction. These include configuring the index register, data register, and control register. The index register stores information about the Opcode, BE, and Addr fields. In addition to these three register configuration transactions, there is also a polling transaction for the control register. The system needs to continuously poll the status of the control register to detect whether the corresponding access transaction has returned. However, the embodiments of this invention significantly reduce this to generating a sideband access transaction after only one mapping, simplifying the original at least three transactions into one transaction. This not only improves the efficiency of access transaction generation but also reduces the time spent consuming hardware resources. Furthermore, traditional methods require at least three register configuration transactions, each containing a request transaction and a completion transaction. Each transaction takes 2-4 clock cycles, and there is a several clock cycle interval between every two register configuration transactions. Therefore, three register configuration transactions require at least a dozen clock cycles. In contrast, this invention only requires one clock cycle to achieve the mapping between signals and fields, significantly improving the generation efficiency of sideband access transactions. In addition, the on-chip interface has a higher clock frequency and faster processing speed, shortening the time for cross-chip register access and improving the efficiency of cross-chip register access and transmission efficiency.

[0043] As an example, taking the APB interface, the specific operation steps are as follows: Step 1: Configure the access address, write data, and other information based on the on-chip interface timing. Taking the APB interface and a write operation as an example, the specific timing diagram is as follows. Figure 4As shown in (a), from the clock signal (PCLK), at time T1, the target address ADDR1 is configured to the address signal (PADDR), and the write data WDATA1 is configured to the write data signal (PWDATA), while the select signal (PSEL) is simultaneously set; at time T2, the enable signal (PENABLE) is set to complete the interaction of the relevant handshake signals. Step 2: Wait for the on-chip interface to return a completion signal. At time Tn, the adapter layer receives the mailbox to complete the transaction, and the ready signal (PREADY) is pulled high, indicating that the cross-chip register access is complete. The slave device error signal (PSLVERR) is not set, indicating that there is no error in the slave device. Taking the APB interface and a read operation as an example, the specific timing diagram is as follows. Figure 4 As shown in (b), at time T1, the target address ADDR1 is configured to the address signal (PADDR) and other signals, and the select signal (PSEL) is set simultaneously; at time T2, the enable signal (PENABLE) is set to complete the interaction of relevant handshake signals. Step 2: Wait for the on-chip interface to return a completion signal. At time Tn, the adapter layer receives the mailbox completion transaction, pulls the ready signal (PREADY) high, indicating that the cross-chip register access is complete, and reads the read data (RDATA1) information through the read data signal (PRDATA). Compared with traditional mailbox operations, there is no need for software or higher layers to poll the mailbox status register multiple times. Only one register access transaction needs to be initiated by the higher layer or software to complete the cross-chip register access, which greatly simplifies the cross-chip register access process.

[0044] In one implementation, when the on-chip interface uses a protocol that supports outstanding data transmission characteristics, S300 further includes: continuously sending multiple sideband request transactions and continuously monitoring the credit status of the receiving end through a detection module; wherein, the credit status is used to record the remote end's ability to receive sideband request transactions. When the credit status is greater than zero, the remote end can receive sideband request transactions; the adapter layer directly initiates a sideband request transaction. When the credit status is zero, the remote end cannot receive sideband request transactions; the adapter layer temporarily stores new sideband request transactions in a local cache queue and continuously monitors the credit status of the receiving end; when the credit status releases the ability to receive a sideband request transaction, the adapter layer initiates a sideband request transaction. For example, when the on-chip interface supports the AXI protocol and the target protocol is the UCIe protocol, a multi-channel concurrent access mechanism can be constructed through the above method: the data over-transmission characteristic of the AXI interface allows multiple new transaction access requests to be initiated before a single transaction is completed, forming a multi-level transmission queue. By combining the end-to-end credit (E2E credit) mechanism defined in the UCIe protocol, the transmission queue depth of the AXI interface is mapped to the end-to-end credit value. The end-to-end credit value of the UCIe protocol determines the AXI's data overtransmission capability. This collaborative design enables: 1) multiple register access operations to proceed in parallel, eliminating the serial waiting of traditional solutions; 2) the credit mechanism ensures data integrity and prevents buffer overflows; and 3) by dynamically adjusting the Outstanding queue and Credit threshold, an optimal balance between link utilization and power consumption is achieved, providing cross-core communication capabilities with near-memory access efficiency for heterogeneous computing scenarios, shortening the time for cross-core register access, and improving the efficiency of cross-core register access.

[0045] Other types of protocols that support outstanding data transmission features also fall within the scope of protection of this invention.

[0046] In summary, the cross-chip register access method based on the target protocol provided by this invention establishes a mapping relationship between the on-chip interface and the target protocol at the adapter layer by multiplexing the on-chip interface. Through direct configuration of the on-chip interface at higher levels, the adapter layer maps the signals of the on-chip interface to the fields of sideband transactions conforming to the target protocol and generates sideband transactions, thereby realizing sideband transaction interaction. By directly constructing the cross-chip communication path through high-level configuration, it bypasses the configuration of mailbox registers, eliminates the dependence on dedicated sideband mailbox mechanisms, requires no additional hardware, and maintains full compatibility with the UCIe protocol. A single register access transaction can complete cross-chip data interaction, shortening operation time and significantly reducing communication latency and system resource consumption. Furthermore, it is fully compatible with software operation logic, supporting the simultaneous initiation of multiple cross-chip register access operations. It provides a solution that combines technological innovation and engineering practicality for efficient communication between heterogeneous chips, effectively improving the overall system energy efficiency ratio and reducing integration design complexity.

[0047] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0048] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0049] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0050] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0051] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A cross-core register access method based on a target protocol, characterized in that, The method includes the following steps: S100, Obtain the target protocol, the target protocol including a higher layer and an adapter layer; S200, a set of on-chip interfaces are configured in the adapter layer, the on-chip interfaces including multiple pins; The adapter layer interacts with the higher layer through the on-chip interface; S300, establish a mapping relationship between multiple pins of the on-chip interface and multiple fields of the target protocol at the adapter layer. The mapping relationship includes a first mapping relationship in the transmission direction and a second mapping relationship in the reception direction. The first mapping relationship is used to map the pin signals of the on-chip interface that conform to the on-chip protocol to the fields of the sideband request transaction that conforms to the target protocol. The second mapping relationship is used to map the fields in the sideband completion transaction that conforms to the target protocol to the corresponding pins of the on-chip interface. S400, when a cross-chip register access transaction is sent, the higher layer configures the on-chip interface of the adapter layer; The adapter layer parses the on-chip interface to obtain the corresponding configuration information, maps the configuration information to the field of the sideband mailbox transaction according to the first mapping relationship, and initiates the sideband request transaction through the sideband processing module of the adapter layer according to the field of the sideband mailbox transaction. S500, when a sideband completion transaction is received, the adapter layer parses the fields in the sideband completion transaction and maps the fields in the sideband completion transaction to the corresponding pins of the on-chip interface according to the second mapping relationship; In S300, when the sending direction is a read operation, the first mapping relationship includes: the address configuration signal of the on-chip interface is mapped to the addr field of the sideband request transaction, and the read / write control signal of the on-chip interface is mapped to the opcode field of the sideband request transaction; the second mapping relationship includes: the status field of the sideband completion transaction is mapped to the reply signal of the on-chip interface, and the data field of the sideband completion transaction is mapped to the read data signal of the on-chip interface. When the transmission direction is a write operation, the first mapping relationship includes: the address configuration signal of the on-chip interface is mapped to the addr field of the sideband request transaction; the read / write control signal of the on-chip interface is mapped to the opcode field of the sideband request transaction; the strobe control signal of the on-chip interface is mapped to the BE field of the sideband request transaction; and the write data signal of the on-chip interface is mapped to the data field of the sideband request transaction. The second mapping relationship includes: the status field of the sideband completion transaction is mapped to the reply signal of the on-chip interface.

2. The method according to claim 1, characterized in that, S400 also includes: continuously sending multiple sideband request transactions and continuously monitoring the credit status of the receiving end through a detection module; wherein, the credit status is used to record the ability to receive sideband request transactions; When the credit status is greater than zero, sideband request transactions can be received; the adapter layer directly initiates sideband request transactions. When the credit status is zero, sideband request transactions cannot be received; the on-chip interface temporarily stores new sideband request transactions in the local cache queue and continuously monitors the credit status of the receiving end; when the credit status releases the ability to receive a sideband request transaction, the adapter layer initiates a sideband request transaction.

3. The method according to claim 1, characterized in that, The standard for the on-chip interface is AMBA, APB, AHB, or AXI.

4. The method according to claim 1, characterized in that, The target protocol is the UCIe protocol.

5. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-4.

6. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 5.

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