Interrupt debugging device and method and artificial intelligence chip

Abstract

The invention provides an interrupt debugging device and method and an artificial intelligence chip, and relates to the technical field of artificial intelligence, and the device comprises an interrupt generation unit which is used for detecting abnormal behaviors generated by each function unit in the process that the artificial intelligence chip executes an original program and generating an interrupt request signal; the interrupt transmission link is used for transmitting the interrupt request signals generated by the interrupt generation units; and the interrupt collection unit is used for generating an interrupt enable signal based on the interrupt request signal generated by each interrupt generation unit and sending the interrupt enable signal to the scheduling control unit, so that the scheduling control unit determines a target thread bundle based on the interrupt enable signal and controls the target thread bundle to execute a debugging program. According to the device and the method provided by the invention, a breakpoint does not need to be set in an original program, and the original program does not need to be modified; the method is suitable for dynamically triggering debugging in the multi-thread beam parallel computing process, so that developers can more accurately position and solve problems, and the debugging efficiency and accuracy are greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to an interrupt debugging device, method and artificial intelligence chip. Background Art

[0002] With the continuous development of information technology, the continuous expansion of program scale and the continuous increase in complexity, software developers will encounter a large number of development problems during the program development process. How to effectively assist software developers in quickly locating and eliminating faults has become a key issue in debugging work.

[0003] Debugging methods used in related technologies involve setting breakpoints and single-stepping. In parallel computing, software programs are relatively large and complex, making setting breakpoints difficult and limiting. Hardware breakpoints rely on the number of debug address registers reserved in the hardware, which is subject to limitations. Once the single-step registers are enabled, the original program enters debug mode for each instruction executed, triggering even locations where debugging is not required, resulting in low debugging efficiency.

[0004] Therefore, how to improve the efficiency and accuracy of software program debugging in parallel computing has become a technical problem that needs to be solved urgently in the industry. Summary of the Invention

[0005] The present invention provides an interrupt debugging device, method and artificial intelligence chip for solving the technical problem of how to improve the efficiency and accuracy of software program debugging in parallel computing.

[0006] The present invention provides an interrupt debugging device, comprising an interrupt generating unit, an interrupt collecting unit and an interrupt transmission link; The interrupt generating unit is connected to each functional unit of the artificial intelligence chip, and is used to detect abnormal behavior generated by each functional unit during the execution of the original program by the artificial intelligence chip and generate an interrupt request signal; The interrupt transmission link is connected to the interrupt generating unit and the interrupt collecting unit, and is used to transmit the interrupt request signal generated by each interrupt generating unit; The interrupt collection unit is connected to the scheduling control unit of the artificial intelligence chip, and is used to generate an interrupt enable signal based on the interrupt request signal generated by each interrupt generation unit, and send the interrupt enable signal to the scheduling control unit so that the scheduling control unit determines the target thread warp based on the interrupt enable signal and controls the target thread warp to execute the debugger.

[0007] In some embodiments, the interrupt transmission link includes a plurality of transmission registers and a plurality of selectors alternately connected in sequence; each selector is respectively connected to each interrupt generating unit; The current transmission register is used to store the interrupt request signal sent by the previous selector; The current selector is used to compare the priority of the first interrupt request signal sent by the previous transmission register and the priority of the second interrupt request signal sent by the interrupt generation unit connected to the current selector, and send the first interrupt request signal or the second interrupt request signal based on the comparison result.

[0008] In some embodiments, the interrupt collection unit includes an interrupt enable register; the interrupt enable register corresponds to the interrupt generation unit; The interrupt enable register is configured to enable or mask the interrupt request signal sent by the interrupt generating unit based on a preset value in the interrupt enable register.

[0009] In some embodiments, the interrupt enable register includes a plurality of first bits; the first bits correspond to the interrupt type generated by the interrupt generating unit; The first bit is configured to: enable an interrupt request signal of the interrupt type when the value of the first bit is a first preset value; and shield the interrupt request signal of the interrupt type when the value of the first bit is a second preset value.

[0010] In some embodiments, the interrupt enable register includes a plurality of second bits; the second bits correspond to the warp control units; The second bit is configured as follows: when the value of the second bit is a first preset value, the thread warp control unit corresponding to the second bit is allowed to execute the debug program; when the value of the second bit is a second preset value, the thread warp control unit corresponding to the second bit is prohibited from executing the debug program.

[0011] In some embodiments, the functional unit includes at least one of a decoding and parsing unit, a calculation unit, and a storage unit.

[0012] In some embodiments, the interrupt request signal includes at least one of an original program instruction address, an interrupt type, an interrupt generating unit number, a warp control unit number, and an original program number.

[0013] The present invention provides an interrupt debugging method, which is applied to the interrupt debugging device, comprising: Receive the current interrupt request signal; Determine, based on the functional unit number in the current interrupt request signal, a target functional unit for requesting interrupt debugging, and an interrupt enable register corresponding to the target functional unit; generating an interrupt enable signal corresponding to the current interrupt request signal based on a preset value in the interrupt enable register; The interrupt enable signal is sent to a scheduling control unit, so that the scheduling control unit determines a target warp based on the interrupt enable signal and controls the target warp to execute a debugger.

[0014] The present invention provides an artificial intelligence chip, comprising a plurality of functional units and the interrupt debugging device described above; The interrupt debugging device is used to detect abnormal behavior of each functional unit and generate an interrupt request signal when the artificial intelligence chip executes the original program, and determine the target thread warp based on the interrupt request signal, and control the target thread warp to execute the debugging program.

[0015] The present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and operable on the processor. When the processor executes the computer program, the interrupt debugging method is implemented.

[0016] The interrupt debugging device, method and artificial intelligence chip provided by the present invention, due to the provision of an interrupt generation unit connected to each functional unit of the artificial intelligence chip, can detect abnormal behavior of each functional unit and generate an interrupt request signal, without the need to set breakpoints in the original program or modify the original program; the interrupt request signal is quickly transmitted to the interrupt collection unit via an interrupt transmission link, thereby improving the real-time performance of debugging; when debugging is triggered, the interrupt collection unit controls the execution of the scheduling control unit, and can select relevant thread bundles to execute the debugging program without introducing redundant debugging; it is suitable for dynamically triggering debugging during parallel computing of multiple thread bundles, allowing developers to more accurately locate and solve problems, greatly improving debugging efficiency and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 It is a structural diagram of the interrupt debugging device provided by the present invention.

[0020] Figure 2 This is one of the structural diagrams of the artificial intelligence chip provided by the present invention.

[0021] Figure 3 It is a structural diagram of the interrupt transmission link provided by the present invention.

[0022] Figure 4 It is a structural diagram of the interrupt enable register provided by the present invention.

[0023] Figure 5 It is a schematic diagram of the operation of the interrupt collection unit provided by the present invention.

[0024] Figure 6 It is a schematic diagram of the operation of the scheduling control unit provided by the present invention.

[0025] Figure 7 It is a schematic diagram of the execution flow of the debugging program provided by the present invention.

[0026] Figure 8 It is a flow chart of the interrupt debugging method provided by the present invention.

[0027] Figure 9 This is the second structural diagram of the artificial intelligence chip provided by the present invention.

[0028] Figure 10 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," and the like in the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps, units, or modules is not necessarily limited to those steps, units, or modules that are explicitly listed, but may include other steps, units, or modules that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0031] The debugging methods in related technologies have the following deficiencies: (1) Setting breakpoints in software programs presents difficulties and limitations. Current software programs are large in scale and complexity, often requiring repeated experimentation to locate the problem. Furthermore, setting breakpoints in software requires modifying the original program content, which may mask the original problem and increase debugging difficulties. Setting breakpoints in software has high requirements and limitations.

[0032] (2) Hardware breakpoints rely on the number of debug address registers reserved in the hardware, which is easily limited in number. They can only debug the instruction sequence of the program. They also have high usage requirements and require developers to list potential problem points and experiment one by one, which usually needs to be done multiple times.

[0033] (3) Once the single-step execution register is enabled, the original program will enter debug mode every time it executes an instruction, and then execute the debug program. This method introduces redundant debugging and triggers at locations that do not need debugging, resulting in low debugging efficiency.

[0034] (4) It can only be applied to single-thread execution debugging. In parallel computing, in addition to the execution of the current thread bundle, the execution status of other thread bundles also affects the behavior of the artificial intelligence chip.

[0035] In order to solve the shortcomings of related technologies, Figure 1 This is a schematic diagram of the structure of the interrupt debugging device provided by the present invention. Figure 1 As shown, the interrupt debugging device 100 includes an interrupt generating unit 110 , an interrupt collecting unit 120 and an interrupt transmission link 130 .

[0036] An interrupt generating unit, connected to each functional unit of the artificial intelligence chip, is used to detect abnormal behavior of each functional unit during the execution of the original program by the artificial intelligence chip and generate an interrupt request signal; An interrupt transmission link, connected to the interrupt generating unit and the interrupt collecting unit, for transmitting the interrupt request signal generated by each interrupt generating unit; The interrupt collection unit is connected to the scheduling control unit of the artificial intelligence chip, and is used to generate an interrupt enable signal based on the interrupt request signal generated by each interrupt generation unit, and send the interrupt enable signal to the scheduling control unit so that the scheduling control unit determines the target thread bundle based on the interrupt enable signal and controls the target thread bundle to execute the debugger.

[0037] Specifically, AI chips often employ instruction pipelining to improve instruction execution efficiency and throughput. This technology breaks down the execution of an instruction into multiple independent stages, each managed by a different functional unit. These units include the instruction cache, instruction fetch unit, decoding and parsing unit, scheduling and control unit, arithmetic unit, and storage unit.

[0038] The interrupt debugging device provided by the present invention aims to address the challenges of debugging artificial intelligence chips during the execution of multiple warps, improving debugging efficiency and accuracy. This device implements single-step debugging through a hardware interrupt trigger mechanism and supports dynamic debugging triggering during warp execution, enabling developers to more accurately locate and resolve issues. The interrupt debugging device can be a separate hardware structure within the artificial intelligence chip.

[0039] Structurally, the interrupt debugging device includes an interrupt generating unit, an interrupt collecting unit and an interrupt transmission link.

[0040] The interrupt generation unit is connected to the various functional units of the AI ​​chip. A functional unit refers to a module within the AI ​​chip that performs a specific function. This can include a decoding and parsing unit, a computing unit, a storage unit, an instruction cache unit, an instruction fetch unit, and a scheduling control unit.

[0041] The interrupt generation unit is used to detect abnormal behavior of various functional units during the execution of the original program by the AI ​​chip and generate an interrupt request signal. The original program refers to the initial version of the program—that is, the program code that has not been modified, optimized, or debugged. The interrupt request signal here is issued when a functional unit triggers a specific abnormal event (such as an illegal instruction or data access error) while executing program instructions, indicating that an interrupt is required.

[0042] Interrupt generation units can be divided into multiple categories, connected to or installed in various functional units, to detect abnormal behavior and generate interrupt request signals. For example, an instruction interrupt generation unit can be installed in the decoding and parsing unit to detect illegal instructions generated during instruction decoding; a calculation interrupt generation unit can be installed in the operation unit to detect illegal operations during the calculation process; and a memory access interrupt generation unit can be installed in the storage unit to detect illegal memory access.

[0043] The interrupt transmission link connects to the interrupt generating unit and the interrupt collection unit and is used to transmit the interrupt request signals generated by each interrupt generating unit. The interrupt transmission link can adopt a variety of topologies, such as star, tree, or linear. In an embodiment of the present invention, to improve efficiency and simplify the internal wiring structure of the artificial intelligence chip, the interrupt transmission link adopts a daisy-chain linear topology, connecting each interrupt generating unit in sequence to transmit the interrupt request signal.

[0044] After receiving interrupt request signals from each interrupt generating unit, the interrupt collection unit determines whether to generate an interrupt enable signal based on the relevant configuration. This interrupt enable signal allows interrupts and debugging. If an interrupt enable signal is generated, it is sent to the scheduling control unit in the AI ​​chip. The scheduling control unit determines the target thread warp based on the interrupt enable signal and controls the target thread warp to execute the debugger. The debugger is program code used to detect, locate, and fix bugs in the original program.

[0045] A warp is a collection of threads that share the same instruction stream during execution. In AI chips, both the source program and the debugger are executed by warps. The target warp is the warp that is associated with the interrupt request signal and needs to execute the debugger.

[0046] An interrupt debugging device provided by an embodiment of the present invention includes an interrupt generating unit, an interrupt collecting unit, and an interrupt transmission link. The interrupt generating unit is configured to detect abnormal behavior generated by each functional unit during execution of an original program by an artificial intelligence chip and generate an interrupt request signal. The interrupt transmission link is configured to transmit the interrupt request signals generated by each interrupt generating unit. The interrupt collecting unit is configured to generate an interrupt enable signal based on the interrupt request signal generated by each interrupt generating unit and transmit the interrupt enable signal to a scheduling control unit, so that the scheduling control unit determines a target thread warp based on the interrupt enable signal and controls the target thread warp to execute a debug program. Due to the provision of an interrupt generating unit connected to each functional unit of the artificial intelligence chip, abnormal behavior of each functional unit can be detected and an interrupt request signal can be generated, eliminating the need to set breakpoints in the original program or modify the original program. The interrupt request signal is quickly transmitted to the interrupt collecting unit via the interrupt transmission link, thereby improving the real-time performance of debugging. When debugging is triggered, the interrupt collecting unit controls the scheduling control unit to execute, and can select the relevant thread warp to execute the debug program, eliminating the introduction of redundant debugging. The device is suitable for dynamically triggering debugging during parallel computing of multiple thread warps, allowing developers to more accurately locate and resolve problems, greatly improving debugging efficiency and accuracy.

[0047] In some embodiments, the functional unit includes at least one of a decoding and parsing unit, an operation unit, and a storage unit.

[0048] Specifically, Figure 2 This is one of the structural diagrams of the artificial intelligence chip provided by the present invention, such as Figure 2 As shown, in addition to the debug registers, instruction cache unit, thread bundle control unit (specifically including instruction acquisition unit, decoding and parsing unit and scheduling control unit), operation unit and storage unit, the artificial intelligence chip is also equipped with an interrupt generation unit, an interrupt collection unit and an interrupt transmission link.

[0049] The debug register is used to store the instruction address of the debug program. The scheduling control unit is used to obtain the debug register and program instruction information, trigger the debug jump and preserve the execution status of the original program.

[0050] Interrupt generation units are used to detect abnormal behavior in functional units and generate interrupts. They are distributed across various functional units of the AI ​​chip, including the decoding and parsing unit, the arithmetic unit, and the storage unit. Accordingly, the interrupt generation units include instruction interrupt generation units, calculation interrupt generation units, and memory access interrupt generation units.

[0051] The instruction interruption generating unit corresponds to the thread warp control unit in the artificial intelligence chip. Each instruction interruption generating unit is set in the decoding and parsing unit.

[0052] The interrupt transmission link connects the instruction interrupt generation unit and other interrupt generation units (including calculation interrupt generation unit and memory access interrupt generation unit, etc.) of each thread warp control unit in sequence, and transmits the interrupt request signal generated by each functional unit to the interrupt collection unit.

[0053] The interrupt collection unit is used to aggregate the generated interrupts and generate an interrupt enable signal.

[0054] The AI ​​chip is connected to the central processing unit (CPU). The CPU is used to configure the debug registers in the AI ​​chip, load the original program and debug program into the instruction cache unit, and receive interrupt information reported by the interrupt collection unit.

[0055] The interrupt debugging device provided by the embodiment of the present invention respectively sets an interrupt generating unit in the decoding and parsing unit, the operation unit and the storage unit, and receives the interrupt request signal sent by each interrupt generating unit. There is no need to set breakpoints in the original program or modify the original program. It is suitable for dynamically triggering debugging during the parallel computing of multiple thread bundles, allowing developers to locate and solve problems more accurately, greatly improving debugging efficiency.

[0056] In some embodiments, the interrupt request signal includes at least one of an original program instruction address, an interrupt type, an interrupt generating unit number, a warp control unit number, and an original program number.

[0057] Specifically, to facilitate transmission of the interrupt request signal in the interrupt transmission link, the data format of the interrupt request signal generated by each interrupt generating unit may be uniformly set, as shown in Table 1. The interrupt request signal may be represented by a data width of 64 bits.

[0058] Table 1 Data format of interrupt request signal

[0059] The decoding and parsing unit has functions related to instructions. It detects illegal instructions that do not conform to the definition obtained by the instruction acquisition unit, such as instruction data is all 0 or all 1; instruction data is an illegal instruction; the number of operands exceeds the limit, etc.

[0060] For the arithmetic unit, its function is related to instruction execution, and it detects illegal input or illegal results during instruction calculation, such as errors in floating-point instruction calculation results; reading and writing the same address of the storage unit at the same time; special function instructions do not comply with the function definition; instructions that do not support a certain data type are forced to input data of that type, etc.

[0061] For storage units, detect unreasonable storage accesses, such as access address out of bounds; access address not meeting design definition; atomic operation error; storage access error, etc.

[0062] If there are many types of interrupts generated, they can also be defined using the reserved fields in the data format.

[0063] The interrupt debugging device provided by the embodiment of the present invention uniformly represents the data format of the interrupt request signal, which can improve the transmission efficiency and accuracy of the interrupt request signal, allowing developers to locate and solve problems more accurately, greatly improving debugging efficiency.

[0064] In some embodiments, the interrupt transmission link includes a plurality of transmission registers and a plurality of selectors alternately connected in sequence; each selector is respectively connected to each interrupt generating unit; The current transmission register is used to store the interrupt request signal sent by the previous selector; The current selector is used to compare the priority of the first interrupt request signal sent by the previous transmission register and the priority of the second interrupt request signal sent by the interrupt generation unit connected to the current selector, and send the first interrupt request signal or the second interrupt request signal based on the comparison result.

[0065] Specifically, Figure 3This is a schematic diagram of the structure of the interrupt transmission link provided by the present invention. Figure 3 As shown, the interrupt transmission link includes multiple transmission registers and multiple selectors, wherein the transmission registers and the selectors are alternately connected in sequence.

[0066] Any transfer register in the interrupt transmission chain is designated as the current transfer register. The current transfer register is used to store the interrupt request signal sent by the previous selector. During each clock cycle, the interrupt request signal can only be output from the previous transfer register, selected by the previous selector, and then transferred to the current register for storage.

[0067] Each selector is connected to the interrupt generation unit corresponding to each functional unit, such as the instruction interrupt generation unit, the calculation interrupt generation unit, and the memory access interrupt generation unit. Any selector in the interrupt transmission chain is considered the current selector. The current selector's inputs include the first interrupt request signal sent by the previous transmission register and the second interrupt request signal sent by the interrupt generation unit connected to the current selector. The current selector compares the priority of the two interrupt request signals and sends either the first interrupt request signal or the second interrupt request signal based on the comparison result.

[0068] Generally, the interrupt request signal from the upstream of the interrupt transmission link can be set to have a higher priority, that is, the first interrupt request signal has a higher priority. The priority of the interrupt request signal can also be set according to the importance of the functional unit or the generation time of the interrupt request signal.

[0069] The interrupt transmission link transmits the interrupt request signal and related data to the interrupt collection unit. At most one interrupt request signal is received by the interrupt collection unit per clock cycle. The interrupt transmission link can be expanded according to the functional units of the artificial intelligence chip.

[0070] The interrupt debugging device provided by the embodiment of the present invention constructs an interrupt transmission link by alternately connecting transmission registers and selectors in sequence, thereby solving the problems of data storage and transmission, improving the transmission efficiency and accuracy of interrupt request signals, allowing developers to locate and solve problems more accurately, and greatly improving debugging efficiency.

[0071] In some embodiments, the interrupt collection unit includes an interrupt enable register; the interrupt enable register corresponds to the interrupt generation unit; The interrupt enable register is configured to enable or mask the interrupt request signal sent by the interrupt generating unit based on a preset value in the interrupt enable register.

[0072] Specifically, an interrupt enable register may be set in the interrupt collection unit. The interrupt enable register corresponds to the interrupt generating unit in a one-to-one manner, that is, a corresponding interrupt enable register is set for each interrupt generating unit that can generate an interrupt request signal.

[0073] According to the type of functional unit corresponding to the interrupt generating unit, the interrupt enable register can be classified into instruction interrupt enable register, calculation interrupt enable register and memory access interrupt enable register.

[0074] For example, an artificial intelligence chip contains N thread warp control units. These thread warp control units can share computing units and storage units. Considering that computing units and storage units occupy a large chip area, in order to save chip area and balance chip performance and area, these thread warp control units share M computing units and K storage units. M is any positive integer from 1 to N; K is any positive integer from 1 to N. When M and K are both 1, it means that all thread warp control units share 1 computing unit and 1 storage unit; when M and K are both N, it means that all thread warp control units have their own corresponding computing units and storage units.

[0075] Figure 4 Schematic diagram of the structure of the interrupt enable register provided by the present invention, such as Figure 4 As shown, N instruction interrupt enable registers can be set for N thread warp control units, namely registers r1 to r(N); M calculation interrupt enable registers can be set for M computing units, namely registers r(N+1) to r(N+M); and K memory access interrupt enable registers can be set for K computing units, namely registers r(N+M+1) to r(N+M+K).

[0076] The size of each interrupt enable register can be set, for example, it can be set to 32 bits, or it can be set according to actual needs.

[0077] The interrupt enable register can be configured to set a preset value and store it in the interrupt enable register. Based on the preset value, it can be determined whether to enable the interrupt request signal sent by the interrupt generating unit (allowing debugging to be triggered) or to mask the interrupt request signal sent by the interrupt generating unit (disabling debugging to be triggered).

[0078] Whether the instruction interrupt generated by the corresponding decoding and parsing unit is valid can be determined according to the preset value in the instruction interrupt enable register. If it is valid, it is enabled; otherwise, it is masked.

[0079] Whether the interrupt generated during the execution of the operation unit is valid can be determined based on the preset value in the calculation interrupt enable register. If it is valid, it is enabled; otherwise, it is masked.

[0080] Whether the interrupt when the storage unit is read or written is valid can be determined based on the preset value in the memory access interrupt enable register. If it is valid, it is enabled; otherwise, it is masked.

[0081] The interrupt debugging device provided by the embodiment of the present invention can enable or shield the interrupt request signal sent by each interrupt generating unit by setting the interrupt enable register, and can selectively implement interrupt debugging, so that developers can locate and solve problems more accurately, greatly improving debugging efficiency and accuracy.

[0082] In some embodiments, the interrupt enable register includes a plurality of first bits; the first bits correspond to the type of interrupt generated by the interrupt generating unit; The first bit is configured to: enable an interrupt request signal of a corresponding interrupt type when the value of the first bit is a first preset value; and shield an interrupt request signal of a corresponding interrupt type when the value of the first bit is a second preset value.

[0083] Specifically, a plurality of first bits may be set in the interrupt enable register. Each first bit corresponds to an interrupt type generated by the interrupt generating unit. It is possible to determine whether to enable or shield the interrupt request signal corresponding to the interrupt type based on the preset value of the first bit.

[0084] The first bit can be configured before the original program starts executing. When the value of the first bit is a first preset value (e.g., 1), the interrupt request signal of the corresponding interrupt type is enabled; when the value of the first bit is a second preset value (e.g., 0), the interrupt request signal of the corresponding interrupt type is disabled.

[0085] For the interrupt collection unit, if an interrupt request signal of a certain interrupt type is received, the first bit in the interrupt enable register is queried. If it is 1, an interrupt enable signal is generated; if it is 0, it is directly discarded and no interrupt enable signal is generated.

[0086] For example, for a given original program and a certain interrupt type, if the developer believes that instruction data set to all 0s or all 1s will not affect the program's execution, they can set bit[0] of interrupt enable register instructions r1 through rN to 0 (bit[0] corresponds to the interrupt type). When threads 1 through N generate this interrupt, they are transmitted to the interrupt collection unit. The interrupt collection unit queries the corresponding bits r1 through rN based on the source information and then queries bit[0] based on the type. If the bit[0] is 0, the interrupt is discarded, without affecting the thread warp's execution of the original program. The same configuration and operating principles apply to other interrupt enable types.

[0087] The interrupt debugging device provided in the embodiment of the present invention can enable or shield different types of interrupt request signals according to the preset value of the first bit in the interrupt enable register, and can selectively implement interrupt debugging, so that developers can locate and solve problems more accurately, greatly improving debugging efficiency and accuracy.

[0088] In some embodiments, the interrupt enable register includes a plurality of second bits; the second bits correspond to the warp control units; The second bit is configured as follows: when the value of the second bit is a first preset value, the thread warp control unit corresponding to the second bit is allowed to execute the debug program; when the value of the second bit is a second preset value, the thread warp control unit corresponding to the second bit is prohibited from executing the debug program.

[0089] Specifically, multiple second bits can be set in the interrupt enable register. Each second bit corresponds to a warp control unit. It can be implemented to determine whether the interrupt can ignore certain warp control units based on the preset value of the second bit.

[0090] The second bit can be configured before the original program starts executing. When the value of the second bit is a first preset value (for example, 1), the warp control unit corresponding to the second bit is allowed to execute the debugger (not ignored). When the value of the first bit is a second preset value (for example, 0), the warp control unit corresponding to the second bit is prohibited from executing the debugger (ignored).

[0091] For example, the compute interrupt enable register includes N second bits, each corresponding to one of the N thread control units. The second bit corresponding to warp control unit 1 is 0, while the second bits corresponding to warp control units 2 through N are 1. Based on the interrupt request signal sent by the compute unit, the interrupt collection unit queries the second bits in the compute interrupt enable register to determine whether to prohibit warp control unit 1 from executing the debugger and whether to allow warp control units 2 through N to execute the debugger.

[0092] The interrupt debugging device provided by the embodiment of the present invention can enable debugging of different thread warp control units according to the preset value of the second bit in the interrupt enable register, so that developers can locate and solve problems more accurately, greatly improving debugging efficiency and accuracy.

[0093] In some embodiments, Figure 5 This is a schematic diagram of the operation of the interrupt collection unit provided by the present invention, such as Figure 5As shown in the figure, the interrupt collection unit receives interrupt data from each module through the interrupt transmission link. It determines whether to generate an interrupt based on the interrupt enable register configured on the host (usually the central controller) and reports the interrupt to the host. By parsing the interrupt data, it can be determined which instruction in which program and in which module caused a certain type of interrupt.

[0094] In some embodiments, Figure 6 This is a schematic diagram of the operation of the scheduling control unit provided by the present invention, such as Figure 6 As shown, the scheduling control unit receives debug enable and instruction decode information. In normal mode, upon receiving the instruction information, the execution resource check is performed before sending it to the arithmetic unit for execution. Upon receiving debug enable, the hardware generates a debug jump instruction and caches the instruction address of the original program. The debug jump is then executed, and upon exiting the debugger, the execution state of the original program is restored.

[0095] In some embodiments, Figure 7 This is a schematic diagram of the execution flow of the debugging program provided by the present invention, such as Figure 7 As shown, the debug register and interrupt enable register can be configured on the host side (Host), respectively defining the starting address of the debugger and which interrupts are ignored or enabled for debugging, and receiving interrupt reports from the interrupt collection unit.

[0096] The debugger defines the hardware's execution behavior after entering debug mode, implementing the execution behavior definition of the thread warp. It determines whether to generate an interrupt enable signal based on the interrupt request signal. If not, the original program continues to execute; if so, an interrupt enable signal is generated.

[0097] The interrupt enable signal is sent to the scheduling control unit, so that the scheduling control unit determines the target thread warp based on the interrupt enable signal and controls the target thread warp to execute the debug program. After the debug program ends, the original program is resumed.

[0098] Based on the above embodiment, the present invention describes the entire process of the interrupt debugging method provided, which includes the following steps: Step 1: The host initializes the debug register and interrupt enable register, sets the starting address of the debug program, and determines which interrupt types are allowed to enable debugging during the running of the original program.

[0099] Step 2: The host loads the original program and the debugger into the instruction cache unit.

[0100] Step 3: Each thread warp starts running the original program. The instruction acquisition unit sends an instruction fetch request to the instruction cache unit, and the instruction cache returns the instruction.

[0101] Step 4: The decoding and parsing unit parses the instruction content and transmits it to the scheduling control unit. At the same time, the instruction interrupt generating unit determines whether to generate an instruction interrupt.

[0102] Step 5: The dispatch control unit manages and allocates the instruction information, sending it to the execution unit for processing. The instruction source is selected based on whether debugging is enabled. If debugging is not enabled, the instruction from the decoder and parser is selected; otherwise, the hardware-generated debug jump instruction is selected. When debugging is enabled, the original program instruction address must be saved in the original program register to facilitate resuming execution.

[0103] Step 6: During the instruction execution process, the interrupt generation units in the operation unit and the storage unit also continuously determine whether an interrupt is generated and send it to the interrupt collection unit through the interrupt transmission link.

[0104] Step 7: After receiving an interrupt, the interrupt collection unit searches the interrupt enable register for the corresponding bit based on the interrupt information and determines how to handle the interrupt. If the interrupt register is not enabled, the interrupt is discarded. If the interrupt register is enabled, a debug enable flag is generated for the scheduling control unit, causing the corresponding warp to enter debug mode and reporting the interrupt to the host.

[0105] Other warps are not affected.

[0106] Step 8: After the corresponding thread bundle has finished executing all debug programs, the original program instruction address is obtained and the execution of the original program is resumed.

[0107] Step 9: All thread warps continue to execute the original program until it ends.

[0108] The interrupt debugging method provided by the present invention has the following beneficial effects: (1) Supports hardware dynamic detection interrupt triggering during program operation, eliminating the need to think about breakpoint settings in the software program, reducing repeated experiments when locating problems, and making debugging fast and efficient; (2) Compared with hardware breakpoint debugging, it is not limited by the number of hardware trigger registers and supports more debugging breakpoints; (3) It is easy to use, reduces debugging difficulties, does not require modification of the original program, and supports debugging functions when multiple thread bundles are executed in parallel; (4) The interrupt transmission link adopts a daisy-chain structure, which does not affect the original data transmission path in the chip, avoids complex wiring, and reduces the chip area of ​​physical implementation.

[0109] The method provided by the embodiment of the present invention is described below. The method described below and the device described above can be referenced to each other.

[0110] Figure 8FIG. 1 is a flow chart of the interrupt debugging method provided by the present invention, as shown in FIG. Figure 8 As shown, the method is applied to the interrupt debugging device in the above embodiment, including: Step 810: Receive a current interrupt request signal; Step 820: Determine the target functional unit for which interrupt debugging is requested, and the interrupt enable register corresponding to the target functional unit, based on the functional unit number in the current interrupt request signal; Step 830: Generate an interrupt enable signal corresponding to the current interrupt request signal based on the preset value in the interrupt enable register; Step 840: Send the interrupt enable signal to the scheduling control unit, so that the scheduling control unit determines the target warp based on the interrupt enable signal and controls the target warp to execute the debugger.

[0111] Specifically, the target functional unit refers to a functional unit in which an abnormal behavior occurs and an interrupt is generated by a corresponding interrupt generating unit.

[0112] The interrupt debugging method provided by the embodiment of the present invention, due to the provision of an interrupt generation unit connected to each functional unit of the artificial intelligence chip, can detect abnormal behavior of each functional unit and generate an interrupt request signal, without the need to set breakpoints in the original program or modify the original program; the interrupt request signal is quickly transmitted to the interrupt collection unit through the interrupt transmission link, thereby improving the real-time performance of debugging; when debugging is triggered, the interrupt collection unit controls the execution of the scheduling control unit, and can select relevant thread bundles to execute the debugging program without introducing redundant debugging; it is suitable for dynamically triggering debugging during parallel computing of multiple thread bundles, allowing developers to more accurately locate and solve problems, greatly improving debugging efficiency and accuracy.

[0113] Figure 9 This is the second structural diagram of the artificial intelligence chip provided by the present invention, such as Figure 9 As shown, the artificial intelligence chip 900 includes multiple functional units 910 and the interrupt debugging device 100 in the above embodiment.

[0114] The interrupt debugging device is used to detect abnormal behavior of each functional unit and generate an interrupt request signal during the execution of the original program by the artificial intelligence chip, and determine the target thread bundle based on the interrupt request signal, and control the target thread bundle to execute the debugging program.

[0115] The artificial intelligence chip provided by the embodiment of the present invention has an interrupt debugging device, which eliminates the need to set breakpoints in the original program or modify the original program. It is suitable for dynamically triggering debugging during multi-threaded bundle parallel computing, allowing developers to more accurately locate and solve problems, greatly improving debugging efficiency and accuracy.

[0116] Figure 10 Schematic diagram of the structure of the electronic device provided by the present invention, such as Figure 10 As shown, the electronic device may include: a processor (Processor) 1010, a communication interface (Communications Interface) 1020, a memory (Memory) 1030 and a communication bus (Communications Bus) 1040, wherein the processor 1010, the communication interface 1020, and the memory 1030 communicate with each other via the communication bus 1040. The processor 1010 may call the logic commands in the memory 1030 to execute the method described in the above embodiments, for example: Receive the current interrupt request signal; determine the target functional unit for requesting interrupt debugging and the interrupt enable register corresponding to the target functional unit based on the functional unit number in the current interrupt request signal; generate an interrupt enable signal corresponding to the current interrupt request signal based on the preset value in the interrupt enable register; send the interrupt enable signal to the scheduling control unit, so that the scheduling control unit determines the target thread bundle based on the interrupt enable signal and controls the target thread bundle to execute the debugging program.

[0117] Furthermore, the logical commands in the aforementioned memory can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several commands for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0118] The processor in the electronic device provided by the embodiment of the present invention can call the logic instructions in the memory to implement the above method. Its specific implementation method is consistent with the implementation method of the above method and can achieve the same beneficial effects, which will not be repeated here.

[0119] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method provided in the above embodiments is implemented.

[0120] Its specific implementation is consistent with the aforementioned method implementation and can achieve the same beneficial effects, so it will not be repeated here.

[0121] An embodiment of the present invention provides a computer program product, including a computer program. When the computer program is executed by a processor, the method described above is implemented.

[0122] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0123] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An interrupt debugging device, characterized in that: It includes an interruption generating unit, an interruption collecting unit and an interruption transmission link; The interrupt generating unit is connected to each functional unit of the artificial intelligence chip, and is used to detect abnormal behavior generated by each functional unit during the execution of the original program by the artificial intelligence chip and generate an interrupt request signal; The interrupt transmission link is connected to the interrupt generating unit and the interrupt collecting unit, and is used to transmit the interrupt request signal generated by each interrupt generating unit; The interrupt collection unit is connected to the scheduling control unit of the artificial intelligence chip, and is used to generate an interrupt enable signal based on the interrupt request signal generated by each interrupt generation unit, and send the interrupt enable signal to the scheduling control unit so that the scheduling control unit determines the target thread warp based on the interrupt enable signal and controls the target thread warp to execute the debugger.

2. The interrupt debugging device according to claim 1, wherein: The interrupt transmission link includes a plurality of transmission registers and a plurality of selectors that are alternately connected in sequence; each selector is respectively connected to each interrupt generating unit; The current transmission register is used to store the interrupt request signal sent by the previous selector; The current selector is used to compare the priority of the first interrupt request signal sent by the previous transmission register and the priority of the second interrupt request signal sent by the interrupt generation unit connected to the current selector, and send the first interrupt request signal or the second interrupt request signal based on the comparison result.

3. The interrupt debugging device according to claim 1, wherein: The interrupt collection unit includes an interrupt enable register; the interrupt enable register corresponds to the interrupt generating unit; The interrupt enable register is configured to enable or mask the interrupt request signal sent by the interrupt generating unit based on a preset value in the interrupt enable register.

4. The interrupt debugging device according to claim 3, wherein: The interrupt enable register includes a plurality of first bits; the first bits correspond to the interrupt types generated by the interrupt generating unit; The first bit is configured to: enable an interrupt request signal of the interrupt type when the value of the first bit is a first preset value; and shield the interrupt request signal of the interrupt type when the value of the first bit is a second preset value.

5. The interrupt debugging device according to claim 3, wherein: The interrupt enable register includes a plurality of second bits; the second bits correspond to the warp control units; The second bit is configured to: when the value of the second bit is a first preset value, allow the thread warp control unit corresponding to the second bit to execute the debugger; When the value of the second bit is a second preset value, the warp control unit corresponding to the second bit is prohibited from executing the debugger.

6. The interrupt debugging device according to any one of claims 1 to 5, characterized in that: The functional unit includes at least one of a decoding and parsing unit, a calculation unit and a storage unit.

7. The interrupt debugging device according to any one of claims 1 to 5, characterized in that: The interrupt request signal includes at least one of an original program instruction address, an interrupt type, an interrupt generating unit number, a warp control unit number, and an original program number.

8. An interrupt debugging method, characterized in that: The interrupt debugging device according to any one of claims 1 to 7 comprises: Receive the current interrupt request signal; Determine, based on the functional unit number in the current interrupt request signal, a target functional unit for requesting interrupt debugging, and an interrupt enable register corresponding to the target functional unit; generating an interrupt enable signal corresponding to the current interrupt request signal based on a preset value in the interrupt enable register; The interrupt enable signal is sent to a scheduling control unit, so that the scheduling control unit determines a target warp based on the interrupt enable signal and controls the target warp to execute a debugger.

9. An artificial intelligence chip, characterized in that: comprising a plurality of functional units, and the interrupt debugging device according to any one of claims 1 to 7; The interrupt debugging device is used to detect abnormal behavior of each functional unit and generate an interrupt request signal when the artificial intelligence chip executes the original program, and determine the target thread warp based on the interrupt request signal, and control the target thread warp to execute the debugging program.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the interrupt debugging method according to claim 8 is implemented.

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