Case cascading device and method supporting multiple interfaces

Abstract

The embodiment of the invention provides a case cascading device and method supporting multiple interfaces. The device comprises a thunder and lightning interface, a thunder and lightning controller, an OcuLink input interface, an OcuLink output interface, a PCIe interface, a PCIe switch and a PXIe interface. The thunder and lightning controller is used for converting a data signal of the thunder and lightning interface into an adaptive input signal of the PCIe switch; the PCIe switch is used for splitting an input signal received by the first end into at least two paths of output signals, and respectively outputting the output signals to the PXIe interface and the OcuLink output interface through the second end and the third end; according to the invention, high-bandwidth and low-delay data transmission can be realized while the system deployment cost is remarkably reduced, and the method has the advantages of simple configuration, stable connection and flexible topology expansion.

Description

Technical Field

[0001] The present application relates to the field of chassis control, and in particular to a chassis cascading device and method supporting multiple interfaces. Background Art

[0002] With the ongoing development of high-performance computing and test and measurement, and the advancement of emerging technologies such as quantum computing and massively parallel testing, traditional single PXIe chassis are increasingly unable to support the growing demand for device deployment and massive data processing. As a modular platform, PXIe offers a certain degree of scalability, but due to limitations in chassis slot count, bandwidth limits, and connectivity options, a single chassis architecture is insufficient for complex application scenarios. Consequently, increasing system integration demands call for a cascade solution that supports efficient connectivity and collaborative processing across multiple PXIe chassis.

[0003] Existing PXIe chassis cascading methods face numerous technical obstacles. For example, while methods based on custom cascading boards can interconnect multiple chassis, they rely on specialized hardware interfaces, resulting in high costs and long development cycles, as well as increased configuration complexity and a high barrier to entry. Another solution based on Thunderbolt 3 offers high transmission rates and hot-swappable capabilities, but it often encounters compatibility issues during deployment and requires cumbersome driver installation and BIOS setup, hindering engineering adoption. Furthermore, the Thunderbolt interface itself has the technical limitation of "input only, no output," making it incapable of signal forwarding and multi-chassis interoperability in complex topologies. As for the high-precision clock synchronization mechanism natively supported by PXI / PXIe, while it provides precise clock alignment, it is essentially limited to synchronization control and cannot handle high-speed data exchange across chassis. Furthermore, its insufficient backplane bandwidth makes it difficult to meet the transmission requirements of large-scale concurrent data streams.

[0004] At the same time, existing PXIe controllers also face bottlenecks in terms of system throughput and interface diversity. For example, the traditional PXI-8110 system has a total bidirectional bandwidth of only 133MB / s. Even on the higher-performance PXIe-8133 platform, the maximum bandwidth per slot is only 1GB / s. This makes data congestion very likely to occur when handling large-scale data acquisition and real-time processing tasks, limiting the overall system performance. Furthermore, PXIe controllers have limited external interface types and support few extension protocols, resulting in insufficient versatility and flexibility, making them difficult to adapt to the complex multi-scenario, multi-protocol test environments of the future. Summary of the Invention

[0005] In response to the problems in the existing technology, the present application provides a chassis cascading device and method that supports multiple interfaces, which can achieve high-bandwidth, low-latency data transmission while significantly reducing system deployment costs, and has the advantages of simple configuration, stable connection and flexible topology expansion.

[0006] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0007] According to a first aspect of an embodiment of the present application, the present application provides a chassis cascade device supporting multiple interfaces, the device including a Thunderbolt interface, a Thunderbolt controller, an OcuLink input interface, an OcuLink output interface, a PCIe interface, a PCIe switch, and a PXIe interface;

[0008] The first end of the PCIe switch is connected to the Thunderbolt interface, the OcuLink input interface, and the PCIe interface respectively, the second end is connected to the PXIe interface, and the third end is connected to the OcuLink output interface;

[0009] The lightning controller is arranged between the first end of the PCIe switch and the lightning interface, and is used to convert the data signal of the lightning interface into an adapted input signal of the PCIe switch;

[0010] The PCIe switch is used to split the input signal received by the first end into at least two output signals, and output the output signals to the PXIe interface and the OcuLink output interface through the second end and the third end respectively.

[0011] According to any embodiment of the present application, the input signal and the output signal include a PCIe x4 signal or a PCIe x8 signal.

[0012] According to any embodiment of the present application, it further includes a signal switching switch, which is placed between the Thunderbolt interface, the OcuLink input interface, the PCIe interface, and the first end of the PCIe switch, and the signal switching switch includes a physical switch and a signal switching circuit;

[0013] The signal switching circuit is used to control a corresponding interface among the Thunderbolt interface, the OcuLink input interface, and the PCIe interface to connect to the PCIe switch according to the closed state of the physical switch.

[0014] According to any embodiment of the present application, the signal switching switch further includes a network port;

[0015] The signal switching circuit is used to control the connection of a corresponding interface among the Thunderbolt interface, the OcuLink input interface and the PCIe interface to the PCIe switch according to the control instruction transmitted by the network port.

[0016] According to any embodiment of the present application, a background monitoring module is also included for collecting the connection status, CPU usage, memory usage, I / O load, network port occupancy and service operation status information of the PXIe device based on system commands.

[0017] According to any embodiment of the present application, the background monitoring module further includes a heartbeat detection unit, which is used to detect the online status of the cascaded chassis by periodically sending heartbeat packets, and determine that the link is abnormal when no response is received for multiple consecutive times.

[0018] According to any embodiment of the present application, the background monitoring module further includes an abnormality log recording unit, which is used to record a log when a link abnormality is determined, and the log includes the time when the abnormality occurs, the chassis or link identifier, and the abnormality type.

[0019] According to any embodiment of the present application, the background monitoring module also includes an intelligent anomaly identification unit, which is used to construct an anomaly identification model based on the log data recorded by the anomaly log recording unit, and identify the link anomaly mode through local reasoning during the operation of the device, and trigger the corresponding preset repair operation according to the link anomaly mode, including restarting the corresponding interface, switching to a backup link or resetting the signal switching state.

[0020] According to any embodiment of the present application, the signal switching switch also includes a bandwidth dynamic allocation unit, which is arranged in the signal switching circuit and is used to dynamically adjust the switching path of the signal channel based on the data traffic or preset priority of each input end when multiple input ends are connected simultaneously in the Thunderbolt interface, OcuLink interface and PCIe interface.

[0021] According to any embodiment of the present application, the signal switching circuit also includes a fault switching unit, which is arranged between the physical switching switch and the signal switching circuit, and is used to switch the current input path to other available interfaces when any input port of the Thunderbolt interface, OcuLink interface or PCIe interface fails.

[0022] According to a second aspect of an embodiment of the present application, the present application provides a chassis cascading method supporting multiple interfaces, comprising:

[0023] Receive input signals from any input port of the Thunderbolt interface, OCuLink input interface or PCIe interface;

[0024] Performing path splitting on the input signal and splitting it into at least two output signals according to a preset bandwidth allocation strategy;

[0025] One of the split output signals is sent to the PXIe interface, and the other output signal is sent to the OCuLink output interface.

[0026] According to any embodiment of the present application, it also includes:

[0027] Collect PXIe device connection status, CPU usage, memory usage, I / O load, network port occupancy, and service operation status information based on system commands;

[0028] The system periodically sends heartbeat packets to detect the online status of the cascaded chassis and determines that the link is abnormal if no response is received for multiple consecutive times.

[0029] When a link is determined to be abnormal, a log is recorded, wherein the log includes the time when the abnormality occurs, the chassis or link identifier, and the abnormality type.

[0030] According to any embodiment of the present application, it also includes:

[0031] An anomaly recognition model is built based on log data, and link anomaly patterns are identified through local reasoning during device operation. Based on the link anomaly patterns, corresponding preset repair operations are triggered, including restarting the corresponding interface, switching to a backup link, or resetting the signal switching status.

[0032] According to any embodiment of the present application, it also includes:

[0033] When multiple input ports are connected simultaneously in the Thunderbolt interface, OcuLink interface, and PCIe interface, the signal channel switching path is dynamically adjusted based on the data traffic or preset priority of each input port.

[0034] According to any embodiment of the present application, it also includes:

[0035] When any input port of the Thunderbolt interface, OcuLink interface or PCIe interface fails, the current input path is switched to other available interfaces.

[0036] According to the third aspect of the embodiment of the present application, the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein when the processor executes the program, the steps of the chassis cascading method supporting multiple interfaces are implemented.

[0037] According to a fourth aspect of the embodiments of the present application, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the chassis cascading method supporting multiple interfaces.

[0038] According to a fifth aspect of the embodiments of the present application, the present application provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the chassis cascading method supporting multiple interfaces.

[0039] As can be seen from the above technical solution, the present application provides a chassis cascading device and method supporting multiple interfaces, the device including a Thunderbolt interface, a Thunderbolt controller, an OcuLink input interface, an OcuLink output interface, a PCIe interface, a PCIe switch and a PXIe interface; the first end of the PCIe switch is respectively connected to the Thunderbolt interface, the OcuLink input interface and the PCIe interface, the second end is connected to the PXIe interface, and the third end is connected to the OcuLink output interface; the Thunderbolt controller is arranged between the first end of the PCIe switch and the Thunderbolt interface, and the Thunderbolt controller is used to convert the data signal of the Thunderbolt interface into an adapted input signal of the PCIe switch; the PCIe switch is used to split the input signal received at the first end into at least two output signals, and output the output signals to the PXIe interface and the OcuLink output interface through the second end and the third end respectively. It can achieve high-bandwidth, low-latency data transmission while significantly reducing the system deployment cost, and has the advantages of simple configuration, stable connection and flexible topology expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 This is one of the schematic diagrams of a chassis cascade device supporting multiple interfaces in an embodiment of the present application;

[0042] Figure 2 This is a second schematic diagram of a chassis cascade device supporting multiple interfaces in an embodiment of the present application;

[0043] Figure 3 This is the third schematic diagram of a chassis cascade device supporting multiple interfaces in an embodiment of the present application;

[0044] Figure 4 This is the fourth schematic diagram of a chassis cascade device supporting multiple interfaces in an embodiment of the present application;

[0045] Figure 5This is the fifth schematic diagram of a chassis cascade device supporting multiple interfaces in an embodiment of the present application;

[0046] Figure 6 Schematic diagram of the process of a chassis cascading method supporting multiple interfaces in an embodiment of the present application. DETAILED DESCRIPTION

[0047] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] The acquisition, storage, use, and processing of data in the technical solution of this application comply with relevant laws and regulations.

[0049] Taking into account the problems existing in the prior art, the present application provides a chassis cascading device and method that supports multiple interfaces, which significantly reduces the system deployment cost while achieving high-bandwidth, low-latency data transmission, and has the advantages of simple configuration, stable connection and flexible topology expansion.

[0050] In order to significantly reduce the system deployment cost while achieving high bandwidth, low latency data transmission, and having the advantages of simple configuration, stable connection and flexible topology expansion, this application provides an embodiment of a chassis cascade device that supports multiple interfaces, see Figure 1 , the chassis cascade device supporting multiple interfaces specifically includes a Thunderbolt interface, a Thunderbolt controller, an OcuLink input interface, an OcuLink output interface, a PCIe interface, a PCIe switch, and a PXIe interface;

[0051] The first end of the PCIe switch is connected to the Thunderbolt interface, the OcuLink input interface, and the PCIe interface respectively, the second end is connected to the PXIe interface, and the third end is connected to the OcuLink output interface;

[0052] The lightning controller is arranged between the first end of the PCIe switch and the lightning interface, and is used to convert the data signal of the lightning interface into an adapted input signal of the PCIe switch;

[0053] The PCIe switch is used to split the input signal received by the first end into at least two output signals, and output the output signals to the PXIe interface and the OcuLink output interface through the second end and the third end respectively.

[0054] Among them, this application aims to achieve unified access, conversion and distribution of multiple high-speed interface signals, thereby meeting the needs of PXIe systems in multi-source data access and downstream expansion.

[0055] The device described in this application integrates three types of input interfaces: Thunderbolt, OCuLink, and PCIe. These interfaces are used to receive high-speed data signals from external devices or upstream chassis, respectively. Due to the signal standard differences between the Thunderbolt protocol and the PCIe protocol, a Thunderbolt controller is provided between the Thunderbolt interface and the main data processing module. The function of this controller is to convert the data signal in the Thunderbolt protocol format into a standard PCIe signal, thereby ensuring that it can be recognized and processed by the downstream PCIe switch.

[0056] The PCIe switch is the core data routing component of the device. Its first end is connected to the Thunderbolt controller (and indirectly to the Thunderbolt interface), the OCuLink input interface, and the PCIe interface, respectively, and can receive PCIe signals from the three different sources mentioned above. When an input signal comes in, the switch processes the received data and splits it into at least two output signals. The second end of the switch is connected to the PXIe interface for sending data to the local PXIe chassis, and the third end is connected to the OCuLink output interface for cascade output to the downstream chassis or other devices, thereby realizing multi-chassis cascade expansion.

[0057] In an optional embodiment, the types of input signals and output signals in the chassis cascade device described in the present application are PCIe x4 signals or PCIe x8 signals, specifically referring to that the number of channels and bandwidth specifications used by the signal during physical transmission comply with the x4 (4-lane) or x8 (8-lane) configuration in the PCI Express (Peripheral Component Interconnect Express) standard.

[0058] In an optional embodiment, a signal switching switch is further included, including a physical switch and a signal switching circuit;

[0059] The signal switching switch is provided between the Thunderbolt interface, the OcuLink input interface, the PCIe interface, and the first end of the PCIe switch;

[0060] The signal switching circuit is used to control a corresponding interface among the Thunderbolt interface, the OcuLink input interface, and the PCIe interface to connect to the PCIe switch according to the closed state of the physical switch.

[0061] In an alternative embodiment, see Figure 2 , further comprising a signal switching switch disposed between the Thunderbolt interface, the OcuLink input interface, the PCIe interface, and the first end of the PCIe switch, the signal switching switch comprising a physical switch and a signal switching circuit;

[0062] The signal switching circuit is used to control a corresponding interface among the Thunderbolt interface, the OcuLink input interface, and the PCIe interface to connect to the PCIe switch according to the closed state of the physical switch.

[0063] Flexible control of the input signal path is achieved through a "signal switch" installed between multiple input interfaces and the PCIe switch. This signal switch selects one of the three active input signal sources: the Thunderbolt interface, the OCuLink input interface, or the PCIe interface, thus preventing signal conflicts or data errors caused by multiple simultaneous input signals.

[0064] A signal switching switch consists of two parts: a physical switch and a signal switching circuit. The physical switch is typically a user-operated dip switch, jumper, or button, whose closed state indicates which interface path is currently selected. The signal switching circuit is a control logic unit that uses a high-speed differential switch chip such as the TMUXHS4212IRKSR. It supports multiple differential high-speed signal input channels and selectively switches on a channel based on the control signal input from the control pin, allowing the data signal of a specific interface to be transmitted to the input of the PCIe switch.

[0065] In actual applications, for example, if the user sets the physical switch to "Thunderbolt input" mode, the signal switching circuit will control the differential channel to close, so that the PCIe signal output by the Thunderbolt interface through the Thunderbolt controller is connected to the PCIe switch; if it is switched to "OCuLink input" mode, the Thunderbolt signal path will be disconnected and the channel from the OCuLink interface to the switch will be turned on, ensuring the system's ability to quickly switch between different signal sources, while also avoiding resource conflicts, improving the flexibility of device access and the stability of system operation.

[0066] In an optional embodiment, the signal switching switch further includes a network port;

[0067] The signal switching circuit is used to control the connection of a corresponding interface among the Thunderbolt interface, the OcuLink input interface and the PCIe interface to the PCIe switch according to the control instruction transmitted by the network port.

[0068] Among them, by adding a network port (such as a standard RJ-45 Ethernet interface), the device has network access capability and can receive remote control instructions, thereby realizing remote switching of the input signal path.

[0069] Specifically, this network port connects the device to a local area network, allowing users to send control commands from a remote terminal such as a computer, server, or control platform. These commands are transmitted via the network to the device's internal signal switching circuitry. Upon receiving the control commands, the signal switching circuitry controls the conduction state of the differential channels connected to the Thunderbolt port, OCuLink input port, or PCIe port, based on the command content. This allows a connection between a specific input port and a PCIe switch to adapt to new tasks or test environments.

[0070] In order to achieve high-bandwidth, low-latency data transmission while significantly reducing system deployment costs, and to have the advantages of simple configuration, stable connection, and flexible topology expansion, the present application provides an embodiment of a chassis cascade device for implementing all or part of the contents of the chassis cascade device supporting multiple interfaces, (1) see Figure 3 , when the Thunderbolt interface input:

[0071] Thunderbolt supports Thunderbolt 3.0 technology, offering a maximum bandwidth of 40Gbps, daisy-chaining, and hot-swapping capabilities. It utilizes a high-speed serial connection for data transmission, supporting multi-device cascading and hot-swapping, thus reducing hardware customization and complex configuration steps, lowering the technical barrier to entry for users.

[0072] When inputting through the Thunderbolt interface, the signal is first converted to a PCIe x4 signal by the Thunderbolt controller. It then enters the PCIe switch and is split into at least two PCIe x4 signals. One PCIe x4 signal enters the PXIe chassis and connects to the corresponding device, while the other is output via the OCuLink x4 signal interface, enabling cascading between chassis.

[0073] See also Figure 4 , when OCuLink interface input:

[0074] OCuLink is a high-speed interface technology based on the PCIe signaling standard, primarily used for high-speed data transmission between chassis. A single channel supports a maximum transfer rate of 128GT / s (x8 PCIe 4.0), meeting the demands of high-bandwidth applications. It achieves high-speed data transmission between chassis through standardized PCIe signal connections, supports multi-device cascading, reduces hardware customization and complex configuration steps, and improves system compatibility and stability.

[0075] When input through the OCuLink interface, the signal is connected to the PCIe switch and split into at least two PCIe x4 / x8 signals. One PCIe x4 / x8 signal enters the PXIe chassis and connects to the corresponding device, and the other PCIe x4 / x8 signal is output through the OCuLink x4 / x8 interface, thereby realizing cascading between chassis.

[0076] See also Figure 5 , when the PCIe interface input:

[0077] PCIe is a high-speed serial computer expansion bus standard widely used in high-performance data transmission scenarios. It is based on differential signal transmission technology, using a pair of complementary differential signal lines (TX+ / TX- and RX+ / RX-) for data transmission. It has strong anti-interference capabilities and high transmission rates. The physical layer is responsible for signal encoding, decoding, and clock synchronization to ensure the accuracy and stability of data transmission. PCIe supports point-to-point connections and multi-channel parallel transmission (such as x4 and x8), which can meet high bandwidth requirements. The implementation method is as follows:

[0078] When input through the PCIe interface, the signal is connected to the PCIe switch and split into at least two PCIe x4 / x8 signals. One PCIe x4 / x8 signal enters the PXIe chassis and connects to the corresponding device, and the other PCIe x4 / x8 signal is output through the OCuLink x4 / x8 interface, thereby achieving cascading between chassis.

[0079] In an optional embodiment, a background monitoring module is further included for collecting the connection status, CPU usage, memory usage, I / O load, network port occupancy and service operation status information of the PXIe device based on system commands.

[0080] The module automatically executes a series of system commands to obtain chassis status information through the integrated system management program or embedded control logic:

[0081] Use the lspci command to scan and identify the PCIe devices connected to the current system to determine whether each slot in the PXIe chassis has a module installed, thereby obtaining device connection status information;

[0082] Use the vmstat and iostat commands to collect real-time information about the chassis controller's current CPU usage, memory usage, and I / O subsystem read and write load, reflecting the overall resource usage level of the chassis.

[0083] Use the ss or netstat command to obtain the usage status and connection status of the network port to determine whether there is abnormal occupancy of the network channel and assist in locating network communication or service blocking problems;

[0084] Use the systemctl command to check and manage the running status of background services (such as remote control services and data processing services), helping to promptly detect service failures or process anomalies.

[0085] In summary, the background monitoring module can be structurally integrated into the signal switching control panel or main control system of the device. Through timed scheduling or event triggering, the above commands are regularly called and the output results are analyzed to generate status reports or trigger early warning mechanisms.

[0086] In an optional embodiment, the background monitoring module further includes a heartbeat detection unit, which is configured to detect the online status of the cascaded chassis by periodically sending heartbeat packets, and determine that the link is abnormal when no response is received for multiple consecutive times.

[0087] In specific implementations, the heartbeat detection unit periodically (for example, every 5 seconds) sends a set of heartbeat packets to a designated port on the downstream PXIe chassis via the TCP protocol. These heartbeat packets can be TCP messages with a fixed format and empty payload or with timestamp information, used to establish and maintain a lightweight network connection. Upon receiving the heartbeat packets, the downstream device immediately returns an acknowledgment response, forming a complete "request-reply" detection link.

[0088] The heartbeat detection unit has an internal failure threshold. If it fails to receive a response three or five times in a row, the link is considered abnormal. At this point, the heartbeat detection unit triggers an abnormality flag and reports the current link status to the backend monitoring module. The subsequent module then logs the abnormality, issues an alarm, and initiates automatic repair actions (such as switching to another available link).

[0089] In an optional embodiment, the background monitoring module further includes an abnormality log recording unit, which is used to record a log when determining that a link is abnormal, and the log includes the abnormality occurrence time, chassis or link identification and abnormality type.

[0090] The abnormality logging unit works in conjunction with components such as the heartbeat detection unit and the resource monitoring unit. When the heartbeat detection unit determines that the downstream chassis connection status is abnormal (for example, no heartbeat response is received continuously) or detects abnormal characteristics such as network link interruption, high latency, or packet loss, the logging mechanism is immediately triggered.

[0091] The recorded log contents include but are not limited to the following fields:

[0092] Abnormality occurrence time: Use system timestamp to accurately record the time when the abnormality is first identified;

[0093] Abnormal chassis or link ID: records the chassis number, link ID, or physical interface ID where the abnormality occurred, which is used to locate the fault source later.

[0094] Exception type: can be recorded as predefined exception categories, such as "link down", "heartbeat timeout", "high latency" or "packet loss";

[0095] Optional system status information: The log can also include resource status such as current CPU usage, memory usage, and network throughput to assist in analyzing the background environment when the exception occurred.

[0096] The exception log recording unit runs in the background of the device, supports asynchronous writing and log rotation strategies, and can completely save abnormal event records without interrupting the transmission of the main data signal, thus building the operation trace foundation of the chassis cascade system.

[0097] In an optional embodiment, the background monitoring module also includes an intelligent anomaly identification unit, which is used to build an anomaly identification model based on the log data recorded by the anomaly log recording unit, and identify the link anomaly mode through local reasoning during the operation of the device, and trigger corresponding preset repair operations according to the link anomaly mode, including restarting the corresponding interface, switching to a backup link, or resetting the signal switching state.

[0098] The intelligent anomaly recognition unit first obtains historical anomaly log data from the anomaly logging unit, including the anomaly time, type, frequency, link identifier, and resource status. Based on this data, it constructs an anomaly recognition model offline using machine learning algorithms such as decision trees, support vector machines (SVMs), random forests, or lightweight neural networks. Model training can be performed locally on the device or generated remotely and deployed locally.

[0099] During device operation, the intelligent anomaly recognition unit continuously receives real-time data input from monitoring modules (such as heartbeat detection and resource monitoring) and compares and analyzes these inputs with the trained model through a local inference engine. If it detects characteristics that are highly similar to historical anomaly patterns, such as a link experiencing a persistently high packet loss rate or latency spike during a specific time period, the unit determines that the link is at potential failure risk.

[0100] Once an anomaly is identified, the unit will automatically trigger the corresponding preset repair actions. These actions may include:

[0101] Restart the corresponding interface: Restore the faulty interface by controlling the interface power or resetting the control signal;

[0102] Switch to backup link: Modify the signal switching circuit status and switch the input to other available interfaces;

[0103] Reset signal switching status: Reinitialize the signal switching switch to clear temporary abnormalities or configuration failures.

[0104] All identification results and processing behaviors will be recorded in the log system for subsequent tracing and strategy optimization.

[0105] In an optional embodiment, the signal switching switch also includes a bandwidth dynamic allocation unit, which is arranged in the signal switching circuit and is used to dynamically adjust the switching path of the signal channel based on the data traffic or preset priority of each input port when multiple input ports are connected simultaneously in the Thunderbolt interface, OcuLink interface and PCIe interface.

[0106] The dynamic bandwidth allocation unit uses a built-in traffic monitoring mechanism to continuously collect operational status information for each input port, including but not limited to the current transmission rate, data queue length, port activity, etc. The unit can also preset a set of input priority parameter tables to distinguish high-priority input sources (such as time-sensitive tasks or critical business links) from low-priority input sources.

[0107] When multiple input interfaces are detected as connected to a device simultaneously, the dynamic bandwidth allocation unit evaluates the real-time data flow and priority weight of the current input to comprehensively determine the optimal signal access path. It then automatically switches the signal path to the input interface with the highest current demand by controlling a high-speed differential switch chip (such as the TMUXHS4212IRKSR) in the signal switching circuit.

[0108] For example, when the Thunderbolt interface, OCuLink interface and PCIe interface are all connected, if the system detects that the current data transmission rate of the OCuLink channel is higher and its priority is higher than other ports, it will prioritize the path from OCuLink to the PCIe switch; if the task corresponding to the Thunderbolt interface is set to the highest priority, the system will automatically switch the signal channel to the Thunderbolt interface, thereby ensuring the transmission continuity of critical data and sufficient bandwidth.

[0109] In an optional embodiment, the signal switching circuit further includes a fault switching unit, which is arranged between the physical switching switch and the signal switching circuit, and is used to switch the current input path to other available interfaces when any input port of the Thunderbolt interface, OcuLink interface or PCIe interface fails.

[0110] The failover unit, through collaboration with the backend monitoring module or heartbeat detection unit, obtains real-time operational status information for input ports such as the Thunderbolt interface, OCuLink interface, and PCIe interface. When an input port detects an anomaly (e.g., communication interruption, link drop, or lack of valid data packet input, which is considered a failure), the failover unit immediately blocks the signal path for that port and initiates access to an alternate port.

[0111] For example, under the premise that the Thunderbolt interface is currently in working state, if an abnormal connection of the interface is detected, such as continuous loss of heartbeat packets or data interruption exceeding the preset threshold, the fault switching unit will actively close the signal path corresponding to the interface, and after availability judgment, switch the signal channel to the input end of the OCuLink or PCIe interface that remains in normal state.

[0112] The unit integrates an interface status management table and an interface switching policy module, which can execute switching logic according to the following policies:

[0113] If there are multiple backup interfaces available, the most recently active, currently idle, or higher priority interface will be selected first.

[0114] After switching, the background module is automatically notified to update the current channel information for use by subsequent data distribution and system management modules;

[0115] The switching action maintains uninterrupted or minimally interrupted switching time to ensure business continuity.

[0116] From the above description, it can be seen that the chassis cascade device supporting multiple interfaces provided in the embodiment of the present application can achieve high-bandwidth, low-latency data transmission while significantly reducing system deployment costs, and has the advantages of simple configuration, stable connection and flexible topology expansion.

[0117] In order to significantly reduce the system deployment cost while achieving high bandwidth, low latency data transmission, and having the advantages of simple configuration, stable connection and flexible topology expansion, this application provides an embodiment of a chassis cascade device that supports multiple interfaces, see Figure 6 , the present application provides a chassis cascading method supporting multiple interfaces, comprising:

[0118] Step S101: receiving an input signal from any input port of a Thunderbolt interface, an OCuLink input interface, or a PCIe interface;

[0119] Step S102: performing path splitting on the input signal and splitting it into at least two output signals according to a preset bandwidth allocation strategy;

[0120] Step S103: sending one output signal after the split to the PXIe interface, and sending the other output signal to the OCuLink output interface.

[0121] For example, the device first receives an input signal through any of the following interfaces: the Thunderbolt interface, the OCuLink input interface, or the PCIe interface. If the input signal comes from the Thunderbolt interface, the Thunderbolt controller inside the device converts it into a standard PCIe signal to ensure that the subsequent processing modules can properly identify and route it.

[0122] All input signals are then converted to PCIe x4 or x8 signals before entering the main signal processing module. The number of channels can be dynamically set based on the physical capabilities or configuration parameters of the input interface. For example, OCuLink input supports up to 8 lanes (x8), while Thunderbolt interface conversion typically uses a x4 configuration.

[0123] After the input signal enters the device's internal data processing module, it is split according to a preset bandwidth allocation strategy or channel mapping rules. This split can be a fixed split, round-robin allocation, or dynamic weighted allocation. For example, in the default system configuration, 50% of the bandwidth is allocated to the PXIe interface output and 50% to the OCuLink output interface. In actual operation, this ratio can be dynamically adjusted based on data volume.

[0124] After the split is completed, one PCIe output signal is transmitted to the local PXIe chassis through the PXIe interface for processing or testing tasks, and the other output is used to connect to downstream cascade devices through the OCuLink output interface to build a multi-chassis cascade structure and realize the continuous transmission of data and control information.

[0125] According to any embodiment of the present application, it also includes:

[0126] Collect PXIe device connection status, CPU usage, memory usage, I / O load, network port occupancy, and service operation status information based on system commands;

[0127] The system periodically sends heartbeat packets to detect the online status of the cascaded chassis and determines that the link is abnormal if no response is received for multiple consecutive times.

[0128] When a link is determined to be abnormal, a log is recorded, wherein the log includes the time when the abnormality occurs, the chassis or link identifier, and the abnormality type.

[0129] According to any embodiment of the present application, it also includes:

[0130] An anomaly recognition model is built based on log data, and link anomaly patterns are identified through local reasoning during device operation. Based on the link anomaly patterns, corresponding preset repair operations are triggered, including restarting the corresponding interface, switching to a backup link, or resetting the signal switching status.

[0131] According to any embodiment of the present application, it also includes:

[0132] When multiple input ports are connected simultaneously in the Thunderbolt interface, OcuLink interface, and PCIe interface, the signal channel switching path is dynamically adjusted based on the data traffic or preset priority of each input port.

[0133] According to any embodiment of the present application, it also includes:

[0134] When any input port of the Thunderbolt interface, OcuLink interface or PCIe interface fails, the current input path is switched to other available interfaces.

[0135] Based on the above examples, this application proposes a chassis cascading device and method that supports multiple interfaces. This device and method enables flexible switching between three high-speed interfaces: Thunderbolt, OCuLink, and PCIe, through a physical switch. This breaks through the limitation of traditional chassis supporting only a single interface, allowing the optimal connection method to be selected based on the needs of different application scenarios, significantly improving device compatibility and deployment flexibility.

[0136] In terms of implementation, high-bandwidth signal routing technology ensures stable data transmission during switching, enabling seamless switching between Thunderbolt's 40Gbps multi-functional transmission and OCuLink's 128Gbps high-speed data throughput. Furthermore, remote signal switching is integrated, allowing users to remotely control input interface switching via the network, significantly improving system maintainability.

[0137] From a hardware perspective, in order to significantly reduce system deployment costs while achieving high-bandwidth, low-latency data transmission, and having the advantages of simple configuration, stable connection, and flexible topology expansion, the present application provides an embodiment of an electronic device for implementing all or part of the contents of the chassis cascade device supporting multiple interfaces, and the electronic device specifically includes the following contents:

[0138] A processor, memory, a communications interface, and a bus; wherein the processor, memory, and communications interface communicate with each other via the bus; the communications interface is used to transmit information between the chassis cascade and related devices such as core business systems, user terminals, and related databases; the logic controller can be a desktop computer, a tablet computer, a mobile terminal, etc., but this embodiment is not limited thereto. In this embodiment, the logic controller can refer to the embodiment of the chassis cascade device supporting multiple interfaces in the embodiment, and its content is incorporated herein, and repeated parts are not repeated.

[0139] It is understandable that the user terminal may include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, etc. Among them, the smart wearable device may include smart glasses, a smart watch, a smart bracelet, etc.

[0140] In practical applications, the portion of the chassis cascading device that supports multiple interfaces may be executed on the electronic device side as described above, or all operations may be performed on the client device. The specific selection may be based on the processing capabilities of the client device and the limitations of the user's usage scenario. This application does not impose any restrictions on this. If all operations are performed on the client device, the client device may also include a processor.

[0141] The client device may include a communication module (i.e., a communication unit) that can establish a communication connection with a remote server to implement data transmission with the server. The server may include a server on the task scheduling center side, and in other implementation scenarios, may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, a server cluster consisting of multiple servers, or a server structure of a distributed device.

[0142] An embodiment of the present application also provides a computer-readable storage medium that can implement all the steps in the chassis cascade device supporting multiple interfaces in the above-mentioned embodiments, in which the execution subject is a server or a client. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements all the steps in the chassis cascade device supporting multiple interfaces in the above-mentioned embodiments, in which the execution subject is a server or a client.

[0143] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0144] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as a combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0145] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0146] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0147] Specific embodiments are used in the present invention to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A chassis cascade device supporting multiple interfaces, characterized in that: The device includes a Thunderbolt interface, a Thunderbolt controller, an OcuLink input interface, an OcuLink output interface, a PCIe interface, a PCIe switch, and a PXIe interface; The first end of the PCIe switch is connected to the Thunderbolt interface, the OcuLink input interface, and the PCIe interface respectively, the second end of the PCIe switch is connected to the PXIe interface, and the third end of the PCIe switch is connected to the OcuLink output interface; The lightning controller is arranged between the first end of the PCIe switch and the lightning interface, and is used to convert the data signal of the lightning interface into an adapted input signal of the PCIe switch; The PCIe switch is used to split the input signal received by the first end into at least two output signals, and output the output signals to the PXIe interface and the OcuLink output interface through the second end and the third end respectively.

2. The chassis cascading device supporting multiple interfaces according to claim 1, wherein: The input signal and the output signal include a PCIex4 signal or a PCIex8 signal.

3. The chassis cascading device supporting multiple interfaces according to claim 1, wherein: Also included is a signal switching switch, disposed between the Thunderbolt interface, the OcuLink input interface, the PCIe interface, and the first end of the PCIe switch, the signal switching switch comprising a physical switch and a signal switching circuit; The signal switching circuit is used to control a corresponding interface among the Thunderbolt interface, the OcuLink input interface, and the PCIe interface to connect to the PCIe switch according to the closed state of the physical switch.

4. The chassis cascading device supporting multiple interfaces according to claim 3, wherein: The signal switching switch further includes a network port; The signal switching circuit is used to control the connection of a corresponding interface among the Thunderbolt interface, the OcuLink input interface and the PCIe interface to the PCIe switch according to the control instruction transmitted by the network port.

5. The chassis cascading device supporting multiple interfaces according to claim 1, wherein: Also includes: The background monitoring module is used to collect PXIe device connection status, CPU usage, memory usage, I / O load, network port occupancy, and service operation status information based on system commands; The background monitoring module also includes a heartbeat detection unit for detecting the online status of the cascaded chassis by periodically sending heartbeat packets, and determining that the link is abnormal when no response is received for multiple consecutive times; The background monitoring module further includes an abnormality log recording unit, which is used to record a log when determining that a link is abnormal. The log includes the time when the abnormality occurs, the chassis or link identifier, and the abnormality type.

6. The chassis cascading device supporting multiple interfaces according to claim 5, wherein: The background monitoring module also includes an intelligent anomaly identification unit, which is used to build an anomaly identification model based on the log data recorded by the anomaly log recording unit, and identify the link anomaly mode through local reasoning during the operation of the device, and trigger the corresponding preset repair operation according to the link anomaly mode, including restarting the corresponding interface, switching to a backup link or resetting the signal switching state.

7. The chassis cascading device supporting multiple interfaces according to claim 3, wherein: The signal switching switch also includes a bandwidth dynamic allocation unit, which is arranged in the signal switching circuit and is used to dynamically adjust the switching path of the signal channel based on the data flow or preset priority of each input port when multiple input ports are connected simultaneously in the Thunderbolt interface, OcuLink interface and PCIe interface.

8. The chassis cascading device supporting multiple interfaces according to claim 3, wherein: The signal switching circuit also includes a fault switching unit, which is arranged between the physical switching switch and the signal switching circuit, and is used to switch the current input path to other available interfaces when any input port of the Thunderbolt interface, OcuLink interface or PCIe interface fails.

9. A chassis cascading method supporting multiple interfaces, characterized in that: include: Receive input signals from any input port of the Thunderbolt interface, OCuLink input interface or PCIe interface; Performing path splitting on the input signal and splitting it into at least two output signals according to a preset bandwidth allocation strategy; One of the split output signals is sent to the PXIe interface, and the other output signal is sent to the OCuLink output interface.

10. The chassis cascading method supporting multiple interfaces according to claim 9, wherein: Also includes: Collect PXIe device connection status, CPU usage, memory usage, I / O load, network port occupancy, and service operation status information based on system commands; The system periodically sends heartbeat packets to detect the online status of the cascaded chassis and determines that the link is abnormal if no response is received for multiple consecutive times. When a link is determined to be abnormal, a log is recorded, wherein the log includes the time when the abnormality occurs, the chassis or link identifier, and the abnormality type.

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