Clock checking method and related equipment
By adjusting the clock check operation during simulation verification, the flexibility problem of the clock check operation in integrated circuit design is solved, the rational use of simulation resources is achieved, and the utilization rate of simulation resources is improved.
Patent Information
- Application Number
- CN202510781495.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-12
- Publication Date
- 2025-09-26
AI Technical Summary
In the simulation verification process of integrated circuit design, how to improve the flexibility of clock check operation of the design under test and realize the rational use of simulation resources.
During simulation verification, clock checking operations are performed on the clock to be verified of the design under test to obtain the usage of simulation resources. The clock checking operations are adjusted according to the usage, including adjusting the time of the trigger event and the checking ratio.
The flexibility of clock checking operation and the utilization rate of simulation resources are improved, resource waste is avoided, and reasonable utilization of simulation resources is achieved.
Smart Images
Figure CN120706341A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of simulation verification, and in particular to a clock checking method and related equipment. Background Art
[0002] The primary purpose of integrated circuit (IC) design verification is to ensure the correctness of the IC design and its consistency with the design specifications. Simulation verification is a widely used method for functional verification of IC designs. It uses the SystemVerilog (SV) language to build a verification platform, write test stimuli, and simulate the design under test (DUT).
[0003] Clock checking plays a crucial role in IC design. Only by ensuring a stable and reliable clock can the proper functioning of all IC design functions be guaranteed. With the rapid development of integrated circuit technology, improving the flexibility of clock checking operations in the IC design under test and ensuring the rational use of simulation resources have become pressing technical challenges in this field. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is how to improve the flexibility of the clock check operation of the design under test and realize the reasonable utilization of simulation resources.
[0005] To solve the above problem, an embodiment of the present invention provides a clock checking method, comprising:
[0006] During simulation verification of the design under test, a clock check operation is performed on a clock to be verified of the design under test;
[0007] Obtaining the usage of simulation resources during simulation verification of the design under test;
[0008] According to the obtained usage of the simulation resources, a clock check operation of the clock to be verified of the design under test is adjusted.
[0009] Optionally, performing a clock check operation on a clock to be verified of the design under test includes: in response to a trigger event of the clock to be verified, checking the clock to be verified within a valid time of the trigger event, wherein a start time of the trigger event is equal to or later than a verification start time of the clock to be verified, and an end time of the trigger event is equal to or earlier than a verification end time of the clock to be verified;
[0010] The adjusting of the clock check operation of the clock to be verified of the design under test includes adjusting at least one of the start time and the effective time of the trigger event.
[0011] Optionally, the design under test includes a module under test, the module under test has multiple clocks to be verified, each of the multiple clocks to be verified has a corresponding check weight, and the check weight is a probability of executing a clock check operation for a corresponding clock to be verified among the multiple verification clocks of the module under test;
[0012] The performing of a clock check operation on a clock to be verified of the design under test comprises: during the simulation verification of the module under test, performing corresponding clock check operations on multiple clocks to be verified of the module under test according to corresponding check weights;
[0013] The adjusting the clock checking operation of the clock to be verified of the design under test includes: adjusting the checking weights of the multiple clocks to be verified in the module under test.
[0014] Optionally, the clock checking method further includes: using a preset clock trigger network data structure to record information on trigger events and check weights of the multiple clocks to be verified in the module under test.
[0015] Optionally, the design under test includes a module under test;
[0016] The performing a clock check operation on the clock to be verified of the design under test includes: responding to a module check event of the module under test, performing a clock check operation on the clock to be verified of the module under test within the effective time of the module check event, wherein the start time of the module check event is equal to or later than the verification start time of the module under test, and the end time of the module check event is equal to or earlier than the verification end time of the module under test;
[0017] The adjusting of the clock check operation of the clock to be verified of the design under test includes: adjusting at least one of the start time and the effective time of the module check event.
[0018] Optionally, the design under test includes a plurality of modules under test, each of the plurality of modules under test having a corresponding module check weight, the module check weight being a probability of executing a clock check operation of a clock to be verified of a corresponding module under test among the plurality of modules under test;
[0019] The performing of a clock check operation on the clock to be verified of the tested design includes: during the simulation verification of the tested chip, performing corresponding clock check operations on the clocks to be verified of the plurality of tested modules according to corresponding module check weights;
[0020] The adjusting the clock check operation of the clock to be verified of the design under test includes: adjusting the module check proportions of the multiple modules under test.
[0021] Optionally, the clock checking method further includes: using a preset module checking network data structure to record information on module checking events and module checking proportions of the clocks to be verified of the multiple tested modules.
[0022] Optionally, when it is determined through the clock checking operation that the clock to be verified has an abnormality or error, the clock checking method further includes: outputting corresponding alarm prompt information.
[0023] Optionally, when it is determined through the clock checking operation that the clock to be verified is abnormal, the clock checking method further includes: stopping the clock checking operation of the clock to be verified.
[0024] Accordingly, an embodiment of the present invention further provides a clock checking device, comprising:
[0025] a clock checking unit adapted to perform a clock checking operation on a clock to be verified of the design under test during simulation verification of the design under test;
[0026] an acquisition unit adapted to acquire usage of simulation resources during simulation verification of a design under test;
[0027] The adjusting unit is adapted to adjust the clock checking operation of the clock to be verified of the design under test according to the usage of the obtained simulation resources.
[0028] Accordingly, an embodiment of the present invention also provides a device comprising at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the clock checking method as described in any one of the above items.
[0029] Accordingly, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, which is used to implement any of the above-mentioned clock checking methods when executed by a processor.
[0030] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the clock checking method as described in any one of the above.
[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0032] The clock checking method provided in an embodiment of the present invention adjusts the clock checking operation of the clock to be verified of the design under test according to the usage of the obtained simulation resources during the simulation verification of the design under test, thereby improving the flexibility of the clock checking operation of the design under test, realizing the rational use of simulation resources, and improving the utilization rate of simulation resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 This is a flow chart of an embodiment of a clock checking method provided by the technical solution of the present invention;
[0034] Figure 2 It is a schematic diagram of a trigger event set for a clock to be verified in the clock checking method provided by the technical solution of the present invention;
[0035] Figure 3 This is a schematic diagram of dynamically adjusting a trigger event using the effective time of the trigger event as a sliding window in the clock checking method provided by the technical solution of the present invention;
[0036] Figure 4 It is a schematic diagram of the clock trigger network data structure of the module under test in the clock checking method provided by the technical solution of the present invention;
[0037] Figure 5 It is a schematic diagram of a network data structure of a module check designed under test in the clock check method provided by the technical solution of the present invention;
[0038] Figure 6 It is a schematic diagram of an embodiment of a clock checking device provided by the technical solution of the present invention;
[0039] Figure 7 This is a schematic diagram of an optional hardware structure of the device provided by the technical solution of the present invention. DETAILED DESCRIPTION
[0040] As can be seen from the background technology, with the vigorous development of integrated circuit technology, how to improve the flexibility of clock check operations of the tested design and achieve rational utilization of simulation resources in the simulation verification process of IC design has become a technical problem that needs to be solved urgently in this field.
[0041] In order to solve the above technical problems, an embodiment of the present invention provides a clock checking method, including: performing a clock checking operation on the clock to be verified of the design under test during simulation verification of the design under test; obtaining the usage of simulation resources during simulation verification of the design under test; and adjusting the clock checking operation of the clock to be verified of the design under test according to the obtained usage of simulation resources.
[0042] The clock checking method provided in an embodiment of the present invention adjusts the clock checking operation of the clock to be verified of the design under test according to the usage of the obtained simulation resources during the simulation verification of the design under test, thereby improving the flexibility of the clock checking operation of the design under test, realizing the rational use of simulation resources, and improving the utilization rate of simulation resources.
[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0044] Figure 1 The flowchart of an embodiment of the clock checking method provided by the technical solution of the present invention is shown. Figure 1 A clock checking method may include the following steps:
[0045] Step S110: During the simulation verification of the design under test, a clock check operation is performed on the clock to be verified of the design under test;
[0046] Step S120: obtaining usage of simulation resources during simulation verification of the design under test;
[0047] Step S130: adjusting the clock check operation of the clock to be verified of the design under test according to the acquired usage of the simulation resources.
[0048] Please continue to refer to Figure 1 , executing step S110, during the simulation verification of the design under test, performing a clock check operation on the clock to be verified of the design under test.
[0049] During simulation verification of the design under test, a clock check operation is performed on the clock to be verified of the design under test to obtain a clock check result of the clock to be verified of the design under test.
[0050] The design under test (DUT) is written in a hardware description language (such as Verilog or SV) and is used to describe the behavior of registers and combinational logic in an IC. This is also the IC design to be simulated. Generally speaking, IC design simulation verification includes two categories: functional verification and timing verification. Functional verification verifies the design functionality of the IC, while timing verification utilizes a standard delay file (SDF) to record device and line delays during the IC layout and routing process. The SDF is back-annotated to simulate signal delays.
[0051] In the embodiment of the present application, the design under test is an IC design to be functionally verified. Specifically, the design under test can be any one of a chip design, a subsystem design, and an intellectual property core (IP core) design.
[0052] During simulation verification of a design under test (DUT), a test platform sends test stimuli to the DUT to verify the correctness of the DUT. This simulation verification of the DUT includes simulating the DUT's clock to verify that its clock period and frequency meet design requirements.
[0053] In an exemplary embodiment, the step of performing a clock check operation on a clock to be verified of a design under test includes: responding to a trigger event (trigger_event) of the clock to be verified, checking the clock to be verified within a valid time of the trigger event, the start time of the trigger event being equal to or later than the verification start time of the clock to be verified, and the end time of the trigger event being equal to or earlier than the verification end time of the clock to be verified.
[0054] A corresponding trigger event is set for the clock to be verified of the design under test, so that the clock to be verified is checked within the valid time of the corresponding trigger event, and the clock check operation of the clock to be verified is not performed during the non-valid time of the corresponding trigger event, so as to facilitate flexible control and dynamic adjustment of the clock check operation of the clock to be verified of the design under test.
[0055] In one exemplary embodiment, the trigger event starts later than the verification start time of the clock to be verified, and ends earlier than the verification end time of the clock to be verified. This means that the clock check operation for the verification clock is not performed throughout the verification process of the clock to be verified. This shortens the clock check time for the verification clock, prevents the clock verification operation from occupying excessive resources, and consequently improves simulation resource utilization.
[0056] For example, please refer to Figure 2 The verification start time and end time of the clock CLK to be verified are t0 and t3 respectively, and the start time and end time of the trigger event trigger_event of the clock CLK to be verified are t1 and t2 respectively, wherein t3>t2>t1>t0.
[0057] It should be noted that if the start time of the trigger event is later than the verification start time of the clock to be verified, and the end time of the trigger event is earlier than the verification end time of the clock to be verified, the effective time of the trigger event of the clock to be verified should not be too short, otherwise it will affect the accuracy of the clock check result. To this end, the effective time of the trigger event is greater than or equal to 10 clock cycles of the clock to be verified.
[0058] In an exemplary embodiment, under the premise that the effective time of the triggering event is determined, the clock checking operation of the clock to be verified is dynamically adjusted during the verification process of the clock to be verified by flexibly setting the start time of the triggering event, that is, using the effective time of the triggering event as a sliding window.
[0059] For example, the time when the clock frequency is detected to have reached a stable state can be used as the start time of the trigger event of the clock to be verified, so as to avoid wasting simulation resources by performing clock check on the clock to be verified when the clock frequency has not reached a stable state; or, when it is detected that the simulation resources are relatively sufficient, the clock check operation of the clock to be verified can be started, thereby avoiding the peak period of simulation resource usage, avoiding the tension of simulation resources, and realizing the rational use of simulation resources.
[0060] Please refer to Figure 3 The verification start time and end time of the clock CLK to be verified are t0 and t3 respectively, while the start time and end time of the trigger event trigger_event of the clock CLK to be verified can be t 11 , t 21 , or t 12 , t 22 , where t3>t 22 >t 21 >t 12 >t 11 >t0.
[0061] It is understandable that, when there are multiple clocks to be verified in the design under test, the triggering events of different clocks to be verified may be the same or different. Those skilled in the art may set them according to actual needs and are not limited here.
[0062] For example, for a clock to be verified with higher importance, a trigger event with a longer validity period can be set, while for a clock to be verified with lower importance, a trigger event with a shorter validity period can be set; for a clock to be verified with lower reliability, a trigger event with a longer validity period can be set, while for a clock to be verified with higher reliability, a trigger event with a shorter validity period can be set, and so on.
[0063] In an exemplary embodiment, the design under test includes a module under test, and the module under test has multiple clocks to be verified. Accordingly, the step of performing a clock check operation on the clocks to be verified in the design under test includes: during simulation verification of the module under test, performing a corresponding clock check operation on each of the multiple clocks to be verified in the module under test according to a corresponding check ratio (trigger_ratio), where the check ratio is a probability of executing the clock check operation on a corresponding clock to be verified among the multiple verification clocks in the module under test.
[0064] The inspection weights of the multiple clocks to be verified in the module under test can be set based on factors such as the importance and reliability of the multiple clocks to be verified in the module under test. For example, a lower inspection weight can be set for a clock to be verified in the module under test that has been inspected for a long time, while a higher inspection weight can be set for a clock to be verified in the module under test that has just started performing a clock inspection operation. For another example, a higher inspection weight can be set for a clock to be verified that had a high error rate in previous clock inspection operations, while a lower inspection weight can be set for a clock to be verified that had a low error rate in previous clock inspection operations, and so on.
[0065] Setting different inspection weights for the multiple clocks to be verified of the module under test can improve the flexibility of the clock inspection operation of the multiple clocks to be verified of the module under test, facilitate the dynamic adjustment of the clock inspection operation of the multiple clocks to be verified of the module under test, and is conducive to the rational use of simulation resources.
[0066] In an exemplary embodiment, the clock checking method further includes: using a preset clock trigger network data structure trigger_clock_net to record information on trigger events and check weights of the multiple clocks to be verified in the module under test.
[0067] Please refer to Figure 4 , when the module under test has n (n is an integer greater than or equal to 2) clocks to be verified clock_1~clock_n, the clock trigger network data structure trigger_clock_net of the module under test respectively records the trigger event trigger_event_1 and check ratio trigger_ratio_1 of the clock to be verified clock_1, the trigger event trigger_event_2 and check ratio trigger_ratio_2 of the clock to be verified clock_2, ..., the trigger event trigger_event_n and check ratio trigger_ratio_n of the clock to be verified clock_n.
[0068] A preset clock trigger network data structure is used to record the trigger events and inspection weight information of the multiple clocks to be verified in the module under test, so that the user can monitor the clock inspection status of the multiple clocks to be verified in the module under test, and dynamically adjust the simulation resources occupied by the clock inspection operation of each clock to be verified in the module under test, thereby realizing the rational use of simulation resources.
[0069] In an exemplary embodiment, the design under test includes a module under test. Accordingly, the step of performing a clock check operation on a clock to be verified of the design under test includes: responding to a module check event (check_module_event) of the module under test, performing a clock check operation on the clock to be verified of the module under test within the effective time of the module check event, wherein the start time of the module check event is equal to or later than the verification start time of the module under test, and the end time of the module check event is equal to or earlier than the verification end time of the module under test.
[0070] By setting a corresponding module check event for the module under test, a clock check is performed on the clock to be verified of the module under test within the valid time of the corresponding module check event, and the clock check operation of the clock to be verified of the module under test is not performed during the non-valid time of the corresponding module check event, so as to flexibly control and dynamically adjust the clock check operation of the clock to be verified of the module under test.
[0071] In an exemplary embodiment, the start time of the module check event is later than the start time of the verification of the module under test, and the end time of the module check event is earlier than the end time of the verification of the module under test, that is, the clock check operation of the clock to be verified of the module under test only occupies part of the verification time of the module under test, rather than performing the clock check operation of the clock to be verified of the module under test during the entire verification process of the module under test. Therefore, the time of the clock check operation of the clock to be verified of the module under test can be shortened, which is beneficial to saving simulation resources occupied by the clock check operation of the clock to be verified of the module under test, and correspondingly helps to achieve rational utilization of simulation resources.
[0072] It is understandable that when the design under test includes multiple modules under test, the module inspection events of different modules under test may be the same or different, which can be determined by a person skilled in the art based on the working status of the modules under test at different verification stages of the design under test.
[0073] In an exemplary embodiment, when the design under test includes multiple modules under test, the step of performing a clock check operation on the clock to be verified of the design under test includes: during simulation verification of the design under test, performing corresponding clock check operations on the clocks to be verified of the multiple modules under test according to corresponding module check ratios (check_module_ratio).
[0074] The detection module detection weight is the execution probability of the clock check operation of the clock to be verified of the corresponding tested module among the multiple tested modules of the tested design. It can be set according to the importance and reliability of the corresponding tested module, and no specific restrictions are made here.
[0075] For example, for a module under test with higher reliability in the design under test, a lower module inspection weight is set, while for a module under test newly added in the design under test, a higher inspection weight can be set.
[0076] Setting different module inspection proportions for the multiple tested modules of the tested design is beneficial to improving the flexibility of the clock inspection operations of the multiple clocks to be verified in the tested modules, facilitating the dynamic adjustment of the clock inspection operations of the multiple tested modules of the tested design, and is beneficial to the rational use of simulation resources.
[0077] In an exemplary embodiment, the clock checking method further includes: using a preset module check network (check_module_net) data structure to record information on module check events and module check proportions of the clocks to be verified of the multiple modules under test.
[0078] Please refer to Figure 5 When the design under test has m (m is an integer greater than or equal to 2) modules under test module_1~module_m, the module check network data structure check_module_net of the design under test respectively records the module check event check_module_event_1 and module check ratio check_module_ratio_1 of the module under test module_1, the module check event check_module_event_2 and module check ratio check_module_ratio_2 of the module under test module_2, ..., the module check event check_module_event_m and module check ratio check_module_ratio_m of the module under test module_m.
[0079] A preset module check network data structure is used to record the module check trigger events and module check proportion information of the multiple modules under test in the design under test, so as to facilitate the user to monitor the clock check status of the multiple modules under test in the design under test, and facilitate the user to dynamically adjust the simulation resources occupied by the clock check operation of each module under test in the design under test, thereby realizing the dynamic adjustment of the simulation resources occupied by the clock check operation of each module under test in the design under test.
[0080] Please continue to refer to Figure 1 , executing step S120, obtaining the usage of simulation resources during the simulation verification of the design under test.
[0081] During simulation verification of the design under test, the usage of simulation resources is obtained, which provides a basis for subsequently adjusting the clock check operation of the clock to be verified of the design under test according to the obtained usage of simulation resources.
[0082] The usage of the simulation resources can be characterized by indicators or parameters such as simulation running time, memory usage, CPU usage, etc., which can be set according to actual needs and are not limited here.
[0083] In an exemplary embodiment, the usage of the simulation resources is obtained by real-time monitoring of the simulation resources. In other embodiments, the usage of the simulation resources can also be monitored according to a preset period.
[0084] Please continue to refer to Figure 1 , executing step S130, adjusting the clock check operation of the clock to be verified of the design under test according to the obtained usage of the simulation resources.
[0085] Adjusting the clock check operation of the clock to be verified of the design under test according to the obtained usage of the simulation resources can prevent the clock check operation of the clock to be verified from occupying too many simulation resources.
[0086] In an exemplary embodiment, the step of adjusting the clock check operation of the clock to be verified of the design under test according to the usage of the obtained simulation resources includes: when it is determined that the simulation resources are relatively sufficient according to the usage of the obtained simulation resources, increasing the simulation resources occupied by the clock check operation of the clock to be verified of the design under test; when it is determined that the simulation resources are relatively tight according to the usage of the obtained simulation resources, reducing the simulation resources occupied by the clock check operation of the clock to be verified of the design under test.
[0087] Specifically, dynamic adjustment of the clock check operation of the clock to be verified in the design under test can be achieved by adjusting the module check events, module check weights of multiple modules under test in the design under test, and at least one of the trigger events and check weights of multiple verification clocks in the module under test.
[0088] In one exemplary embodiment, a preset clock trigger network data structure is used to record information about trigger events and check weights for multiple clocks to be verified in the module under test. Accordingly, by adjusting the trigger events and check weights for the multiple clocks to be verified recorded in the clock trigger network data structure, dynamic adjustment of clock check operations for the multiple verification clocks in the module under test is achieved.
[0089] In one exemplary embodiment, the module check network data structure is used to record module check events and module check weights for the clocks to be verified for the multiple modules under test. Accordingly, by adjusting the module check events and module check weights for each module in the module check network data structure, dynamic adjustment of clock check operations for the multiple modules under test in the design under test is achieved.
[0090] In an exemplary embodiment, the clock checking method further includes: when it is determined through the clock checking operation that the clock to be verified has an abnormality or an error, outputting corresponding alarm prompt information.
[0091] The abnormality of the clock to be verified means that before the clock check operation on the clock to be verified is completed, the clock check result of the clock to be verified indicates that the level of the clock to be verified cannot be flipped, such as the clock to be verified is always maintained at a high level or a low level.
[0092] The clock to be verified has an error, which means that the clock check operation on the clock to be verified is completed, and the clock check result of the clock to be verified indicates that the clock period / frequency of the clock to be verified is significantly different from the expected clock period / frequency of the clock to be verified.
[0093] When the clock check operation determines that the clock to be verified has an abnormality or error, the corresponding alarm prompt information is output, so that the user can obtain the information of the abnormality or error of the clock to be verified in time, and can take corresponding measures to improve the utilization of simulation resources.
[0094] In an exemplary embodiment, the clock checking method further includes: when it is determined through the clock checking operation that the clock to be verified is abnormal, stopping the clock checking operation of the clock to be verified.
[0095] If the clock check operation determines that the clock to be verified is abnormal, that is, the level of the clock to be verified remains high or low, indicating that the clock to be verified is no longer operating normally, the clock check operation for the clock to be verified is stopped. This can avoid the waste of simulation resources caused by continuing to execute the clock check operation for the clock to be verified, thereby helping to improve the utilization of simulation resources.
[0096] Correspondingly, an embodiment of the present invention further provides a clock checking device.
[0097] Figure 6 The structure diagram of an embodiment of a clock checking device provided by the technical solution of the present invention is shown. Figure 6 A clock checking device 60 may include: a checking unit 601, adapted to perform a clock checking operation on a clock to be verified of a design under test during simulation verification of the design under test; an acquiring unit 602, adapted to acquire a usage status of simulation resources during simulation verification of the design under test; and an adjusting unit 603, adapted to adjust the clock checking operation of the clock to be verified of the design under test according to the acquired usage status of the simulation resources.
[0098] The clock checking device in the embodiment of the present invention can be used to execute the aforementioned clock checking method, or other functional modules can be used to execute the aforementioned clock checking method. For the clock checking method provided by the embodiment of the present invention, please refer to the detailed description in the above part, which will not be repeated here.
[0099] Correspondingly, an embodiment of the present invention further provides a device, which can implement the clock checking method provided by the embodiment of the present invention by loading the above clock checking method in the form of a program.
[0100] refer to Figure 7 , which shows an optional hardware structure diagram of a device provided by an embodiment of the present invention. The device in the embodiment of the present invention includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.
[0101] In this embodiment, the number of each of the processor 01 , the communication interface 02 , the memory 03 and the communication bus 04 is at least one, and the processor 01 , the communication interface 02 and the memory 03 communicate with each other via the communication bus 04 .
[0102] The communication interface 02 may be an interface of a communication module for network communication, such as an interface of a GSM module.
[0103] The processor 01 may be a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the clock checking method of this embodiment.
[0104] The memory 03 may include a high-speed RAM memory, or may also include a non-volatile memory, such as at least one disk storage. The memory 03 stores one or more computer instructions, which are executed by the processor 01 to implement the clock checking method provided in the aforementioned embodiment.
[0105] It should be noted that the above-mentioned electronic device may also include other devices (not shown) that may not be necessary for understanding the contents disclosed in the embodiments of the present invention; since these other devices may not be necessary for understanding the contents disclosed in the embodiments of the present invention, the embodiments of the present invention will not introduce them one by one.
[0106] Accordingly, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, which is used to implement the clock checking method described in the embodiment of the present invention when executed by a processor.
[0107] An embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the clock checking method provided in the above embodiment.
[0108] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise mentioned, elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any one embodiment may be included in another embodiment and may be replaced by the corresponding configuration of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the appended claims may be combined into embodiments of the present invention, or may be included as new claims in amendments after submitting this application.
[0109] The embodiments of the present invention may be implemented by various means such as hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to the exemplary embodiment of the present invention may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.
[0110] In a firmware or software configuration, the embodiments of the present invention may be implemented in the form of modules, procedures, functions, and the like. Software codes may be stored in a memory unit and executed by a processor. The memory unit may be located inside or outside the processor and may send and receive data to and from the processor via various known means.
[0111] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.
[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A clock checking method, characterized in that: include: During simulation verification of the design under test, a clock check operation is performed on a clock to be verified of the design under test; Obtaining the usage of simulation resources during simulation verification of the design under test; According to the obtained usage of the simulation resources, a clock check operation of the clock to be verified of the design under test is adjusted.
2. The clock checking method according to claim 1, wherein: The performing of a clock check operation on the clock to be verified of the design under test includes: responding to a trigger event of the clock to be verified, checking the clock to be verified within the effective time of the trigger event, wherein the start time of the trigger event is equal to or later than the verification start time of the clock to be verified, and the end time of the trigger event is equal to or earlier than the verification end time of the clock to be verified; The adjusting of the clock check operation of the clock to be verified of the design under test includes adjusting at least one of the start time and the effective time of the trigger event.
3. The clock checking method according to claim 2, wherein: The design under test includes a module under test, the module under test has multiple clocks to be verified, each of the multiple clocks to be verified has a corresponding check weight, and the check weight is a probability of executing a clock check operation for a corresponding clock to be verified among the multiple verification clocks of the module under test; The performing of a clock check operation on a clock to be verified of the design under test comprises: during the simulation verification of the module under test, performing corresponding clock check operations on multiple clocks to be verified of the module under test according to corresponding check weights; The adjusting the clock checking operation of the clock to be verified of the design under test includes: adjusting the checking weights of the multiple clocks to be verified in the module under test.
4. The clock checking method according to claim 3, wherein: Also includes: A preset clock trigger network data structure is used to record the trigger events and check weight information of the multiple clocks to be verified in the module under test.
5. The clock checking method according to any one of claims 1 to 4, wherein: The design under test includes a module under test; The performing a clock check operation on the clock to be verified of the design under test includes: responding to a module check event of the module under test, performing a clock check operation on the clock to be verified of the module under test within the effective time of the module check event, wherein the start time of the module check event is equal to or later than the verification start time of the module under test, and the end time of the module check event is equal to or earlier than the verification end time of the module under test; The adjusting of the clock check operation of the clock to be verified of the design under test includes: adjusting at least one of the start time and the effective time of the module check event.
6. The clock checking method according to claim 5, wherein: The design under test includes a plurality of modules under test, each of the plurality of modules under test having a corresponding module check weight, wherein the module check weight is a probability of executing a clock check operation of a clock to be verified of a corresponding module under test among the plurality of modules under test; The performing of a clock check operation on the clock to be verified of the tested design includes: during the simulation verification of the tested chip, performing corresponding clock check operations on the clocks to be verified of the plurality of tested modules according to corresponding module check weights; The adjusting the clock check operation of the clock to be verified of the design under test includes: adjusting the module check proportions of the multiple modules under test.
7. The clock checking method according to claim 6, wherein: Also includes: A preset module inspection network data structure is used to record information on module inspection events and module inspection proportions of the clocks to be verified of the plurality of modules under test.
8. The clock checking method according to claim 1, wherein: When it is determined through the clock checking operation that the clock to be verified has an abnormality or an error, the method further includes: outputting corresponding alarm prompt information.
9. The clock checking method according to claim 1, wherein: When it is determined through the clock checking operation that the clock to be verified is abnormal, the method further includes: stopping the clock checking operation of the clock to be verified.
10. A clock checking device, characterized in that: include: a checking unit adapted to perform a clock checking operation on a clock to be verified of the design under test during simulation verification of the design under test; an acquisition unit adapted to acquire usage of simulation resources during simulation verification of a design under test; The adjusting unit is adapted to adjust the clock checking operation of the clock to be verified of the design under test according to the usage of the obtained simulation resources.
11. A device, characterized in that The system comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the clock checking method according to any one of claims 1 to 9.
12. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, it is used to implement the clock checking method according to any one of claims 1 to 9.
13. A storage medium, characterized in that: The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the clock checking method according to any one of claims 1 to 9.