Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel is provided with a display area and a non-display area and comprises a plurality of pixel circuits located in the display area, and each pixel circuit comprises a light-emitting device; the at least two power supply selection circuits are located in the non-display area, and each power supply selection circuit is connected with the cathode of the corresponding light-emitting device and is configured to respond to the effective potential of a first control signal in the light-emitting stage and write a first power supply voltage into the cathode of the connected light-emitting device, and the cathodes of the light-emitting devices connected with different power supply selection circuits are electrically isolated. The cathodes of the light-emitting devices connected with different power supply selection circuits are electrically isolated, so that line-by-line lightening of pixels is realized under high resolution, and the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of micro-display products such as AR or VR products, higher requirements are placed on the resolution of display panels.

[0003] Display panels consist of sub-pixels and pixel circuits, which drive the connected sub-pixels to emit light. As the resolution of a display panel increases, the area of ​​each sub-pixel decreases. As a result, in many high-resolution display panels, the pixel circuits are unable to drive the sub-pixels to light up row by row, causing all pixels to light up or off simultaneously. This causes noticeable flicker on the screen, affecting the viewing experience. Summary of the Invention

[0004] The present invention provides a display panel and a display device, which can realize row-by-row lighting of pixels at high resolution and improve display effect.

[0005] According to one aspect of the present invention, there is provided a display panel having a display area and a non-display area, comprising:

[0006] A plurality of pixel circuits are located in the display area, each of the pixel circuits comprising a light emitting device;

[0007] At least two power selection circuits are located in the non-display area, each of the power selection circuits is connected to the cathode of the corresponding light-emitting device, and is configured to write a first power supply voltage to the cathode of the connected light-emitting device in response to the effective potential of a first control signal during the light-emitting stage, wherein the cathodes of the light-emitting devices connected to different power selection circuits are electrically isolated.

[0008] Optionally, in a display frame, the first control signal configured for each power selection circuit enters the effective potential at different times.

[0009] Optionally, each of the power selection circuits is further configured to write a second power supply voltage into the cathode of the connected light-emitting device in response to the effective potential of a second control signal before the light-emitting stage, wherein the first power supply voltage is less than the second power supply voltage.

[0010] Optionally, the second control signal configured for each power selection circuit enters a failure potential at different times.

[0011] Optionally, a plurality of the pixel circuits are arranged into a plurality of rows, and one power selection circuit is connected to cathodes of at least part of the light-emitting devices in an n-th row among the plurality of rows, where n≥1.

[0012] Optionally, one of the power selection circuits is connected to cathodes of at least two rows of the light-emitting devices in the multiple rows.

[0013] Optionally, the pixel circuit includes a driving module, a data writing module, an initialization module and a compensation module, wherein:

[0014] The initialization module is connected to the control terminal of the driving module, and the initialization module is used to write the third power supply voltage into the control terminal of the driving module in a first initialization phase;

[0015] The data writing module is connected to the control terminal of the driving module and has a coupling node, and the data writing module is used to write a first reference voltage into the coupling node during the threshold compensation phase, so that the control terminal of the driving module has an initialization voltage related to the third power supply voltage and the first reference voltage;

[0016] The compensation module is connected between the control terminal and the first terminal of the driving module, and is used to write the threshold voltage of the transistor in the driving module into the control terminal of the driving module during the threshold compensation phase;

[0017] The data writing module is further configured to couple the data voltage to the control terminal of the driving module during the data writing phase;

[0018] A first terminal of the driving module is connected to the anode of the light-emitting device, and a second terminal of the driving module is connected to the third power supply voltage.

[0019] Optionally, each of the power selection circuits is configured to write the second power supply voltage into the cathode of the connected light-emitting device during the first initialization phase, the threshold compensation phase, and the data writing phase.

[0020] Optionally, the driving module includes a first transistor, a first electrode of the first transistor is connected to a third power supply voltage, a second electrode of the first transistor is connected to an anode of the light-emitting device, and a gate of the first transistor is connected to the data writing module, the compensation module, and the initialization module respectively;

[0021] The compensation module includes a second transistor, a first electrode of the second transistor is connected to the first end of the driving module, a second electrode of the second transistor is connected to the control end of the driving module, and a gate of the second transistor is connected to the first scanning signal;

[0022] The initialization module includes a third transistor, a first electrode of the third transistor is connected to the third power supply voltage, a second electrode of the third transistor is connected to the control end of the driving module, and a gate of the third transistor is connected to the second scanning signal.

[0023] Optionally, the data writing module includes a data writing unit, a coupling unit, a storage unit and a reset unit;

[0024] The reset unit is connected to the coupling node, and the reset unit is used to write the first reference voltage into the coupling node during the threshold compensation phase;

[0025] The first end of the coupling unit is connected to the coupling node, and the second end of the coupling unit is connected to the control end of the driving module;

[0026] The data writing unit is connected to the coupling node and is used to write the data voltage into the coupling node during the data writing phase, so that the coupling unit couples the data voltage to the control terminal of the driving module;

[0027] The storage unit is connected to the coupling node.

[0028] Optionally, the storage unit includes a first capacitor, the coupling unit includes a second capacitor, a first end of the first capacitor is connected to the coupling node, a second end of the first capacitor is connected to the third power supply voltage, a first end of the second capacitor is connected to the coupling node, and a second end of the second capacitor is connected to the control end of the driving module; the reset unit includes a fourth transistor, a first electrode of the fourth transistor is connected to the first reference voltage, a second electrode of the fourth transistor is connected to the coupling node, and a gate of the fourth transistor is connected to the third scanning signal;

[0029] The data writing unit includes a fifth transistor, a first electrode of the fifth transistor is connected to the data voltage, a second electrode of the fifth transistor is connected to the coupling node, and a gate of the fifth transistor is connected to a fourth scanning signal.

[0030] Optionally, in a display frame, the fourth scanning signals connected to the pixel circuits corresponding to different power selection circuits enter the effective potential at different moments.

[0031] Optionally, the fourth transistor and the fifth transistor are both oxide transistors, and the first transistor, the second transistor and the third transistor are all low-temperature polysilicon transistors.

[0032] Optionally, the fourth transistor and the fifth transistor are N-type oxide transistors, and the first transistor, the second transistor and the third transistor are P-type low-temperature polysilicon transistors.

[0033] Optionally, the power selection circuit includes a first gating unit;

[0034] The first gating unit is connected to the cathode of the connected light emitting device and is configured to write the first power supply voltage into the cathode of the connected light emitting device in response to an effective potential of the first control signal during a light emitting phase.

[0035] Optionally, the first gating unit includes a sixth transistor, a first electrode of the sixth transistor is connected to the first power supply voltage, a second electrode of the sixth transistor is connected to the cathode of the light-emitting device, and a gate of the sixth transistor is connected to the first control signal.

[0036] Optionally, the power selection circuit includes a first gating unit and a second gating unit;

[0037] The first gating unit is connected to the cathode of the connected light emitting device and is configured to write the first power supply voltage into the cathode of the connected light emitting device in response to the effective potential of the first control signal during the light emitting phase;

[0038] The second gating unit is connected to the cathode of the connected light emitting device and is configured to write the second power supply voltage into the cathode of the light emitting device in response to the effective potential of the second control signal before the light emitting phase.

[0039] Optionally, the first gating unit includes a sixth transistor, a first electrode of the sixth transistor is connected to the first power supply voltage, a second electrode of the sixth transistor is connected to the cathode of the light-emitting device, and a gate of the sixth transistor is connected to the first control signal;

[0040] The second gating unit includes a seventh transistor, a first electrode of the seventh transistor is connected to the second power supply voltage, a second electrode of the seventh transistor is connected to the cathode of the light emitting device, and a gate of the seventh transistor is connected to the second control signal.

[0041] According to another aspect of the present invention, there is provided another display panel having a display area and a non-display area, comprising:

[0042] A plurality of pixel circuits are located in the display area, each of the pixel circuits comprising a light emitting device;

[0043] A plurality of isolation structures are located in the display area, each of the isolation structures encloses a plurality of isolation openings, and the cathode of each light emitter is located in the corresponding isolation opening and overlaps with the corresponding isolation structure;

[0044] at least two power selection circuits located in the non-display area, each of the power selection circuits being connected to a corresponding isolation structure and configured to write a first power supply voltage to a cathode of the light-emitting device through the isolation structure in response to an effective potential of a first control signal during a light-emitting phase;

[0045] Wherein, the isolation structures connected to different power selection circuits are electrically isolated from each other.

[0046] Optionally, in a display frame, the first control signal configured for each power selection circuit enters the effective potential at different times.

[0047] Optionally, a plurality of the isolation structures are arranged in a plurality of rows, and one power selection circuit is connected to at least part of the isolation structures in an n-th row of the plurality of rows, where n≥1;

[0048] Optionally, each of the isolation structures is electrically isolated.

[0049] Optionally, the isolation structures in each row are connected in one piece.

[0050] Optionally, the isolation structures in every m rows are connected in one piece.

[0051] Optionally, each of the power selection circuits is also configured to write a second power supply voltage into the cathode of the connected light-emitting device through the isolation structure in response to the effective potential of the second control signal before the light-emitting stage, wherein the first power supply voltage is less than the second power supply voltage.

[0052] Optionally, the second control signal configured for each power selection circuit enters a failure potential at different times.

[0053] Optionally, the pixel circuit includes a driving module, a data writing module, an initialization module and a compensation module, wherein: the initialization module is connected to the control terminal of the driving module, and the initialization module is used to write a third power supply voltage to the control terminal of the driving module in a first initialization phase; the data writing module is connected to the control terminal of the driving module and has a coupling node, and the data writing module is used to write a first reference voltage to the coupling node in a threshold compensation phase, so that the control terminal of the driving module has an initialization voltage related to the third power supply voltage and the first reference voltage; the compensation module is connected between the control terminal and the first terminal of the driving module, and the compensation module is used to write the threshold voltage of the transistor in the driving module to the control terminal of the driving module in the threshold compensation phase; the data writing module is further used to couple the data voltage to the control terminal of the driving module in the data writing phase; the first terminal of the driving module is connected to the anode of the light-emitting device, and the second terminal of the driving module is connected to the third power supply voltage;

[0054] Each of the power selection circuits is configured to write the second power supply voltage into the cathode of the connected light-emitting device through the isolation structure during the first initialization phase, the threshold compensation phase, and the data writing phase;

[0055] Optionally, the power selection circuit includes a first gating unit and a second gating unit;

[0056] The first gating unit is connected to the cathode of the connected light-emitting device and is configured to write the first power supply voltage into the cathode of the connected light-emitting device through the isolation structure in response to the effective potential of the first control signal during the light-emitting phase;

[0057] The second gating unit is connected to the cathode of the light emitting device and is configured to write the second power supply voltage into the cathode of the light emitting device through the isolation structure in response to the effective potential of the second control signal before the light emitting phase.

[0058] According to another aspect of the present invention, a display device is provided, comprising any one of the display panels described above.

[0059] In the technical solution of the embodiment of the present invention, the power selection circuit is configured to write a first power supply voltage to the corresponding light-emitting device during the light-emitting phase, so that the voltage difference between the anode and cathode of the light-emitting device is greater than the turn-on voltage, thereby illuminating the light-emitting device. Because the display panel includes at least two power selection circuits, each power selection circuit controls the light-emitting device connected to it, and different power selection circuits are connected to different light-emitting devices. Therefore, the light-emitting devices in different rows can be illuminated in a time-sharing manner under the control of different power selection circuits, solving the problem of screen flicker caused by all pixels being illuminated simultaneously and the screen not emitting light for a long time, thereby improving the display effect. At the same time, the power selection circuit is set in the non-display area, which can reduce the area occupied by the display area AA, facilitate the arrangement of more pixels 10 in the display area AA, and thus facilitate the realization of a high resolution of the display panel.

[0060] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0063] Figure 2 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0064] Figure 3 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0065] Figure 4 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0066] Figure 5 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0067] Figure 6 In accordance with Figure 5 The timing drive shown Figure 4 The simulation diagram of the pixel circuit shown;

[0068] Figure 7 A timing diagram of two different light-emitting durations in a pixel circuit provided by an embodiment of the present invention;

[0069] Figure 8 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0070] Figure 9 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0071] Figure 10 A cross-sectional view of a display panel provided by an embodiment of the present invention;

[0072] Figure 11 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0073] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0074] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0075] As described in the background, the pixel circuits in many high-resolution display panels are unable to drive sub-pixels to illuminate row by row. The inventors have discovered that this is due to the relatively small number of transistors in the pixel drive circuit at higher resolutions. Specifically, the prior art generally uses a 7T1C pixel circuit to drive light-emitting devices. However, to increase the resolution of display panels, the number of transistors in the pixel circuit is typically reduced, with 2T1C, 3T1C, or 4T2C circuits used to drive light-emitting devices. However, the 2T1C, 3T1C, or 4T2C circuits lack light-emitting control transistors, resulting in the pixel circuits connecting light-emitting devices in different rows being unable to control the conduction paths for the drive current formed row by row, making it impossible for the pixel circuits to drive the light-emitting devices to illuminate row by row.

[0076] In view of the above problems, the present invention provides a novel display panel to achieve individual control of light emission of different light emitting devices at high resolution. Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the display panel includes: a plurality of pixel circuits located in the display area AA, each pixel circuit including a light emitting device;

[0077] At least two power selection circuits 11 are located in the non-display area NAA, each power selection circuit 11 is connected to the cathode of the corresponding light-emitting device, and is configured to write the first power supply voltage VSS1 into the cathode of the connected light-emitting device in response to the effective potential of the first control signal EM1 during the light-emitting stage, wherein the cathodes of the light-emitting devices connected to different power selection circuits 11 are electrically isolated.

[0078] In this embodiment, a pixel circuit includes a light-emitting device, and a light-emitting device can be regarded as a sub-pixel. Optionally, a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G constitute a pixel 10. The light-emitting device can be an organic light-emitting diode (OLED). The light-emitting device includes an anode and a cathode. When the voltage difference between the anode and the cathode of the light-emitting device is greater than the turn-on voltage of the light-emitting device, the light-emitting device can be illuminated. The turn-on voltage is the external voltage value when driving the light-emitting device to emit light.

[0079] A power selection circuit 11 is connected to at least one light-emitting device. Different power selection circuits 11 are used to individually control the light emission of at least some different light-emitting devices. During the light-emitting phase, the power selection circuit 11 transmits a first power supply voltage VSS1 to the cathode of the connected light-emitting device. The first power supply voltage VSS1 can be a negative voltage, so that the voltage difference between the anode and cathode of the light-emitting device exceeds the turn-on voltage, thereby illuminating the light-emitting device. At least some different light-emitting devices are connected to different power selection circuits 11. Different power selection circuits 11 can transmit the first power supply voltage VSS1 at different times, allowing different light-emitting devices to emit light at different times, thus achieving individual control of the light emission of at least some of the light-emitting devices.

[0080] The power selection circuit 11 primarily functions as a time-sharing voltage transmission mechanism, thereby controlling the light emission of the light-emitting devices. This function is achieved through a switch module. Therefore, compared to the prior art, a 7T1C pixel circuit is typically used to drive the light-emitting devices row by row to achieve row-by-row illumination of pixels. In this 7T1C circuit, the light-emission control transistors (including a first light-emission control transistor and a second light-emission control transistor) and the drive transistor are connected in series between a third power supply and a second power supply, where the third power supply is used to provide a third power supply voltage, and the second power supply is used to provide a first power supply voltage. During the light-emitting phase, the light-emission control transistors are turned on to form a path for the drive current to flow, driving the light-emitting devices to emit light. The light-emission control transistors in different rows are turned on row by row, thereby achieving row-by-row illumination of the light-emitting devices. In this embodiment, light-emission control of the light-emitting devices is achieved through the power selection circuit 11, eliminating the need for additional first and second light-emission control transistors in the pixel circuit. Furthermore, the power selection circuit 11 is located in the non-display area, reducing the area occupied by the display area AA and facilitating high resolution.

[0081] In the technical solution of the embodiment of the present invention, the power selection circuit is configured to write a first power supply voltage to the corresponding light-emitting device during the light-emitting phase, so that the voltage difference between the anode and cathode of the light-emitting device is greater than the turn-on voltage, thereby illuminating the light-emitting device. Because the display panel includes at least two power selection circuits, each power selection circuit controls the light-emitting device connected to it, and different power selection circuits are connected to different light-emitting devices. Therefore, the light-emitting devices in different rows can be illuminated in a time-sharing manner under the control of different power selection circuits, solving the problem of screen flicker caused by all pixels being illuminated simultaneously and the screen not emitting light for a long time, thereby improving the display effect. At the same time, the power selection circuit is set in the non-display area, which can reduce the area occupied by the display area AA, facilitate the arrangement of more pixels 10 in the display area AA, and thus facilitate the realization of a high resolution of the display panel.

[0082] Continue to refer Figure 1 Optionally, during a display frame, the first control signal EM1 configured for each power selection circuit 11 enters an active potential at different times. The first control signal EM1 includes a disabled potential and an active potential. The active potential of the first control signal EM1 is the potential that controls the connection of the first power supply voltage VSS1 to the cathode of the light-emitting device, while the disabled potential of the first control signal EM1 is the potential that disconnects the first power supply voltage VSS1 from the cathode of the light-emitting device. The first control signals EM1 connected to different power selection circuits 11 enter an active potential at different times, causing the light-emitting devices connected to different power selection circuits 11 to be illuminated at different times. Optionally, multiple pixel circuits are arranged in multiple rows, with one power selection circuit 11 connected to each row of pixel circuits. The first control signals EM1 connected to the power selection circuits 11 in each row of pixel circuits sequentially enter an active potential, thereby illuminating the light-emitting devices row by row. Exemplarily, a display panel includes ten power selection circuits 11. The first control signals EM1 connected to each of the ten power selection circuits 11 sequentially enter an active potential, causing each of the ten power selection circuits 11 to control the lighting of the connected light-emitting devices in sequence.

[0083] Continue to refer Figure 1 Optionally, each power selection circuit 11 is further configured to write the second power supply voltage VSS2 into the cathode of the connected light-emitting device in response to the effective potential of the second control signal EM2 before the light-emitting stage, wherein the first power supply voltage is less than the second power supply voltage.

[0084] The second control signal EM2 includes a disabled potential and an active potential. The active potential of the second control signal EM2 is the potential that controls the connection of the second power supply voltage VSS2 to the cathode of the light-emitting device, while the disabled potential of the second control signal EM2 is the potential that disconnects the second power supply voltage VSS2 from the cathode of the light-emitting device. Optionally, within a frame, the phase during which the disabled potential of the first control signal EM1 overlaps the phase during which the active potential of the second control signal EM2 is present. Before the light-emitting phase, the power selection circuit 11 is configured to transmit the second power supply voltage VSS2 to the cathode of the connected light-emitting device. The second power supply voltage VSS2 can be a positive voltage, which minimizes the voltage difference between the anode and cathode of the light-emitting device and prevents it from reaching the turn-on voltage, thereby preventing the light-emitting device from being illuminated. Before the light-emitting phase, connecting the cathode of the light-emitting device to the second power supply voltage VSS2 via the power selection circuit 11 can reduce the time the cathode potential of the light-emitting device remains floating, disconnecting the leakage path of the driver transistor included in the pixel circuit, and thereby improving display uniformity.

[0085] Optionally, the second control signal EM2 configured for each power selection circuit 11 enters the failure potential at different times, so that the first control signal EM1 configured for each power selection circuit 11 enters the valid potential at different times, so that different light-emitting devices connected to each power selection circuit 11 are lit at different times.

[0086] Figure 2 A schematic diagram of another display panel structure provided by an embodiment of the present invention, referring to Figure 2 Optionally, multiple pixel circuits are arranged into multiple rows, and a power selection circuit 11 is connected to the cathodes of at least part of the light-emitting devices in the nth row among the multiple rows, where n≥1.

[0087] In an optional embodiment, one power selection circuit 11 is connected to cathodes of a portion of light-emitting devices in the nth row, and cathodes of another portion of light-emitting devices in the nth row may be connected to at least one other power selection circuit 11 . Figure 2 As shown in the example, a row of pixel circuits is connected to two power selection circuits 11. For example, a row of the display panel includes q columns of pixels. One power selection circuit 11 is connected to h columns in the nth row, and the other power selection circuit 11 is connected to the pixels in the remaining columns of the nth row, that is, to the pixels in qh columns, to achieve bilateral driving. Where q is an integer greater than or equal to 2, and n and h are integers greater than or equal to 1.

[0088] In another alternative embodiment, one power selection circuit 11 is connected to the cathodes of all light-emitting devices in the nth row. That is, one power selection circuit 11 is connected to the light-emitting devices in one row, controlling the light-emitting devices in one row to light up simultaneously. The first control signal EM1 connected to different power selection circuits 11 can sequentially enter the effective potential at different times, thereby achieving row-by-row lighting of the light-emitting devices.

[0089] In another optional embodiment, one power selection circuit 11 is connected to the cathodes of at least two rows of light-emitting devices in a plurality of rows, such as one power selection circuit 11 connected to the cathodes of all light-emitting devices in a plurality of rows, thereby reducing the number of power selection circuits 11. At least two rows of pixel circuits are connected to the same power selection circuit 11. During the light-emitting phase, all light-emitting devices connected to the same power selection circuit 11 emit light simultaneously. Because the first control signal EM1 and the second control signal EM2 are both output signals that are shifted step by step, if the light-emitting devices in L rows of pixel circuits connected to the same power selection circuit 11 are considered as a single light-emitting unit, all light-emitting units emit light sequentially. Exemplarily, one power selection circuit 11 is connected to two adjacent rows of pixel circuits, and the first control signal EM1 and the second control signal EM2 connected to the power selection circuits 11 arranged along the column direction of the pixel circuit arrangement are shifted one by one. In this case, during the driving process of the display panel, after the light-emitting devices in the first and second rows of pixel circuits emit light simultaneously, the light-emitting devices in the third and fourth rows of pixel circuits also emit light simultaneously, and so on, thereby achieving independent control of the light emission of at least some pixel circuits.

[0090] Figure 3 A schematic diagram of another display panel structure provided by an embodiment of the present invention, referring to Figure 2 and Figure 3 Optionally, the pixel circuit includes a driving module 12, a data writing module 13, an initialization module 14 and a compensation module 15; wherein:

[0091] The initialization module 14 is connected to the control terminal N1 of the driving module 12. The initialization module 14 is used to write the third power supply voltage VDD into the control terminal N1 of the driving module 12 during the first initialization phase.

[0092] The data writing module 13 is connected to the control terminal N1 of the driving module 12 and has a coupling node. The data writing module 13 is used to write the first reference voltage Vref into the coupling node during the threshold compensation phase so that the control terminal of the driving module has an initialization voltage related to the third power supply voltage VDD and the first reference voltage Vref.

[0093] The compensation module 15 is connected between the control terminal N1 and the first terminal of the driving module 12. The compensation module 15 is used to write the threshold voltage of the transistor in the driving module 12 into the control terminal N1 of the driving module 12 during the threshold compensation phase.

[0094] The data writing module 13 is used to couple the data voltage Vdata to the control terminal N1 of the driving module 12 during the data writing phase;

[0095] A first terminal of the driving module 12 is connected to the anode of the light emitting device LD, and a second terminal of the driving module 12 is connected to the third power supply voltage VDD.

[0096] The pixel circuit is used to drive the light emitting device LD to emit light, and the pixel circuit can be arranged in a one-to-one correspondence with the light emitting device LD.

[0097] The driver module 12 and the light-emitting device LD are sequentially connected in series between a third power supply voltage VDD and a power supply selection circuit 11 connected to the light-emitting device LD. The data writing module 13 includes at least a switch module. Both the initialization module 14 and the compensation module 15 are switch modules. When the switch module is turned on, the two ends of the switch module are connected. For example, the initialization module 14, when turned on, connects the third power supply voltage VDD to the control terminal N1 of the driver module 12. When the initialization module 14 is turned off, the connection between the third power supply voltage VDD and the control terminal N1 of the driver module 12 is disconnected. The third power supply voltage VDD is greater than the first power supply voltage VSS1.

[0098] The operation process of the pixel circuit sequentially includes a first initialization phase, a threshold compensation phase, a data writing phase, and a light-emitting phase. During the first initialization phase, the initialization module 14 is turned on to transmit the third power supply voltage VDD to the control terminal N1 of the driver module 12, initializing the driver module 12 and preventing the residual charge at the control terminal from affecting the brightness of the current frame. During the threshold compensation phase, the data writing module 13 writes the first reference voltage Vref to the coupling node, thereby transmitting a voltage related to the initialization voltage Vref to the control terminal N1 of the driver module 12. The potential of the control terminal N1 of the driver module 12 decreases, thereby turning on the driver module 12. The third power supply voltage VDD is charged to the control terminal N1 of the driver module 12 through the driver module 12 and the compensation module 15, thereby writing the threshold voltage to the control terminal N1 of the driver module 12. During the threshold compensation phase, the control terminal of the driver module has an initialization voltage related to the third power supply voltage VDD and the first reference voltage Vref. Therefore, in the subsequent light-emitting phase, the driving current generated by the driver module 12 is independent of the third power supply voltage VDD, avoiding the influence of IR drop and improving display uniformity. During the data writing phase, the data writing module 13 is turned on, coupling the data voltage Vdata to the control terminal N1 of the driver module 12. Each power selection circuit 11 is configured to write the second power supply voltage VSS2 to the cathode of the connected light-emitting device LD during the first initialization phase, the threshold compensation phase, and the data writing phase to prevent the light-emitting device LD from being induced. Furthermore, writing the second power supply voltage VSS2 to the cathode of the light-emitting device during the first initialization phase, the threshold compensation phase, and the data writing phase reduces the time the cathode potential remains suspended, cutting off the leakage path between the control terminal of the driver module 12 and the cathode of the light-emitting device. This helps maintain the stability of the potential at the control terminal of the driver module 12 and improves display uniformity. During the light-emitting phase, the power selection circuit 11 writes the first power supply voltage VSS1 to the cathode of the connected light-emitting device LD. The driver module 12 generates a drive current based on the potential at the control terminal N1, driving the light-emitting device LD to emit light. The cathode of the light-emitting device LD is connected to a lower potential, thereby forming a current path between the third power supply voltage VDD and the first power supply voltage VSS1, ensuring that the light-emitting device LD is illuminated.

[0099] Based on the above embodiments, Figure 4 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 4 Optionally, the data writing module 13 includes a data writing unit 131, a coupling unit 132, a storage unit 133 and a reset unit 134;

[0100] The reset unit 134 is connected to the coupling node N2, and the reset unit 134 is used to write the first reference voltage Vref into the coupling node N2 during the threshold compensation phase;

[0101] A first end of the coupling unit 132 is connected to the coupling node N2, and a second end of the coupling unit 132 is connected to the control end N1 of the driving module 12;

[0102] The data writing unit 131 is connected to the coupling node N2 and is used to write the data voltage into the coupling node N2 during the data writing phase, so that the coupling unit 132 couples the data voltage to the control terminal N1 of the driving module 12;

[0103] The storage unit 133 is connected to the coupling node N2. Specifically, a first end of the storage unit 133 is connected to the coupling node N2, and a second end of the storage unit 133 is connected to the third power supply voltage VDD.

[0104] The data write unit 131 has a first terminal connected to the data voltage Vdata, and a second terminal connected to the coupling node N2. The data write unit 131 is a switch unit. When turned on, the data voltage Vdata is connected to the coupling node N2. When turned off, the data voltage Vdata is disconnected from the coupling node N2. The reset unit 134 has a first terminal connected to the first reference voltage Vref, and a second terminal connected to the coupling node N2. The reset unit 134 is a switch unit. When turned on, the first reference voltage Vref is connected to the coupling node N2. When turned off, the reset unit 134 is a switch unit. When turned on, the first reference voltage Vref is connected to the coupling node N2. When turned off, the reset unit 134 is a switch unit. When turned on, the first reference voltage Vref is connected to the coupling node N2.

[0105] The control terminal of the compensation module 15 is connected to the first scanning signal S1, the control terminal of the initialization module 14 is connected to the second scanning signal S2, the control terminal of the reset unit 134 is connected to the third scanning signal S3, and the control terminal of the data writing unit 131 is connected to the fourth scanning signal S4. The initialization module is turned on in response to the active potential of the second scanning signal S2, the compensation module S1 is turned on in response to the active potential of the first scanning signal S1, the reset unit 134 is turned on in response to the active potential of the third scanning signal S3, and the data writing unit 131 is turned on in response to the active potential of the fourth scanning signal S4.

[0106] Continue to refer Figure 4 Optionally, the power selection circuit 11 includes a first gating unit 111; the first gating unit 111 is connected to the cathode of the connected light-emitting device LD, and is used to write the first power supply voltage VSS1 into the cathode of the light-emitting device LD in response to the effective potential of the first control signal EM1 during the light-emitting stage.

[0107] The first gating unit 111 is a switching unit. When the first gating unit 111 is turned on, the first power supply voltage VSS1 is connected to the cathode of the light-emitting device LD connected to the first gating unit 111. When the first gating unit 111 is turned off, the connection between the first power supply voltage VSS1 and the light-emitting device LD is disconnected. The first gating unit included in the power selection circuit 11 is a switching unit with a simple structure and is easy to implement.

[0108] On the basis of the above embodiment, when each power selection circuit 11 is further configured to write the second power supply voltage VSS2 into the cathode of the connected light-emitting device in response to the active potential of the second control signal EM2 before the light-emitting phase, the power selection circuit 11 further includes a second gating unit 112;

[0109] The second gating unit 112 is connected to the cathode of the connected light-emitting device LD and is used to write the second power supply voltage VSS2 into the cathode of the light-emitting device LD in response to the effective potential of the second control signal EM2 before the light-emitting stage, such as the first initialization stage, the threshold compensation stage and the data writing stage.

[0110] The second gating unit 112 is a switching unit. When the second gating unit 112 is turned on, the second power supply voltage VSS2 is connected to the cathode of the light-emitting device LD connected to the second gating unit 112. When the second gating unit 112 is turned off, the connection between the second power supply voltage VSS2 and the light-emitting device LD is disconnected. The power supply selection circuit 11 includes only the first gating unit 111 and the second gating unit 112, and has a simple structure and is easy to implement.

[0111] Figure 5 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention, Figure 6 A simulation waveform diagram of a pixel circuit provided by an embodiment of the present invention, Figure 5 Applies to Figure 4 The pixel circuit shown, Figure 6 In accordance with Figure 5 The timing drive shown Figure 4 The simulation diagram of the pixel circuit shown in the figure is as follows: Figure 6 The horizontal axis is time t, unit is ms, and the vertical axis is voltage U, unit is V. Figure 4-Figure 6 The first gating unit 11 is turned on in response to the effective potential of the first control signal EM1, and the second gating unit 112 is turned on in response to the effective potential of the second control signal EM2. In this embodiment, the effective potentials of the first scan signal S1, the second scan signal S2, the first control signal EM1, and the second control signal EM2 are all low, and the effective potentials of the third scan signal S3 and the fourth scan signal S4 are both high.

[0112] The pixel circuit's operating process includes a pre-stage p0, a first initialization stage P1, a threshold compensation stage P2, a data writing stage P3, a transition stage P4, and a light-emitting stage P5. During the pre-stage p0, the first gating unit 111 is turned off in response to a high level of the first control signal EM1, the compensation module 15 is turned off in response to a high level of the first scan signal S1, the reset unit 134 is turned off in response to a low level of the third scan signal S3, and the data writing unit 131 is turned off in response to a low level of the fourth scan signal S4. The second gating unit 112 is turned on in response to a low level of the second control signal EM2, transmitting the second power supply voltage VSS2 to the cathode of the light-emitting device LD connected to the second gating unit 112, ensuring that the voltage difference between the anode and cathode of the light-emitting device LD is less than the turn-on voltage of the light-emitting device LD, thus ensuring that the light-emitting device is in an extinguished state.

[0113] During the first initialization phase p1, the compensation module 15 is turned off in response to the high level of the first scan signal S1, the reset unit 134 is turned off in response to the low level of the third scan signal S3, the data write unit 131 is turned off in response to the low level of the fourth scan signal S4, and the first selection unit 111 is turned off in response to the high level of the first control signal EM1. The second selection unit 112 is turned on in response to the low level of the second control signal EM2 to transmit the second power supply voltage VSS2 to the cathode of the light-emitting device LD connected to the second selection unit 112. The initialization module 14 is turned on in response to the low level of the second scan signal S2 to transmit the third power supply voltage VDD to the control terminal of the driver module 12, thereby initializing the driver module 12.

[0114] In the threshold compensation phase p2, the initialization module 14 is turned off in response to the high level of the second scan signal S2, the data writing unit 131 is turned off in response to the low level of the fourth scan signal S4, and the first selection unit 111 is turned off in response to the high level of the first control signal EM1. The reset unit 134 is turned on in response to the high level of the third scan signal S3 to write the first reference voltage Vref to the coupling node N2. Because the voltage of the first reference voltage Vref is a negative voltage, before writing the first reference voltage Vref, the potential of the coupling node N2 is the data voltage written in the previous frame. Therefore, after the first reference voltage Vref is written in the current frame, the potential of the coupling node N1 is pulled down. Under the action of capacitive coupling, the potential of the second end of the coupling unit 132 is also pulled down, and the first reference voltage Vref must ensure that the potential of the second end of the coupling unit 132 can be pulled down to V N1 -VDD <V TH , where V N1 is the potential of the second end of the coupling unit 132, V THis the threshold voltage of the transistor in the driving module 12 to ensure that the driving module 12 is turned on. The compensation module 15 is turned on in response to the low level of the first scanning signal S1, and the second end of the driving module 12 is connected to the third power supply voltage VDD. The third power supply voltage VDD is charged to the control end of the driving module 12 through the driving module 12 and the compensation module 15 until the potential of the control end is VDD+V TH , so as to write the threshold voltage of the transistor in the driving module 12 into the control terminal of the driving module 12. In other embodiments, the stage of writing the first reference voltage Vref into the coupling node N2 and the stage of writing the threshold voltage of the transistor in the driving module 12 into the control terminal of the driving module 12 by the compensation module 15 can be two independent stages.

[0115] During data write phase p3, initialization module 14 is turned off in response to the high level of second scan signal S2, compensation module 15 is turned off in response to the high level of first scan signal S1, reset unit 134 is turned off in response to the low level of third scan signal S3, and first selection unit 111 is turned off in response to the high level of first control signal EM1. Data write unit 131 is turned on in response to the high level of fourth scan signal S4 and writes data voltage Vdata to the first terminal of coupling unit 132. The voltage change at the first terminal of coupling unit 132 is Vdata-Vref. Due to the effect of the capacitors in coupling unit 132 and storage unit 133, the voltage change at the second terminal of coupling unit 132 is (Vdata-Vref)*(C1+C2) / C2, where C1 is the capacitance of the capacitor included in storage unit 133, and C2 is the capacitance of the capacitor included in coupling unit 132. Finally, the potential of the control terminal of the driving module 12 is: (Vdata-Vref)*(C1 / C2)-Vref+VDD+Vdata+V TH In this embodiment, the data voltage Vdata writes voltage information related to the data voltage Vdata to the control terminal N1 of the driving module 12 through capacitive coupling, thereby enabling the driving module 12 to control the luminous brightness according to the potential of its own control terminal N1. The data writing unit 132 receives the fourth scanning signal S4 as a row-by-row shift signal to ensure that the data voltage Vdata can be shifted row by row. Since the voltages across the capacitors change synchronously during capacitive coupling, the speed at which the data voltage Vdata is written to the control terminal N1 of the driving module 12 is very fast, making the pixel circuit almost unrestricted in terms of the length of the data writing time, and is suitable for products with a large number of rows.

[0116] During transition phase p4, initialization module 14 is turned off in response to the high level of second scan signal S2, compensation module 15 is turned off in response to the high level of first scan signal S1, reset unit 134 is turned off in response to the low level of third scan signal S3, and data write unit 131 is turned off in response to the low level of fourth scan signal S4. First gating unit 111 is turned off in response to the high level of first control signal EM1. Second gating unit 112 is turned off in response to the high level of the second control signal. During transition phase p4, both first gating unit 111 and second gating unit 112 are turned off. This allows first gating unit 111 to be turned on again after second gating unit 112 is completely turned off in the subsequent light-emitting phase p5. This prevents first gating unit 111 from turning on when second gating unit 112 is not completely turned off, thereby affecting the cathode potential.

[0117] During light-emitting phase p5, the initialization module 14 is turned off in response to the high level of the second scan signal S2, the compensation module 15 is turned off in response to the high level of the first scan signal S1, the reset unit 134 is turned off in response to the low level of the third scan signal S3, and the data write unit 131 is turned off in response to the low level of the fourth scan signal S4. The second gating unit 112 is turned off in response to the high level of the second control signal. The first gating unit 111 is turned on in response to the low level of the first control signal EM1. The driver module 12 generates a drive current based on the potential of the control terminal, driving the light-emitting device LD to emit light. After the cathode of the light-emitting device LD is connected to the second power supply voltage VSS2, a drive current flow path is formed between the third power supply voltage VDD and the second power supply voltage VSS2, ensuring that the light-emitting device LD is illuminated.

[0118] In this embodiment, the first control signal EM1 and the second control signal EM2 connected to the multiple power selection circuits 11 in different rows are provided in a step-by-step manner, thereby enabling the pixels in different rows connected to the different power selection circuits 11 to emit light row by row. This prevents the formation of a path between the data voltage Vdata and the second power supply voltage VSS2 during the data writing phase, thereby preventing the light-emitting device LD from being erroneously illuminated. Furthermore, the cathode potential of the light-emitting device LD is maintained at the first power supply voltage VSS1 before and after data writing, minimizing the time the cathode potential remains suspended, thus cutting off the leakage path of the control terminal N1 of the driver module 12 and preventing the potential of the control terminal N1 of the driver module 12 from being lost after data writing is completed.

[0119] Figure 7 A timing diagram of two different light-emitting durations in a pixel circuit provided by an embodiment of the present invention, referring to Figure 4 and Figure 7 , optional, Figure 7The first and second first control signals EM1 have the same signal period, but the duration of the light-emitting phase p5 corresponding to the first set of timing diagrams is longer than the duration of the light-emitting phase p5 corresponding to the second set of timing diagrams. By adjusting the duty ratio of the first and second control signals EM1 and EM2, the duration of the light-emitting phase p5 can be adjusted, thereby achieving PWM dimming.

[0120] Based on the above embodiment, this embodiment provides a specific pixel circuit structure. Figure 8 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 8 Optionally, the driving module 12 includes a first transistor T1, a first electrode of the first transistor T1 is connected to the third power supply voltage VDD, a second electrode of the first transistor T1 is connected to the anode of the light-emitting device LD, and a gate of the first transistor T1 is respectively connected to the data writing module 13, the compensation module 15 and the initialization module 14;

[0121] The compensation module 15 includes a second transistor T2, a first electrode of the second transistor T2 is connected to the first end of the driving module 12, a second electrode of the second transistor T2 is connected to the control end N1 of the driving module 12, and a gate of the second transistor T2 is connected to the first scanning signal S1;

[0122] The initialization module 14 includes a third transistor T3 , a first electrode of the third transistor T3 is connected to the third power supply voltage VDD, a second electrode of the third transistor T3 is connected to the control terminal N1 of the driving module 12 , and a gate of the third transistor T3 is connected to the second scanning signal S2 .

[0123] Optionally, the storage unit 133 includes a first capacitor Cst1, and the coupling unit 132 includes a second capacitor Cst2, wherein a first end of the first capacitor Cst1 is connected to the coupling node N2, a second end of the first capacitor Cst1 is connected to the third power supply voltage VDD, a first end of the second capacitor Cst2 is connected to the coupling node N2, and a second end of the second capacitor Cst2 is connected to the control terminal N1 of the driving module 12;

[0124] The reset unit 134 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the first reference voltage Vref, a second electrode of the fourth transistor T4 is connected to the coupling node N2, and a gate of the fourth transistor T4 is connected to the third scan signal S3;

[0125] The data writing unit 131 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is connected to the data voltage Vdata, a second electrode of the fifth transistor T5 is connected to the coupling node N2, and a gate of the fifth transistor T5 is connected to the fourth scan signal S4;

[0126] Optionally, the fourth transistor T4 and the fifth transistor T5 are both oxide transistors. Further, the fourth transistor T4 and the fifth transistor T5 are both N-type oxide transistors, thereby reducing the voltage jump at the first terminal of the second capacitor Cst2, thereby reducing the voltage jump at the control terminal N1 of the driving module 12, which is beneficial for maintaining the stability of the potential of the control terminal N1 of the driving module 12, thereby ensuring stable light emission of the light-emitting device LD. The first transistor T1, the second transistor T2, and the third transistor T3 are all low-temperature polysilicon transistors. Further, the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type low-temperature polysilicon transistors. Low-temperature polysilicon transistors have a faster turn-on speed and are more suitable for high-frequency operation of the display panel. Optionally, in a display frame, the fourth scan signal S4 connected to the pixel circuits corresponding to different power selection circuits 11 respectively enters the effective potential at different times, so that the pixel circuits connected to the different power selection circuits 11 are written with data voltages one by one, so that the light-emitting devices in the pixel circuits connected to the different power selection circuits 11 can emit light at different times.

[0127] Continue to refer Figure 8 Optionally, the first gating unit 111 includes a sixth transistor T6, a first electrode of the sixth transistor T6 is connected to the first power supply voltage VSS1, a second electrode of the sixth transistor T6 is connected to the cathode of the light emitting device LD, and a gate of the sixth transistor T6 is connected to the first control signal EM1;

[0128] The second selection unit 112 includes a seventh transistor T7 , a first electrode of the seventh transistor T7 is connected to the second power supply voltage VSS2 , a second electrode of the seventh transistor T7 is connected to the cathode of the light emitting device LD, and a gate of the seventh transistor T7 is connected to the second control signal EM2 .

[0129] Each transistor can be either an N-type transistor or a P-type transistor. In this embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors, and the fourth transistor T4 and the fifth transistor T5 are N-type transistors. Figure 8 The pixel circuit shown can be used Figure 5 The specific working process is the same as the driving timing shown in Figure 4 The working process of the pixel circuit shown is similar and will not be repeated here.

[0130] An embodiment of the present invention further provides another display panel. Figure 9 A schematic diagram of another display panel structure provided by an embodiment of the present invention, referring to Figure 9 The display panel has a display area AA and a non-display area NAA, including:

[0131] A plurality of pixel circuits are located in the display area AA, each pixel circuit including a light emitting device;

[0132] A plurality of isolation structures 16 are located in the display area AA. Each isolation structure 16 encloses a plurality of isolation openings. The cathode of each light emitter is located in a corresponding isolation opening and overlaps with the corresponding isolation structure 16.

[0133] At least two power selection circuits 11 are located in the non-display area NAA, each power selection circuit 11 is connected to a corresponding isolation structure 16, and is configured to write a first power supply voltage VSS1 to the cathode of the light-emitting device through the isolation structure 16 in response to the effective potential of the first control signal EM1 during the light-emitting phase;

[0134] The isolation structures 16 connected to different power selection circuits 11 are electrically isolated from each other.

[0135] An isolation structure 16 is disposed around the periphery of each light-emitting device. This isolation structure 16 is fabricated before forming the cathode of the light-emitting device. The isolation structure 16 has a certain height so that the protruding isolation structure 16 can isolate the cathodes of different light-emitting devices during the deposition of the cathodes. The isolation structure 16 can have a structure that is wide at the top and narrow at the bottom, for example, with an inverted trapezoidal cross-section. Each isolation structure 16 can overlap the cathode of at least one light-emitting device. A power selection circuit 11 is connected to at least one isolation structure, and the first power supply voltage VSS1 is then written to the cathode of each corresponding light-emitting device via the isolation structure 16. The isolation structures 16 connected to different power selection circuits 11 are electrically isolated from each other, thereby electrically isolating the light-emitting devices corresponding to the different power selection circuits 11. This allows the different light-emitting devices connected to different power selection circuits 11 to be independently controlled, further enabling the different light-emitting devices to emit light at different times.

[0136] In the technical solution of an embodiment of the present invention, the power selection circuit is configured to write a first power supply voltage to the corresponding light-emitting device through an isolation structure during the light-emitting phase, so that the voltage difference between the anode and cathode of the light-emitting device is greater than the turn-on voltage, thereby illuminating the light-emitting device. Because the display panel includes at least two power selection circuits, each power selection circuit controls the light-emitting device connected to it, and different power selection circuits are connected to different light-emitting devices. Therefore, light-emitting devices in different rows can be illuminated in a time-sharing manner under the control of different power selection circuits, solving the problem of screen flicker caused by all pixels being illuminated simultaneously and the screen being non-luminous for a long time, thereby improving the display effect. At the same time, the power selection circuit is located in the non-display area, which can reduce the area occupied by the display area AA, facilitate the arrangement of more pixels in the display area, and thus facilitate the realization of a high resolution of the display panel.

[0137] Figure 10A cross-sectional view of a display panel provided by an embodiment of the present invention, wherein: Figure 10 For the Figure 9 The cross-section of AA', see Figure 9 and Figure 10 Optionally, in a display frame, the first control signal EM1 configured for each power selection circuit 11 enters an effective potential at different times. The first control signal EM1 connected to different power selection circuits 11 enters an effective potential at different times, so that the light-emitting devices connected to different power selection circuits 11 are illuminated at different times.

[0138] Optionally, multiple isolation structures 16 are arranged in multiple rows, and one power selection circuit 11 is connected to at least a portion of the isolation structures 16 in the nth row, where n ≥ 1. Optionally, multiple isolation structures 16 are arranged in a row, and one power selection circuit 11 writes the first power supply voltage VSS1 to the corresponding light-emitting device through at least a portion of the isolation structures 16 in the row. In one optional embodiment, a row of isolation structures 16 may correspond to multiple power selection circuits 11, such as one power selection circuit 11 connected to a portion of the isolation structures 16 in the nth row, and another power selection circuit 11 connected to another portion of the isolation structures 16 in the nth row, thereby enabling multiple power selection circuits 11 to drive the pixel circuits in a row to emit light. In another optional embodiment, the isolation structures 16 in the nth row are electrically connected, and one power selection circuit 11 is connected to the isolation structures 16 in a row, so that one power selection circuit 11 drives the light-emitting devices in a row of pixel circuits to emit light simultaneously. Optionally, the isolation structures 16 are electrically isolated, and one power selection circuit 11 is connected to one isolation structure 16, so that different light-emitting devices corresponding to different isolation structures 16 can be independently controlled. When the power selection circuit 11 and the cathode of the light-emitting device are formed in different layers, they can be connected through vias. The power selection circuit 11 is disposed in the border area of ​​the non-display area NAA. When the isolation structure 16 is an integrated structure, the power selection circuit 11 is electrically connected to the portion of the isolation structure near the border area, which is easier to implement.

[0139] Optionally, the isolation structures 16 in each row are connected in one piece, and one isolation structure 16 is connected to a corresponding power selection circuit 11, and the first control signal EM1 connected to the isolation structures 16 of different rows is controlled to enter the effective potential in turn, so that the light-emitting devices in different rows can emit light row by row. When preparing the isolation structure 16, the entire layer of conductive metal material can be evaporated, and then patterned to form a plurality of openings, and the light-emitting layer and the cathode layer are deposited in the openings. Among them, the conductive metal material evaporated at the isolation structure boundary area CT when the isolation structure 16 is formed is etched away to ensure the electrical isolation edge between the isolation structures 16 of different rows. Optionally, the isolation structures 16 in every m rows are connected in one piece, and m is a positive integer greater than or equal to 2, such as Figure 9The illustration shows the integrated connection of isolation structures 16 corresponding to every two rows of pixels. An isolation structure boundary region CT exists between each two rows of pixels 10. During the deposition of cathode conductive material, the deposited cathode conductive material is etched away from the isolation structure boundary region CT, eliminating the cathode conductive material. This insulates the isolation structures 16 at both ends of the isolation structure boundary region CT, enabling independent control of the light emission of each two rows of pixels. A power selection circuit 11 is connected to every m rows. By sequentially controlling the first control signal EM1 supplied to different isolation structures 16 to an effective potential, m rows of light-emitting devices are simultaneously illuminated, with each m row emitting light sequentially.

[0140] Continue to refer Figure 9 and Figure 10 Optionally, each power selection circuit 11 is further configured to, prior to the light-emitting phase, respond to the active voltage of the second control signal EM2 and, through the isolation structure, write the second power supply voltage VSS2 to the cathode of the connected light-emitting device, where the first power supply voltage is less than the second power supply voltage. The first power supply voltage VSS1 can be a negative voltage, and the second power supply voltage VSS2 can be a positive voltage. Before the light-emitting phase, the second power supply voltage VSS2 is written to the cathode of the connected light-emitting device through the isolation structure 16 to prevent the light-emitting device from being induced. Optionally, the second control signal EM2 configured in each power selection circuit 11 enters a disabled voltage at different times.

[0141] refer to Figure 3 、 Figure 9 and Figure 10 Optionally, the pixel circuit includes a driving module 12, a data writing module 13, an initialization module 14 and a compensation module 15, wherein: the initialization module 14 is connected to the control terminal N1 of the driving module 12, and the initialization module 14 is used to write the third power supply voltage VDD into the control terminal N1 of the driving module 12 in a first initialization phase; the data writing module 13 is connected to the control terminal of the driving module 15 and has a coupling node, and the data writing module 13 is used to write the first reference voltage Vref into the coupling node in a threshold compensation phase, so that the control terminal of the driving module 12 has an initialization voltage related to the third power supply voltage VDD and the first reference voltage Vref; the compensation module 15 is connected between the control terminal N1 and the first terminal of the driving module 12, and the compensation module 15 is used to write the threshold voltage of the transistor in the driving module 12 into the control terminal N1 of the driving module 12 in the threshold compensation phase; the data writing module 13 is further used to couple the data voltage to the control terminal N1 of the driving module 12 in the data writing phase; the first terminal of the driving module 12 is connected to the anode of the light-emitting device LD, and the second terminal of the driving module 12 is connected to the third power supply voltage VDD;

[0142] Each power selection circuit 11 is configured to write the second power supply voltage VSS2 to the cathode of the connected light-emitting device via the isolation structure 16 during the first initialization phase, the threshold compensation phase, and the data writing phase to prevent the light-emitting device LD from being erroneously illuminated. Furthermore, writing the second power supply voltage VSS2 to the cathode of the connected light-emitting device via the isolation structure 16 during the first initialization phase, the threshold compensation phase, and the data writing phase can reduce the time the cathode potential of the light-emitting device remains suspended, cut off the leakage path of the driver module 12, and facilitate improved display uniformity.

[0143] refer to Figure 4 、 Figure 9 and Figure 10 , Optionally, the power selection circuit 11 includes a first gating unit 111 and a second gating unit 112;

[0144] The first gating unit 111 is connected to the cathode of the connected light emitting device LD and is configured to write the first power supply voltage VSS1 into the cathode of the connected light emitting device through the isolation structure 16 in response to the effective potential of the first control signal EM1 during the light emitting phase;

[0145] The second gating unit 112 is connected to the cathode of the light emitting device LD and is configured to write the second power supply voltage VSS2 into the cathode of the light emitting device through the isolation structure 16 in response to the active potential of the second control signal EM2 before the light emitting phase.

[0146] Both the first gating unit 111 and the second gating unit 112 are switching units. When turned on, they connect the two ends of the units. Taking the first gating unit 111 as an example, when the first gating unit 111 is turned on, the light-emitting device LD is connected to the first power supply voltage VSS1 through the isolation structure 16. When the first gating unit 111 is turned off, the connection between the light-emitting device LD and the first power supply voltage VSS1 is severed. The power selection circuit 11 uses the isolation structure connected by the two gating units to connect the first power supply voltage VSS1 and the second power supply voltage VSS2 to the corresponding light-emitting device in a time-sharing manner, thereby controlling the light emission of the light-emitting device. This simple structure is easy to implement.

[0147] An embodiment of the present invention further provides a display device, Figure 11 This is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, wherein the display device includes the above-mentioned display panel 3. The display device 2 can be Figure 11 The mobile phone shown may also be a computer, a television, a smart wearable display device, etc., and the embodiment of the present invention does not specifically limit this.

[0148] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0149] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: It has a display area and a non-display area, including: A plurality of pixel circuits are located in the display area, each of the pixel circuits comprising a light emitting device; At least two power selection circuits are located in the non-display area, each of the power selection circuits is connected to the cathode of the corresponding light-emitting device, and is configured to write a first power supply voltage to the cathode of the connected light-emitting device in response to the effective potential of a first control signal during the light-emitting stage, wherein the cathodes of the light-emitting devices connected to different power selection circuits are electrically isolated.

2. The display panel according to claim 1, wherein: In a display frame, the first control signal configured for each of the power selection circuits enters the effective potential at different times.

3. The display panel according to claim 1, wherein: Each of the power selection circuits is further configured to write a second power supply voltage into the cathode of the connected light-emitting device in response to an effective potential of a second control signal before the light-emitting phase, wherein the first power supply voltage is less than the second power supply voltage; Preferably, the second control signal configured for each of the power selection circuits enters a failure potential at different times.

4. The display panel according to claim 1, wherein: The plurality of pixel circuits are arranged in a plurality of rows, and one power selection circuit is connected to cathodes of at least part of the light-emitting devices in an n-th row among the plurality of rows, where n≥1; Preferably, one power selection circuit is connected to cathodes of at least two rows of the light emitting devices in the plurality of rows.

5. The display panel according to claim 3, wherein: The pixel circuit includes a driving module, a data writing module, an initialization module and a compensation module, wherein: The initialization module is connected to the control terminal of the driving module, and the initialization module is used to write the third power supply voltage into the control terminal of the driving module in a first initialization phase; The data writing module is connected to the control terminal of the driving module and has a coupling node, and the data writing module is used to write a first reference voltage into the coupling node during the threshold compensation phase, so that the control terminal of the driving module has an initialization voltage related to the third power supply voltage and the first reference voltage; The compensation module is connected between the control terminal and the first terminal of the driving module, and is used to write the threshold voltage of the transistor in the driving module into the control terminal of the driving module during the threshold compensation phase; The data writing module is further configured to couple the data voltage to the control terminal of the driving module during the data writing phase; The first end of the driving module is connected to the anode of the light-emitting device, and the second end of the driving module is connected to the third power supply voltage; Preferably, each of the power selection circuits is used to write the second power supply voltage into the cathode of the connected light-emitting device during the first initialization phase, the threshold compensation phase, and the data writing phase; Preferably, the driving module includes a first transistor, a first electrode of the first transistor is connected to a third power supply voltage, a second electrode of the first transistor is connected to an anode of the light-emitting device, and a gate of the first transistor is connected to the data writing module, the compensation module, and the initialization module respectively; The compensation module includes a second transistor, a first electrode of the second transistor is connected to the first end of the driving module, a second electrode of the second transistor is connected to the control end of the driving module, and a gate of the second transistor is connected to the first scanning signal; The initialization module includes a third transistor, a first electrode of the third transistor is connected to the third power supply voltage, a second electrode of the third transistor is connected to the control end of the driving module, and a gate of the third transistor is connected to the second scanning signal.

6. The display panel according to claim 5, wherein: The data writing module includes a data writing unit, a coupling unit, a storage unit and a reset unit; The reset unit is connected to the coupling node, and the reset unit is used to write the first reference voltage into the coupling node during the threshold compensation phase; The first end of the coupling unit is connected to the coupling node, and the second end of the coupling unit is connected to the control end of the driving module; The data writing unit is connected to the coupling node and is used to write the data voltage into the coupling node during the data writing phase, so that the coupling unit couples the data voltage to the control terminal of the driving module; The storage unit is connected to the coupling node; Preferably, the storage unit includes a first capacitor, the coupling unit includes a second capacitor, a first end of the first capacitor is connected to the coupling node, a second end of the first capacitor is connected to the third power supply voltage, a first end of the second capacitor is connected to the coupling node, and a second end of the second capacitor is connected to the control end of the driving module; the reset unit includes a fourth transistor, a first electrode of the fourth transistor is connected to the first reference voltage, a second electrode of the fourth transistor is connected to the coupling node, and a gate of the fourth transistor is connected to the third scanning signal; The data writing unit includes a fifth transistor, a first electrode of the fifth transistor is connected to the data voltage, a second electrode of the fifth transistor is connected to the coupling node, and a gate of the fifth transistor is connected to the fourth scanning signal; Preferably, in a display frame, the fourth scanning signals connected to the pixel circuits corresponding to different power selection circuits enter the effective potential at different moments respectively; Preferably, the fourth transistor and the fifth transistor are both oxide transistors, and the first transistor, the second transistor and the third transistor are all low-temperature polysilicon transistors; Preferably, the fourth transistor and the fifth transistor are N-type oxide transistors, and the first transistor, the second transistor and the third transistor are P-type low-temperature polysilicon transistors.

7. The display panel according to any one of claims 1 to 6, characterized in that: The power selection circuit includes a first gating unit; The first gating unit is connected to the cathode of the connected light-emitting device, and is used to write the first power supply voltage into the cathode of the connected light-emitting device in response to the effective potential of the first control signal during the light-emitting phase; Preferably, the first gating unit includes a sixth transistor, a first electrode of the sixth transistor is connected to the first power supply voltage, a second electrode of the sixth transistor is connected to the cathode of the light-emitting device, and a gate of the sixth transistor is connected to the first control signal.

8. The display panel according to claim 3, wherein: The power selection circuit includes a first gating unit and a second gating unit; The first gating unit is connected to the cathode of the connected light emitting device and is configured to write the first power supply voltage into the cathode of the connected light emitting device in response to the effective potential of the first control signal during the light emitting phase; The second gating unit is connected to the cathode of the connected light emitting device and is used to write the second power supply voltage into the cathode of the light emitting device in response to the effective potential of the second control signal before the light emitting phase; Preferably, the first gating unit includes a sixth transistor, a first electrode of the sixth transistor is connected to the first power supply voltage, a second electrode of the sixth transistor is connected to the cathode of the light-emitting device, and a gate of the sixth transistor is connected to the first control signal; The second gating unit includes a seventh transistor, a first electrode of the seventh transistor is connected to the second power supply voltage, a second electrode of the seventh transistor is connected to the cathode of the light emitting device, and a gate of the seventh transistor is connected to the second control signal.

9. A display panel, characterized in that: It has a display area and a non-display area, including: A plurality of pixel circuits are located in the display area, each of the pixel circuits comprising a light emitting device; A plurality of isolation structures are located in the display area, each of the isolation structures encloses a plurality of isolation openings, and the cathode of each light emitter is located in the corresponding isolation opening and overlaps with the corresponding isolation structure; at least two power selection circuits located in the non-display area, each of the power selection circuits being connected to a corresponding isolation structure and configured to write a first power supply voltage to a cathode of the light-emitting device through the isolation structure in response to an effective potential of a first control signal during a light-emitting phase; Wherein, the isolation structures connected to different power selection circuits are electrically isolated from each other.

10. The display panel according to claim 9, wherein: In a display frame, the first control signal configured for each power selection circuit enters the effective potential at different times; Preferably, the plurality of isolation structures are arranged in a plurality of rows, and one power selection circuit is connected to at least part of the isolation structures in the nth row of the plurality of rows, where n≥1; Preferably, each of the isolation structures is electrically isolated; Preferably, the isolation structures in each row are connected in one piece; Preferably, the isolation structures in every m rows are connected in one piece.

11. The display panel according to claim 9, wherein Each of the power selection circuits is further configured to, before the light emitting phase, write a second power supply voltage into the cathode of the connected light emitting device through the isolation structure in response to an effective potential of a second control signal, wherein the first power supply voltage is less than the second power supply voltage; Preferably, the second control signal configured for each of the power selection circuits enters a failure potential at different times; Preferably, the pixel circuit includes a driving module, a data writing module, an initialization module, and a compensation module, wherein: the initialization module is connected to the control terminal of the driving module, and is used to write a third power supply voltage to the control terminal of the driving module in a first initialization phase; the data writing module is connected to the control terminal of the driving module and has a coupling node, and is used to write a first reference voltage to the coupling node in a threshold compensation phase, so that the control terminal of the driving module has an initialization voltage related to the third power supply voltage and the first reference voltage; the compensation module is connected between the control terminal and the first terminal of the driving module, and is used to write the threshold voltage of the transistor in the driving module to the control terminal of the driving module in the threshold compensation phase; the data writing module is further used to couple the data voltage to the control terminal of the driving module in the data writing phase; the first terminal of the driving module is connected to the anode of the light-emitting device, and the second terminal of the driving module is connected to the third power supply voltage; Each of the power selection circuits is configured to write the second power supply voltage into the cathode of the connected light-emitting device through the isolation structure during the first initialization phase, the threshold compensation phase, and the data writing phase; Preferably, the power selection circuit includes a first gating unit and a second gating unit; The first gating unit is connected to the cathode of the connected light-emitting device and is configured to write the first power supply voltage into the cathode of the connected light-emitting device through the isolation structure in response to the effective potential of the first control signal during the light-emitting phase; The second gating unit is connected to the cathode of the light emitting device and is configured to write the second power supply voltage into the cathode of the light emitting device through the isolation structure in response to the effective potential of the second control signal before the light emitting phase.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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