Signal calibration method for flash memory chip and flash memory controller

Abstract

The invention provides a signal calibration method for a flash memory chip and a flash memory controller, and the signal calibration method for the flash memory chip comprises the steps: obtaining a first calibration value which enables a first signal of the flash memory chip coupled with a first channel to be delayed by a specified period through a first calibration device; the first calibration device calibrates the first signal according to the first calibration value; acquiring a second calibration value according to the first calibration value; the second calibration device calibrates a second signal of the flash memory chip coupled with the second flash memory channel according to the second calibration value.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a signal calibration method for a flash memory chip and a flash memory controller. Background Art

[0002] Interface standards such as ONFI and TOGGLE define how to operate NAND flash memory. When operating NAND flash memory, it is necessary to adjust the sampling window of the sampling signal relative to the DQ signal, sampling the DQ signal at the appropriate time to obtain ideal data. ONFI, TOGGLE, and other interface standards also define signals such as DQS and CLK used to access NAND flash memory.

[0003] When sending a program command to the NAND flash memory, the flash memory controller provides the DQS and DQ signals to the NAND flash memory. The flash memory controller needs to adjust the phase of the DQS signal so that the DQ signal appears and stabilizes when the DQS signal transitions. The ideal phase difference between the DQS signal and the DS signal is 1T / 4 (T is the period of the DQS signal).

[0004] When sending a read command to NAND flash memory, the NAND flash memory provides DQS and DQ signals to the flash memory controller. In some cases, the DQS and DQ signals provided by the NAND flash memory are in phase. The flash memory controller needs to delay the DQS signal so that the DQ signal is present and stable when the DQS signal transitions. The ideal phase difference between the DQS signal and the DS signal used for reading data is 1T / 4. Summary of the Invention

[0005] Due to changes in integrated circuit technology, operating temperature, and operating voltage, the phase difference between the DQS signal and the DS signal also changes. Therefore, the ideal sampling position of the DQ signal needs to be tracked in the flash memory controller.

[0006] A flash memory controller may include multiple flash memory channels, each of which provides its own DQS / CLK signals and connects to the flash memory chips on its own flash memory channel. Obtaining independent calibration values ​​for the DQS / CLK signals coupled to each flash memory chip increases the calibration process time and the usage of the flash memory channels.

[0007] The present application provides a signal calibration method for a flash memory chip and a flash memory controller to solve one or more problems existing in the prior art.

[0008] According to the first aspect of the present application, a signal calibration method for a first flash memory chip according to the first aspect of the present application is provided, which includes: obtaining a first calibration value that delays a first signal coupled to the flash memory chip by a specified period through a first calibration device; and the first calibration device calibrates the first signal based on the first calibration value.

[0009] According to the first signal calibration method for a flash memory chip according to the first aspect of the present application, a second signal calibration method for a flash memory chip according to the first aspect of the present application is provided, wherein first data is read from the flash memory chip based on a first calibration value; and the first calibration value is updated based on whether the first data is correct.

[0010] According to the first or second signal calibration method for a flash memory chip according to the first aspect of the present application, a third signal calibration method for a flash memory chip according to the first aspect of the present application is provided, wherein first data is read from the flash memory chip based on a first calibration value; and based on whether the first data is correct, an optimal first calibration value is selected from multiple first calibration values.

[0011] According to one of the first to third signal calibration methods for flash memory chips according to the first aspect of the present application, a fourth signal calibration method for flash memory chips according to the first aspect of the present application is provided, which further includes: obtaining a second calibration value based on the first calibration value; and a second calibration device calibrating the second signal coupled to the flash memory chip based on the second calibration value.

[0012] According to one of the first to fourth signal calibration methods for flash memory chips according to the first aspect of the present application, a fifth signal calibration method for flash memory chips according to the first aspect of the present application is provided, which further includes: obtaining a second calibration value that delays the second signal coupled to the flash memory chip by a specified period through a second calibration device; and recording the association relationship mapping the first calibration value to the second calibration value.

[0013] According to the fifth signal calibration method for flash memory chips according to the first aspect of the present application, a sixth signal calibration method for flash memory chips according to the first aspect of the present application is provided, which is characterized in that it also includes: recording the association relationship between the first calibration value and the second calibration value under multiple operating temperatures and / or operating voltages.

[0014] According to one of the fourth to sixth signal calibration methods for flash memory chips according to the first aspect of the present application, a seventh signal calibration method for flash memory chips according to the first aspect of the present application is provided, which further includes: reading second data from the flash memory chip based on the second calibration value; and updating the second calibration value based on whether the second data is correct.

[0015] According to one of the fourth to seventh signal calibration methods for flash memory chips according to the first aspect of the present application, an eighth signal calibration method for flash memory chips according to the first aspect of the present application is provided, which further includes: periodically or non-periodically updating the association relationship.

[0016] According to one of the fifth to eighth signal calibration methods for flash memory chips according to the first aspect of the present application, a ninth signal calibration method for flash memory chips according to the first aspect of the present application is provided, which further includes: obtaining a second calibration value based on the first calibration value and the association relationship; and a second calibration device calibrates the second signal coupled to the flash memory chip based on the second calibration value.

[0017] According to one of the fifth to ninth signal calibration methods for flash memory chips according to the first aspect of the present application, a tenth signal calibration method for flash memory chips according to the first aspect of the present application is provided, which further includes: obtaining a first correlation corresponding to the current operating temperature and / or operating voltage; obtaining a second calibration value based on the first calibration value and the first correlation; and a second calibration device calibrating the second signal coupled to the flash memory chip based on the second calibration value.

[0018] According to one of the fifth to tenth signal calibration methods for flash memory chips according to the first aspect of the present application, an eleventh signal calibration method for flash memory chips according to the first aspect of the present application is provided, wherein the correlation relationship satisfies a linear equation with a slope of 1.

[0019] According to one of the fifth to eleventh signal calibration methods for flash memory chips according to the first aspect of the present application, a twelfth signal calibration method for flash memory chips according to the first aspect of the present application is provided, wherein the association relationship is recorded in a lookup table.

[0020] According to the second aspect of the present application, a signal calibration method for a first flash memory chip according to the second aspect of the present application is provided, which includes: a first calibration device in a flash memory controller calibrates a first signal based on a first calibration value; the flash memory controller reads first data from the flash memory chip; if the first data is correct, records the first calibration value; and the first calibration device calibrates the first signal sent to the flash memory chip based on the first calibration value.

[0021] According to the first signal calibration method for flash memory chips according to the second aspect of the present application, a second signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein an optimal first calibration value is selected from multiple first calibration values ​​that can obtain correct first data.

[0022] According to the second signal calibration method for flash memory chips according to the second aspect of the present application, a third signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein the middle value or average value of multiple first calibration values ​​that can obtain correct first data is selected as the optimal first calibration value.

[0023] According to one of the first to third signal calibration methods for flash memory chips according to the second aspect of the present application, a fourth signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein the first data is compared with known reference data to determine whether the first data is correct.

[0024] According to one of the first to third signal calibration methods for flash memory chips according to the second aspect of the present application, a fifth signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein an ECC decoder is used to perform error correction on the first data to determine whether the first data is correct.

[0025] According to one of the first to fifth signal calibration methods for flash memory chips according to the second aspect of the present application, a sixth signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein at least one second calibration device is set with a first calibration value to calibrate at least a second signal sent to the flash memory chip.

[0026] According to one of the first to fifth signal calibration methods for flash memory chips according to the second aspect of the present application, a seventh signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein:

[0027] A second calibration value is obtained according to the first calibration value, and at least one second calibration device is set using the second calibration value to calibrate at least a second signal sent to the flash memory chip.

[0028] According to the seventh signal calibration method for flash memory chips according to the second aspect of the present application, an eighth signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein the first calibration value is mapped by a linear equation to obtain the second calibration value.

[0029] According to the eighth signal calibration method for flash memory chips according to the second aspect of the present application, a ninth signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein the slope of the linear equation is not equal to 1.

[0030] According to the eighth signal calibration method for flash memory chips according to the second aspect of the present application, a tenth signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein the slope of the linear equation is equal to 1 and the constant term is 0.

[0031] According to the eighth signal calibration method for flash memory chips according to the second aspect of the present application, an eleventh signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein the slope and constant term of the linear equation are different for different second calibration devices.

[0032] According to the eighth signal calibration method for flash memory chips according to the second aspect of the present application, a twelfth signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein each second calibration device has its own linear equation parameters, the slope of the linear equation parameters of each second calibration device is the same, and the constant terms are different.

[0033] According to the eighth signal calibration method for flash memory chips according to the second aspect of the present application, a thirteenth signal calibration method for flash memory chips according to the second aspect of the present application is provided, wherein the slope and / or constant term of the linear equation is determined by temperature.

[0034] According to the eighth signal calibration method for flash memory chips according to the second aspect of the present application, a fourteenth signal calibration method for flash memory chips according to the second aspect of the present application is provided, which includes: obtaining the current temperature of the flash memory controller, and determining the parameters of the linear equation for the second calibration device according to the current temperature.

[0035] According to one of the first to sixth signal calibration methods for flash memory chips according to the second aspect of the present application, a fifteenth signal calibration method for flash memory chips according to the second aspect of the present application is provided, which includes: a first calibration controller of a first calibration device searches for a third calibration value; a first delay line obtains a first calibration value based on the third calibration value; the first delay line delays the first signal based on the first calibration value and provides it to the flash memory chip.

[0036] According to one of the first to seventh signal calibration methods for flash memory chips according to the second aspect of the present application, a sixteenth signal calibration method for flash memory chips according to the second aspect of the present application is provided, which further includes: a first calibration controller searches for a fourth calibration value; at least two second delay lines connected in series delay the first signal according to the fourth calibration value to obtain a third signal, and output the third signal to the input end of a D-type flip-flop; a clock end of the D-type flip-flop receives the first signal, and an output of the D-type flip-flop is provided to the first calibration controller; in response to a flip of the output of the D-type flip-flop, the first calibration controller sets the fourth calibration value to the first calibration value.

[0037] According to the sixteenth signal calibration method for flash memory chips according to the second aspect of the present application, there is provided a seventeenth signal calibration method for flash memory chips according to the second aspect of the present application, wherein a first calibration controller searches for a fourth calibration value range that causes the D flip-flop to flip, and selects an optimal fourth calibration value from the fourth calibration value range.

[0038] According to the eighth signal calibration method for a flash memory chip according to the second aspect of the present application, an eighteenth signal calibration method for a flash memory chip according to the second aspect of the present application is provided, wherein a first calibration value is obtained and set during an idle time when there is no data transmission on the flash memory channel.

[0039] According to a third aspect of the present application, a first flash memory controller according to the third aspect of the present application is provided, comprising a first calibration device, a mapping device and at least one second calibration device; the first calibration device calibrates a first signal coupled to the flash memory chip; the first calibration device outputs a first calibration value for calibrating the first signal; the mapping device maps the first calibration value to a second calibration value; and the second calibration device uses the second calibration value to calibrate the second signal coupled to the flash memory chip.

[0040] According to the first flash memory controller of the third aspect of the present application, a second flash memory controller according to the third aspect of the present application is provided, wherein the first calibration device is coupled to the mapping device to provide a first calibration value to the mapping device; the second calibration device is coupled to the mapping device to obtain a second calibration value from the mapping device.

[0041] According to the first or second flash memory controller of the third aspect of the present application, a third flash memory controller according to the third aspect of the present application is provided, wherein the mapping device linearly transforms the first calibration value to obtain the second calibration value; or the mapping device obtains the second calibration value by querying a lookup table with the first calibration value as an index.

[0042] According to one of the first to third flash memory controllers of the third aspect of the present application, a fourth flash memory controller according to the third aspect of the present application is provided, wherein the flash memory controller also includes a third calibration device; the mapping device maps the first calibration value to a third calibration value; and the third calibration device uses the third calibration value to calibrate a third signal coupled to the flash memory chip.

[0043] According to one of the first to fourth flash memory controllers of the third aspect of the present application, a fifth flash memory controller according to the third aspect of the present application is provided, wherein the first signal is a DQS signal for accessing the flash memory chip; and the second signal is a CLK signal for accessing the flash memory chip.

[0044] According to one of the first to fifth flash memory controllers of the third aspect of the present application, a sixth flash memory controller according to the third aspect of the present application is provided, wherein a first calibration device includes a first calibration controller, a D-type flip-flop, and a first delay line and a second delay line connected in series; a first signal is coupled to the input end of the first delay line; the first calibration controller selects the taps of the first delay line and the second delay line; the output end of the second delay line is coupled to the input end of the D-type flip-flop, the clock end of the D-type flip-flop is coupled to the first signal, and the output end of the D-type flip-flop is coupled to the first calibration controller.

[0045] According to the sixth flash memory controller of the third aspect of the present application, a seventh flash memory controller according to the third aspect of the present application is provided, wherein the first calibration controller generates a first calibration value based on the taps of the selected first delay line and the second delay line in response to the output flip of the D trigger.

[0046] According to the sixth or seventh flash memory controller of the third aspect of the present application, there is provided an eighth flash memory controller according to the third aspect of the present application, wherein the output of the first delay line serves as the output of the first calibration device.

[0047] According to one of the sixth to eighth flash memory controllers of the third aspect of the present application, a ninth flash memory controller according to the third aspect of the present application is provided, wherein the first calibration device also includes a third delay line, the input end of the third delay line is coupled to the first signal, the first calibration controller selects the tap of the third delay line; and the output of the third delay line serves as the output of the first calibration device.

[0048] According to one of the first to ninth flash memory controllers of the third aspect of the present application, a tenth flash memory controller according to the third aspect of the present application is provided, wherein the second calibration device includes a second calibration controller and a fourth delay line, and the second signal is coupled to the input end of the fourth delay line; the second calibration controller selects the tap of the fourth delay line, and the output end of the fourth delay line serves as the output of the second calibration controller.

[0049] According to one of the first to tenth flash memory controllers of the third aspect of the present application, an eleventh flash memory controller according to the third aspect of the present application is provided, wherein the first calibration device includes a third calibration controller and a fifth delay line; the third calibration controller selects the tap of the fifth delay line according to the received calibration value.

[0050] According to the first to eleventh flash memory controllers of the third aspect of the present application, there is provided a twelfth flash memory controller according to the third aspect of the present application, wherein the flash memory controller includes a temperature sensor.

[0051] According to the twelfth flash memory controller of the third aspect of the present application, there is provided a thirteenth flash memory controller according to the third aspect of the present application, wherein the mapping device maps the first calibration value to the second calibration value based on the value of the temperature sensor.

[0052] The beneficial effects achieved by this application are as follows:

[0053] (1) In the embodiment of the present application, calibration values ​​are obtained from one calibration device and applied to other calibration devices. Since these calibration devices are located in the same flash memory controller and have substantially the same process, temperature and / or operating voltage, the calibration values ​​obtained from one calibration device can compensate for the drift of other calibration devices. When setting new calibration values ​​for other calibration devices, there is no need to obtain calibration values, which reduces the time required for the calibration process and also reduces the occupancy of the flash memory channel.

[0054] (2) The embodiment of the present application utilizes a dedicated calibration device to obtain a primary calibration value, and applies the calibration value to the DQS and CLK signals on the flash memory channel through a pre-stored association relationship. When obtaining the primary calibration value, the DQS, CLK and other signals on the flash memory channel are not affected, and the time required to update the calibration device on the flash memory channel is shortened. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can also be obtained based on these drawings.

[0056] Figure 1 is a structural diagram of a flash memory according to an embodiment of the present application;

[0057] Figure 2 This is a schematic diagram of using a delay line to delay the DQS signal;

[0058] Figure 3 is a circuit block diagram of a calibration device according to an embodiment of the present application;

[0059] Figure 4 is a circuit block diagram of a flash memory controller according to an embodiment of the present application; and

[0060] Figure 5 4 is a flow chart of a signal calibration method for a flash memory chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0061] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0062] Example 1

[0063] Figure 1FIG is a structural diagram of a flash memory according to an embodiment of the present application. Figure 1 As shown, the flash memory controller 120 is coupled to one or more flash memory chips (135, 145, 155). The flash memory chips are, for example, NAND flash memory chips. The DQS / CLK and other pins of the flash memory controller 120 are connected to the corresponding DQS / CLK pins of the flash memory chips (135, 145, 155). The flash memory controller 120 may include multiple flash memory channels, each flash memory channel providing its own DQS / CLK signal and connected to the flash memory chips on its own flash memory channel.

[0064] The flash controller 120 generates signals such as DQS / CLK that comply with the ONFI / TOGGLE standard to operate the flash memory chips (135, 145, 155). The following describes the implementation of the present application using the DQS signal as an example.

[0065] See Figure 1 The flash memory chip 135 and the flash memory chip 145 belong to the same flash memory channel and share signals such as DQS and CLK.

[0066] The DQS and DS signals generated by the flash memory controller 120 have the same phase. The DQS signal generated by the flash memory controller 120 passes through the calibration device 152 and is then connected to the DQS pin of the flash memory chip (135, 145). The calibration device 152 performs delay calibration on the DQS signal and provides the delay-calibrated DQS signal to the flash memory chip (135, 145). Similarly, the calibration device 154 performs delay calibration on the CLK signal generated by the flash memory controller 120 and provides the delay-calibrated CLK signal to the CLK signal pin of the flash memory chip (135, 145).

[0067] Optionally, the calibration device 152 delays the DQS signal by 1T / 4, where T is the period of the DQS signal.

[0068] Optionally, flash controller 120 obtains a calibration value from calibration device 152 and applies the calibration value suitable for calibration device 152 to calibration device 154 , calibration device 156 , and calibration device 158 .

[0069] There are multiple ways to obtain a calibration value. For example, the flash memory controller 120 obtains a calibration value that delays the DQS signal coupled to the flash memory chip 135 by 1T / 4 through the calibration device 152. Furthermore, the flash memory controller 120 sets the calibration device 152 and / or the calibration device 154 based on the calibration value and reads data from the flash memory chip 135. Whether the calibration value is appropriate is determined based on whether the read data is correct. If the data read from the flash memory chip 135 is correct, the calibration controller 120 deems the calibration value appropriate and uses the calibration value to set other calibration devices (154, 156, 158) of the flash memory controller. If the data read from the flash memory chip 135 using the calibration value is erroneous or has a high error rate, the calibration value is adjusted. Optionally, multiple calibration values ​​within a certain range can all read correct data from the flash memory chip 135, and the flash memory controller selects the optimal calibration value from the multiple calibration values. For example, the middle value or average value of consecutive calibration values ​​is selected as the optimal calibration value.

[0070] In one embodiment, a reference page or reference data (e.g., flash memory chip ID) is provided at a specified address of the flash memory chip 135, and the content of the reference page or the reference data is known, so that the read data can be compared with the known data to identify whether the read data is correct.

[0071] In another embodiment, the flash memory controller 120 writes designated data into the flash memory chip 135 using different calibration values, and reads data from the flash memory chip 135 according to the different calibration values, and determines whether the calibration value used is appropriate based on whether the read data is the designated data.

[0072] In yet another embodiment, an ECC (Error Correction Code) decoder is used to perform error correction on the read data to determine whether the read data is correct.

[0073] Optionally, the calibration device also obtains the calibration value of the calibration device 152 regularly or irregularly.

[0074] Optionally, the calibration value of the calibration device 152 is obtained and set during idle time when there is no data transmission on the flash channel.

[0075] Figure 2 This diagram shows how to calibrate the DQS signal using a delay line. By adjusting the delay line taps, the delay line delays the input DQS signal by varying amounts of time and outputs the delayed signal (denoted as DQS').

[0076] Figure 31 is a circuit block diagram of a calibration device according to an embodiment of the present application. Calibration device 152 includes a calibration controller 320, a D-type flip-flop 340, and delay lines 310 and 312 connected in series. A DQS signal is coupled to the input of delay line 310, and the output of delay line 312 is coupled to the input of D-type flip-flop 340. The DQS signal is also directly coupled to the clock terminal of D-type flip-flop 340, and the output of D-type flip-flop 340 is coupled to calibration controller 320. Calibration controller 320 is coupled to the taps of delay line 310 and delay line 312 to select taps at the same position on delay lines 310 and 312. Calibration controller 320 obtains a calibration value based on the selected delay line taps.

[0077] Calibration controller 320 adjusts the taps of delay lines 310 and 312 and identifies the output of D flip-flop 340. In response to a toggle in the output of D flip-flop 340, calibration controller 320 records a calibration value corresponding to the position of the corresponding delay line tap. Calibration controller 320 connects to the tap of delay line 314 and applies the resulting calibration value to delay line 314. Delay line 314 delays the DQS signal by 1T / 4 based on this calibration value (resulting in a delayed signal DQS′) and provides it to flash memory chip 135.

[0078] Optionally, the calibration controller 320 further searches for a calibration value range that causes the output of the D flip-flop 340 to flip, and selects an optimal calibration value from the calibration value range.

[0079] Alternatively, the output of the delay line 310 is directly provided to the flash memory chip 135 as the output of the calibration device 152 , thereby eliminating the need to use the delay line 314 .

[0080] Still optionally, the calibration controller 320 is set with a calibration value through an external input, and adjusts the taps of the delay lines 310 , 312 , and / or 314 using the set calibration value.

[0081] Optionally, the calibration device (154, 156, 158) has a calibration controller and a delay line, the input signal of the calibration device (154, 156, 158) is coupled to the input end of the delay line, the calibration controller selects the tap of the delay line, and the output end of the delay line serves as the output of the calibration controller (154, 156, 158).

[0082] According to an embodiment of the present application, calibration values ​​are obtained from calibration device 152 and applied to other calibration devices. Because these calibration devices are located in the same flash memory controller and have substantially the same process, temperature, and / or operating voltage, the calibration values ​​obtained from one calibration device can compensate for the drift of other calibration devices. When setting new calibration values ​​for other calibration devices, there is no need to obtain calibration values, which reduces the time required for the calibration process and reduces the occupancy of flash memory channels.

[0083] Example 2

[0084] Figure 4 FIG is a circuit block diagram of a flash memory controller according to an embodiment of the present application. Figure 4 As shown, in the second embodiment, the flash memory controller includes a calibration device 450, a mapping device 452, a calibration device 456, and a calibration device 458. The calibration device 450 is coupled to the mapping device 452 to provide the calibration value x to the mapping device 452. The calibration devices 456 and 458 are coupled to the mapping device 452 to obtain calibration values ​​y1 and y2 from the mapping device 452. The calibration device 450 calibrates the signal coupled to the flash memory chip and outputs the obtained calibration value x to the mapping device 452. The mapping device 452 maps the calibration value x of the calibration device 450 to the calibration values ​​of the calibration devices 456 and 458.

[0085] like Figure 4 As shown, the calibration device 450 includes a calibration controller 420 , a delay line 410 , a delay line 412 , and a D flip-flop 440 .

[0086] Delay lines 410 and 412 are connected in series. Input signal A is connected to the input of delay line 410. The output of delay line 412 is coupled to the input of D flip-flop 440. Input signal A is also directly coupled to the clock terminal of D flip-flop 440. The output of the D flip-flop is coupled to calibration controller 420. Calibration controller 420 is connected to the taps of delay line 410 and delay line 412 to select the same tap position on delay lines 410 and 412. Calibration controller 420 obtains a calibration value based on the selected delay line tap.

[0087] Calibration controller 420 adjusts the taps of delay lines 410 and 412 and identifies the output of D flip-flop 440. In response to a toggle in the output of D flip-flop 440, calibration controller 420 records a calibration value x corresponding to the position of the corresponding delay line tap and outputs the obtained calibration value x to mapping device 452.

[0088] It should be noted that signal A is a signal inside the calibration device 450, rather than a signal provided to the flash memory chip. By calibrating the signal inside the calibration device 450, the calibration process does not need to interrupt data transmission on the flash memory channel.

[0089] Mapping device 452 records the association between calibration value x obtained from calibration device 450 and the calibration values ​​provided to calibration devices 456 and 458. Mapping device 452 obtains calibration values ​​y1 and y2 provided to calibration devices 456 and 458 based on calibration value x output by calibration device 450 and the association. Calibration value y1 is used to set the tap of delay line 416 of calibration device 456, and calibration value y2 is used to set the tap of delay line 418 of calibration device 458, so that delay line 416 calibrates the DQS signal coupled to the flash memory chip, while delay line 418 calibrates the CLK signal coupled to the flash memory chip.

[0090] Optionally, mapping device 452 includes a lookup table that records the association between calibration value x of calibration device 450 and calibration values ​​of calibration devices 456 and 458. Mapping device 452 obtains the calibration values ​​of calibration devices 456 and 458 by querying the lookup table using calibration value x of calibration device 450 as an index.

[0091] Optionally, the association relationship in mapping device 452 is a linear equation y=ax+b. Before the solid-state storage device is operated (for example, in a laboratory, during the production process of the solid-state storage device, or during the initialization phase of the solid-state storage device), the flash memory controller obtains a calibration value x from calibration device 450, and obtains calibration values ​​y1 and y2 for delaying the DQS signal and CLK signal of the coupled flash memory chip by 1 / 4T via calibration devices 456 and 458. The flash memory controller then fits coefficients a and b to obtain calibration value y from calibration value x, and records the coefficients in mapping device 452.

[0092] As an embodiment, when obtaining the calibration values ​​of the calibration device 456 and the calibration device 458, the flash memory controller generates specified data, writes the specified data into the flash memory chip using different calibration values, and reads it out. The calibration value of the calibration device 456 is determined by judging whether the read data is correct, or the optimal calibration value is selected from multiple calibration values.

[0093] Optionally, the association relationship in the mapping device 452 is updated periodically or aperiodically.

[0094] When the solid-state storage device is running, the calibration value x is obtained from the calibration device 450 periodically or when the calibration device needs to be set; the calibration value y1 of the calibration device 456 and the calibration value y2 of the calibration device 458 are obtained using the recorded coefficients a and b, and the calibration values ​​y1 and y2 are used to set the delay line 416 of the calibration device 456 and the delay line 418 of the calibration device 458.

[0095] Optionally, for calibration device 456 and calibration device 458, the slope of the linear equation y = ax + b is 1 (i.e., a = 1). Based on this, optionally, a = 1 and b = 0, i.e., x = y, that is, calibration device 456 and calibration device 458 are set with the calibration value x.

[0096] Optionally, the slope of the linear equation is not equal to 1.

[0097] Optionally, the slope a and the constant term b are different for each calibration device (456 and 458).

[0098] Still optionally, each calibration device has the same slope a, and a different constant term b.

[0099] Furthermore, the flash memory controller includes a temperature sensor and / or a voltage sensor. The mapping device 452 maps the calibration value x to calibration values ​​y1 and y2 based on the value of the temperature sensor and / or the voltage sensor, that is, the slope and / or constant term of the linear equation y=ax+b depends on the temperature and / or voltage. Before the solid-state storage device is operated, coefficients a and b at different temperatures and / or voltages are generated. When the solid-state storage is running, the current temperature and / or current voltage of the flash memory controller are obtained, and the corresponding coefficients a and b are determined according to the current temperature and / or current voltage. According to the calibration value x obtained from the calibration device 450, the calibration values ​​y1 and y2 are obtained according to the obtained coefficients a and b, and the calibration devices 456 and 458 are set.

[0100] In the second embodiment, a special calibration device (450) is used to obtain a primary calibration value (x), and the calibration value is applied to calibrate the DQS and CLK signals on one or more flash memory channels through a pre-stored association relationship. When the primary calibration value is obtained, the DQS, CLK and other signals on the flash memory channel are not affected, and the time required to update the calibration device on the flash memory channel is shortened.

[0101] Figure 5 Flowchart of a signal calibration method for a flash memory chip according to an embodiment of the present application. To calibrate a signal coupled to a flash memory chip, a calibration device (e.g., Figure 1 The calibration device 152, Figure 4 The calibration value is obtained (510) on the calibration device 450 of the embodiment, and the calibration value obtained is updated to be applied to one or more other calibration devices (e.g., Figure 1 calibration device 154, calibration device 156, calibration device 158, Figure 4The calibration value (520) obtained by the calibration device 456 and the calibration device 458 is obtained, and the updated calibration value is provided to one or more other calibration devices so that the other calibration devices calibrate the signal coupled to the flash memory chip using the updated calibration value (530). The updated calibration value can be updated by looking up the obtained calibration value in a table to obtain a new calibration value, or performing a linear transformation on the obtained calibration value to obtain a new calibration value, or adding an offset value to the obtained calibration value to obtain a new calibration value, or mapping the obtained calibration value to the new calibration value based on a mapping relationship obtained according to the current temperature and / or voltage.

[0102] Although preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this application. Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if such changes and modifications fall within the scope of the claims of this application and their equivalents, then this application is intended to include such changes and modifications.

Claims

1. A signal calibration method for a flash memory chip, characterized in that: include: Obtaining a first calibration value by delaying a first signal of a flash memory chip coupled to a first flash memory channel by a specified period through a first calibration device; The first calibration device calibrates the first signal according to the first calibration value; obtaining a second calibration value based on the first calibration value; The second calibration device calibrates the second signal of the flash memory chip coupled to the second flash memory channel according to the second calibration value.

2. The signal calibration method for a flash memory chip according to claim 1, wherein: in, The flash memory controller sets a first calibration device according to a first calibration value and reads data from a flash memory chip coupled to the first flash memory channel; If the read data is correct, a second calibration value is obtained according to the first calibration value.

3. The signal calibration method for a flash memory chip according to claim 2, wherein: in, If the read data is wrong, update the first calibration value; A second calibration value is obtained according to the updated first calibration value.

4. The signal calibration method for a flash memory chip according to any one of claims 1 to 3, characterized in that: in, The second calibration device calibrates the DQS signal of the flash memory chip coupled to the second flash memory channel according to the second calibration value; or The second calibration device calibrates the CLK signal of the flash memory chip coupled to the second flash memory channel according to the second calibration value.

5. The signal calibration method for a flash memory chip according to any one of claims 1 to 4, characterized in that: in, A primary calibration value is obtained through a special calibration device, and a first calibration value or a second calibration value is obtained according to the primary calibration value.

6. The signal calibration method for a flash memory chip according to any one of claims 1 to 5, characterized in that: in, The first calibration value is mapped to a second calibration value through a linear equation.

7. The signal calibration method for a flash memory chip according to claim 6, characterized in that: in, Each second calibration device has its own linear equation parameters, and the linear equation parameters of each second calibration device have different slopes and / or constant terms.

8. The signal calibration method for a flash memory chip according to claim 6 or 7, characterized in that: in, The current temperature of the flash memory controller is obtained, and parameters of a linear equation for the second calibration device are determined according to the current temperature.

9. A flash memory controller comprising a first calibration device, a mapping device, and at least one second calibration device; The first calibration device calibrates a first signal of a flash memory chip coupled to a first flash memory channel; The first calibration device outputs a first calibration value for calibrating the first signal; The mapping device maps the first calibration value to a second calibration value; as well as The second calibration device calibrates the second signal of the flash memory chip coupled to the second flash memory channel using the second calibration value.

10. The flash memory controller according to claim 9, wherein: in, The first calibration device includes a calibration controller and a delay line; the calibration controller selects a tap of the delay line according to a received calibration value.

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