Flash memory controller and access method of flash memory
By converting the basic matrix into a compressed matrix and adopting a grouping strategy, the iterative calculation amount of the LDPC decoder is reduced and the decoding efficiency of the flash memory is improved.
Patent Information
- Application Number
- CN202411351054.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-22
- Filing Date
- 2024-09-26
- Publication Date
- 2025-10-24
AI Technical Summary
In the prior art, an LDPC decoder needs to perform calculations on each column of a matrix block column by column during each iterative operation, resulting in low efficiency.
By converting the basic matrix into a compressed matrix, the number of column blocks that need to be processed in each iteration is reduced, and a grouping strategy is adopted to enable the VN unit to perform calculations column by column.
The decoding cycle of the VN unit in each iteration is significantly reduced, and the decoding throughput is improved.
Smart Images
Figure CN120832082A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a storage device, and in particular to a flash memory controller and a method for accessing a flash memory. BACKGROUND
[0002] NAND flash memory is one of the mainstream storage devices. For ensuring the data reliability of NAND flash memory, the execution of error correction is crucial. Low-Density Parity-Check (LDPC) is a high-performance and high-speed channel coding and decoding technology, which has been widely applied in the Error-correcting code (ECC) technology of NAND flash memory. Through the LDPC decoder, the data read from the flash memory can be decoded and corrected.
[0003] However, in the prior art, at each iteration operation, the variable node (VN) unit of the LDPC decoder needs to perform the calculation of each column matrix block according to the base matrix column by column, which is quite time-consuming and reduces the efficiency. In view of this, the present application provides a flash memory controller and a method for accessing a flash memory to solve the above technical problems. SUMMARY
[0004] To solve the above problems of the prior art, the purpose of the present application is to provide a flash memory controller and a method for accessing a flash memory, which can reduce the decoding period of the VN unit at each iteration, thereby significantly increasing the decoding throughput.
[0005] In a first aspect, a flash memory controller is provided for accessing a flash memory. The flash memory controller includes a read-only memory, a microprocessor, and a decoder. The read-only memory is configured to store a program code. The microprocessor is configured to execute the program code to control access to the flash memory. The decoder is configured to perform a decoding operation of a base matrix of a low-density parity-check code to decode read information obtained from the flash memory, the base matrix having a size of N x M. The decoder includes a controller, a variable node (VN) unit, and a check node (CN) unit. The controller is configured to convert the base matrix into a compressed matrix of N x S, where S is less than M, and each column of the compressed matrix has its matrix blocks grouped according to a same column of the base matrix. The VN unit is coupled to the controller and includes a plurality of first inputs. The CN unit is coupled to the VN unit, where the VN unit and the CN unit are configured to perform message updates between variable nodes and check nodes to generate a decoding result converging to a codeword. In each iteration operation, the VN unit performs a calculation of each column of matrix blocks according to the compressed matrix column by column, and the values of the matrix blocks of each column of the compressed matrix are sequentially input to the plurality of first inputs of the VN unit according to the grouping.
[0006] In some embodiments, the VN unit further includes a column sum calculation circuit and a group selection circuit. The column sum calculation circuit includes a plurality of adders. The group selection circuit is connected to the column sum calculation circuit, where the group selection circuit selects paths of the plurality of adders to be turned on according to the grouping of the matrix blocks of a same column of the compressed matrix, and the column sum calculation circuit adds values of the matrix blocks of a same group based on the path selection result of the group selection circuit.
[0007] In some embodiments, the plurality of first inputs are divided into a plurality of sub-sets, each of the sub-sets is connected to an adder of the column sum calculation circuit, the adder adds values input through the sub-set, and values from a same group of matrix blocks are input to one or more of the sub-sets, and each of the sub-sets only inputs values from a same group of matrix blocks.
[0008] In some embodiments, the controller of the decoder includes a grouping unit configured to merge matrix blocks of at least two columns of the base matrix according to a grouping strategy, where the grouping strategy is that a number of corresponding variable nodes of each row in the matrix blocks of the at least two columns is at most one.
[0009] In some embodiments, the grouping strategy further comprises that in the matrix blocks of the at least two columns, the number of the matrix blocks of non-blank elements is at most N, and the VN unit sequentially performs the calculation of each column of matrix blocks according to the compressed matrix, and the calculation result of each column of matrix blocks is the V2C message generated in the current iteration.
[0010] In some embodiments, the VN unit comprises N first input terminals, and the number of the matrix blocks of each column in the compressed matrix is sequentially input to the N first input terminals of the VN unit according to the grouping.
[0011] In some embodiments, the grouping strategy further comprises that in the matrix blocks of the at least two columns, the number of the matrix blocks of non-blank elements is at most P, and P is less than N. The compressed matrix is divided into a plurality of sub-matrices, and when the number of non-blank elements contained in the matrix blocks of one column in the base matrix is greater than P, the matrix blocks of the column are arranged in different sub-matrices. In each iteration operation, the VN unit sequentially performs the calculation of each column of matrix blocks according to the plurality of sub-matrices.
[0012] In some embodiments, the VN unit comprises a register for storing the calculation results of the VN unit according to each of the sub-matrices, and the VN unit adds the calculation results of the corresponding same column in all the previous sub-matrices when performing the calculation of each column of matrix blocks according to the last sub-matrix, and the final result is the sum of the values of each group of matrix blocks in the same column of the compressed matrix in the current iteration.
[0013] In some embodiments, the VN unit comprises P first input terminals, and the number of the matrix blocks of each column in the compressed matrix is sequentially input to the P first input terminals of the VN unit according to the grouping.
[0014] In some embodiments, the decoder further comprises a C2V unit coupled between the VN unit and the CN unit, for associating the C2V message generated by the CN unit with the compressed matrix and transmitting to the VN unit.
[0015] In a second aspect, the present application provides a method for accessing a flash memory, applied to a memory controller, the method comprising: obtaining read information from a flash memory; performing a decoding operation of a base matrix of a low-density parity-check code by a decoder to decode the read information, the base matrix having a size of N x M; converting the base matrix into a compressed matrix of N x S, where S is less than M; grouping matrix blocks of each column of the compressed matrix according to matrix blocks of a same column of the base matrix; performing message update between variable nodes (VN) and check nodes (CN) by a VN unit and a CN unit of the decoder to generate a decoding result converging to a codeword, wherein in each iteration operation, the VN unit performs calculation of each column of matrix blocks column by column according to the compressed matrix, and values of matrix blocks of each column of the compressed matrix are sequentially input to a plurality of first input terminals of the VN unit in accordance with the grouping.
[0016] In some embodiments, the VN unit further comprises a column sum calculation circuit and a group selection circuit, and the method further comprises: the group selection circuit correspondingly selecting to turn on paths of adders of the column sum calculation circuit according to the grouping of matrix blocks of a same column of the compressed matrix, and the column sum calculation circuit adding values of matrix blocks of a same group based on a path selection result of the group selection circuit.
[0017] In some embodiments, the plurality of first input terminals are divided into a plurality of sub-sets, each of the sub-sets is connected to an adder of the column sum calculation circuit, the adder adds values input through the sub-set, and values from a same group of matrix blocks are input to one or more of the sub-sets, and each of the sub-sets only inputs values from a same group of matrix blocks.
[0018] In some embodiments, in the conversion of the base matrix into the compressed matrix of N x S, the method further comprises: merging matrix blocks of at least two columns of the base matrix according to a grouping strategy, wherein the grouping strategy is that in the matrix blocks of the at least two columns, a number of corresponding variable nodes of each row is at most one.
[0019] In some embodiments, the grouping strategy further comprises that in the matrix blocks of the at least two columns, a number of non-blank element matrix blocks is at most N, and the calculation result of each column of matrix blocks performed by the VN unit according to the compressed matrix is a V2C message generated in the iteration.
[0020] In some embodiments, the VN unit comprises N first input terminals, and values of matrix blocks of each column of the compressed matrix are sequentially input to the N first input terminals of the VN unit in accordance with the grouping.
[0021] In some embodiments, the grouping strategy further comprises that in the matrix block of the at least two columns, the number of matrix blocks of non-blank elements is at most P, and P is less than N. The compressed matrix is divided into a plurality of sub-matrixes, and when the number of non-blank elements contained in the matrix block of one column in the base matrix is greater than P, the matrix block of the column is arranged in different sub-matrixes. In each iteration operation, the VN unit sequentially performs column-by-column calculation of each column matrix block according to the plurality of sub-matrixes.
[0022] In some embodiments, the VN unit comprises a register for storing the calculation results of the VN unit according to each of the sub-matrixes, and the VN unit adds the calculation results of the corresponding same column in all previous sub-matrixes when performing column-by-column calculation of each column matrix block according to the last sub-matrix, and the final result is the sum of the values of the same column matrix block of the compressed matrix in the iteration.
[0023] In some embodiments, the VN unit comprises P first input terminals, and the values of the matrix blocks of each column in the compressed matrix are sequentially input to the P first input terminals of the VN unit according to the grouping.
[0024] In some embodiments, the decoder further comprises a C2V unit coupled between the VN unit and the CN unit, for associating the C2V message generated by the CN unit with the compressed matrix and transmitting to the VN unit.
[0025] Compared with the prior art, the application provides a flash memory controller and a flash memory access method, which reorganizes the base matrix into a compressed matrix with fewer columns, so that the number of column blocks that need to be processed by the VN unit in each iteration is reduced. Therefore, the decoding period of the VN unit in each iteration is reduced, thereby significantly increasing the decoding throughput. BRIEF DESCRIPTION OF DRAWINGS
[0026] Figure 1 A block diagram of a storage device according to an embodiment of the application is shown;
[0027] Figure 2 A block diagram of a decoder of Figure 1 is shown;
[0028] Figure 3 A base matrix using the IEEE 802.3ca standard protocol is shown;
[0029] Figure 4 A schematic diagram of a matrix grouping operation according to a first embodiment is shown;
[0030] Figure 5shows a schematic diagram of a C2V cell and a V2C cell according to the first embodiment;
[0031] Figure 6 shows a circuit schematic diagram of a VN cell according to the first embodiment;
[0032] Figure 7 shows a schematic diagram of a C2V cell and a V2C cell according to the second embodiment;
[0033] Figure 8 shows a circuit schematic diagram of a VN cell according to the second embodiment;
[0034] Figure 9 shows a flowchart of an access method of a flash memory according to an embodiment of the present application. DETAILED DESCRIPTION
[0035] Example embodiments of the present application will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art. Like reference numerals refer to like elements throughout the drawings, and thus continuous description thereof will be omitted.
[0036] In an information transmission system, an original information is processed by an encoder at a transmitting end. The encoder appends a certain number of parity check codes to the original information to obtain a codeword. After transmission through a channel, a receiving end receives a received information. A decoder at the receiving end determines whether there is an error in the received information caused by channel noise based on the encoding process at the transmitting end. If an error is found, the decoder performs a corresponding algorithm to correct the error. Through this error correction process, the decoder is able to restore the original codeword and then extract the original information therefrom. Hereinafter, a storage device is taken as an example of an application scenario of the information transmission system.
[0037] Reference is made to Figure 1 which shows a block diagram of a storage device 10 according to an embodiment of the present application. The storage device 10 includes a flash memory controller 100 and a flash memory 200. The flash memory controller 100 is used to control the operation of the storage device 10 and access the flash memory 200, and the flash memory 200 is used to store data. The storage device 10 can include, but is not limited to, a solid state drive and various types of embedded storage devices, such as an embedded storage device conforming to the Peripheral Component Interconnect Express (PCIe) standard, etc.
[0038] As Figure 1As shown, the flash memory controller 100 can include a control logic circuit 110, an interface circuit 120, a microprocessor 130, a buffer 140, and a read-only memory 150. The flash memory controller 100 is coupled to the flash memory 200 through the control logic circuit 110 to transmit data and commands. The flash memory controller 100 can be connected to a host device through the interface circuit 120. The microprocessor 130 is electrically coupled to the control logic circuit 110, the interface circuit 120, the buffer 140, and the read-only memory 150. Examples of the buffer 140 include a dynamic random access memory (DRAM), a static random access memory (SRAM), or other volatile memory, without limitation. The read-only memory 150 is used to store a program code 151.
[0039] Optionally, the host device can include a processor and a power supply circuit coupled to each other. The processor can be used to control the operation of the host device, and the power supply circuit can be used to provide power to the processor and the memory device 10, and output one or more drive voltages to the memory device 10. The memory device 10 can be used to provide storage space for the host device, and obtain one or more drive voltages from the host device as a power source of the memory device 10. The host device mentioned herein can include, but is not limited to, a mobile device, a wearable device, a tablet computer, and a personal computer such as a desktop computer and a laptop computer.
[0040] Optionally, the interface circuit 120 of the flash memory controller 100 can comply with a specific communication standard, including but not limited to, a Serial Advanced Technology Attachment (Serial ATA or SATA) standard, a Peripheral Component Interconnect (PCI) standard, a PCIe standard, a Universal Flash Storage (UFS) standard, and the like, and can communicate according to the specific communication standard, for example, to perform communication between the host device and the flash memory controller 100, wherein the host device can include a corresponding transmission interface circuit complying with the specific communication standard to perform communication between the host device and the memory device 10.
[0041] In some embodiments, the flash memory controller 100, which executes the program code 151 through the microprocessor 130, can utilize its internal components to perform various control operations, such as controlling access to the flash memory 200 using the control logic circuit 110, communicating with the host device using the interface circuit 120, and performing required buffering using the buffer 140. For example, the host device can transmit a host command and a corresponding logical address to the flash memory controller 100. The microprocessor 130 of the flash memory controller 100 receives the host command and the logical address through the interface circuit 120, converts the host command into a storage operation command, and further uses the control logic circuit 110 to control the flash memory 200 with the operation command to perform operations such as reading and / or writing to storage cells (e.g., data pages) at certain physical addresses in the flash memory 200, where the physical addresses correspond to the logical addresses.
[0042] like Figure 1 As shown, the control logic circuit 110 may include an encoder 111 and a decoder 112. The encoder 111 is used to encode data written into the flash memory 200, while the decoder 112 is used to decode data received from the flash memory 200.
[0043] In some embodiments, the flash memory controller 100 can access the flash memory 200 according to the logical address of the write command of the host device, wherein the logical address information can be a logical block address or other logical address. Specifically, when the host device issues a write command, the data to be written can be temporarily stored in the buffer 140. The microprocessor 130 can convert / decode the write command (including the logical address) of the host device into a corresponding internal control signal (including the physical address of the flash memory 200), and provide the internal control signal to the control logic circuit 110 and / or the buffer 140. The encoder 111 of the control logic circuit 110 can encode the data temporarily stored in the buffer 140 into a codeword. According to the internal control signal, the control logic circuit 110 can address / control the flash memory 200 to write the codeword into the flash memory 200.
[0044] In some embodiments, when the host device issues a read command, the microprocessor 130 can convert / decode the read command of the host device (including the logical address) into corresponding internal control signals (including the physical address of the flash memory 200). According to the internal control signals, the control logic circuit 110 can address / control the flash memory 200 to read out the original codeword within the flash memory 200. The decoder 112 of the control logic circuit 110 can perform a decoding operation of a base matrix of the LDPC code to decode the read information obtained from the flash memory, thereby decoding the original codeword into data, and temporarily storing the decoded data in the buffer 140. Subsequently, the microprocessor 130 can return the data temporarily stored in the buffer 140 to the host device.
[0045] It should be understood that the above-mentioned flash memory 200 can be a NAND flash memory. As one of the mainstream storage media at present, the NAND flash memory has the advantages of high performance, high density, non-volatility, and low power consumption. For ensuring the data reliability of the NAND flash memory, the execution of error correction is crucial, and therefore a special controller (such as the flash memory controller 100 mentioned above) needs to be designed for data management. The LDPC is a high-efficiency and high-speed channel encoding and decoding technology, and has been widely applied in the ECC technology of the NAND flash memory. Specifically, as mentioned above, the flash memory controller 100 writes data into the flash memory 200 through the LDPC encoder (such as the encoder 111), and the flash memory controller 100 can also transmit the data read out from the flash memory 200 to the LDPC decoder (such as the decoder 112) for decoding and error correction.
[0046] Please refer to Figure 2 , which shows a block diagram of the decoder of Figure 1 . The decoder 112 can perform iteration operation of the LDPC to decode the original codeword (channel value) to obtain the original and noise-free codeword (decoding result), and then extract the original information therefrom. Alternatively, the original codeword can be temporarily stored in the buffer 140, or in the channel storage, without being limited thereto. The decoder 112 includes a variable node (VN) unit 21, a check node (CN) unit 22, a C2V (CN to VN) unit 23, a V2C (VN to CN) unit 24, a controller 25, and a syndrome check circuit 26. The VN unit 21, the CN unit 22, the C2V unit 23, the V2C unit 24, and the controller 25 are coupled to each other, and the VN unit 21 is further coupled to the syndrome check circuit 26.
[0047] As Figure 2As shown, the VN units 21 and the CN units 22 are configured to perform message updates between the variable nodes and the check nodes to generate a decoding result converging to a codeword. Specifically, the VN units 21 are configured to calculate V2C messages from the variable nodes to the check nodes according to C2V messages. The CN units 22 are configured to calculate C2V messages from the check nodes to the variable nodes according to the V2C messages. The controller 25 is configured to convert an N x M base matrix into an N x S compressed matrix, and the conversion method will be described later. The C2V units 23 are configured to transmit the C2V messages, and associate the C2V messages with the compressed matrix according to a grouping operation and transmit to the VN units 21. The V2C units 24 are configured to transmit the V2C messages, and associate the V2C messages with the base matrix according to an ungrouping operation and transmit to the CN units 22. The syndrome check circuit 26 is configured to check whether the decoded codeword conforms to the equation: C.H T = S = 0, where H is the base matrix, C is the received codeword, and S is a syndrome value. When S is equal to zero, it indicates that the decoding procedure has been completed.
[0048] In the present embodiment, one iteration is composed of one time of "calculating V2C messages of all variable nodes" and one time of "calculating C2V messages of all check nodes". After each iteration is completed, the decoder 112 judges whether the LDPC iterative operation has converged to a codeword. After multiple iterations in the LDPC operation, the information of the variable nodes converges, indicating that the LDPC decoding is successful, and thus the decoder 112 can stop / completes the LDPC iterative operation.
[0049] It should be understood that in the new generation of communication standards, the LDPC code is adopted by many standards and applied in many different communication systems. In the following, the specific working mode of the decoder proposed in the present application will be described in combination with the drawings by taking the LDPC decoder and its decoding operation applied in the IEEE 802.3ca system as an example. However, it should be understood that the present application can also be applied in other communication systems, and is not limited thereto.
[0050] Please refer to Figure 3 which shows a base matrix in the IEEE 802.3ca standard protocol. In the 802.3ca system, the size of the base matrix is a 12 x 69 matrix. The base matrix defines the relationship between a plurality of variable nodes and a plurality of check nodes. The number of rows of the base matrix represents the number of check nodes, and the number of columns of the base matrix represents the number of variable nodes. In the LDPC operation, information is transmitted between the variable nodes and the check nodes.
[0051] It should be understood that if the VN unit 21 performs "calculating V2C messages of all variable nodes" means performing the calculation of each column matrix block column by column. That is, in the prior art, the VN unit 21 needs to perform 69 decoding cycles at each iteration operation, which results in time-consuming and low efficiency. In order to avoid the above-mentioned shortcomings, the present application adds a matrix grouping operation in the decoding process to reduce the decoding cycle of each iteration, thereby significantly increasing the decoding throughput. The specific description of the grouping operation is as follows.
[0052] First embodiment:
[0053] Please refer to Figure 4 , Figure 5 and Figure 6 , wherein Figure 4 shows a schematic diagram of the matrix grouping operation according to the first embodiment, Figure 5 shows a schematic diagram of the C2V unit and the V2C unit according to the first embodiment, and Figure 6 shows a circuit schematic diagram of the VN unit according to the first embodiment.
[0054] As shown in Figure 5 , the controller 25 of the decoder 112 includes a processor 251, a memory 252, a grouping unit 253 and a de-grouping unit 254. The memory 252 is used to store compressed matrices and computer programs. The computer programs are executed by the processor 251 to control the grouping unit 253 and the de-grouping unit 254 to perform matrix grouping and de-grouping related operations.
[0055] As shown in Figure 4 , the grouping unit 253 of the controller 25 combines / compresses the matrix blocks of at least two columns in the base matrix according to a grouping strategy. For example, Figure 4 shows the combination of the first column M1 and the second column M2 in the base matrix of Figure 3 . In this embodiment, the grouping strategy is that in the matrix blocks of the at least two columns of the base matrix for combination, the number of corresponding variable nodes of each row is at most one. Specifically, the matrix blocks of the base matrix include non-blank elements and blank elements, wherein the non-blank elements mean 0 or positive integers. Combination means combining the matrix blocks of all non-blank elements in multiple columns into one column. Furthermore, "the number of corresponding variable nodes of each row is at most one" means that in the matrix blocks of the multiple columns for combination, there is at most one matrix block of non-blank elements in each row. It should be understood that when the combined column contains a matrix block of blank elements, in the subsequent operation, the matrix block is automatically brought into a 0 value.
[0056] As shown in Figure 3As shown, based on the grouping strategy of this embodiment, the number of matrix blocks of non-blank elements in each column of the compressed matrix is at most 12. Therefore, the size of the basic matrix is compressed from 12×69 to a compressed matrix of 12×27 (1st column S1 to 27th column S27).
[0057] like Figure 4 As shown, the grouping unit 253 is further configured to group the matrix blocks in each column of the compressed matrix according to the matrix blocks in the same column of the basic matrix, so that the matrix blocks from the same column of the basic matrix are grouped into the same group. Figure 4 As shown, the grouping unit 253 merges the 1st column M1 and the 2nd column M2 in the basic matrix, and assigns the matrix block from the 1st column M1 of the basic matrix to a group number (such as group 0), and assigns the matrix block from the 2nd column M2 of the basic matrix to another group number (such as group 1), where the group numbers can be interchangeable and are not limited to this.
[0058] It should be understood that, while assigning group numbers to the matrix blocks, the grouping unit 253 also assigns an index value to each matrix block, such as h(1,1), h(1,2), etc. The index value corresponds to the matrix coordinate position of the matrix block in the base matrix. For example, h(1,1) indicates that the matrix block is from the first row and first column of the base matrix. In addition, the memory 252 is also used to store the group number and index value of the compressed matrix and each of its matrix blocks.
[0059] like Figure 5 As shown, the C2V unit 23 includes a group connection unit 231, which is used to connect the C2V messages CN0 to CN calculated by the CN unit 22. 11 Associated with the compression matrix, and through the corresponding barrel shifters BS0~BS 11 Sent to VN unit. C2V message CN0~CN 11 The number of is the same as the number of rows of the base matrix, and the barrel shifters BS0 to BS 11 The number of Figure 6 The number of the first input terminals 64 of the VN units 21 is associated with the grouping strategy of the compression matrix. Specifically, in this embodiment, Figure 6 As shown in FIG. 1 , the number of the first input terminals 64 of the VN unit is N (ie, 12). Figure 4 As shown, in the compressed matrix of this embodiment, the number of matrix blocks of non-blank elements in each column is at most N (ie, 12).
[0060] In this embodiment, when calculating each column of matrix blocks, the grouping unit 253 controls the group connection unit 231 to rearrange the matrix blocks of the corresponding column in the compressed matrix so as to arrange the matrix blocks of the same group in the same column together. Optionally, in this embodiment, the group connection unit 231 can be implemented by 12 multiplexers (mux). Specifically, the group number corresponding to the matrix blocks of a column is input into the multiplexer, so that the multiplexer can arrange the matrix blocks of the same group together according to the group number. For example, Figure 4 As shown, the group connection unit 231 rearranges the values of the first column of the compressed matrix {80, 0, 91, 105, 170, 46, 137, 118, 208, 0, 209, 53} into {80, 105, 137, 0, 209, 53, 0, 91, 170, 46, 118, 208} according to the group number, that is, the matrix blocks of group 0 and group 1 are arranged together. The group connection unit 231 passes the rearranged values through the barrel shifters BS0 to BS 11 The corresponding first input terminals 64 of the VN units are input in sequence.
[0061] like Figure 6 As shown, the VN unit 21 includes a column sum calculation circuit 61, a group selection circuit 62, a subtractor circuit 63, a first input terminal 64, a second input terminal 65, a delay input terminal 66, and an output terminal 67. The column sum calculation circuit 61 includes a plurality of adders.
[0062] like Figure 6 As shown, the first input terminals 64 are used to input multiple values from the same column of the compressed matrix, such as values R1-R3. It should be noted that these values are input into the first input terminals 64 according to the order of the groups, rather than according to the order of their corresponding row numbers in the compressed matrix. That is, the values of the matrix blocks in each column of the compressed matrix are input into the multiple first input terminals 64 of the VN unit 21 sequentially according to the groups. Furthermore, the first input terminals 64 are divided into multiple subsets. In this embodiment, three first input terminals 64 are used as a subset, but this is not limited to this. Values from the same group of matrix blocks are input into one or more subsets, and each subset only inputs values from the same group of matrix blocks. For example, when a column of matrix blocks in the compressed matrix contains four matrix blocks assigned to group 0 and six matrix blocks assigned to group 1, the values of the four matrix blocks in group 0 are input into the two subsets, respectively, and the two first input terminals 64 without input values are automatically set to 0. In addition, the values of the six matrix blocks of the first group are input into the other two subsets respectively.
[0063] like Figure 6As shown, the first input terminal 64 inputs the values of the same column in the compressed matrix at one time, and the column sum calculation circuit 61 is used to add the values of the same group in the same column. Specifically, the group selection circuit 62 selects the values of the same group among the values according to the grouping of the matrix blocks, and the column sum calculation circuit 61 is used to add the values of the same group selected by the group selection circuit 62. In this embodiment, the column sum calculation circuit 61 includes a first-order adder, a second-order adder, and a third-order adder. Each first-order adder is connected to a subset. The first-order adder is used to add the values input through its respective subset and output the summed value of each subset. The second-order adder is connected to two first-order adders. The third-order adder is connected to two second-order adders.
[0064] like Figure 6 As shown, the group selection circuit 62 is connected to the controller 25 and obtains relevant information such as the group number of each matrix block of the compressed matrix and its associated matrix blocks stored in the memory 252. The second-order adder and the third-order adder of the column sum calculation circuit 61 are connected to the group selection circuit 62. The group selection circuit 62 generates a selection result based on the group number of each matrix block currently input. Furthermore, the group selection circuit 62 selects the paths that connect the adders based on the grouping of matrix blocks in the same column of the compressed matrix. Specifically, based on the selection result, the controller 25 controls the transmission path of the multiplexer of the group selection circuit 62, thereby controlling the operation of the second-order adder and the third-order adder. For example, the summed values of two subsets are added together via the second-order adder, or the summed values of three or four subsets are added together via the second-order adder and the third-order adder, or the summed values of the subsets are directly output through a bypass. The column sum calculation circuit 61 adds the values of the matrix blocks in the same group based on the path selection result of the group selection circuit 62.
[0065] like Figure 6 As shown, the second input terminal 65 is used to input the reliability value of each variable node, such as CV0 to CV2. The reliability value is used to convey reliability information about each variable node to help the decoder better correct errors. The decoder uses the reliability value to update the estimate of the variable node and continuously optimizes these estimates in multiple iterations. The sum of the values of the matrix blocks in the same group output by the column sum calculation circuit 61 is added to the corresponding reliability value through an adder, and the result of the addition is the a posteriori probability (APP) value of the variable node.
[0066] like Figure 6 As shown, the delay input terminal 66 is used to input the value R of the corresponding matrix block in the calculation of a column. 1,dl ~R 3,dlAfter the sum of the values of the same group in the same column obtained by the column sum calculation circuit 61 and the group selection circuit 62 is added to the reliability value, the values of each matrix block in the same group are subtracted by the subtractor circuit 63 to obtain the V2C messages Q1~Q 12 Specifically, the calculation formula for V2C message Q is as follows:
[0067] Q I =CV+∑R I-1 -R I-1 , where I and I-1 represent the number of iterations, CV is the reliability value, ∑R I-1 is the sum of the values of the same group in the same column obtained by the column sum calculation circuit 61, and R I-1 are the values of each matrix block in the same group.
[0068] like Figure 6 As shown, output terminal 67 outputs the V2C message Q in the order of the groups. In this embodiment, the number of matrix blocks containing non-blank elements in each column of the compressed matrix is at most 12, and the number of first input terminals 64 of the VN unit is also 12. When performing calculations on each column, the values of the matrix blocks in a column of the compressed matrix are all input to the first input terminal 64 of the N unit at once. Therefore, the calculation result of each column performed by the VN unit 21 on the compressed matrix is the V2C message generated in that iteration.
[0069] like Figure 5 As shown, the V2C unit 24 includes a depacketizing connection unit 241, which is used to send the V2C messages VN0 to VN1 calculated by the VN unit 21 to the V2C message VN0 to VN2. 11 Through the corresponding barrel shifter BS0 ~ BS 11 The V2C messages output by the VN unit 21 are associated with the base matrix and transmitted to the CN unit. Specifically, the degrouping unit 254 of the controller 25 controls the degrouping connection unit 241 to rearrange the V2C messages output by the VN unit 21 according to the group. Optionally, in this embodiment, the degrouping connection unit 241 can be implemented by 12 multiplexers. Specifically, the group number corresponding to the matrix block of a column is input into the multiplexer, so that the multiplexer can return the V2C messages output by the VN unit 21 to their original row and column positions according to the group number. It should be understood that since the group number and index value of each matrix block are stored in the memory, the degrouping unit 254 can assign each matrix block to the original (pre-merger) column in units of groups and map it to the correct row, thereby restoring it to the corresponding coordinates in the base matrix. Based on the restored base matrix, the CN unit 22 calculates the C2V message transmitted from the check node to the variable node according to the V2C message.
[0070] For example, if Figure 4As shown, since the values of the matrix blocks of the first column of the compressed matrix are input into the plurality of first input terminals 64 of the VN unit 21 in the order of the groups, the values of the first column of the compressed matrix are input into the first input terminals 64 of the VN unit 21 in the order of {80, 105, 137, 0, 209, 53, 0, 91, 170, 46, 118, 208}. In terms of rows, the row numbers of the values input after the grouping arrangement are {R1, R4, R7, R 10 11 12 ,R2, R3, R5, R6, R8, R9}, in which the values 1 to 12 actually correspond to the row numbers of the compressed matrix. It can be understood that the V2C messages output by the VN unit 21 after performing the matrix block operation of the first column of the compressed matrix are in the order of {Q1, Q4, Q7, Q 10 11 12 ,Q2, Q3, Q5, Q6, Q8, Q9}, in which the values 1 to 12 actually correspond to the row numbers of the compressed matrix. In the present application, in order to make the output V2C messages available for subsequent calculations, the de-grouping unit 254 controls the de-grouping connection unit 241 to rearrange the V2C messages output by the VN unit 21 in the order of Q1 to Q 12 .
[0071] In the first embodiment of the present application, based on the grouping strategy, the number of the matrix blocks of the non-blank elements of each column of the compressed matrix is at most 12. The size of the base matrix is compressed from 12x69 to a compressed matrix with a size of 12x27 (as shown in Figure 3 the first column S1 to the 27th column S27), so that the number of column blocks to be processed in each iteration is reduced from 69 to 27. That is, the decoding period of each iteration is reduced from 69 to 27, thereby significantly increasing the decoding throughput. On the other hand, in the present application, the memory 252 only needs to store the compressed matrix with a size of 12x27 and another matrix composed of the group numbers and index values of each matrix block. It can be understood that the capacity for storing the above two matrices is much smaller than the capacity for storing the base matrix with a size of 12x69. Therefore, the present application can also effectively reduce the storage cost of the memory 252.
[0072] Second embodiment:
[0073] Please refer to Figure 7 and Figure 8 , in which Figure 7 shows the schematic diagram of the C2V unit and the V2C unit according to the second embodiment, and Figure 8 A circuit schematic of a VN unit according to the second embodiment is shown. It should be understood that the second embodiment employs the same architecture as the decoder described above. Both the first and second embodiments are substantially the same, with the difference being in the circuit configuration of the VN unit and the grouping strategy, which are described below.
[0074] As shown in FIG. 2, the controller 25 of the decoder 112 includes a processor 251, a memory 252, a grouping unit 253, and a de-grouping unit 254. The memory 252 is used to store the compressed matrix and computer programs. The computer programs, when executed by the processor 251, cause the processor 251 to control the grouping unit 253 and the de-grouping unit 254 to perform the matrix grouping and de-grouping related operations. Figure 7 As shown in FIG. 3, the grouping unit 253 of the controller 25 merges / compresses the matrix blocks of at least two columns in the base matrix according to the grouping strategy. In this embodiment, the grouping strategy is that the number of corresponding variable nodes in each row in the matrix blocks of the at least two columns to be merged in the base matrix is at most one. Specifically, the matrix blocks in the base matrix include non-blank elements and blank elements, where the non-blank elements mean 0 or positive integers. The merging means merging the matrix blocks of all non-blank elements in the multiple columns into one column. Furthermore, the "the number of corresponding variable nodes in each row is at most one" means that in the matrix blocks of the multiple columns to be merged, there is at most one matrix block of non-blank elements in each row. It should be understood that when the merged column contains a matrix block of blank elements, the matrix block is automatically brought into a 0 value in subsequent operations.
[0075] Figure 7 In the compressed matrix in this embodiment, the number of matrix blocks of non-blank elements in each column is at most P, where P is less than N. For example, as shown in FIG. 4, since the number of matrix blocks of non-blank elements in the first column Ml of the base matrix is 6, after conversion, the first column Ml of the base matrix is not merged with other columns and serves as the first column of the compressed matrix. For another example, since the number of matrix blocks of non-blank elements in the 18th column Ml 8 and the 19th column Ml 9 of the base matrix is 3 and 3 respectively, the 18th column Ml 8 and the 19th column Ml 9 of the base matrix can be merged to serve as a new column of the compressed matrix.
[0076] In the compressed matrix in this embodiment, the number of matrix blocks of non-blank elements in each column is at most P, where P is less than N. For example, as shown in FIG. 4, since the number of matrix blocks of non-blank elements in the first column Ml of the base matrix is 6, after conversion, the first column Ml of the base matrix is not merged with other columns and serves as the first column of the compressed matrix. For another example, since the number of matrix blocks of non-blank elements in the 18th column Ml 8 and the 19th column Ml 9 of the base matrix is 3 and 3 respectively, the 18th column Ml 8 and the 19th column Ml 9 of the base matrix can be merged to serve as a new column of the compressed matrix. Figure 3 It should be noted that in this embodiment, the compressed matrix is divided into multiple sub-matrices. Specifically, when the number of non-blank elements contained in the matrix blocks of one column in the base matrix is greater than P, the matrix blocks of the column are configured in different sub-matrices. For example, as shown in FIG. 5, since the number of non-blank elements contained in the matrix blocks of the 20th column M20 of the base matrix is greater than P, the matrix blocks of the 20th column M20 of the base matrix are configured in different sub-matrices.
[0077] Figure 3 As shown, since the number of matrix blocks of non-blank elements in the 26th column M26 of the basic matrix is 12, after the conversion, the compressed matrix is divided into two sub-matrices, and the 12 matrix blocks of the column are respectively configured in the two sub-matrices of the compressed matrix.
[0078] like Figure 7 As shown, the grouping unit 253 is further configured to group the matrix blocks in each column of the compressed matrix according to the basic matrix, so that the matrix blocks from the same column of the basic matrix are grouped into the same group. Figure 3 As shown, if the 18th column M18 and the 19th column M19 of the basic matrix are merged, the grouping unit 253 will assign the matrix block from the 18th column M18 of the basic matrix to a group number (such as group 0), and assign the matrix block from the 19th column M19 of the basic matrix to another group number (such as group 1), where the group numbers can be interchangeable and are not limited to this.
[0079] It should be understood that, while assigning a group number to the matrix block, the grouping unit 253 also assigns an index value to each matrix block. The index value corresponds to the matrix coordinate position of the matrix block in the base matrix. In addition, the memory 252 is also used to store the group number and index value of the compressed matrix and each matrix block thereof.
[0080] like Figure 7 As shown, the group connection unit 232 of the C2V unit 230 is used to connect the C2V messages CN0 to CN calculated by the CN unit. 11 Associated with the compression matrix, and transmitted to the VN unit through the corresponding barrel shifters BS0-BS5. C2V messages CN0-CN 11 The number of is the same as the number of rows of the base matrix. The number of barrel shifters BS0 to BS5 (equivalent to Figure 8 The number of the first input terminals 74 of the VN unit 210 is associated with the grouping strategy of the compressed matrix. Specifically, as described above, in the compressed matrix of this embodiment, the number of matrix blocks of non-blank elements in each column is at most P.
[0081] In this embodiment, when calculating each column of matrix blocks, the grouping unit 253 controls the group connection unit 232 to rearrange the matrix blocks in the corresponding column of the compressed matrix, so that the matrix blocks in the same group in the same column are arranged together. Optionally, in this embodiment, taking P equal to 6 as an example, the group connection unit 232 can be implemented by 6 multiplexers. Specifically, the group numbers corresponding to the matrix blocks in a column are input into the multiplexers, so that the multiplexers can arrange the matrix blocks in the same group together based on the group numbers. The group connection unit 231 sequentially inputs the rearranged values into the corresponding first input terminals 74 of the VN units through barrel shifters BS0-BS5.
[0082] likeFigure 8 As shown, the VN unit 210 includes a column sum calculation circuit 71 , a group selection circuit 72 , a subtractor circuit 73 , a first input terminal 74 , a second input terminal 75 , a delay input terminal 76 , an output terminal 77 and a register 78 .
[0083] like Figure 8 As shown, the first input terminals 74 are used to input multiple values from the same column of the compressed matrix. It should be noted that these values are input into the first input terminals 74 according to the order of the groups, rather than according to the order of their corresponding row numbers in the compressed matrix. In other words, the values of the matrix blocks in each column of the compressed matrix are input into the multiple first input terminals 74 of the VN unit 210 in sequence according to the groups. Furthermore, the first input terminals 74 are divided into multiple subsets. In this embodiment, three first input terminals 74 are used as a subset, but this is not limited to this. Each subset only inputs values from the same group of matrix blocks.
[0084] like Figure 8 As shown, the first input terminal 74 inputs the values of the same column in the compressed matrix at one time, and the column sum calculation circuit 71 is used to add the values of the same group in the same column. Specifically, the group selection circuit 72 selects the values of the same group among the values according to the grouping of the matrix blocks, and the column sum calculation circuit 71 is used to add the values of the same group selected by the group selection circuit 72. In this embodiment, the column sum calculation circuit 71 includes a first-order adder and a second-order adder. Each first-order adder is connected to a subset. The first-order adder is used to add the values input through each subset and output the summed value of each subset. The second-order adder is connected to two first-order adders.
[0085] like Figure 8 As shown, the group selection circuit 72 is connected to the controller 25 and obtains relevant information such as the group number of the compressed matrix and each matrix block stored in the memory 252. The second-order adder of the column sum calculation circuit 71 is connected to the group selection circuit 72. The group selection circuit 72 generates a selection result based on the group number of each matrix block currently input. In addition, the group selection circuit 72 selects the path for conducting the adders based on the grouping of matrix blocks in the same column of the compressed matrix. Specifically, based on the selection result, the controller 25 controls the transmission path of the multiplexer of the group selection circuit 72, thereby controlling the operation of the second-order adder. For example, the summed values of two subsets are added together by the second-order adder, or the summed value of the subsets is directly output through a bypass. The column sum calculation circuit 71 adds the values of the matrix blocks in the same group based on the path selection result of the group selection circuit 72.
[0086] It should be understood that in the present embodiment, the compressed matrix region is divided into a plurality of sub-matrices. In each iteration, the VN unit 210 sequentially performs the calculation of each column of matrix blocks according to the sub-matrices. The VN unit 210 stores the calculation results according to each sub-matrix in the register 78. As shown in Figure 8 the register 78 is connected to the column sum calculation circuit 71. The sum calculation circuit 71 comprises a third-order adder. When the VN unit 210 performs the calculation of each column of matrix blocks according to the last sub-matrix, the VN unit 210 adds the calculation results of the same column of matrix blocks of all the previous sub-matrices (if any) through the third-order adder of the sum calculation circuit 71, and the final result is the sum of the same column of matrix blocks of the compressed matrix in the present iteration.
[0087] For example, taking P equal to 6 as an example, in the present example, the compressed matrix region is divided into two sub-matrices. The VN unit 210 first performs the calculation of each column of matrix blocks according to the first sub-matrix. And the VN unit 210 first stores the calculation results according to the first sub-matrix in the register 78. Then, when the VN unit 210 performs the calculation of each column of matrix blocks according to the second sub-matrix, the VN unit 210 adds the calculation results of the same column of matrix blocks of the first sub-matrix, and the summed value is equal to the sum of the same column of matrix blocks of the compressed matrix.
[0088] As shown in Figure 8 the second input terminal 75 is used to input the reliability values of each variable node, such as CV0~CV1. The reliability values are used to convey the reliability information of each variable node to help the decoder better correct errors. The decoder uses the reliability values to update the estimates of the variable nodes and continuously optimizes these estimates in multiple iterations. The sum of the values of the same group of matrix blocks output by the column sum calculation circuit 71 is added to the corresponding reliability value through an adder, and the added result is the a posteriori probability value of the variable node.
[0089] As shown in Figure 8 the delay input terminal 76 is used to input the values of the corresponding matrix blocks in the calculation of a column. After the sum of the values of the same group in the same column obtained by the column sum calculation circuit 71 and the group selection circuit 72 is added to the reliability value, the values of each matrix block in the same group are then subtracted through the subtracter circuit 73 to obtain the V2C messages Q1~Q6. The calculation formula of the V2C messages Q is described above and will not be repeated here.
[0090] As shown in Figure 8As shown, output terminal 77 outputs the V2C message Q in the order of the groups. In this embodiment, since the number of matrix blocks containing non-blank elements in each column of the compressed matrix is at most six, and the number of first input terminals 74 of the VN unit is also six, the compressed matrix needs to be divided into multiple sub-matrices. Furthermore, as described above, the VN unit 210 sequentially performs calculations on each column of the matrix blocks based on the multiple sub-matrices, column by column, and the resulting result is the V2C message generated in that iteration.
[0091] like Figure 7 As shown, the V2C unit 240 includes a degrouping and connecting unit 242, which is used to associate the V2C messages VN0-VN5 calculated by the VN unit 210 with the base matrix via corresponding barrel shifters BS0-BS5 and transmit them to the CN unit. Specifically, the degrouping unit 254 of the controller 25 controls the degrouping and connecting unit 242 to rearrange the V2C messages output by the VN unit 210 according to the group. Optionally, taking P equal to 6 as an example, the degrouping and connecting unit 242 can be implemented by 6 multiplexers. Specifically, the group number corresponding to the matrix block of a column is input into the multiplexer, so that the multiplexer can reorder the V2C messages output by the VN unit 210 back to their original row and column positions based on the group number. The specific degrouping method is described above and will not be repeated here. It should be understood that since the group number and index value of each matrix block are stored in memory, the degrouping unit can assign each matrix block to the original (pre-merging) columns on a group basis and map it to the correct rows, thereby restoring the corresponding coordinates in the base matrix. Based on the restored base matrix, the CN unit 22 calculates the C2V message transmitted from the check node to the variable node according to the V2C message.
[0092] In the second embodiment of the present invention, based on a grouping strategy, the base matrix is reorganized / compressed into a compressed matrix with fewer columns, thereby reducing the number of column blocks that need to be processed in each iteration. This reduces the decoding cycles per iteration, significantly increasing decoding throughput. Furthermore, while the compressed matrix in the second embodiment has a larger number of columns and requires more decoding cycles than the first embodiment, it reduces the hardware resources used by the VN unit 210, thereby reducing manufacturing costs.
[0093] This application also provides a flash memory access method, applied to a storage controller. The flash memory controller is coupled to the flash memory to transmit data and commands. The specific structure and function of the flash memory controller and the flash memory are described above and are not further elaborated here. Specifically, the microprocessor of the flash memory controller is generally configured to control the overall operation of the storage device. The microprocessor executes program code to perform all or part of the decoding steps described in the first and second embodiments.
[0094] Please refer to Figure 9FIG. 9 is a flowchart showing an access method of a flash memory according to an embodiment of the present application. The access method of the flash memory includes at least steps S91-S95. In step S91, read information is obtained from a flash memory. In step S92, decoding operation of a base matrix of a low-density parity-check code is performed by a decoder to decode the read information, the base matrix having a size of N x M. In step S93, the base matrix is converted into a compressed matrix of N x S, where S is less than M. In step S94, matrix blocks of each column of the compressed matrix are grouped according to matrix blocks of the same column in the base matrix. In step S95, message update between variable nodes and check nodes is performed by a variable node (VN) unit and a check node (CN) unit of the decoder to generate a decoding result converging to a codeword, where in each iteration operation, the VN unit performs calculation of each column of matrix blocks column by column according to the compressed matrix, and the values of matrix blocks of each column of the compressed matrix are sequentially input to a plurality of first input terminals of the VN unit according to the grouping.
[0095] In some embodiments, the VN unit further includes a column sum calculation circuit and a group selection circuit, and the method further includes that the group selection circuit correspondingly selects to turn on paths of adders of the column sum calculation circuit according to the grouping of matrix blocks of the same column in the compressed matrix, and the column sum calculation circuit adds values of matrix blocks of the same group based on the path selection result of the group selection circuit.
[0096] In some embodiments, the plurality of first input terminals are divided into a plurality of sub-sets, each of the sub-sets is connected to an adder of the column sum calculation circuit, the adder adds values input through the sub-set, and values from the same group of matrix blocks are input to one or more of the sub-sets, and each of the sub-sets only inputs values from the same group of matrix blocks.
[0097] In some embodiments, in the conversion of the base matrix into the compressed matrix of N x S, the method further includes that matrix blocks of at least two columns in the base matrix are merged according to a grouping strategy, where the grouping strategy is that the number of corresponding variable nodes of each row in the matrix blocks of the at least two columns is at most one.
[0098] In some embodiments, the grouping strategy further includes that the number of non- blank matrix blocks in the matrix blocks of the at least two columns is at most N, and the calculation result of each column of matrix blocks performed by the VN unit according to the compressed matrix is a V2C message generated in the iteration.
[0099] In some embodiments, the VN unit comprises N first inputs, and the values of the matrix blocks of each column of the compressed matrix are input to the N first inputs of the VN unit sequentially according to the grouping.
[0100] In some embodiments, the grouping strategy further comprises that in the matrix blocks of the at least two columns, the number of matrix blocks with non-blank elements is at most P, and P is less than N. The compressed matrix is divided into a plurality of sub-matrices, and when the number of non-blank elements contained in the matrix blocks of one column of the base matrix is greater than P, the matrix blocks of the column are arranged in different sub-matrices. In each iteration operation, the VN unit sequentially performs the calculation of each column of matrix blocks according to the plurality of sub-matrices column by column.
[0101] In some embodiments, the VN unit comprises a register for storing the calculation results of the VN unit according to each of the sub-matrices, and the VN unit adds the calculation results of the corresponding same column in all the previous sub-matrices when performing the calculation of each column of matrix blocks according to the last sub-matrix column by column, and the final result is the sum of the values of the matrix blocks of the same column of the compressed matrix in the iteration.
[0102] In some embodiments, the VN unit comprises P first inputs, and the values of the matrix blocks of each column of the compressed matrix are input to the P first inputs of the VN unit sequentially according to the grouping.
[0103] In some embodiments, the decoder further comprises a C2V unit coupled between the VN unit and the CN unit, for associating the C2V message generated by the CN unit with the compressed matrix and transmitting to the VN unit.
[0104] The above merely describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Those skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A flash memory controller for accessing a flash memory, characterized in that: The flash memory controller comprises: a read-only memory for storing a program code; a microprocessor for executing the program code to control access to the flash memory; and a decoder for performing a decoding operation of a base matrix of a low-density parity-check code to decode read information obtained from the flash memory, the base matrix having a size of N x M, the decoder comprising: a controller for converting the base matrix into a compressed matrix of N x S, where S is less than M, and each column of the compressed matrix has its matrix blocks grouped according to the matrix blocks of a same column of the base matrix; a variable node (VN) unit coupled to the controller and comprising a plurality of first inputs; a check node (CN) unit coupled to the VN unit, wherein the VN unit and the CN unit are configured to perform message updates between variable nodes and check nodes to generate a decoding result converging to a codeword; wherein in each iteration operation, the VN unit performs calculation of each column of matrix blocks according to the compressed matrix column by column, and the values of the matrix blocks of each column of the compressed matrix are sequentially input to the plurality of first inputs of the VN unit according to the grouping.
2. The flash controller of claim 1, wherein, The VN unit further comprises: a column sum calculation circuit comprising a plurality of adders; a group selection circuit connected to the column sum calculation circuit, wherein the group selection circuit selects paths of the plurality of adders to be turned on according to the grouping of the matrix blocks of a same column of the compressed matrix, and the column sum calculation circuit adds values of the matrix blocks of a same group based on the path selection result of the group selection circuit.
3. The flash controller of claim 2, wherein, The plurality of first inputs are divided into a plurality of sub-sets, each of the sub-sets is connected to an adder of the column sum calculation circuit, the adder adds values input through the sub-set, and wherein values from a same group of matrix blocks are input to one or more of the sub-sets, and each of the sub-sets only inputs values from a same group of matrix blocks.
4. The flash controller of claim 1, wherein, The controller of the decoder comprises a grouping unit for merging matrix blocks of at least two columns of the base matrix according to a grouping strategy, wherein the grouping strategy is that the number of variable nodes corresponding to each row in the matrix blocks of the at least two columns is at most one.
5. The flash controller of claim 4, wherein, The grouping strategy further comprises that the number of matrix blocks of non-blank elements in the matrix blocks of the at least two columns is at most N, and the calculation result of each column of matrix blocks performed by the VN unit according to the compressed matrix is a V2C message generated in the iteration.
6. The flash controller of claim 5, wherein, The VN unit comprises N first inputs, and the values of the matrix blocks of each column of the compressed matrix are sequentially input to the N first inputs of the VN unit according to the grouping.
7. The flash controller of claim 4, wherein, The grouping strategy further comprises that the number of matrix blocks of non-blank elements in the matrix blocks of the at least two columns is at most P, where P is less than N; the compressed matrix is divided into a plurality of sub-matrices, and when the number of non-blank elements contained in the matrix blocks of a column of the base matrix is greater than P, the matrix blocks of the column are arranged in different sub-matrices; and In each iteration operation, the VN unit sequentially performs the calculation of each column of matrix blocks according to the plurality of sub-matrices column by column.
8. The flash controller of claim 7, wherein, The VN unit comprises a register for storing the calculation results of the VN unit according to each of the sub-matrices, and the VN unit adds the calculation results of the corresponding same column of all the previous sub-matrices when performing the calculation of each column of matrix blocks according to the last sub-matrix column by column, and the final result is the addition result of the values of each group of matrix blocks in the same column of the compressed matrix in the iteration.
9. The flash controller of claim 7, wherein, The VN unit comprises P first input terminals, and the values of the matrix blocks in each column of the compressed matrix are sequentially input into the P first input terminals of the VN unit according to grouping.
10. The flash controller of claim 1, wherein, The decoder further comprises a C2V unit coupled between the VN unit and the CN unit, for associating the C2V message generated by the CN unit with the compressed matrix and transmitting to the VN unit.
11. An access method of a flash memory, applied to a memory controller, characterized in that, The method comprises: obtaining read information from a flash memory; performing a decoding operation of a base matrix of a low-density parity-check code by a decoder to decode the read information, the base matrix having a size of N×M; converting the base matrix into a compressed matrix of N×S, wherein S is less than M; grouping the matrix blocks in each column of the compressed matrix according to the matrix blocks in the same column of the base matrix; performing message updating between variable nodes (VN) and check nodes (CN) by a VN unit and a CN unit of the decoder to generate a decoding result converging to a codeword, wherein in each iteration operation, the VN unit performs the calculation of each column of matrix blocks according to the compressed matrix column by column, and the values of the matrix blocks in each column of the compressed matrix are sequentially input into a plurality of first input terminals of the VN unit according to grouping.
12. The method of accessing the flash memory as claimed in claim 11, wherein, The VN unit further comprises a column sum calculation circuit and a group selection circuit, and the method further comprises that the group selection circuit selects a path of a plurality of adders of the column sum calculation circuit according to the grouping of the matrix blocks in the same column of the compressed matrix, and the column sum calculation circuit adds the values of the matrix blocks in the same group based on the path selection result of the group selection circuit.
13. The method of accessing the flash memory as claimed in claim 12, wherein, The plurality of first input terminals are divided into a plurality of sub-sets, each of the sub-sets is connected to an adder of the column sum calculation circuit, the adder adds the values input through the sub-set, and wherein the values from the same group of matrix blocks are input into one or more sub-sets, and each sub-set only inputs values from the same group of matrix blocks.
14. The method of accessing the flash memory as claimed in claim 11, wherein, In the conversion of the base matrix into the compressed matrix of N×S, the method further comprises merging the matrix blocks of at least two columns in the base matrix according to a grouping strategy, wherein in the matrix blocks of the at least two columns, the number of corresponding variable nodes in each row is at most one.
15. The method of accessing the flash memory as claimed in claim 14, wherein, The grouping strategy further comprises grouping the matrix blocks in the at least two columns, and the number of the matrix blocks of non-blank elements in each column is at most N, and the VN unit sequentially performs the calculation of each column of matrix blocks according to the compressed matrix, and the calculation result of each column of matrix blocks is a V2C message generated in the current iteration.
16. The method of accessing the flash memory as claimed in claim 15, wherein, The VN unit comprises N first input terminals, and the number of the matrix blocks of each column in the compressed matrix is sequentially input to the N first input terminals of the VN unit according to the grouping.
17. The method of accessing the flash memory as claimed in claim 14, wherein, The grouping strategy further comprises grouping the matrix blocks in the at least two columns, and the number of the matrix blocks of non-blank elements in each column is at most P, and P is less than N; The compressed matrix is divided into a plurality of sub-matrices, and when the number of non-blank elements included in the matrix blocks of one column in the base matrix is greater than P, the matrix blocks of the column are arranged in different sub-matrices. And In each iteration operation, the VN unit sequentially performs the calculation of each column of matrix blocks according to the plurality of sub-matrices.
18. The method of accessing the flash memory as claimed in claim 17, wherein, The VN unit comprises a register for storing the calculation results of the VN unit according to each of the sub-matrices, and when the VN unit sequentially performs the calculation of each column of matrix blocks according to the last sub-matrix, the VN unit adds the calculation results of the corresponding column in all the previous sub-matrices to obtain the final result, which is the sum of the values of the matrix blocks of the same column in the compressed matrix in the current iteration.
19. The method of accessing the flash memory as claimed in claim 17, wherein, The VN unit comprises P first input terminals, and the number of the matrix blocks of each column in the compressed matrix is sequentially input to the P first input terminals of the VN unit according to the grouping.
20. The method of accessing the flash memory as claimed in claim 11, wherein, The decoder further comprises a C2V unit coupled between the VN unit and the CN unit, configured to associate the C2V message generated by the CN unit with the compressed matrix and transmit to the VN unit.