Board-level packaging method and structure

Abstract

The invention discloses a board-level packaging method and a board-level packaging structure. The board-level packaging method comprises the following steps of: 1, providing a carrier board; 2, mounting a first chip on the carrier plate; 3, wrapping the first chip with a first dielectric layer; 4, bonding a carrier on the surface of the first dielectric layer, and detaching the carrier; 5, manufacturing a metal circuit on the surface of the first chip; 6, mounting a plurality of chips on the surface of the first chip; 7, wrapping the plurality of chips in the step 6 by using a second dielectric layer; 8, manufacturing a through hole in the second dielectric layer; ninthly, through hole metallization is carried out; tenthly, covering the surface of the structure obtained in the last step with a passivation dielectric layer; eleventhly, preparing a surface metal layer on the surface of the structure obtained in the tenth step; and twelfthly, the carrier is disassembled, the packaging body is cut into single pieces, and integration of multiple chips is achieved. Chip and antenna integration is efficiently achieved, the packaging efficiency is high, tens of thousands of packaging bodies can be packaged at a time, the packaging cost is reduced, and the product performance is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a board-level packaging method and structure. Background Art

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs), which control the voltage or current of a device, are used in nearly all power industrial products. A single power chip is often equipped with one or more transistors, so power devices generally require multi-chip interconnect packaging. Traditional gold-bonding wire packaging and flip-chip packaging processes struggle to meet the increasingly complex and dense wiring requirements, making it difficult to meet the modular packaging requirements of power devices, particularly those for high-performance, high-computing, and high-memory devices.

[0003] Traditional antennas are usually assembled on a PCB board with other chips in the form of antenna chips, occupying additional circuit board area. The package is large in size, large in area, and consumes high power. The product has poor integration and high cost, which is not conducive to miniaturization and high-efficiency applications. Summary of the Invention

[0004] In order to solve the technical problem in the prior art that traditional packaging processes are difficult to achieve multi-chip integration, the purpose of the present invention is to provide a board-level packaging method and structure.

[0005] In order to achieve the above-mentioned purpose and the above-mentioned technical effect, the technical solution adopted by the present invention is:

[0006] A board-level packaging method comprises the following steps:

[0007] The first step is to provide a carrier board;

[0008] The second step is to mount the first chip on the carrier board;

[0009] Step three, wrapping the first chip with a first dielectric layer;

[0010] Step 4: Bonding a carrier to the surface of the first dielectric layer, and then removing the substrate;

[0011] Step 5: Fabricate metal circuits on the surface of the first chip;

[0012] Step 6: Mount several chips on the surface of the first chip;

[0013] Step 7: Wrap the chips prepared in step 6 with a second dielectric layer;

[0014] Step 8: Making a through hole on the second dielectric layer;

[0015] The ninth step is to perform through-hole metallization;

[0016] Step 10: Covering the surface of the structure obtained in step 9 with a passivation dielectric layer;

[0017] Step 11, preparing a surface metal layer on the surface of the structure obtained in Step 10;

[0018] The twelfth step is to dismantle the carrier and cut the package into individual pieces to achieve multi-chip integration.

[0019] Furthermore, in the first step, a peeling layer is prepared on a carrier, the carrier is a metal, glass or organic substrate, and the peeling layer is a temporary bonding adhesive or film.

[0020] Furthermore, in the second step, the first chip has a first metal pad 4, and the first chip is a power chip, a computing chip, a storage chip or other types of chips.

[0021] Furthermore, in the fourth step, a carrier is bonded to the surface of the first dielectric layer through a temporary bonding layer, and the carrier is a metal, glass or organic substrate.

[0022] Furthermore, in the fifth step, a metal circuit is first made on the surface of the first chip, and then a passivation layer is made to protect the metal circuit. The passivation layer is covered on the surface of the first chip by spraying glue, printing glue or pressing a passivation film. When the passivation layer uses a photolithography material, the opening on the passivation layer is realized by exposure and development. When the passivation layer uses a non-photolithography material, the opening on the passivation layer is opened by laser.

[0023] Furthermore, in the sixth step, a second chip and a third chip are mounted on the surface of the first chip, the second chip has a second metal pad, the third chip has a third metal pad, and the second chip and the third chip are the same or different chips.

[0024] Furthermore, in the eighth step, a through hole is formed on the second dielectric layer by laser to expose the metal pad of the chip.

[0025] Furthermore, in the tenth step, a passivation dielectric layer is covered on the surface of the structure obtained in the ninth step by spraying glue, printing glue or pressing a passivation film. When the passivation dielectric layer adopts a photolithographic material, the opening on the passivation dielectric layer is realized by exposure and development. When the passivation dielectric layer adopts a non-photolithographic material, the opening on the passivation dielectric layer is opened by laser.

[0026] Furthermore, in the twelfth step, the carrier and the temporary bonding layer thereon are removed.

[0027] The present invention also discloses a board-level packaging structure, which is prepared using a board-level packaging method as described above. The board-level packaging structure includes a first dielectric layer, a first chip is encapsulated in the first dielectric layer, a metal circuit and a passivation layer are provided on the surface of the first chip, a plurality of chips are mounted on the surface of the first chip, and the plurality of chips are encapsulated in a second dielectric layer, a metal column and a metal layer are formed on the second dielectric layer, and a passivation dielectric layer and a surface metal layer are provided on the surface of the second dielectric layer.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1) Using carriers and substrates, and adopting board-level packaging technology, it solves the multi-chip integration problem that is difficult to solve with traditional packaging processes. It can package tens of thousands of packages at a time, significantly improving packaging efficiency and reducing packaging costs;

[0030] 2) The chip and antenna structure are integrated during packaging, so that the chip signal can be effectively transmitted and received, multiplying the signal quality of the entire device;

[0031] 3) When integrating the chip, an antenna structure (metal pillars and metal layers) will be formed, which will indirectly reduce the proportion of the solder mask layer in the conventional package, thereby reducing the stress and warping of the entire package and improving product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of the first step of the present invention;

[0033] Figure 2 It is a structural schematic diagram of the second step of the present invention;

[0034] Figure 3 It is a structural schematic diagram of the third step of the present invention;

[0035] Figure 4-5 It is a structural schematic diagram of the fourth step of the present invention;

[0036] Figure 6 It is a structural schematic diagram of the fifth step of the present invention;

[0037] Figure 7 It is a structural schematic diagram of the sixth step of the present invention;

[0038] Figure 8 It is a structural schematic diagram of the seventh step of the present invention;

[0039] Figure 9 It is a structural schematic diagram of the eighth step of the present invention;

[0040] Figure 10 It is a structural schematic diagram of the ninth step of the present invention;

[0041] Figure 11 It is a structural schematic diagram of the tenth step of the present invention;

[0042] Figure 12 It is a structural schematic diagram of the eleventh step of the present invention;

[0043] Figure 13 It is a structural schematic diagram of the twelfth step of the present invention. DETAILED DESCRIPTION

[0044] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0045] The following is a brief summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceivable aspects and is neither intended to identify key or critical elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be provided later.

[0046] like Figure 1-13 As shown, a board-level packaging method includes the following steps:

[0047] The first step, such as Figure 1 As shown, a peeling layer 2 is prepared on a carrier 1, wherein the carrier 1 can be a metal, glass or organic substrate, and the peeling layer 2 is a temporary bonding adhesive or film;

[0048] The second step is Figure 2 As shown, a first chip 3 with a first metal pad 4 is mounted on a carrier board 1, wherein the first chip 3 is generally a power chip, a computing chip, a memory chip or other types of chips;

[0049] The third step, such as Figure 3 As shown, the first chip 3 is wrapped with a first dielectric layer 5. The first dielectric layer 5 is generally a plastic packaging material, which is achieved through a plastic packaging process. It can also be other passivation insulating materials.

[0050] The fourth step is as follows Figure 4-5 As shown, a carrier 7 is bonded to the surface of the dielectric layer 5 through a temporary bonding layer 6, and then the substrate 1 and the peeling layer 2 are removed, wherein the carrier 7 can be a metal, glass or organic substrate;

[0051] Step 5: Figure 6As shown, a metal circuit 8 and a passivation layer 9 are made on the surface of the first chip 3 to lead the electrical signal of the first chip 3 outward from the first metal pad 4. First, a metal circuit 8 is made on the surface of the first chip 3, and then a passivation layer 9 is made. A metal seed layer is prepared by physical vapor deposition, a pattern is prepared by photolithography, a thick metal layer structure is prepared by electroplating, and a thin seed layer is etched on the entire surface to realize metal circuitization and form a metal circuit 8. The passivation layer 9 is made of a passivation material, which can be covered on the surface of the first chip 3 by spraying glue, printing glue or pressing a passivation film. When the passivation material is a photolithographic material, the opening on the passivation layer 9 can be realized by exposure and development. When it is a non-photolithographic material, the opening on the passivation layer 9 can be opened by laser;

[0052] Step 6: Figure 7 As shown, several chips are mounted on the surface of the first chip 3. Preferably, a second chip 10 and a third chip 11 are mounted on the surface of the first chip 3. The second chip 10 has a second metal pad 12, and the third chip 11 has a third metal pad 13. The second chip 10 and the third chip 11 are generally power controllers, but may also be other types of chips. The second chip 10 and the third chip 11 may be the same chip or different chips.

[0053] Step 7: Figure 8 As shown, the second chip 10 and the third chip 11 are wrapped with a second dielectric layer 14. The second dielectric layer 13 is generally a plastic packaging material, which is achieved through a plastic packaging process. It can also be other passivation insulating materials.

[0054] Step 8: Figure 9 As shown, a through hole 15 is formed on the second dielectric layer 14 by laser, so that the metal pads of the second chip 10 and the third chip 11 are exposed;

[0055] Step 9: Figure 10 As shown, through-hole metallization is performed to obtain metal pillars 16 and metal layers 17, which lead the electrical signals of each chip outward from their respective metal pads and form an antenna structure to achieve signal reception and transmission. Generally, a metal seed layer is prepared by physical vapor deposition, a circuit pattern is prepared by photolithography, a thick metal layer is prepared by electroplating, and finally a thin layer of seed layer is etched across the entire surface to achieve through-hole metallization to obtain metal pillars 16 and metal layers 17;

[0056] Step 10, such as Figure 11 As shown, a passivation dielectric layer 18 is formed of a passivation material. The passivation material can be coated on the surface of the structure obtained in the ninth step by spraying, printing, or pressing a passivation film. When the passivation material is a photolithographic material, the opening 19 on the passivation dielectric layer 18 can be realized by exposure and development. When the passivation material is a non-photolithographic material, the opening 19 on the passivation dielectric layer 18 can be opened by laser.

[0057] Step 11, such as Figure 12 As shown, in order to meet the signal transmission requirements of multiple pins of multiple chips, a surface metal layer 20 is prepared on the surface of the structure obtained in the tenth step, and the preparation method is the same as that of the metal layer 17;

[0058] Step 12: Figure 13 As shown, the temporary bonding layer 6 and the carrier 7 are removed, and the package body is cut into individual pieces to achieve the integration of the first, second, and third chips.

[0059] A board-level packaging structure is prepared using the board-level packaging method described above, including a first dielectric layer 5, a first chip 3 is encapsulated in the first dielectric layer 5, a metal circuit 8 and a passivation layer 9 are provided on the surface of the first chip 3, a plurality of chips are mounted on the surface of the first chip 3, and the plurality of chips are encapsulated in a second dielectric layer 14, a metal column 16 and a metal layer 17 are formed on the second dielectric layer 14, and a passivation dielectric layer 18 and a surface metal layer 20 are provided on the surface of the second dielectric layer 14.

[0060] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0061] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A board-level packaging method, characterized in that: The following steps are involved: The first step is to provide a carrier board; The second step is to mount the first chip on the carrier board; Step three, wrapping the first chip with a first dielectric layer; Step 4: Bonding a carrier to the surface of the first dielectric layer, and then removing the substrate; Step 5: Fabricate metal circuits on the surface of the first chip; Step 6: Mount several chips on the surface of the first chip; Step 7: Wrap the chips prepared in step 6 with a second dielectric layer; Step 8: Making a through hole on the second dielectric layer; The ninth step is to perform through-hole metallization; Step 10: Covering the surface of the structure obtained in step 9 with a passivation dielectric layer; Step 11, preparing a surface metal layer on the surface of the structure obtained in Step 10; The twelfth step is to dismantle the carrier and cut the package into individual pieces to achieve multi-chip integration.

2. A board-level packaging method according to claim 1, characterized in that: In the first step, a release layer is prepared on a carrier, which is a metal, glass or organic substrate, and the release layer is a temporary bonding adhesive or film.

3. The board-level packaging method according to claim 1, wherein: In the second step, the first chip has a first metal pad 4, and the first chip is a power chip, a computing chip, a memory chip or other types of chips.

4. The board-level packaging method according to claim 1, wherein: In the fourth step, a carrier is bonded to the surface of the first dielectric layer through a temporary bonding layer, and the carrier is a metal, glass or organic substrate.

5. The board-level packaging method according to claim 1, wherein: In the fifth step, a metal circuit is first made on the surface of the first chip, and then a passivation layer is made. The passivation layer is covered on the surface of the first chip by spraying glue, printing glue or pressing a passivation film. When the passivation layer is made of photolithographic material, the opening on the passivation layer is realized by exposure and development. When the passivation layer is made of non-photolithographic material, the opening on the passivation layer is opened by laser.

6. The board-level packaging method according to claim 1, wherein: In the sixth step, a second chip and a third chip are mounted on the surface of the first chip, wherein the second chip has a second metal pad, and the third chip has a third metal pad, and the second chip and the third chip are the same or different chips.

7. The board-level packaging method according to claim 1, wherein: In the eighth step, a through hole is formed on the second dielectric layer by laser to expose the metal pad of the chip.

8. The board-level packaging method according to claim 1, wherein: In the tenth step, a passivation dielectric layer is covered on the surface of the structure obtained in the ninth step by spraying glue, printing glue or pressing a passivation film. When the passivation dielectric layer adopts a photolithographic material, the opening on the passivation dielectric layer is realized by exposure and development. When the passivation dielectric layer adopts a non-photolithographic material, the opening on the passivation dielectric layer is opened by laser.

9. The board-level packaging method according to claim 1, wherein: In the twelfth step, the carrier and the temporary bonding layer thereon are removed.

10. A board-level packaging structure, characterized in that: The board-level packaging structure is prepared using a board-level packaging method according to any one of claims 1 to 9, wherein the board-level packaging structure includes a first dielectric layer, a first chip is encapsulated in the first dielectric layer, a metal circuit and a passivation layer are provided on the surface of the first chip, a plurality of chips are mounted on the surface of the first chip, and the plurality of chips are encapsulated in a second dielectric layer, a metal column and a metal layer are formed on the second dielectric layer, and a passivation dielectric layer and a surface metal layer are provided on the surface of the second dielectric layer.

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