A semiconductor cascade device and a packaging method thereof

Abstract

The application relates to a semiconductor cascade device and a packaging method thereof, and belongs to the technical field of semiconductor packaging. The packaging method of the semiconductor cascade device comprises the following steps: fan-out packaging of electrodes of a first semiconductor chip to obtain a third semiconductor chip, and forming a first redistribution layer on a front surface of the third semiconductor chip, wherein the third semiconductor chip comprises a first area and a second area arranged transversely, the first semiconductor chip is packaged in the first area, and a heat dissipation passage is arranged in the second area; the first redistribution layer comprises a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a part of a front surface of the second area; a second semiconductor chip is attached on the cascade metal layer; and metal interconnection and plastic packaging are performed to obtain the semiconductor cascade device. The application reduces the area of the semiconductor chip, reduces parasitic parameters, and improves the overall heat dissipation effect of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a semiconductor cascade device and a packaging method thereof. BACKGROUND

[0002] GaN HEMT (Gallium Nitride High Electron Mobility Transistor) is a kind of semiconductor chip based on gallium nitride (GaN) material, which occupies an important position in the modern electronic field with high frequency, high power, high efficiency and other characteristics. In practical applications, the depletion mode GaN HEMT is often combined with the MOSFET tube to form a common-source common-gate cascade Cascode device for realizing the normally-off operation. In order to improve the performance of the device, such as realizing the drain voltage balance, improving the switching speed, avoiding the generation of overshoot voltage peak, etc., resistors, capacitors or diodes are added in the Cascode device. The GaN HEMT can also be used as a functional level device of the circuit to form an IC control and discrete power level circuit structure with the control semiconductor chip to meet the needs of high frequency, high efficiency and high reliability in different application scenarios. The above-mentioned various semiconductor chips containing GaN HEMT are collectively referred to as GaN cascade devices.

[0003] The packaging of GaN cascade devices mainly includes two types, one is a horizontal packaging structure, and the other is a laminated packaging structure. Taking Cascode as an example, in the existing horizontal packaging structure, MOSFET and GaN HEMT are arranged horizontally, and DPC (Direct Plating Copper) substrate, silicon substrate or ceramic substrate are used as the horizontal arrangement medium of MOSFET (such as the scheme in the patent application with publication number CN113782511A). Although this method is mature in technology, the horizontal layout method requires a large-area substrate, resulting in a large size of the semiconductor chip, which is difficult to meet the miniaturization demand of the semiconductor chip; the electrode spacing in the horizontal packaging structure is long, and the long-distance wiring will introduce parasitic inductance and capacitance, affecting the high-frequency performance. In the existing laminated packaging structure, MOSFET is usually stacked above the active region of GaN HEMT (such as the scheme in the patent application with publication number CN113826206A), thereby reducing the size of the semiconductor chip and solving the problem of large size of the semiconductor chip in the horizontal packaging structure. However, the laminated packaging structure has the contradiction between heat management and area optimization. Specifically, the heat generated by MOSFET needs to pass through the GaN active region to be conducted to the heat dissipation substrate, the heat dissipation path is long, and the thermal resistance is large; the local power density of MOSFET is high, which easily causes the concentration of device thermal stress, resulting in the decrease of the reliability of the device; in addition, the laminated structure occupies the space of the active region, limiting the layout of resistors, capacitors and other passive components, causing the difficulty in integrating passive devices. SUMMARY

[0004] In order to solve the above technical problems, according to one aspect of the present application, a semiconductor cascade device and a packaging method and structure thereof are provided, which can reduce the area of semiconductor chips, optimize the heat management path and reduce parasitic parameters.

[0005] In order to solve the above technical problems, according to one aspect of the present application, a semiconductor cascade device and a packaging method and structure thereof are provided, which can reduce the area of semiconductor chips, optimize the heat management path and reduce parasitic parameters.

[0006] The first semiconductor chip is fan-out packaged to obtain a third semiconductor chip, and a first redistribution layer is formed on the front surface of the third semiconductor chip, wherein the third semiconductor chip comprises a first region and a second region arranged laterally, the first semiconductor chip is packaged in the first region, and the second region comprises a heat dissipation path; the first redistribution layer comprises a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least the front surface of the second region; and the cascade metal layer is connected with the heat dissipation path in the second region.

[0007] The second semiconductor chip is attached on the cascade metal layer.

[0008] The first electrode fan-out metal layer and the second electrode of the second semiconductor chip are interconnected to realize the electrical connection relationship between the first semiconductor chip and the second semiconductor chip and obtain a structure comprising a plurality of device electrodes of the semiconductor cascade device; and

[0009] The structure realizing the metal interconnection is plastic encapsulated to obtain the semiconductor cascade device.

[0010] Optionally, the step of fan-out packaging the first semiconductor chip to obtain a third semiconductor chip comprises:

[0011] The first semiconductor chip is first fan-out packaged to form a second redistribution layer, wherein the second redistribution layer comprises a first electrode fan-out metal layer leading to the front surface and a first electrode fan-out metal layer leading to the back surface beyond the body of the first semiconductor chip.

[0012] The first electrode fan-out metal layer leading to the front surface is fan-out packaged on the front surface, the first electrode fan-out metal layer leading to the back surface is fan-out packaged on the back surface, a first redistribution layer is formed on the front surface of the third semiconductor chip, and a third redistribution layer is formed on the back surface of the third semiconductor chip; the first redistribution layer includes the first electrode fan-out metal layer of the first semiconductor chip and a cascaded metal layer covering at least a part of the front surface of the second region; and the third redistribution layer includes at least the first electrode fan-out metal layer.

[0013] Optionally, the step of fan-out packaging the electrodes of the first semiconductor chip includes:

[0014] The first semiconductor chip and a third structure are arranged side by side, the front surface and the back surface of the third structure include metal layers respectively; and

[0015] The electrodes of the first semiconductor chip and the third structure arranged side by side are fan-out packaged to obtain a third semiconductor chip, and a first redistribution layer is formed on the front surface of the third semiconductor chip;

[0016] Optionally, the first semiconductor chip is packaged in the first region of the third semiconductor chip, and the third structure is packaged in the second region and forms the heat dissipation passage; and the first redistribution layer includes a cascaded metal layer covering at least a part of the front surface of the second region, which is obtained by fan-out packaging the front surface metal layer of the third structure.

[0017] Optionally, a second region exceeding the first semiconductor chip is obtained when the electrodes of the first semiconductor chip are fan-out packaged, a metal column penetrating through the second region is formed in the second region, and the metal column forms the heat dissipation passage.

[0018] Optionally, when the first redistribution layer is formed on the front surface of the third semiconductor chip, the first electrode fan-out metal layer of the first semiconductor chip and the cascaded metal layer covering at least a part of the front surface of the second region are insulated and separated from each other; or the first electrode fan-out metal layer of the first semiconductor chip and the cascaded metal layer are integrally formed; or the cascaded metal layer extends from a part of the front surface of the second region to a part of the front surface of the first region.

[0019] Optionally, the step of interconnecting the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to realize the electrical connection relationship between the first semiconductor chip and the second semiconductor chip includes:

[0020] The third semiconductor chip is mounted on a lead frame, and the lead frame includes device pins as device electrodes; and

[0021] The metal interconnection is performed by wire bonding, or by metal strip interconnection through strip bonding, or by metal sheet interconnection through compression bonding.

[0022] Optionally, the step of interconnecting the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve the electrical connection relationship between the first semiconductor chip and the second semiconductor chip comprises:

[0023] The first electrode fan-out metal layer and the second electrode of the second semiconductor chip are fan-out packaged one or more times, and at each time of fan-out packaging, the electrical connection relationship between the first semiconductor chip and the second semiconductor chip is achieved through the redistribution layer.

[0024] According to another aspect of the present application, the present application further provides a semiconductor cascade device, comprising:

[0025] A third semiconductor chip comprising a first region and a second region arranged laterally, the first region encapsulating the first semiconductor chip, and the second region comprising a heat dissipation passage; a first redistribution layer is formed on the front surface of the third semiconductor chip, the first redistribution layer comprising the first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least the front surface of the second region; the cascade metal layer is connected to the heat dissipation passage in the second region;

[0026] A second semiconductor chip is attached to the cascade metal layer;

[0027] A metal interconnection structure is connected to the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve the electrical connection relationship between the first semiconductor chip and the second semiconductor chip and obtain a plurality of device electrodes comprising the semiconductor cascade device.

[0028] Optionally, the third semiconductor chip further comprises a second redistribution layer inside, the second redistribution layer comprising the first electrode fan-out metal layer leading to the front surface and the first electrode fan-out metal layer leading to the back surface beyond the body of the first semiconductor chip; correspondingly, the back surface of the third semiconductor chip comprises a third redistribution layer, the third redistribution layer comprising at least the first electrode fan-out metal layer.

[0029] Optionally, the second region of the third semiconductor chip comprises a metal column penetrating the second region for forming the heat dissipation passage, the top of the metal column being connected to the cascade metal layer.

[0030] Optionally, the second region of the third semiconductor chip is internally encapsulated with a third structure, the front surface and the back surface of the third structure respectively comprising a metal layer; correspondingly, part or all of the cascaded metal layers in the first redistribution layer are fan-out metal layers of the front surface metal layer of the third structure, and the third structure and the fan-out metal structure thereof form the heat dissipation channel.

[0031] Optionally, the front surface metal layer and / or the back surface metal layer of the third structure are one or two or more insulated from each other.

[0032] Optionally, the third structure is a substrate, a substrate integrated with an embedded circuit, or a fourth semiconductor chip.

[0033] When the third structure is a substrate integrated with an embedded circuit, the front surface metal layer and / or the back surface metal layer are electrical connection points of the embedded circuit.

[0034] When the third structure is a fourth semiconductor chip, the front surface metal layer and / or the back surface metal layer are electrodes of the fourth semiconductor chip.

[0035] Optionally, the embedded circuit comprises any combination of one or more of a resistor, a capacitor, and a diode.

[0036] Optionally, the back surface of the second semiconductor chip comprises a second electrode, a first electrode fan-out metal layer of the first semiconductor chip has an electrical connection relationship with the second electrode of the back surface of the second semiconductor chip and is insulated and separated from the cascaded metal layer, and the second electrode of the second semiconductor chip is simultaneously attached to the first electrode fan-out metal layer having an electrical connection relationship therewith and the cascaded metal layer.

[0037] Optionally, the back surface of the second semiconductor chip comprises a second electrode, a first electrode fan-out metal layer of the first semiconductor chip has an electrical connection relationship with the second electrode of the back surface of the second semiconductor chip, and the first electrode fan-out metal layer having an electrical connection relationship with the second electrode of the back surface of the second semiconductor chip is integrally connected with the cascaded metal layer.

[0038] Optionally, the first semiconductor chip is a depletion-mode semiconductor chip, and the second semiconductor chip is an enhancement-mode semiconductor chip; or the first semiconductor chip is an enhancement-mode semiconductor chip, and the second semiconductor chip is a depletion-mode semiconductor chip; or the second semiconductor chip is a driving IC chip of the first semiconductor chip, or the first semiconductor chip is a driving IC chip of the second semiconductor chip.

[0039] Optionally, the second semiconductor chip body and the first semiconductor chip body longitudinally overlap.

[0040] Compared with the existing horizontal packaging structure, the application reduces the semiconductor chip area, reduces the electrode pitch, and thus reduces the parasitic parameters; compared with the existing laminated packaging structure, the application optimizes the heat management path, avoids heat concentration, improves the overall heat dissipation effect of the semiconductor cascade device, and improves the integration flexibility of the embedded device. BRIEF DESCRIPTION OF DRAWINGS

[0041] In the following, the preferred embodiments of the application will be further described in detail with reference to the accompanying drawings, in which:

[0042] Figure 1 is a brief flow chart of the packaging method of the semiconductor cascade device according to an embodiment of the application;

[0043] Figure 2 is an electrical schematic diagram of the semiconductor cascade device according to embodiment one of the application;

[0044] Figure 3 is a flow chart of the packaging method of the semiconductor cascade device according to embodiment one of the application;

[0045] Figure 4 is a device packaging structure schematic diagram corresponding to part of the packaging method shown in Figure 3 ;

[0046] Figure 5 is a front packaging structure schematic diagram of a semiconductor cascade device obtained according to the packaging method shown in Figure 3 ;

[0047] Figure 6 is another flow chart of the fan-out packaging method of the HEMT 11 and the substrate 13 according to embodiment two of the application;

[0048] Figure 7 is a flow chart of a method of fan-out packaging of the side-by-side arranged HEMT 11 and the substrate 13 to obtain a third semiconductor chip 14 according to embodiment three of the application;

[0049] Figure 8 is a packaging structure schematic diagram corresponding to part of the fan-out packaging method shown in Figure 7 ;

[0050] Figure 9 is a structure top surface schematic diagram corresponding to step S204 in embodiment three of the application;

[0051] Figure 10 is a front packaging structure schematic diagram of a semiconductor cascade device obtained according to the packaging method of embodiment three;

[0052] Figure 11 is a flow chart of a packaging method for a semiconductor cascade device according to the fourth embodiment of the present application;

[0053] Figure 12 is a schematic diagram of a device package structure corresponding to the Figure 11 packaging method shown in FIG. 12;

[0054] Figure 13 is a schematic diagram of a top structure of a lead frame according to the fourth embodiment of the present application;

[0055] Figure 14 is a schematic diagram of a front package structure of a semiconductor cascade device according to the fourth embodiment of the present application;

[0056] Figure 15 is a schematic diagram of a device package structure for packaging steps of a semiconductor cascade device according to the fifth embodiment of the present application;

[0057] Figure 16 is an electrical schematic diagram of a first semiconductor cascade device according to the sixth embodiment of the present application;

[0058] Figure 17 is a schematic diagram of a device package structure corresponding to the Figure 16 electrical schematic shown in FIG. 14;

[0059] Figure 18 is an electrical schematic diagram of a second semiconductor cascade device according to the sixth embodiment of the present application;

[0060] Figure 19 is an electrical schematic diagram of a third semiconductor cascade device according to the sixth embodiment of the present application;

[0061] Figure 20 is a schematic diagram of a front structure of a substrate 13 according to the sixth embodiment of the present application;

[0062] Figure 21 is a schematic diagram of a back structure of a substrate 13 according to the sixth embodiment of the present application;

[0063] Figure 22 is a schematic diagram of a device package structure corresponding to the Figure 19 electrical schematic shown in FIG. 16;

[0064] Figure 23 is a front schematic diagram of a device package structure corresponding to the Figure 19 electrical schematic shown in FIG. 17;

[0065] Figure 24 is an electrical schematic diagram of a fourth semiconductor cascade device according to the sixth embodiment of the present application;

[0066] Figure 25 is a schematic diagram of a device package structure corresponding to theFigure 24 Fig. 6 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the electrical principle of the sixth semiconductor cascade device in the embodiment six of the present application;

[0067] Figure 26 Fig. 7 is an electrical schematic diagram of a semiconductor cascade device according to the seventh semiconductor cascade device in the embodiment six of the present application;

[0068] Figure 27 Fig. 8 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the electrical principle of the seventh semiconductor cascade device in the embodiment six of the present application; Figure 26 Fig. 9 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the electrical principle of the eighth semiconductor cascade device in the embodiment six of the present application;

[0069] Figure 28 Fig. 10 is an electrical schematic diagram of a semiconductor cascade device according to the ninth semiconductor cascade device in the embodiment six of the present application;

[0070] Figure 29 Fig. 11 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the electrical principle of the ninth semiconductor cascade device in the embodiment six of the present application; Figure 28 Fig. 12 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the electrical principle of the tenth semiconductor cascade device in the embodiment six of the present application;

[0071] Figure 30 Fig. 13 is an electrical schematic diagram of a semiconductor cascade device according to the eleventh semiconductor cascade device in the embodiment six of the present application;

[0072] Figure 31 Fig. 14 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the electrical principle of the eleventh semiconductor cascade device in the embodiment six of the present application; Figure 30 Fig. 15 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the electrical principle of the twelfth semiconductor cascade device in the embodiment six of the present application;

[0073] Figure 32 Fig. 16 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the partial steps of the packaging method of the semiconductor cascade device in the embodiment seven of the present application;

[0074] Figure 33 Fig. 17 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the embodiment eight of the present application; and

[0075] Figure 34 Fig. 18 is a schematic diagram of a packaging structure of a semiconductor cascade device according to the embodiment nine of the present application. DETAILED DESCRIPTION

[0076] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0077] In the following detailed description, reference will be made to the accompanying drawings, which form a part of this description, illustrating certain embodiments of the present application. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The embodiments of the present application will be described in sufficient detail to enable those skilled in the art to make and use it. It is to be understood that other embodiments can be utilized and that structural, logical, and electrical changes can be made without departing from the scope of the present application. Additionally, the term "first", "second", and the like, used throughout are employed for purposes of nomenclature only and do not necessarily indicate a sequence or order of execution. It is to be understood that the terms "comprising", "including", "containing", or "having" and variations thereof do not exclude the presence of other elements or materials. It is to be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. It must be noted that, as used herein, the singular form "a", "an", and "the" include plural references unless the context clearly dictates otherwise. The terms "approximately", "substantially", and "about" can be used herein to include ±10% of the value stated, unless the context clearly dictates otherwise.

[0078] Referring to Figure 1 , Figure 1 is a brief flow chart of a packaging method of a semiconductor cascaded device according to an embodiment of the present application, the semiconductor cascaded device in the present application includes a first semiconductor chip and a second semiconductor chip having an electrical connection relationship, the packaging method of the semiconductor cascaded device includes:

[0079] In step S11, fan-out packaging is performed on the first semiconductor chip to obtain a third semiconductor chip. The third semiconductor chip includes a first region and a second region arranged laterally, the first semiconductor chip is packaged in the first region, and the second region includes a heat dissipation passage. In the fan-out packaging process, a first redistribution layer is formed on a front surface of the third semiconductor chip, the first redistribution layer includes one or more first electrode fan-out metal layers of the first semiconductor chip and a cascaded metal layer covering at least a front surface portion of the second region, and the cascaded metal layer is connected to the heat dissipation passage in the second region.

[0080] In step S12, the second semiconductor chip is attached on at least the cascaded metal layer, and the second semiconductor chip includes a plurality of second electrodes.

[0081] In step S13, metal interconnection is performed on the first electrode fan-out metal layers and the second electrodes of the second semiconductor chip to realize the electrical connection relationship between the first semiconductor chip and the second semiconductor chip, and then a structure including a plurality of device electrodes (or external terminals) of the semiconductor cascaded device is obtained.

[0082] In step S14, plastic packaging is performed on the structure in which the metal interconnection is realized to obtain the semiconductor cascaded device.

[0083] In the present application, when the first semiconductor chip is a depletion-mode semiconductor chip, the second semiconductor chip is an enhancement-mode semiconductor chip. When the first semiconductor chip is an enhancement-mode semiconductor chip, the second semiconductor chip is a depletion-mode semiconductor chip, and thus the first semiconductor chip and the second semiconductor chip can constitute a cascaded device.

[0084] The application is characterized in that when the semiconductor cascade device is packaged, a basic semiconductor device is obtained by fan-out packaging of the first semiconductor chip (die) at wafer level, the basic semiconductor device being the third semiconductor chip in step S11, and the second semiconductor chip is attached to the metal layer (i.e. the cascade metal layer mentioned above) on the surface of the basic semiconductor device and in communication with the heat dissipation passage in the second area. Compared with the traditional horizontal packaging scheme, the horizontal packaging size is reduced, the distance between the electrical connection points having an electrical connection relationship is shortened, and thus the parasitic parameters such as parasitic resistance, parasitic inductance and / or parasitic capacitance caused by wire bonding for metal interconnection are reduced. Compared with the existing vertical stacking packaging scheme, the heat dissipation path of the second semiconductor chip is separated from the heat dissipation path of the first semiconductor chip, and thus the heat dissipation effect of the device is good. Since the fan-out packaging can replace part or all of the wire bonding, the parasitic parameters can be further reduced, and the second semiconductor chip can be an enhancement chip or a control IC chip according to the design requirements of the product. The application can also introduce active elements (such as diodes, enhancement chips) or passive elements (such as resistors, capacitors, etc.) in the second area or the first semiconductor chip according to the design requirements of the product. Therefore, the packaging structure of the semiconductor cascade device provided by the application has high integration and good heat dissipation effect, and can realize packaging of semiconductor cascade devices with various electrical structures.

[0085] The semiconductor cascade device and the packaging method thereof of the application will be described in detail below through specific circuit structures and specific structures of chips. It should be noted that the packaging structure diagrams of the semiconductor cascade device in the following embodiments of the application are all schematic diagrams, and the positions, shapes and sizes of various structures in the diagrams are for illustrating the packaging method and principle, and are not used for production. In order to clearly show various necessary structures in the device in the structure diagram, part of the structures is enlarged or simplified when drawing.

[0086] Embodiment one

[0087] Figure 2is an electrical schematic diagram of a semiconductor cascode device according to the embodiment one of the present application. The semiconductor cascode device in this embodiment is commonly known as Cascode device or Common Gate Cascode device, which comprises a depletion mode High Electron Mobility Transistor (HEMT) 11 and an enhancement mode Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) 12, wherein the drain D of the MOSFET 12 is electrically connected to the source S of the HEMT 11, the gate G of the MOSFET 12 is the device gate 101 of the Cascode device, the source S of the MOSFET 12 is connected to the gate G of the HEMT 11 and is the device source 103 of the Cascode device. The drain D of the HEMT 11 is the device drain 102 of the Cascode device.

[0088] Figure 3 is a flow chart of a packaging method of a semiconductor cascode device according to the embodiment one of the present application. Figure 4 is a device packaging structure schematic diagram corresponding to Figure 3 part of the packaging method shown in Figure 5 is a front packaging structure schematic diagram of a semiconductor cascode device obtained according to Figure 3 the packaging method shown in Figure 5 the dashed line in indicates the internal structure of the device. In order to be able to indicate the lead-out condition of the chip electrode in the packaging process, the embodiment illustrates the three electrodes of the HEMT 11 in a parallel manner in the xz plane in Figure 4 the actual electrode layout manner, due to the position relationship of the electrodes in the y direction, it is not possible to show the position of the three electrodes in the xz plane, in order to express the fan-out condition of each electrode, the embodiment uses a parallel manner to draw the three electrodes in the figure, Figure 5 illustrated in is the conventional chip electrode position. In this embodiment, the three electrodes of the HEMT 11 are all located on the front surface of the chip, and include two gate electrode surfaces (or PADs). The drain D of the MOSFET 12 is located on the back surface of the chip, and the source S and the gate G are located on the front surface of the chip. Taking the coordinate axes in Figure 4 as an example, the front surface in the present application refers to the surface in the upward direction of the z axis, and the back surface refers to the surface in the downward direction of the z axis. Taking the HEMT 11 in this embodiment as an example, the surface including the three electrodes is the front surface of the chip, and the opposite surface is the back surface of the chip.

[0089] Referring to Figure 3 , the packaging method of the semiconductor cascode device according to the embodiment one of the present application comprises the following steps:

[0090] Step S101, provide HEMT 11 and substrate 13, and brush conductive glue on the back. The substrate 13 can be a direct plating copper (DPC) substrate, a ceramic substrate with a metal layer on the surface, a laminated resin plate, a sapphire substrate or other insulating material substrate, or a silicon substrate with a metal layer on the surface of the dielectric layer. The upper and lower surfaces of the substrate 13 are electrically insulated. In addition to brushing conductive glue on the back of the HEMT 11 and the substrate 13, a metal layer can be deposited on the back of the HEMT 11 and the substrate 13 as an alternative.

[0091] Step S102, use the patch process to mount the HEMT 11 and the substrate 13 on the temporary carrier 200. In this embodiment, the drain D, source S and gate G of the HEMT 11 are on the front surface of the chip.

[0092] Step S103, form metal posts on the electrode surfaces of the HEMT 11 and the metal layer surfaces of the substrate 13. As shown in Figure 4 , drain metal posts 311, gate metal posts 312 and source metal posts 313 are formed on the surfaces of the drain D, gate G and source S of the HEMT 11, and substrate metal posts 314 are formed on the metal layer surfaces of the substrate 13. In this embodiment, the metal posts formed on the chip electrode surfaces are a specific implementation of the conductive structure, and other conductive structures such as metal balls obtained by ball planting or other packaging processes can also be used.

[0093] Regarding the foregoing steps S102 and S103, when a HEMT wafer is provided, the metal posts can be grown on the wafer first, and then the wafer can be mounted on the temporary carrier 200. Since the HEMT 11 provided in this embodiment is a single die that has been diced, the HEMT 11 is first mounted on the temporary carrier 200 using the patch process, and then the metal posts are grown. The growth of the metal posts on the substrate 13 is similar.

[0094] Step S104, encapsulate the current structure to obtain a first encapsulated body 300.

[0095] Step S105, grind the surface of the first encapsulated body 300 to expose the surface of the metal posts, as shown in Figure 4 .

[0096] Step S106, a first redistribution layer 320 is formed on the front surface of the first plastic package 300 exposing the surface of the metal pillar, the first redistribution layer 320 includes a first drain metal layer 321 electrically connected to the drain D of the HEMT 11, a first gate metal layer 322 electrically connected to the gate G of the HEMT 11, and a cascade metal layer 323 electrically connected to the source S of the HEMT 11 and the front surface metal layer of the substrate 13. The first drain metal layer 321 and the first gate metal layer 322 can be collectively referred to as the first electrode fan-out metal layer of the HEMT 11.

[0097] From step S103 to step S106, the fan-out packaging of the HEMT 11 and the substrate 13 is completed.

[0098] Step S107, the temporary carrier 200 is removed to obtain a complete third semiconductor chip 14. The third semiconductor chip 14 includes two regions, the left region is the first region 303 in which the HEMT 11 is packaged, and the right region is the second region 304 in which the substrate 13 is packaged.

[0099] Step S108, the third semiconductor chip 14 is attached to the lead frame 400. As shown in Figure 5 , the lead frame 400 includes a chip pad 401 and a pin, such as a device drain pin 402, a device source pin 403, and a KS pin 404. The third semiconductor chip 14 is attached to the chip pad 401. The lead frame 400 in the embodiment includes four pins, of course, it can also include three pins, or a lead frame of other structure.

[0100] Step S109, the MOSFET 12 is attached to the cascade metal layer 323 on the surface of the third semiconductor chip 14 by the patch process.

[0101] Step S110, metal interconnection is performed. In the metal interconnection, wire bonding process can be used for wire interconnection, or strip bonding process can be used for metal strip interconnection, or metal sheet interconnection by pressure welding bridging process. For simplicity of illustration, Figure 4 , the bonding wire 410 is used to represent the interconnection mode, and Figure 5 , the metal strip 411 is used to represent the interconnection mode. Among them, refer to Figure 4 and Figure 5The first drain metal layer 321 on the surface of the third semiconductor chip 14 is connected to the device drain pin 402 of the lead frame 400 by a bonding wire 410 or a metal strip 411 (such as an aluminum strip or a copper strip), the first gate metal layer 322 on the surface of the third semiconductor chip 14 is electrically connected to the source S of the MOSFET 12, and the source S of the MOSFET 12 is electrically connected to the chip pad 401 of the lead frame 400. The chip pad 401 of the lead frame 400 is at the same potential as the device source pin 403 and the KS pin 404. The gate G of the MOSFET 12 is electrically connected to the device gate pin 405.

[0102] In step S111, the structure with metal interconnection is plastic encapsulated. For example, a plastic encapsulation process is used to encapsulate plastic encapsulation material such as epoxy resin around the chip, the bonding wire, and the like, and then to protect the same. According to actual scenarios such as production equipment and production lines, a transfer molding method, a compression molding method, or the like can be used. This step can also include a step of surface grinding the plastic encapsulation material to expose a flat electrode surface.

[0103] In step S112, electroplating, laser marking, cutting, and deburring are performed. After this step, a single semiconductor cascade device is obtained. Specifically, the electrode surface of the device is plated or electroplated with Ag, Au, or sputtered with aluminum or other metals that can be welded to facilitate electrical connection with other devices when applied. The surface of the plastic encapsulation body of the device is marked, for example, laser or ink is used to print chip information such as brand, model, batch, production cycle, version, and place of production on the surface of the chip. The overall plastic encapsulation body is cut to remove the connecting ribs, burrs, and the like. After the above processing, a single semiconductor cascade device is obtained.

[0104] By Figure 4 and Figure 5 As can be seen, the MOSFET 12 in the embodiment is attached to the cascade metal layer 323 on the surface of the third semiconductor chip 14, and the cascade metal layer 323 is integrally connected with the fan-out metal layer of the source S of the HEMT 11, so that the MOSFET 12 can be vertically arranged above the body of the HEMT 11 and the body of the substrate 13, which not only realizes the electrical connection relationship between the back drain D of the MOSFET 12 and the source S of the HEMT 11, but also provides a heat dissipation path for the MOSFET 12 independent of the HEMT 11. Compared with the heat dissipation accumulation phenomenon caused by the MOSFET stacked on the HEMT in the prior art, the overall heat dissipation of the device in the embodiment is better.

[0105] In the foregoing step S103, when forming the metal post on the electrode surface of the HEMT 11 and the metal layer surface of the substrate 13, taking the formation of the metal post on the electrode surface of the HEMT 11 as an example, a seed layer is first formed on the upper surface of the HEMT 11, for example, a copper layer is grown, which covers the electrode surface of the HEMT 11. Then a dry film is coated on the surface of the seed layer. The dry film is a photosensitive material, which generally consists of a photosensitive layer, a protective layer and a bottom layer, and the photosensitive layer is sandwiched between the protective layer and the bottom layer. The photosensitive layer has the characteristic of being sensitive to light, and undergoes a chemical reaction (dissolution or solidification) after being irradiated by ultraviolet light, so that a specific pattern can be formed by exposing and developing the dry film. Then the specified position of the dry film is exposed by a programmed control of the exposure machine, and in this embodiment, the dry film in the electrode surface area is exposed. Then the exposed dry film is removed by using a developing solution (generally a dilute alkaline solution, such as Na2CO3 solution) to expose the electrode surface where the long copper post is needed. Then copper or nickel or gold and other metals are electroplated on the exposed area, and the electroplating is stopped when the metal post reaches the required height, and the dry film remaining in other positions is removed by using a special stripping solution (generally an alkaline solution), and the seed layer in other unnecessary positions is removed by flash etching process.

[0106] In addition, the method of growing the metal post and forming the redistribution layer in step S106 on the front surface of the first plastic package 300 which exposes the surface of the metal post, and the method of growing the metal post and forming the redistribution layer in the following embodiments are similar, and will not be described in detail.

[0107] Embodiment Two

[0108] Figure 6 is another method flow chart for fan-out packaging of the HEMT 11 and the substrate 13 according to the embodiment two of the present application. In this embodiment, after the HEMT 11 and the substrate 13 are attached on the temporary carrier 200 by using the patching process, the following steps are included:

[0109] Step S1031, the electrode surface of the HEMT 11 and the front surface of the substrate 13 are plated or electroplated with metal. The metal can be copper or silver or gold, and the thickness is 3-10 um.

[0110] Step S1032, the HEMT 11 and the substrate 13 arranged side by side are plastic packaged to obtain a plastic package.

[0111] Step S1033, holes are drilled on the front surface of the plastic package. Specifically, holes are drilled downward at positions corresponding to the electrodes of the HEMT 11 and the metal layer on the front surface of the substrate 13, until the electrode surface of the HEMT 11 and the metal layer on the front surface of the substrate 13 are reached.

[0112] Step S1034, the metal post in the hole and the first redistribution layer 320 on the surface are formed by electroplating metal.

[0113] This embodiment implements fan-out packaging in another way.

[0114] Example 3

[0115] Figure 7 This is a flowchart of a method for fan-out packaging of a parallel HEMT 11 and a substrate 13 to obtain a third semiconductor chip 14 according to Embodiment 3 of the present invention. Figure 8 It corresponds to Figure 7 The diagram shows a partial packaging structure diagram of the fan-out packaging method. In this embodiment, the gate G of HEMT 11 is fanned out to the back of the device and electrically connected to the lead frame 400, thereby reducing the wire bonding between the gate G of HEMT 11 and the front source S of MOSFET 12, thus reducing the parasitic parameters caused by wire bonding.

[0116] Figure 7 Omitted Figure 3 The same steps, following Figure 3 The method shown in step S102, which involves mounting the HEMT 11 and substrate 13 on the temporary carrier 200 and then fan-out packaging the parallel-arranged HEMT 11 and substrate 13 to obtain the third semiconductor chip 14, specifically includes the following steps:

[0117] Step S201: Metal posts are formed on the electrode surface of HEMT 11 and the front metal layer surface of substrate 13. For example... Figure 8 As shown, drain metal pillars 311, gate metal pillars 312, and source metal pillars 313 are formed on the surfaces of the drain D, source S, and gate G of HEMT 11, and substrate metal pillars 314 are formed on the surface of the metal layer of substrate 13.

[0118] Step S202: The current structure is encapsulated to obtain the first encapsulated body 300.

[0119] Step S203: Grind the surface of the first molding compound 300 to expose the surface of the metal pillar, such as... Figure 8 As shown.

[0120] In step S204, a second redistribution layer 330 is formed on the front surface of the first molding compound 300 exposing the metal pillar surface. The second redistribution layer 330 includes a second drain metal layer 331 electrically connected to the drain D of HEMT 11, a second gate metal layer 332 electrically connected to the gate G of HEMT 11, a second source metal layer 333 electrically connected to the source S of HEMT 11, and a substrate metal layer 334 electrically connected to the front metal layer of the substrate 13. See also... Figure 9 , Figure 9This is a top view of the structure corresponding to step S204 in Embodiment 3 of the present invention. The dashed lines in the figure represent metal pillars located under the redistribution layer. In this embodiment, the gate G of HEMT 11 is a fan-out electrode, and the area of ​​the second gate metal layer 332 in the second redistribution layer 330 extends beyond the position of the gate G of HEMT 11 on the body.

[0121] Step S205: In the second redistribution layer 330, a second layer of metal pillars is grown on each metal layer that needs to fan outwards to the front, such as... Figure 8 As shown in the image.

[0122] Step S206: The current structure is encapsulated to obtain the second encapsulated body 301.

[0123] Step S207: Grind the front surface of the second molding compound 301 to expose the surface of the second metal pillar.

[0124] In step S208, a first redistribution layer 320 is formed on the front surface of the second molding compound 301 that exposes the surface of the second metal pillar. The first redistribution layer includes a first drain metal layer 321 and a cascaded metal layer 323 that are electrically connected to the drain D of HEMT 11. The cascaded metal layer 323 is a fan-out metal layer of the source S of HEMT 11 and a fan-out metal layer of the front metal layer of the substrate 13 that are electrically connected in one piece.

[0125] Step S209: Remove the current temporary carrier board 200, and attach the current structure onto the temporary carrier board 200 with the first redistribution layer 320 facing down, at which point the back side of the first molding compound 300 faces up. To facilitate explanation of the HEMT 11 gate G fanning out towards the back side, in... Figure 8 Step S209 illustrates the two gates G of HEMT 11 and their corresponding second gate metal layer 332.

[0126] In step S210, a hole is drilled on the back side of the first molding compound 300 to obtain a first hole 302. Specifically, the hole is drilled at the location where the HEMT11 gate G needs to be brought out, until the second gate metal layer 332 in the second redistribution layer 330 is reached.

[0127] In step S211, a metal pillar and a third wiring layer 340 on the surface are formed in the hole by electroplating, and the temporary carrier 200 is removed to obtain the third semiconductor chip 14.

[0128] The subsequent process and Figure 3 The process shown is the same, that is, the third semiconductor chip 14 is mounted on the lead frame 400, and metal interconnection, molding, cutting and other processes are performed to finally obtain a single semiconductor cascade device, which will not be described in detail here.

[0129] Figure 10is a schematic diagram of the front encapsulation structure of a semiconductor cascade device obtained according to the encapsulation method of Embodiment Three. In the present embodiment, when some electrodes of the HEMT 11, such as the gate G of the HEMT 11 in the present embodiment, need to be led to the back surface, a re-distribution layer can be added in the plastic encapsulation body for transferring the electrodes that need to be led to the back surface, and then a re-distribution layer is constructed on the back surface through drilling, metal plating, and the like, so that the back surface of the third semiconductor chip 14 is the gate G of the HEMT 11. When the third semiconductor chip 14 is attached to the lead frame 400, the gate G of the HEMT 11 is electrically connected to the chip pad of the lead frame 400 in a contact manner. Based on subsequent metal interconnection, the chip pad of the lead frame 400 is electrically connected to the source S of the MOSFET 12, so that the gate G of the HEMT 11 is electrically connected to the source S of the MOSFET 12, and no wire bonding is needed, thereby reducing the parasitic parameters introduced by wire bonding and the like.

[0130] Embodiment Four

[0131] Figure 11 is a flowchart of the encapsulation method of the semiconductor cascade device according to Embodiment Four of the present application, Figure 12 is a schematic diagram of the device encapsulation structure corresponding to part of the encapsulation method shown in Figure 11 . The semiconductor cascade device in the present embodiment is still a Cascode device, and the electrical schematic diagram thereof is shown in Figure 2 . The electrode layout of the HEMT 11 and the MOSFET 12 is the same as that in Embodiment One. The encapsulation method of the Cascode device in the present embodiment includes the following steps:

[0132] Step S401, providing the HEMT 11 and brushing conductive glue on the back surface. As an alternative, a metal layer can be deposited on the back surface of the HEMT 11 and the substrate 13.

[0133] Step S402, attaching the HEMT 11 on the temporary carrier 200 by means of die bonding. In the present embodiment, the drain D, the source S, and the gate G of the HEMT 11 are all located on the front surface of the chip.

[0134] Step S403, forming metal columns on the electrode surfaces of the HEMT 11. As shown in Figure 12 , drain metal columns 311, gate metal columns 312, and source metal columns 313 are formed on the surfaces of the drain D, the source S, and the gate G of the HEMT 11.

[0135] Step S404, the current structure is molded to obtain a first molded body 300, wherein the first molded body 300 exceeds the HEMT 11 by a preset distance in the x direction, and the preset distance is adapted to the mounting width of the MOSFET 12, for example, is equal to or less than the chip width of the MOSFET 12. That is, the first molded body 300 includes two regions, the left region is a first region 303 for molding the HEMT 11, and the right region is a second region 304 filled with molding material.

[0136] Step S405, grinding the surface of the first molded body 300 to expose the surface of the metal column, as shown in Figure 12

[0137] Step S406, forming a first redistribution layer 320 on the front surface of the first molded body 300 exposing the surface of the metal column, the first redistribution layer 320 includes a first drain metal layer 321 electrically connected to the drain D of the HEMT 11, a first gate metal layer 322 electrically connected to the gate G of the HEMT 11, and a first source metal layer electrically connected to the source S of the HEMT 11, wherein the source metal layer extends from the first region 303 to the second region 304 of the first molded body 300 to form a cascade metal layer 323.

[0138] Step S407, removing the temporary carrier 200, and inversely mounting the third semiconductor chip 14 on the temporary carrier 200.

[0139] Step S408, drilling a second hole 305 in the second region 304 of the first molded body 300 to reach the cascade metal layer 323.

[0140] Step S409, electroplating metal in the second hole 305 to form a metal column 315 inside the first molded body 300 connected to the cascade metal layer 323.

[0141] Step S410, removing the temporary carrier 200, and obtaining the complete third semiconductor chip 14.

[0142] From step S403 to step S410, the fan-out packaging of the HEMT 11 is completed.

[0143] Step S411, providing a lead frame 400 on which the third semiconductor chip 14 is mounted. The structure of the lead frame 400 is adapted to the third semiconductor chip 14. In this embodiment, the chip pads for mounting the first region 303 and the second region 304 of the first molded body 300 are separated in the lead frame 400. See Figure 13 , Figure 13 ​Fig. 4 is a schematic diagram of a top structure of a lead frame according to the fourth embodiment of the present application. The lead frame 400 includes a chip pad 401 and pins, the chip pad 401 includes a first pad area 4011 and a second pad area 4012 which are insulated from each other, and when the third semiconductor chip 14 is attached to the chip pad 401, the first area 303 of the third semiconductor chip 14 is soldered to the first pad area 4011 of the chip pad 401, and the second area 304 of the third semiconductor chip 14 is soldered to the second pad area 4012. In this embodiment, four pins are included, and other forms of lead frames can also be used.

[0144] In step S412, the MOSFET 12 is attached to the cascade metal layer 323 on the surface of the third semiconductor chip 14 by a die attach process.

[0145] In step S413, metal interconnection is performed. The first drain metal layer 321 on the surface of the third semiconductor chip 14 is connected to the device drain pin 402 of the lead frame 400 by a bonding wire or a metal strip (such as an aluminum strip or a copper strip), the first gate metal layer 322 on the surface of the third semiconductor chip 14 is electrically connected to the source S of the MOSFET 12, and the source S of the MOSFET 12 is electrically connected to the device source pin 403, the first pad area 4011 and the first gate metal layer 322 of the lead frame 400, respectively. The first pad area 4011 of the lead frame 400 is at the same potential as the device source pin 403 and the KS pin 404. The gate G of the MOSFET 12 is electrically connected to the device gate pin 405. The drain D of the MOSFET 12 is electrically connected to the cascade metal layer 323, and thus to the source S of the HEMT 11, and a schematic diagram of the front surface packaging structure is shown in Fig. 5. Figure 14

[0146] In step S414, the structure after metal interconnection is subjected to plastic packaging, electroplating, laser marking, rib forming and deburring, and thus a single semiconductor cascade device is obtained.

[0147] In this embodiment, no substrate is used, and the MOSFET 12 is still provided with a heat dissipation path independent of the HEMT 11, and thus the semiconductor cascade device achieves good overall heat dissipation effect.

[0148] Embodiment Five

[0149] Figure 15 Fig. 6 is a schematic diagram of a device packaging structure of a packaging step of a semiconductor cascade device according to the fifth embodiment of the present application. The semiconductor cascade device in this embodiment is still a Cascode device, and an electrical schematic diagram thereof is shown in Fig. 7. Figure 2 ​As shown, the electrode layout of the HEMT 11 and the MOSFET 12 is the same as that of Embodiment Four. In the present embodiment, the packaging method of the Cascode device in the present embodiment comprises the following steps:

[0150] In step S501, the HEMT 11 is provided, and conductive glue is brushed on the back surface. As an alternative, a metal layer can be deposited on the back surface of the HEMT 11 and the substrate 13.

[0151] In step S502, the HEMT 11 is attached on a temporary carrier 200 by die bonding. In the present embodiment, the drain D, the source S and the gate G of the HEMT 11 are located on the front surface of the chip.

[0152] In step S503, the HEMT 11 is encapsulated to obtain a first encapsulated body 300, wherein the first encapsulated body 300 exceeds the HEMT 11 by a preset distance in the x direction, and the preset distance is adapted to the attachment width of the MOSFET 12, for example, is equal to or less than the chip width of the MOSFET 12. That is, the first encapsulated body 300 comprises two regions, a first region 303 for encapsulating the HEMT 11 on the left side, and a second region 304 filled with encapsulating material on the right side. The first encapsulated body 300 exceeds the HEMT 11 by a preset distance in the z direction.

[0153] In step S504, holes are drilled in the first region 303 and the second region 304 of the first encapsulated body 300 to obtain first holes 302.

[0154] In step S505, metal is grown in the holes, and a first redistribution layer 320 is formed on the front surface of the first encapsulated body 300, wherein the first redistribution layer 320 comprises a first drain metal layer 321 electrically connected to the drain D of the HEMT 11, a first gate metal layer 322 electrically connected to the gate G of the HEMT 11, and a cascade metal layer 323 integrally electrically connected to the source S of the HEMT 11 and the metal column inside the second region 304.

[0155] In step S506, the temporary carrier 200 is removed, and a complete third semiconductor chip 14 is obtained.

[0156] From step S503 to step S506, the fan-out packaging of the HEMT 11 is completed.

[0157] In step S507, a lead frame 400 is provided, and the third semiconductor chip 14 is attached on the lead frame 400. The structure of the lead frame 400 is adapted to the third semiconductor chip 14. In the present embodiment, the chip pads for attaching the first region 303 and the second region 304 of the first encapsulated body 300 are separated in the lead frame 400. Referring toFigure 13 , Figure 13 Fig. 4 is a schematic diagram of a top view of a lead frame according to an embodiment of the present application. The lead frame 400 includes a die pad 401 and leads 402. The die pad 401 includes a first die pad area 4011 and a second die pad area 4012 which are separated and insulated from each other. When the third semiconductor chip 14 is attached to the die pad 401, the first area 303 of the third semiconductor chip 14 is soldered to the first die pad area 4011 of the die pad 401, and the second area 304 of the third semiconductor chip 14 is soldered to the second die pad area 4012. In this embodiment, four leads are included. Of course, other forms of lead frames can also be used.

[0158] In step S508, the MOSFET 12 is attached to the cascaded metal layer 323 on the surface of the third semiconductor chip 14 by die bonding.

[0159] In step S509, metal interconnection is performed. The first drain metal layer 321 on the surface of the third semiconductor chip 14 is connected to the device drain lead 402 of the lead frame 400 by a bonding wire or a metal strip (such as an aluminum strip or a copper strip). The first gate metal layer 322 on the surface of the third semiconductor chip 14 is connected to the source S of the MOSFET 12, and the source S of the MOSFET 12 is connected to the device source lead 403 of the lead frame. The first die pad area 4011 of the lead frame 400 is at the same potential as the device source lead 403 and the KS lead 404. The gate G of the MOSFET 12 is connected to the device gate lead 405. The drain D of the MOSFET 12 is connected to the cascaded metal layer 323, thereby realizing an electrical connection relationship between the source S of the HEMT 11 and the drain D of the MOSFET 12.

[0160] In step S510, the structure with metal interconnection is subjected to plastic packaging, electroplating, laser marking, cutting and forming, and deburring, thereby obtaining a single semiconductor cascaded device.

[0161] Embodiment Six

[0162] When the semiconductor cascaded device is a Cascode device, a circuit such as a capacitor, a resistor, a diode, or a combination thereof can be embedded in the device. For example, as shown in Fig. 5, a capacitor 501 is embedded in the device. Figure 16 Figure 16 ​is the electrical schematic diagram of the first semiconductor cascode device according to the sixth embodiment of the present application, a capacitor Cx is connected between the drain D and the source S of the MOSFET 12, and the charge balance can be achieved by adding the capacitor Cx between the MOSFET 12 and the HEMT 11, so that the voltage between the drain and the source of the MOSFET 12 and the voltage between the gate and the source of the HEMT 11 can not generate a large overshoot spike in the dynamic switching behavior, thereby avoiding the avalanche breakdown of the MOSFET 12 in the switching process and causing the failure of the cascode device. For this circuit structure, the packaging structure of the present embodiment includes a substrate 13, and the metal layer on the front surface and the back metal layer of the substrate 13 constitute the capacitor Cx. The thickness of the substrate 13 and the type of dielectric are determined according to the parameter requirements. The packaging structure can adopt any one of the packaging structures in the first embodiment to the third embodiment. For example, Figure 17 is the packaging structure of the semiconductor cascode device corresponding to the electrical schematic shown in Figure 16 . The substrate 13 corresponds to the capacitor Cx.

[0163] For another example, referring to Figure 18 , Figure 18 is the electrical schematic diagram of the second semiconductor cascode device according to the sixth embodiment of the present application, a resistor R is connected between the drain D and the source S of the MOSFET 12. By adding the resistor R between the MOSFET 12 and the HEMT 11, the drain balance can be achieved, so that the voltage between the drain and the source of the MOSFET 12 and the voltage between the gate and the source of the HEMT 11 can not generate a large overshoot spike in the static off state, thereby avoiding the avalanche breakdown of the MOSFET 12 in the switching process and causing the failure of the cascode device. The packaging structure of the semiconductor cascode device corresponding to the electrical schematic shown in Figure 18 is also shown in Figure 17 . The substrate 13 corresponds to the resistor R.

[0164] In addition, in the cascode device, a parallel circuit of a diode and a resistor, a parallel circuit of a capacitor and a resistor can also be included between the drain and the source of the MOSFET 12, and the packaging structure of the corresponding cascode device can also be shown in Figure 17 , which will not be described here.

[0165] In addition, the connection mode of the resistor, the capacitor and the diode in the cascode device can also have other forms, referring to Figure 19 , Figure 19is the electrical schematic diagram of the third semiconductor cascade device according to the sixth embodiment of the present application. In this embodiment, two reverse-parallel diodes are included between the gate G and the source S of the MOSFET 12. By adding two reverse-parallel diodes between the gate and the source of the MOSFET 12, the voltage between the gate and the source of the MOSFET 12 is stabilized, the gate and the source of the device are protected from ESD damage, and the ESD protection capability is improved. When the diode circuit is integrated in the substrate 13, according to the circuit connection relationship and the function of the heat dissipation path of the substrate 13, see Figure 20 , Figure 20 is the front surface structure schematic diagram of the substrate 13 according to the sixth embodiment of the present application. Figure 21 is the back surface structure schematic diagram of the substrate 13 according to the sixth embodiment of the present application. The front surface of the substrate 13 includes a first front surface metal layer 131 and a second front surface metal layer 132 which are isolated from each other, and the back surface includes a back surface metal layer 133, see Figure 19 , the two electrical connection points of the diode circuit are the second front surface metal layer 132 and the back surface metal layer 133 of the substrate 13. When packaging the cascode device of this embodiment, the first front surface metal layer 131 and the second front surface metal layer 132 are simultaneously fanned out to the surface of the plastic package, the first front surface metal layer 131 of the substrate 13 is integrated with the fanned-out metal layer of the source S of the HEMT 11 to form a cascade metal layer 323, and the second front surface metal layer 132 of the substrate 13 is fanned out to the surface of the plastic package to form a metal layer 324, see Figure 22 and Figure 23 , Figure 22 is the packaging structure schematic diagram of the semiconductor cascade device corresponding to the electrical schematic shown in Figure 19 Figure 23 is the front surface schematic diagram of the packaging structure of the semiconductor cascade device corresponding to the electrical schematic shown in Figure 19 In this embodiment, the electrode fanning-out packaging method of the HEMT 11 is the same as that of the third embodiment, that is, a re-distribution layer is formed inside the plastic package, and the gate G of the HEMT 11 is fanned out to the back surface. In this embodiment, the diode circuit is integrated in the substrate 13, one electrical connection point of which is located on the back surface of the substrate 13 and is electrically connected with the gate G of the HEMT 11 through the third re-distribution layer 340. The second electrical connection point of the diode circuit is the second front surface metal layer 132 of the substrate 13 and is fanned out to the front surface of the plastic package, that is, the metal layer 324 in Figure 23 When the MOSFET 12 is mounted, the MOSFET 12 is mounted on the cascade metal layer 323 through the patch process. When the metal interconnection is performed, the source S of the MOSFET 12 is electrically connected with the chip pad 401 of the lead frame 400, and the gate G of the MOSFET 12 is electrically connected with the metal layer 324 and the device gate pin 405 of the lead frame 400. ​

[0166] As can be seen from the sixth embodiment, when passive elements or active elements are integrated through the substrate 13, according to the connection relationship with the HEMT 11 and the MOSFET 12, corresponding connection points are formed on the substrate 13, and are led out to the front surface or the back surface of the third semiconductor chip 14 through the fan-out packaging, so that the electrical connection relationship with the HEMT 11 and the MOSFET 12 is realized when the metal interconnection is performed.

[0167] The passive elements and active elements and the circuits composed of the combination thereof in the present embodiment are integrated in the substrate 13, however, can also be integrated in the HEMT 11, when integrated in the HEMT 11, according to the electrical connection relationship, corresponding connection electrodes are formed on the chip surface when needed. For example, for the circuit shown in Figure 16 , no external connection electrode needs to be reserved when the capacitor Cx is formed between the source S and the gate G of the HEMT 11, and similar structures are also shown in Figure 18 . And for the circuit shown in Figure 19 , one electrical connection electrode of the diode circuit is reserved on the front surface of the HEMT 11, which is used for electrical connection with the gate G of the MOSFET 12, thus when the electrodes of the HEMT 11 are fan-out packaged, the connection electrode of the diode circuit and the drain D on the front surface are simultaneously fan-out packaged to the front surface of the third semiconductor chip 14, and when the metal interconnection is performed, the traditional interconnection method is used to realize the electrical connection with the gate G of the MOSFET 12.

[0168] In addition, the substrate 13 and the elements integrated thereon can also be replaced by other chips according to the needs of the cascaded device, such as Figure 24 , Figure 24 is an electrical schematic diagram of the fourth semiconductor cascaded device in the sixth embodiment of the present application. In the present embodiment, another enhancement device, such as the second MOSFET 15, is connected in parallel between the drain and the source of the MOSFET 12. According to the position of the MOSFET chip electrode, when the third semiconductor chip 14 is formed through the fan-out packaging, various packaging structures can be formed, such as Figure 25 , Figure 25 is a packaging structure schematic diagram of the semiconductor cascaded device corresponding to the electrical schematic shown in Figure 24 . The drain D and the gate G of the second MOSFET 15 are distributed on the front surface of the chip, and the source S is distributed on the back surface of the chip. In Figure 25The electrode fan-out packaging structure of the HEMT 11 is the same as that of Embodiment Three. Since the gate G of the second MOSFET 15 has no connection relationship with the other two chips, it does not need to be led out of the third semiconductor chip 14, and the drain D of the second MOSFET 15 is led upward to form a cascade metal layer 323 on the front surface of the third semiconductor chip 14. When the MOSFET 12 is attached to the cascade metal layer 323, it is electrically connected with the drain D on the back of the MOSFET 12. The gate G of the HEMT 11 is fan-out to the back of the third semiconductor chip 14 through the internal redistribution layer, and is electrically connected with the third redistribution layer 340. The source S of the second MOSFET 15 is electrically connected with the third redistribution layer 340 on the back of the third semiconductor chip 14, thereby realizing the electrical connection between the source S of the second MOSFET 15 and the gate G of the HEMT 11. In this embodiment, the second MOSFET 15 not only realizes the electrical connection relationship with the other two chips, but also provides a heat dissipation path for the MOSFET 12, and since it is packaged internally, the distance with the HEMT 11 can be minimized, thereby reducing the overall volume of the semiconductor cascade device.

[0169] Figure 26 is an electrical schematic diagram of the fifth semiconductor cascade device according to Embodiment Six of the present application, Figure 27 is a packaging structure schematic diagram of the semiconductor cascade device corresponding to Figure 26 the electrical schematic shown. In this embodiment, the drain D of the second MOSFET 15 is electrically connected with the drain D of the MOSFET 12 and the source S of the HEMT 11; the gate G of the second MOSFET 15 is electrically connected with the source S of the MOSFET 12 and the gate G of the HEMT 11; and the source S of the second MOSFET 15 has no electrical connection relationship. Correspondingly, referring to Figure 27 , the drain D and the source S of the second MOSFET 15 are distributed on the front surface of the chip, and the gate G is distributed on the back surface of the chip. The drain D of the second MOSFET 15 is led upward to form a cascade metal layer 323 on the front surface of the third semiconductor chip 14. When the MOSFET 12 is attached to the cascade metal layer 323, it is electrically connected with the drain D on the back of the MOSFET 12. The gate G of the HEMT 11 is fan-out to the back of the third semiconductor chip 14 through the internal redistribution layer, and is electrically connected with the third redistribution layer 340. The gate G of the second MOSFET 15 is electrically connected with the third redistribution layer 340 on the back of the third semiconductor chip 14, thereby realizing the electrical connection between the gate G of the second MOSFET 15 and the gate G of the HEMT 11.

[0170] Figure 28 is an electrical schematic diagram of the sixth semiconductor cascade device according to Embodiment Six of the present application,Figure 29 is a packaging structure diagram of the semiconductor cascaded device corresponding to the electrical principle shown in Figure 28 . The drain D of the second MOSFET 15 in the embodiment is electrically connected with the drain D of the MOSFET 12 and the source S of the HEMT 11; the gate G and the source S of the second MOSFET 15 are electrically connected with the source S of the MOSFET 12 and the gate G of the HEMT 11 at the same time. Correspondingly, referring to Figure 29 , the drain D of the second MOSFET 15 is distributed on the front surface of the chip, and the gate G and the source S are distributed on the back surface of the chip. The same fan-out packaging form as that in Embodiment Three is adopted in the embodiment, the drain D of the second MOSFET 15 is faned out to the front surface of the third semiconductor chip 14 and constitutes the cascaded metal layer 323, when the MOSFET 12 is attached on the cascaded metal layer 323, the drain D of the second MOSFET 15 is electrically connected with the drain D on the back surface of the MOSFET 12. The gate G and the source S of the second MOSFET 15 are electrically connected with the third redistribution layer 340 on the back surface of the third semiconductor chip 14, so as to realize the electrical connection between the gate G and the source S of the second MOSFET 15 and the gate G of the HEMT 11.

[0171] Figure 30 is an electrical principle diagram of the seventh semiconductor cascaded device according to Embodiment Six of the present application, Figure 31 is a packaging structure diagram of the semiconductor cascaded device corresponding to the electrical principle shown in Figure 30 . The drain D of the second MOSFET 15 in the embodiment has no electrical connection relationship with other chips, and the gate G and the source S of the second MOSFET 15 are electrically connected with the source S of the MOSFET 12 and the gate G of the HEMT 11 at the same time. Correspondingly, referring to Figure 31 , the drain D of the second MOSFET 15 is distributed on the front surface of the chip, and the gate G and the source S are distributed on the back surface of the chip. In the embodiment, the front surface of the second MOSFET 15 grows a metal layer insulated and isolated from the drain D and is faned out to the front surface of the third semiconductor chip 14 to constitute the cascaded metal layer 323. The gate G and the source S of the second MOSFET 15 are electrically connected with the third redistribution layer 340 on the back surface of the third semiconductor chip 14, so as to realize the electrical connection between the gate G and the source S of the second MOSFET 15 and the gate G of the HEMT 11. Although the drain D of the second MOSFET 15 in the embodiment has no electrical connection relationship, it can still connect the MOSFET 12 through the metal layer on the surface thereof to provide a heat dissipation path for the MOSFET 12.

[0172] Based on the foregoing embodiments, it can be seen that based on the electrode distribution of the second MOSFET 15 and the electrical connection relationship with the HEMT 11 and the MOSFET 12, the fan-out packaging can not only realize the corresponding electrical connection relationship, but also provide a heat dissipation path for the MOSFET 12 in the cascaded device. The other electrical connection relationships of the second MOSFET 15 with the HEMT 11 and the MOSFET 12 and the corresponding packaging structures are not described again.

[0173] Embodiment Seven

[0174] Figure 32 is a schematic diagram of a packaging structure in part of steps in a semiconductor cascaded device packaging method according to an embodiment seven of the present application. In the present embodiment, the cascode device is still taken as an example. The packaging structure of the cascode device in the present embodiment includes a depletion-mode HEMT 11, an enhancement-mode MOSFET 12, and a substrate 13. The three electrodes of the HEMT 11 are located on the front surface of the chip, the drain D of the MOSFET 12 is located on the back surface of the chip, and the gate G and the source S of the MOSFET 12 are located on the front surface of the chip. The substrate 13 in the present embodiment can be the substrate 13 in the foregoing embodiments one to three, or can be the substrate integrated with elements or circuits as in embodiment six or replaced by other chips. The part of steps in the packaging method of the semiconductor cascaded device in the present embodiment are the same as those in embodiment three, that is, the third semiconductor chip 14 is obtained according to the steps S201-S211 in embodiment three, and then the following steps are executed:

[0175] Step S711, the MOSFET 12 is attached on the cascaded metal layer 323 on the surface of the third semiconductor chip 14 through a patch process.

[0176] Step S712, the third layer of metal columns is formed on the first drain metal layer 321 and the electrode surfaces of the source S and the gate G of the MOSFET 12.

[0177] Step S713, the current structure is molded to obtain a third molded body 306.

[0178] Step S714, the front surface of the third molded body 306 is ground to expose the surface of the third layer of metal columns.

[0179] Step S715, a fourth redistribution layer 350 is formed on the front surface of the third molded body 306 exposing the surface of the third layer of metal columns, which includes a fourth drain metal layer 351 electrically connected with the drain D of the HEMT 11, a fourth source metal layer 352 electrically connected with the source S of the MOSFET 12, and a fourth gate metal layer 353 electrically connected with the gate G of the MOSFET 12, wherein each metal layer extends to a position outside the packaging body boundary of the chip of the third semiconductor chip 14 by a proper distance.

[0180] Step S716, remove the current temporary carrier 200, and attach the current structure patch on the temporary carrier 200 with the fourth redistribution layer 350 facing down.

[0181] Step S717, drill holes on the back of the third plastic package 306 to obtain the first holes 302. Specifically, drill holes at the positions where the HEMT 11 gate G needs to be led out until reaching the second gate metal layer 332 in the second redistribution layer 330. Drill holes at the positions corresponding to the fourth drain metal layer 351 electrically connected to the HEMT 11 drain D, the fourth source metal layer 352 electrically connected to the MOSFET 12 source S, and the fourth gate metal layer 353 electrically connected to the MOSFET 12 gate G, respectively, and until reaching the respective metal layers.

[0182] Step S718, form metal pillars in the holes and the surface third redistribution layer 340 by electroplating, wherein the third redistribution layer 340 includes three metal layers separated from each other, including the third drain metal layer 3041 as the drain D of the cascaded device, the third source metal layer 3042 as the source S of the cascaded device, and the third gate metal layer 3043 as the gate G of the cascaded device.

[0183] Step S719, remove the temporary carrier 200, and then perform plastic packaging and subsequent processing such as plating metal layer on the electrode surface, to obtain a single semiconductor cascaded device.

[0184] In this embodiment, metal interconnection is achieved through the metal structure of fan-out packaging, such as redistribution layer and metal pillar, thereby omitting the lead frame.

[0185] Embodiment Eight

[0186] Figure 33is a schematic diagram of a packaging structure of a semiconductor cascode device according to Embodiment Eight of the present application. In this embodiment, the packaging structure of the cascode device still takes the cascode device as an example, and includes the depletion-mode HEMT 11, the enhancement-mode MOSFET 12, and the substrate 13. The three electrodes of the HEMT 11 are located on the front surface of the chip, the drain of the MOSFET 12 is located on the back surface of the chip, and the gate and the source of the MOSFET 12 are located on the front surface of the chip. The packaging method of Embodiment Eight is different from the packaging method of Embodiment Three in step S208, and the other steps are the same, which will not be described here. In step S208 of Embodiment Eight, when the first redistribution layer 320 is formed on the front surface of the second plastic package 301 exposing the surface of the second metal pillar, the first redistribution layer 320 includes the first drain metal layer 321 electrically connected to the drain D of the HEMT 11, the source metal layer 325 electrically connected to the source S of the HEMT 11, and the cascade metal layer 323 integrally and electrically connected to the front metal layer of the substrate 13. When the MOSFET 12 is attached, the drain D on the back surface of the MOSFET 12 is partially attached to the source metal layer 325 electrically connected to the source S of the HEMT 11, and partially attached to the cascade metal layer 323. In a better embodiment, the area of the source metal layer 325 is smaller than the area of the cascade metal layer 323, for example, the area of the cascade metal layer 323 can be more than 3 times the area of the source metal layer 325.

[0187] The separated wiring structure of the source metal layer 325 and the cascade metal layer 323 in this embodiment facilitates testing. That is, after the HEMT 11 and the substrate 13 are packaged and the third semiconductor chip 14 is obtained, the HEMT 11 and the substrate 13 can be independently tested to measure whether their respective functions are good, which is more conducive to testing, especially when the substrate 13 integrates elements or the substrate 13 itself is a chip.

[0188] Secondly, mutual interference between different circuits is avoided. Since the HEMT 11 and the MOSFET 12 form a main power circuit, the working current of the cascode device mainly flows through this main power circuit, and the current flowing through the substrate 13 and the MOSFET 12 is much smaller than the current in the main power circuit. When the source metal layer 325 and the cascade metal layer 323 are separated, the two circuits can be separated, thereby effectively avoiding mutual interference between the circuits.

[0189] In addition, the heat dissipation is better. The heat dissipation path of the MOSFET 12 in the embodiment is shown by the arrows in the figure. When the cascade metal layer 323 is separated from the source metal layer 325 and the area of the cascade metal layer 323 is larger than that of the source metal layer 325, most of the heat of the MOSFET 12 can be dissipated through the cascade metal layer 323 and the substrate 13, avoiding the situation that when the cascade metal layer 323 and the source metal layer 325 are integrated, part of the heat is conducted back to the HEMT 11 through the source metal layer 325.

[0190] The first redistribution layer structure of the embodiment is also applicable to other embodiments, which will not be described here.

[0191] Embodiment Nine

[0192] Figure 34 is a schematic diagram of a packaging structure of a semiconductor cascode device according to the embodiment nine of the present application. In the embodiment, the three electrodes of the MOSFET 12 are distributed on the front surface of the chip, so in the packaging structure of the semiconductor cascode device, when the metal interconnection is performed, the drain D of the MOSFET 12 chip is connected to the cascade metal layer 323 by wire bonding. Since the cascade metal layer 323 is integrally connected with the source S fan-out metal layer of the HEMT 11, the electrical connection between the drain D of the MOSFET 12 and the source S of the HEMT 11 is achieved. The other structures are the same as those of the foregoing embodiments, which will not be described here.

[0193] In addition, since the electrode distribution of the first semiconductor chip in the semiconductor cascode device can have other situations, it can be determined according to the electrode distribution whether the electrode lead-out needs to be transferred by the redistribution layer inside the package. For example, when the gate of the HEMT 11 is distributed on the back surface of the chip, the second redistribution layer 330 is not needed.

[0194] In the foregoing embodiments taking the cascode as an example, the HEMT in depletion mode (D mode) is taken as the first semiconductor chip, and the MOSFET in enhancement mode (E mode) is taken as the second semiconductor chip, and the HEMT is first fan-out packaged. However, it can be known that the first semiconductor chip can also be a MOSFET in D mode, a JFET in D mode or other D mode devices; and the second semiconductor chip can also be an HEMT in E mode or other E mode devices. In addition, the positions of the two types of chips can also be exchanged during packaging, the E mode device is taken as the first semiconductor chip, and the D mode device is taken as the second semiconductor chip, and the E mode device is first fan-out packaged. The packaging method is the same, which will not be described here.

[0195] In the electrical structure of some other semiconductor cascade devices, the semiconductor cascade device can be composed of a semiconductor chip and an integrated chip, such as a HEMT and a driving IC chip, and the semiconductor device of this electrical structure can still be packaged by using the packaging method provided by the application.

[0196] The semiconductor cascade device provided by the application has high integration and good heat dissipation effect, can flexibly match passive devices such as capacitors and resistors or active devices such as diodes in the semiconductor device according to needs, improves the performance of the device, and can also select discrete chips or integrated chips based on the needs of products, so that the flexibility of product design is higher.

[0197] The above examples are only used to illustrate the application and are not intended to limit the application. Those skilled in the art can make various changes and modifications without departing from the scope of the application. Therefore, all equivalent technical solutions shall belong to the scope of the application.

Claims

1. A packaging method of a semiconductor cascade device including a first semiconductor chip and a second semiconductor chip having an electrical connection relationship, the first semiconductor chip including a plurality of first electrodes, the second semiconductor chip including a plurality of second electrodes, characterized by, The packaging method of the semiconductor cascade device comprises: fan-out packaging electrodes of the first semiconductor chip to obtain a third semiconductor chip, and forming a first redistribution layer on a front surface of the third semiconductor chip, wherein the third semiconductor chip comprises a first region and a second region arranged laterally, the first semiconductor chip is packaged in the first region, and the second region comprises a heat dissipation passage; the first redistribution layer comprises a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a part of a front surface of the second region, and the cascade metal layer is connected with the heat dissipation passage in the second region; attaching a second semiconductor chip on the cascade metal layer; metal interconnection of the first electrode fan-out metal layer and second electrodes of the second semiconductor chip to realize an electrical connection relationship between the first semiconductor chip and the second semiconductor chip and obtain a structure comprising a plurality of device electrodes of the semiconductor cascade device; and plastic packaging of the structure realizing the metal interconnection to obtain the semiconductor cascade device.

2. The method of packaging a semiconductor cascade device according to claim 1, wherein, The step of fan-out packaging electrodes of the first semiconductor chip to obtain a third semiconductor chip comprises: first fan-out packaging electrodes of the first semiconductor chip to form a second redistribution layer, wherein the second redistribution layer comprises a first electrode fan-out metal layer leading to a front surface and a first electrode fan-out metal layer leading to a back surface beyond a body of the first semiconductor chip; front surface fan-out packaging of the first electrode fan-out metal layer leading to the front surface and back surface fan-out packaging of the first electrode fan-out metal layer leading to the back surface, forming a first redistribution layer on a front surface of the third semiconductor chip obtained after the packaging is completed, and forming a third redistribution layer on a back surface of the third semiconductor chip; the first redistribution layer comprises the first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least a part of a front surface of the second region; and the third redistribution layer comprises at least the first electrode fan-out metal layer.

3. The method of packaging a semiconductor cascade device according to claim 1 or 2, characterized in that, The step of fan-out packaging electrodes of the first semiconductor chip comprises: parallel arrangement of the first semiconductor chip and a third structure, wherein the third structure comprises a metal layer on a front surface and a back surface thereof; and fan-out packaging electrodes of the first semiconductor chip and the third structure arranged in parallel to obtain a third semiconductor chip, and forming a first redistribution layer on a front surface of the third semiconductor chip; wherein the first semiconductor chip is packaged in a first region of the third semiconductor chip, and the third structure is packaged in a second region and forms the heat dissipation passage; and the first redistribution layer comprises a cascade metal layer covering at least a part of a front surface of the second region, which is obtained by fan-out packaging a front surface metal layer of the third structure.

4. The packaging method of a semiconductor cascade device according to claim 1 or 2, wherein The second region beyond the body of the first semiconductor chip is formed when the first semiconductor chip is fan-out packaged, a metal column is formed in the second region, and the metal column forms the heat dissipation passage.

5. The method of packaging a semiconductor cascade device according to claim 1, wherein In the process of forming the first redistribution layer on the front surface of the third semiconductor chip, the first electrode fan-out metal layer of the first semiconductor chip and the cascade metal layer covering at least part of the front surface of the second region are insulated and separated from each other; or, the first electrode fan-out metal layer of the first semiconductor chip and the cascade metal layer are integrally formed; or, the cascade metal layer extends from the front surface of the second region to part of the front surface of the first region.

6. The method of packaging a semiconductor cascade device according to claim 1, wherein, The step of metal interconnection between the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve the electrical connection relationship between the first semiconductor chip and the second semiconductor chip includes: The third semiconductor chip is mounted on a lead frame, and the lead frame includes device pins as device electrodes; and The metal interconnection is achieved by wire bonding, metal strip bonding or metal sheet bonding.

7. The method of packaging a semiconductor cascade device according to claim 1, wherein, The step of metal interconnection between the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve the electrical connection relationship between the first semiconductor chip and the second semiconductor chip includes: The first electrode fan-out metal layer and the second electrode of the second semiconductor chip are subjected to one or more times of fan-out packaging, and in each time of fan-out packaging, the electrical connection relationship between the first semiconductor chip and the second semiconductor chip is achieved through a redistribution layer.

8. A semiconductor cascade device, characterized by It includes: The third semiconductor chip includes a first region and a second region arranged laterally, the first region encapsulates the first semiconductor chip, and the second region includes a heat dissipation passage; a first redistribution layer is formed on the front surface of the third semiconductor chip, the first redistribution layer includes a first electrode fan-out metal layer of the first semiconductor chip and a cascade metal layer covering at least part of the front surface of the second region, and the cascade metal layer is connected with the heat dissipation passage in the second region; The second semiconductor chip is mounted on the cascade metal layer; A metal interconnection structure is connected with the first electrode fan-out metal layer and the second electrode of the second semiconductor chip to achieve the electrical connection relationship between the first semiconductor chip and the second semiconductor chip and obtain multiple device electrodes of the semiconductor cascade device.

9. A semiconductor cascade device according to claim 8, characterised in that The third semiconductor chip further includes a second redistribution layer, and the second redistribution layer includes a first electrode fan-out metal layer leading to the front surface and a first electrode fan-out metal layer leading to the back surface beyond the body of the first semiconductor chip; correspondingly, the back surface of the third semiconductor chip includes a third redistribution layer, and the third redistribution layer includes at least a first electrode fan-out metal layer.

10. A semiconductor cascade device according to claim 8 or 9, c h a r a c t e r i s e d in that The second region of the third semiconductor chip includes a metal column penetrating through the second region for forming a heat dissipation passage, and the top of the metal column is connected with the cascade metal layer.

11. A semiconductor cascade device according to claim 8 or 9, characterised in that The second region of the third semiconductor chip is internally encapsulated with a third structure, the front surface and the back surface of the third structure respectively comprising a metal layer; correspondingly, part or all of the cascaded metal layers in the first redistribution layer are fan-out metal layers of the front surface metal layer of the third structure, and the third structure and its fan-out metal structure form the heat dissipation channel.

12. A semiconductor cascade device according to claim 11, characterised in that The front surface metal layer and / or the back surface metal layer of the third structure are one or two or more mutually insulated.

13. A semiconductor cascade device according to claim 12, characterised in that The third structure is a substrate, a substrate integrated with an embedded circuit or a fourth semiconductor chip. When the third structure is a substrate integrated with an embedded circuit, the front surface metal layer and / or the back surface metal layer are electrical connection points of the embedded circuit. When the third structure is a fourth semiconductor chip, the front surface metal layer and / or the back surface metal layer are electrodes of the fourth semiconductor chip.

14. A semiconductor cascade device according to claim 13, characterised in that The embedded circuit includes any combination of one or more of a resistor, a capacitor and a diode.

15. A semiconductor cascade device according to claim 8, c h a r a c t e r i z e d b y that The back surface of the second semiconductor chip comprises a second electrode, a first electrode fan-out metal layer of the first semiconductor chip has an electrical connection relationship with the second electrode of the back surface of the second semiconductor chip and is mutually insulated and separated from the cascaded metal layer, and the second electrode of the second semiconductor chip is simultaneously attached to the first electrode fan-out metal layer and the cascaded metal layer having an electrical connection relationship therewith.

16. A semiconductor cascade device according to claim 8, c h a r a c t e r i z e d b y that The back surface of the second semiconductor chip comprises a second electrode, a first electrode fan-out metal layer of the first semiconductor chip has an electrical connection relationship with the second electrode of the back surface of the second semiconductor chip, and the first electrode fan-out metal layer having an electrical connection relationship with the second electrode of the back surface of the second semiconductor chip is integrally connected together with the cascaded metal layer.

17. A semiconductor cascade device according to claim 8, c h a r a c t e r i z e d in that The first semiconductor chip is a depletion-mode semiconductor chip, and the second semiconductor chip is an enhancement-mode semiconductor chip; or, the first semiconductor chip is an enhancement-mode semiconductor chip, and the second semiconductor chip is a depletion-mode semiconductor chip. Alternatively, the second semiconductor chip is a driving IC chip of the first semiconductor chip. Alternatively, the first semiconductor chip is a driving IC chip of the second semiconductor chip.

18. A semiconductor cascade device according to claim 8, characterised in that The second semiconductor chip body and the first semiconductor chip body longitudinally partially overlap.

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