A bidirectional normally-off device and a packaging method thereof

Abstract

The application relates to a bidirectional normally closed device and a packaging method thereof, and the packaging method comprises the following steps: fan-out packaging of electrodes of a bidirectional depletion type semiconductor chip to obtain a first packaging structure part of a plastic package body which exceeds a body of the bidirectional depletion type semiconductor chip, and forming a first redistribution layer on a front surface of the first packaging structure part, the first packaging structure part comprises a first area, a second area and a third area which are horizontally arranged, the bidirectional depletion type semiconductor chip is plastic packaged in the second area, and the first area and the third area respectively comprise heat dissipation channels; the first redistribution layer comprises a first cascade metal layer and a second cascade metal layer; a first enhancement type semiconductor chip is attached on the first cascade metal layer, and a second enhancement type semiconductor chip is attached on the second cascade metal layer. The application reduces the chip area of the bidirectional normally closed device, reduces the parasitic parameter, and improves the overall heat dissipation effect of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a bidirectional normally-off device and a packaging method thereof. BACKGROUND

[0002] The bidirectional normally-off device is composed of a bidirectional depletion-mode transistor (or bidirectional depletion-mode semiconductor chip, referred to as D-BI) 11 and two enhancement-mode transistors (or enhancement-mode semiconductor chips). Figure 1 Figure 1 is an electrical schematic diagram of a bidirectional normally-off device in the prior art. The bidirectional normally-off device includes a D-BI 11 and two enhancement-mode transistors, for example, a bidirectional III-V depletion-mode high electron mobility transistor fabricated on the same substrate. The enhancement-mode transistors are, for example, enhancement-mode metal-oxide semiconductor field-effect transistors (MOSFETs), such as the first MOSFET 12 and the second MOSFET 13 in the figure. The drain D of each MOSFET is connected to one source S in the D-BI 11 to form a cascade structure. The source S of each MOSFET is the first device source S11 and the second device source S12 of the bidirectional normally-off device, respectively, and the gate G of each MOSFET and the two gates G of the D-BI 11 are the first device gate G11, the second device gate G12, the third device gate G13, and the fourth device gate G14 of the bidirectional normally-off device, respectively. Figure 2 Figure 3 Figure 2 is a schematic diagram of a packaging structure of the D-BI 11 in the prior art in the xz plane, Figure 3 is a schematic diagram of a packaging structure of the D-BI 11 in the prior art in the xy plane. The D-BI 11 includes four electrodes. In order to clearly show the four electrodes of the D-BI 11, the present application draws the positions of the four electrodes in a side-by-side manner in Figure 2 , thus Figure 2 is only a schematic diagram and is not an actual layout structure diagram of the device electrodes. The D-BI 11 includes a first gate G1, a second gate G2, a first source S1, and a second source S2, and the electrode pads (PADs) are all distributed on the surface of the front face of the chip. In the present application, the front face refers to the face in the upward direction of the z axis, and the back face refers to the face in the downward direction of the z axis. The MOSFET includes three electrodes, as shown in Figure 4 Figure 4 is a schematic diagram of a packaging structure of the MOSFET in the prior art in the xz plane, Figure 5 ​​​​is a schematic diagram of the structure principle of a packaging structure of a MOSFET in the prior art in the xy plane. Take the first MOSFET 12 as an example. The first MOSFET 12 includes a second chip gate G3, a second chip source S3, and a second chip drain D3. The electrode pads of the second chip gate G3 and the second chip source S3 are located on the surface of the front face of the chip, and the electrode pad of the second chip drain D3 is located on the surface of the back face of the chip.

[0003] Referring to Figure 6 , Figure 6 is an electrical schematic diagram of another bidirectional normally-off device in the prior art. Figure 6 The two gates G of the D-BI11 in are connected with the source S of each MOSFET, respectively. Generally, in the chip packaging structure for this electrical schematic, the bidirectional normally-off device includes four electrodes, i.e., the gate G and the source S of each MOSFET as the first device gate G11, the second device gate G12, the first device source S11, and the second device source S12 of the bidirectional normally-off device.

[0004] The requirements of device packaging usually include miniaturization of the chip, high power, excellent heat dissipation, and low cost, etc. For the bidirectional normally-off device composed of a bidirectional depletion transistor and two enhancement transistors, the common packaging structure is the same as that of a cascode device (such as a Cascode device composed of a MOSFET and a GaN HEMT). The packaging structure of the Cascode device mainly includes two types: one is a horizontal packaging structure, and the other is a laminated packaging structure. In the horizontal packaging structure of the Cascode device, the MOSFET and the GaN HEMT are arranged horizontally, and a DPC (direct plating copper) substrate, a silicon substrate, or a ceramic substrate is needed as the horizontal arrangement medium of the MOSFET (such as the scheme in the patent application with the publication number CN113782511A). Although this method is mature in process, it needs to occupy a large substrate area for horizontal layout, and for the bidirectional normally-off device requiring two enhancement transistors, the size of the packaged chip is larger, which is difficult to meet the miniaturization requirement of the semiconductor chip. In addition, the electrode spacing in the horizontal packaging structure is long, and long-distance wiring will introduce parasitic inductance and capacitance, affecting the high-frequency performance.

[0005] In the laminated packaging structure of the cascode device, the MOSFET is usually stacked above the GaN HEMT active region (as in the scheme in the patent application with publication number CN113826206A), thereby reducing the size of the semiconductor chip and solving the problem of large semiconductor chip size in the horizontal packaging structure. However, the laminated packaging structure has the contradiction between heat management and area optimization. In particular, the heat generated by the MOSFET needs to pass through the GaN to be conducted to the heat dissipation substrate, the heat dissipation path is long, and the thermal resistance is large; the local power density of the MOSFET is high, which is easy to cause the stress concentration of the device, thereby causing the reliability of the device to decrease; in addition, the laminated structure occupies the space of the active region, which limits the layout of passive components such as resistors and capacitors, thereby causing the difficulty in integrating passive devices. SUMMARY

[0006] In view of the technical problems in the prior art, the present application provides a bidirectional normally-off device and a packaging method thereof, which are used to reduce the packaging volume of the device and improve the heat dissipation effect of the device.

[0007] In order to solve the above technical problems, according to one aspect of the present application, a packaging method of a bidirectional normally-off device is provided, the bidirectional normally-off device comprising a first enhancement-type semiconductor chip, a bidirectional depletion-type semiconductor chip and a second enhancement-type semiconductor chip, the bidirectional depletion-type semiconductor chip comprising a plurality of first chip electrodes, the first enhancement-type semiconductor chip comprising a plurality of second chip electrodes, and the second enhancement-type semiconductor chip comprising a plurality of third chip electrodes, the packaging method of the bidirectional normally-off device comprising:

[0008] fan-out packaging of the electrodes of the bidirectional depletion-type semiconductor chip to obtain a first packaging structure part of a plastic package body beyond the body of the bidirectional depletion-type semiconductor chip, and forming a first redistribution layer on the front surface of the first packaging structure part, the first packaging structure part comprising a first area, a second area and a third area arranged horizontally, the bidirectional depletion-type semiconductor chip being plastic packaged in the second area, and the first area and the third area each comprising a heat dissipation channel; the first redistribution layer comprising a first chip electrode fan-out metal layer of the bidirectional depletion-type semiconductor chip, and a first cascade metal layer covering at least the front surface of the first area and a second cascade metal layer covering at least the front surface of the third area.

[0009] attaching the first enhancement-type semiconductor chip on the first cascade metal layer and attaching the second enhancement-type semiconductor chip on the second cascade metal layer to obtain a second packaging structure part; and

[0010] electrode lead-out processing and plastic packaging of the first chip electrode fan-out metal layer, the second chip electrode and the third chip electrode in the second packaging structure part according to the number of electrodes of the bidirectional normally-off device and the corresponding electrical connection relationship to obtain the bidirectional normally-off device.

[0011] Optionally, in the fan-out packaging of the electrode of the bidirectional depletion type semiconductor chip, after obtaining the first packaging structure of the plastic package body exceeding the body of the bidirectional depletion type semiconductor chip, the metal pillars penetrating the first area and the third area are respectively formed in the first area and the third area.

[0012] Correspondingly, in the formation of the first redistribution layer on the front surface of the first packaging structure, the metal pillars in the first area are connected with the first cascade metal layer covering at least the front surface of the first area; the metal pillars in the third area are connected with the second cascade metal layer covering at least the front surface of the third area; the metal pillars in the first area and the third area form the heat dissipation channels in the first area and the third area, respectively.

[0013] Optionally, the step of the fan-out packaging of the electrode of the bidirectional depletion type semiconductor chip to obtain the first packaging structure of the plastic package body exceeding the body of the bidirectional depletion type semiconductor chip includes:

[0014] horizontally arranging the bidirectional depletion type semiconductor chip and two structures, the front surface and the back surface of the structure including metal layers, respectively; and

[0015] fan-out packaging the first chip electrode of the horizontally arranged bidirectional depletion type semiconductor chip and the front surface metal layer and / or the back surface metal layer of the two structures to obtain the first packaging structure, wherein the bidirectional depletion type semiconductor chip and the two structures are respectively and correspondingly plastic packaged in the second area, the first area and the third area of the first packaging structure.

[0016] forming a first redistribution layer on the front surface of the first packaging structure, the first redistribution layer including the fan-out metal layer of the front surface metal layer of the structure in the first area covering at least the front surface of the first area, the fan-out metal layer of the front surface metal layer of the structure in the third area covering at least the front surface of the third area and the fan-out metal layer of the first chip electrode of the bidirectional depletion type semiconductor chip;

[0017] wherein the structure in the first area and its fan-out metal structure form the heat dissipation channel in the first area, the structure in the third area and its fan-out metal structure form the heat dissipation channel in the third area, the fan-out metal layer of the front surface metal layer of the structure in the first area covering at least the front surface of the first area constitutes part or all of the first cascade metal layer, and the fan-out metal layer of the front surface metal layer of the structure in the third area covering at least the front surface of the third area constitutes part or all of the second cascade metal layer.

[0018] Optionally, when the structure includes a front metal layer and a back metal layer, when the first chip electrode and the front metal layer and / or the back metal layer of the two structures of the horizontally arranged bidirectional depletion mode semiconductor chip are fan-out packaged, the front metal layer of the structure is fan-out to the front, and the back metal layer of the structure is fan-out to the back; or the front metal layer and the back metal layer of the structure are respectively fan-out to the front.

[0019] Optionally, when the first redistribution layer is formed on the front surface of the first packaging structure, the first chip electrode fan-out metal layer includes a first source electrode fan-out metal layer, a second source electrode fan-out metal layer, a first gate electrode fan-out metal layer and a second gate electrode fan-out metal layer.

[0020] Optionally, the first source electrode fan-out metal layer is integrally connected with the first cascade metal layer on the front surface of the first region; and / or the second source electrode fan-out metal layer is integrally connected with the second cascade metal layer on the front surface of the third region.

[0021] Optionally, the first source electrode fan-out metal layer is separated from the first cascade metal layer covering at least the front surface of the first region, and correspondingly, when the first enhancement type semiconductor chip is mounted on the first cascade metal layer, the first enhancement type semiconductor chip is simultaneously mounted on the first source electrode fan-out metal layer and the first cascade metal layer; and / or the second source electrode fan-out metal layer is separated from the second cascade metal layer covering at least the front surface of the third region, and correspondingly, when the second enhancement type semiconductor chip is mounted on the second cascade metal layer, the second enhancement type semiconductor chip is simultaneously mounted on the second source electrode fan-out metal layer and the second cascade metal layer.

[0022] Optionally, after the first redistribution layer is formed on the front surface of the first packaging structure, further comprising:

[0023] A lead frame is provided, and the first packaging structure is mounted on the chip pad of the lead frame.

[0024] Correspondingly, the steps of electrode leading-out processing of the first chip electrode fan-out metal layer, the second chip electrode and the third chip electrode in the second packaging structure include: metal interconnection of the first chip electrode fan-out metal layer, the second chip electrode, the third chip electrode and the corresponding device pins on the lead frame.

[0025] Optionally, the step of metal interconnection includes:

[0026] The metal interconnection is performed by wire bonding process through bonding wire, or by ribbon bonding process through metal ribbon, or by solder bridge process through metal sheet.

[0027] Optionally, the step of electrode leading-out processing the first chip electrode fan-out metal layer, the second chip electrode and the third chip electrode in the second packaging structure includes:

[0028] The first chip electrode fan-out metal layer, the second chip electrode of the first enhancement type semiconductor chip and the third chip electrode of the second enhancement type semiconductor chip are subjected to one or more times of fan-out packaging, and the electrical connection relationship is realized through the metal pillars and the redistribution layers formed during the fan-out packaging, and the plurality of metal layers in the surface redistribution layer obtained after the last time of fan-out packaging respectively constitute the device electrodes.

[0029] According to another aspect of the present application, the present application further provides a bidirectional normally-off device, which comprises:

[0030] A first packaging structure includes a first region, a second region and a third region arranged horizontally, a bidirectional depletion type semiconductor chip is encapsulated in the second region, and the first region and the third region respectively include heat dissipation channels; a first redistribution layer is formed on the front surface of the first packaging structure, and the first redistribution layer includes a first cascade metal layer covering at least the front surface of the first region, a first chip electrode fan-out metal layer of the bidirectional depletion type semiconductor chip and a second cascade metal layer covering at least the front surface of the third region;

[0031] A first enhancement type semiconductor chip is attached to the first cascade metal layer, and the first enhancement type semiconductor chip includes a plurality of second chip electrodes;

[0032] A second enhancement type semiconductor chip is attached to the second cascade metal layer, and the second enhancement type semiconductor chip includes a plurality of third chip electrodes; and

[0033] An electrode leading-out structure is connected to the first chip electrode fan-out metal layer, the second chip electrode and the third chip electrode respectively to realize corresponding electrical connection relationship and obtain device electrodes meeting the quantity requirement.

[0034] Optionally, the first region and the third region respectively include metal pillars, the metal pillars in the first region are connected to the first cascade metal layer covering at least the front surface of the first region, and the metal pillars in the third region are connected to the second cascade metal layer covering at least the front surface of the third region.

[0035] Optionally, the first region and the third region respectively include structures, the front surface and the back surface of the structure respectively include metal layers, the front surface metal layer of the structure in the first region is connected to the first cascade metal layer through a fan-out metal structure, and the front surface metal layer of the structure in the third region is connected to the second cascade metal layer through a fan-out metal structure.

[0036] Optionally, the first redistribution layer further comprises a first fan-out metal layer of the back metal layer of each structure body;

[0037] The back of the first packaging structure comprises a second redistribution layer, and the second redistribution layer comprises a second fan-out metal layer connected with the back metal layer of each structure body;

[0038] The first fan-out metal layer of the back metal layer of each structure body in the first redistribution layer is connected with the second fan-out metal layer of the back metal layer of the corresponding structure body in the second redistribution layer through a metal column.

[0039] Optionally, the structure body is a substrate, a substrate integrated with an embedded circuit, or an enhanced semiconductor chip;

[0040] When the structure body is a substrate integrated with an embedded circuit, the front metal layer and / or the back metal layer of the structure body is an electrical connection point of the embedded circuit;

[0041] When the structure body is an enhanced semiconductor chip, the front metal layer and / or the back metal layer of the structure body is an electrode of the enhanced semiconductor chip.

[0042] Optionally, the two structure bodies are located on the same insulating substrate and are separated from each other by insulation.

[0043] Optionally, the first enhanced semiconductor chip body and the bidirectional depletion type semiconductor chip body partially overlap in the longitudinal direction; and / or, the second enhanced semiconductor chip body and the bidirectional depletion type semiconductor chip body partially overlap in the longitudinal direction.

[0044] Optionally, the first chip electrode fan-out metal layer comprises a first source electrode fan-out metal layer, a second source electrode fan-out metal layer, a first gate electrode fan-out metal layer, and a second gate electrode fan-out metal layer.

[0045] The first source electrode fan-out metal layer is integrally connected with the first cascade metal layer on the front surface of the first region; or the second source electrode fan-out metal layer is integrally connected with the second cascade metal layer on the front surface of the third region.

[0046] Alternatively, the first source electrode fan-out metal layer is separated from the first cascade metal layer covering at least the front surface of the first region, and correspondingly, the first enhanced semiconductor chip is simultaneously attached to the first source electrode fan-out metal layer and the first cascade metal layer; and / or, the second source electrode fan-out metal layer is separated from the second cascade metal layer covering at least the front surface of the third region; correspondingly, the second enhanced semiconductor chip is simultaneously attached to the second source electrode fan-out metal layer and the second cascade metal layer.

[0047] Optionally, the electrode lead-out structure comprises a lead frame and a metal interconnection structure, the first packaging structure is attached to the chip pad of the lead frame; and the metal interconnection structure is used to interconnect the first chip electrode fan-out metal layer, the second chip electrode, the third chip electrode and corresponding device pins on the lead frame to realize corresponding electrical connection relationship.

[0048] Optionally, the electrode lead-out structure comprises a metal column and a redistribution layer obtained by one or more times of fan-out packaging of the first chip electrode fan-out metal layer, the second chip electrode and the third chip electrode, wherein a plurality of metal layers in the surface redistribution layer obtained by the last time of fan-out packaging respectively constitute device electrodes.

[0049] Compared with the existing horizontal row packaging structure, the chip area of the bidirectional normally-off device is reduced, and the electrode spacing is reduced, thereby reducing the parasitic parameters; compared with the existing laminated packaging structure, the heat management path is optimized, the heat is avoided to be concentrated, the overall heat dissipation effect of the bidirectional normally-off device is improved, the embedded device is facilitated to be added inside the device, and the integration flexibility of the device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0050] Hereinafter, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, in which:

[0051] Figure 1 is an electrical schematic diagram of a bidirectional normally-off device in the prior art;

[0052] Figure 2 is a structure principle schematic diagram of a packaging structure of D-BI 11 in the prior art in the xz plane;

[0053] Figure 3 is a structure principle schematic diagram of a packaging structure of D-BI 11 in the prior art in the xy plane;

[0054] Figure 4 is a structure principle schematic diagram of a packaging structure of MOSFET in the prior art in the xz plane;

[0055] Figure 5 is a structure principle schematic diagram of a packaging structure of MOSFET in the prior art in the xy plane;

[0056] Figure 6 is an electrical schematic diagram of another bidirectional normally-off device in the prior art;

[0057] Figure 7 is a brief flowchart of a packaging method of a bidirectional normally-off device according to an embodiment of the present application;

[0058] Figure 8This is a flowchart of a packaging method for a bidirectional normally closed device according to Embodiment 1 of the present invention;

[0059] Figure 9 Is with Figure 8 A schematic diagram of the device packaging structure corresponding to some steps of the packaging method shown.

[0060] Figure 10 It is based on Figure 8 A top view of the first molded body 400 obtained by the encapsulation method shown;

[0061] Figure 11 This is a schematic diagram of the top structure of the first encapsulation structure 14 according to Embodiment 1 of the present invention;

[0062] Figure 12 This is a schematic diagram of the top structure of the lead frame 500 according to Embodiment 1 of the present invention;

[0063] Figure 13 This is a schematic diagram of the top structure of the second encapsulation structure 15 according to Embodiment 1 of the present invention;

[0064] Figure 14 This is a schematic diagram of the top structure of the device after metal interconnection according to Embodiment 1 of the present invention;

[0065] Figure 15 This is a schematic diagram of the corresponding structure in the process of realizing metal interconnection through the redistribution layer in the fan-out package according to Embodiment 1 of the present invention.

[0066] Figure 16 According to the first embodiment of the present invention Figure 15 A schematic diagram of the top structure of the device after metal interconnection using the method shown.

[0067] Figure 17 This is a partial structural schematic diagram of the packaging method flow for a bidirectional normally closed device according to Embodiment 2 of the present invention;

[0068] Figure 18 This is a schematic diagram of the structure of mounting the first packaging structure 14 on the lead frame according to Embodiment 2 of the present invention;

[0069] Figure 19 This is a flowchart of the packaging method for a bidirectional normally closed device according to Embodiment 3 of the present invention;

[0070] Figure 20 Is with Figure 19 A schematic diagram of the device packaging structure corresponding to some steps of the packaging method shown.

[0071] Figure 21 This is an electrical schematic diagram of a bidirectional normally closed device according to Embodiment 4 of the present invention;

[0072] Figure 22 Fig. 6 is a partial package structure schematic diagram of a bidirectional normally closed device according to the fourth embodiment of the present application;

[0073] Figure 23 Fig. 7 is another partial package structure schematic diagram of a bidirectional normally closed device according to the fourth embodiment of the present application;

[0074] Figure 24 Fig. 8 is a partial package structure schematic diagram of a bidirectional normally closed device according to the fifth embodiment of the present application;

[0075] Figure 25 Fig. 9 is an electrical schematic diagram of a bidirectional normally closed device according to the sixth embodiment of the present application;

[0076] Figure 26 Fig. 10 is a partial package structure schematic diagram of a bidirectional normally closed device according to the sixth embodiment of the present application;

[0077] Figure 27 Fig. 11 is a structure schematic diagram of arranging D-BI 11, first substrate 61 and second substrate 62 on temporary carrier 200 according to the seventh embodiment of the present application;

[0078] Figure 28 Fig. 12 is a partial package structure schematic diagram of a bidirectional normally closed device according to the eighth embodiment of the present application;

[0079] Figure 29 Fig. 13 is a partial package structure schematic diagram of a bidirectional normally closed device according to the ninth embodiment of the present application;

[0080] Figure 30 Fig. 14 is another partial package structure schematic diagram of a bidirectional normally closed device according to the ninth embodiment of the present application. DETAILED DESCRIPTION

[0081] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0082] In the following detailed description, reference will be made to the accompanying drawings, which form a part of this description, illustrating certain embodiments of the present application. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The embodiments of the present application will be described in sufficient detail to enable those skilled in the art to make and use it, and it is to be understood that other embodiments can be utilized and that structural, logical, and electrical changes can be made without departing from the scope of the present application. Additionally, the term "first", "second", etc. before a name of a technical feature in the description and claims are used only to identify different technical features, and do not indicate sequence of priority.

[0083] Referring to Figure 7 , Figure 7 is a brief flow chart of a packaging method of a bidirectional normally-off device according to an embodiment of the present application. In this embodiment, the bidirectional normally-off device in the present application includes a first enhancement type semiconductor chip, a bidirectional depletion type semiconductor chip and a second enhancement type semiconductor chip. The bidirectional depletion type semiconductor chip includes a plurality of first chip electrodes. The first enhancement type semiconductor chip includes a plurality of second chip electrodes. The second enhancement type semiconductor chip includes a plurality of third chip electrodes. The chips in the present application, such as the first enhancement type semiconductor chip, the bidirectional depletion type semiconductor chip and the second enhancement type semiconductor chip, can be dies in a semiconductor packaging process or packaged chips. The packaging method of the bidirectional normally-off device includes:

[0084] In step S11, the bidirectional depletion type semiconductor chip is fan-out packaged to obtain a first packaging structure. In the fan-out packaging, a first redistribution layer is formed on the front surface of the first packaging structure. The first packaging structure includes a first region, a second region and a third region arranged horizontally. The bidirectional depletion type semiconductor chip is packaged in the second region. The first redistribution layer includes a fan-out metal layer of the first chip electrodes of the bidirectional depletion type semiconductor chip and a first cascade metal layer covering at least a part of the front surface of the first region and a second cascade metal layer covering at least a part of the front surface of the third region. The first region and the third region each include a heat dissipation channel.

[0085] Step S12, mounting the enhancement-mode semiconductor chip. Specifically, the first enhancement-mode semiconductor chip is mounted on the first cascaded metal layer, and the second enhancement-mode semiconductor chip is mounted on the second cascaded metal layer. The part of the body of the first enhancement-mode semiconductor chip and / or the part of the body of the second enhancement-mode semiconductor chip is above the body of the bidirectional depletion-mode semiconductor chip. The body of the first enhancement-mode semiconductor chip and the body of the bidirectional depletion-mode semiconductor chip are partially overlapped or misaligned in the longitudinal direction, and / or the body of the second enhancement-mode semiconductor chip and the body of the bidirectional depletion-mode semiconductor chip are partially overlapped or misaligned in the longitudinal direction, so as to reduce the overall horizontal size of the device.

[0086] Step S13, electrode lead-out processing and plastic packaging. According to the number of electrodes of the bidirectional normally-off device and the corresponding electrical connection relationship, the corresponding electrode lead-out processing mode is adopted to obtain the electrodes of the device. For example, when the number of electrodes of the bidirectional normally-off device is 6 as shown in Figure 1 , and the electrode distribution of the enhancement-mode semiconductor chip is as shown in Figure 4 and Figure 5 , the electrical connection relationship between the drain D of the enhancement-mode semiconductor chip and the source S of the bidirectional normally-off device can be realized when the enhancement-mode semiconductor chip is mounted. At this time, only the metal pillars need to be grown on the electrode surfaces of the source S and the gate G of the enhancement-mode semiconductor chip and the gate G of the bidirectional normally-off device, and the electrode lead-out processing is realized. When the number of electrodes of the bidirectional normally-off device is 4 as shown in Figure 6 , and the electrode distribution of the enhancement-mode semiconductor chip is as shown in Figure 4 and Figure 5 , the electrical connection relationship between the drain D of the enhancement-mode semiconductor chip and the source S of the bidirectional normally-off device is realized when the enhancement-mode semiconductor chip is mounted, and then the source S of each enhancement-mode semiconductor chip and one gate G of the bidirectional normally-off device need to be connected through a metal interconnection structure. The metal interconnection structure is, for example, a wire bonding process for wire bonding, a ribbon bonding process for metal strip connection, or a press welding process for metal sheet connection. Finally, metal pillars are grown on the electrode surfaces of the source S and the gate G of the enhancement-mode semiconductor chip, and the electrode lead-out processing is realized. When the electrode distribution of the enhancement-mode semiconductor chip is other cases, such as three electrodes distributed on the front surface, metal interconnection is first performed to realize the corresponding electrical connection relationship, and then metal pillars are grown to lead out the corresponding electrodes. Finally, plastic packaging is performed, and the surface is polished to expose the electrode surface, and the corresponding bidirectional normally-off device is obtained.

[0087] Wherein, the application obtains a basic semiconductor device by wafer-level fan-out packaging of the bidirectional depletion-mode semiconductor chip, i.e. the first packaging structure in step S11, which reduces the lateral packaging size compared with the traditional lateral packaging scheme; two heat dissipation channels are formed inside the basic semiconductor device during the fan-out packaging and are connected with the cascade metal layer on the front surface. When the enhancement-mode semiconductor chip is attached to the cascade metal layer connected with the heat dissipation channels, not only longitudinal heat dissipation is achieved, but also partial electrical connection between the enhancement-mode semiconductor chip and the bidirectional depletion-mode semiconductor chip can be achieved through the attachment. Since part of the enhancement-mode semiconductor chip can be stacked above the body of the bidirectional depletion-mode semiconductor chip, the bidirectional normally-closed device provided by the application reduces the lateral packaging volume compared with the lateral packaging scheme in the prior art, and is more in line with the development requirement of device miniaturization. Compared with the vertical stacking packaging scheme in the prior art, since the basic semiconductor device is internally provided with the heat dissipation path of the enhancement-mode semiconductor chip, the heat dissipation path of the enhancement-mode semiconductor chip is separated from the heat dissipation path of the bidirectional depletion-mode semiconductor chip, so that the heat dissipation effect of the device is better. Since the fan-out packaging can replace part or all of the bonding wires used to achieve the electrical connection relationship, the parasitic parameters such as parasitic resistance, parasitic inductance and / or parasitic capacitance are reduced. In addition, active elements (such as diodes, enhancement-mode chips) or passive elements (resistors, capacitors, etc.) can be introduced into the bidirectional normally-closed device packaging structure of the application according to the design requirements of the product, thereby improving the integration of the bidirectional normally-closed device.

[0088] The packaging structure and method of the bidirectional normally-closed device in the application will be described in detail below through specific circuit structures and specific packaging structures of chips. It should be noted that the packaging structure diagrams of the bidirectional normally-closed device in the following embodiments of the application are all schematic diagrams, and the positions, shapes and sizes of various structures in the diagrams are for the purpose of explaining the packaging method and principle, and are not used for production. In order to clearly show various necessary structures in the packaging structure in the structural diagram, part of the structure is enlarged or simplified when drawing. For the convenience of description, the bidirectional depletion-mode semiconductor chip in the bidirectional normally-closed device in the following embodiments is taken as an example of D-BI 11, and the principle schematic diagram of the chip packaging structure of D-BI 11 is shown in Figure 2 and Figure 3 The enhancement-mode semiconductor chip is taken as an example of MOSFET, and the principle schematic diagram of the chip packaging structure is shown in Figure 4 and Figure 5 .

[0089] Embodiment one

[0090] Referring to Figure 8 , Figure 8 is a packaging method flowchart of a bidirectional normally-closed device according to embodiment one of the application, wherein,Figure 9 is a schematic diagram of a device packaging structure corresponding to the partial steps of the packaging method shown in Figure 8 The packaging method of the bidirectional normally-off device of the first embodiment of the present application comprises the following steps:

[0091] In step S101, the D-BI 11 is provided and pre-processed. The pre-processing includes brushing conductive glue 101 on the back of the D-BI 11. In addition to brushing conductive glue on the back of the D-BI 11, a metal layer can be pre-plated or plated on the back as an alternative. The purpose of the pre-processing of the back of the D-BI 11 is to facilitate the subsequent chip mounting process, such as facilitating the subsequent mounting of the D-BI 11 on the temporary carrier 200.

[0092] In step S102, metal balls or metal posts are planted on the surface of the electrodes (PAD) on the front. As shown in Figure 9 The first source metal post 311, the first gate metal post 312, the second gate metal post 313, and the second source metal post 314 are respectively formed on the surface of the first source S1, the first gate G1, the second gate G2, and the second source S2 of the D-BI 11.

[0093] In step S103, the D-BI 11 is mounted on the temporary carrier 200 using a patch process.

[0094] In this embodiment, the D-BI 11 is provided in the form of a wafer, so that step S101 can be performed on the wafer, and step S102 can be performed on the dies (a D-BI die, also known as a die) on the wafer, and then the wafer is broken to obtain single D-BI dies with grown metal posts, as shown in Figure 9 the structure diagram corresponding to step S102. However, it can be seen that when a single D-BI die is provided, step S103 needs to be performed first, i.e., the single D-BI die is mounted on the temporary carrier first, and then step S102 is performed.

[0095] In step S104, the current structure is molded to obtain a first molded body 400. Referring to Figure 9 and Figure 10 , Figure 10 is a top view of the first molded body 400 obtained according to the packaging method shown in Figure 8 The first molded body 400 exceeds the body of the D-BI 11, and the area corresponding to the molded D-BI 11 in the first molded body 400 is the second area 402, and the excess areas are the first area 401 and the third area 403, respectively, as shown in Figure 10The dotted line frame in the figure represents the electrode position inside the first plastic package 400 and the body position of the D-BI 11, and the dotted line frame represents three areas, i.e. the first area 401, the second area 402 and the third area 403.

[0096] Step S105, grinding the surface of the first plastic package 400 to expose the surface of the metal column.

[0097] Step S106, forming a first redistribution layer 320 on the front surface of the first plastic package 400 which exposes the surface of the metal column. The first redistribution layer 320 includes the electrode fan-out metal layer of the D-BI 11, which includes the first source electrode fan-out metal layer 321, the first gate electrode fan-out metal layer 322, the second gate electrode fan-out metal layer 323 and the second source electrode fan-out metal layer 324, wherein the first source electrode fan-out metal layer 321 and the second source electrode fan-out metal layer 324 exceed the body of the D-BI 11 and cover part of the front surface of the first area 401 and part of the front surface of the third area 403 respectively.

[0098] Step S107, removing the temporary carrier 200 and pasting the current structure on the temporary carrier 200 with the first redistribution layer 320 facing down, at this time the back of the first plastic package 400 faces up.

[0099] Step S108, drilling holes on the back of the first plastic package 400 corresponding to the positions of the first area and the third area, respectively obtaining the first hole 4011 and the second hole 4032, the first hole 4011 reaches the first source electrode fan-out metal layer 321, and the second hole 4032 reaches the second source electrode fan-out metal layer 324.

[0100] Step S109, forming a metal column in the hole by electroplating and electrically connecting with the metal layer on the front surface. The metal column 315 formed in the first hole 4011 is electrically connected with the first source electrode fan-out metal layer 321, and the metal column 316 formed in the second hole 4032 is electrically connected with the second source electrode fan-out metal layer 324. Thus, an intermediate process chip is realized, which is called the first packaging structure 14 in the present application.

[0101] Referring to Figure 9 and Figure 11 , Figure 11 is a top structure schematic diagram of the first packaging structure 14 according to the first embodiment of the present application. The first packaging structure 14 includes the first area 401, the second area 402 and the third area 403 arranged horizontally (see Figure 10), the second region 402 encapsulates the D-BI 11, the first redistribution layer 320 includes a first chip electrode fan-out metal layer covering the D-BI 11 on the front surface of the second region 402, the first chip electrode fan-out metal layer includes a first gate electrode fan-out metal layer 322, a second gate electrode fan-out metal layer 323, a first source electrode fan-out metal layer 321 and a second source electrode fan-out metal layer 324, each of which is independent, wherein the first source electrode fan-out metal layer 321 extends to the first region 401 and covers at least the front surface of the first region, thereby forming a first cascade metal layer, and the second source electrode fan-out metal layer 324 extends to the third region 403 and covers at least the front surface of the third region, thereby forming a second cascade metal layer. The first cascade metal layer and the metal column 315 inside the first region 401 form a heat dissipation channel, and the second cascade metal layer and the metal column 316 inside the third region 403 form a heat dissipation channel.

[0102] Step S110, remove the temporary carrier 200, and attach the back surface of the first packaging structure 14 to the lead frame 500. The lead frame 500 includes a chip pad 501 and a plurality of pins 502, and the lead frame 500 in this embodiment includes three mutually insulated and isolated chip pads, as shown in Figure 12 Figure 12 is a schematic diagram of the top structure of the lead frame 500 according to Embodiment One of the present application. The lead frame 500 includes a first chip pad 5011, a second chip pad 5012 and a third chip pad 5013, which are mutually insulated and isolated. When the first packaging structure 14 is attached to the chip pads of the lead frame 500, the first region 401, the second region 402 and the third region 403 of the first packaging structure are attached to the first chip pad 5011, the second chip pad 5012 and the third chip pad 5013, respectively. Figure 6 The lead frame 500 in this embodiment includes four pins 502, corresponding to two gates G and two sources S in the schematic diagram. Of course, it can also be six pins, corresponding to four gates G and two sources S in Figure 1

[0103] Step S111, attach the first MOSFET 12 and the second MOSFET 13 to obtain the second packaging structure 15. Referring to Figure 9 and Figure 13 Figure 13 ​​​is a top view of the second packaging structure 15 according to the first embodiment of the present application. Since the drain D of the two MOSFETs in this embodiment is located at the back of the chip, after the first MOSFET 12 is attached to the first source fan-out metal layer 321 (the extended part of which is the first cascade metal layer), the second chip drain D3 of the first MOSFET 12 is electrically connected to the first source S1 of the D-BI 11. After the second MOSFET 13 is attached to the second source fan-out metal layer 324 (the extended part of which is the second cascade metal layer), the third chip drain D4 of the second MOSFET 13 is electrically connected to the second source S2 of the D-BI 11. The structure of attaching the first MOSFET 12 and the second MOSFET 13 is referred to as the second packaging structure 15.

[0104] In step S112, metal interconnection is performed by wire bonding. Referring to Figure 14 , Figure 14 is a top view of the device after metal interconnection according to the first embodiment of the present application. In this embodiment, the second chip source S3 and the first gate fan-out metal layer 322 of the first MOSFET 12 are electrically connected by wire bonding to realize the cascade connection of the first MOSFET 12 and the D-BI 11, and the third chip source S4 and the second gate fan-out metal layer 323 of the second MOSFET 13 are electrically connected by wire bonding to realize the cascade connection of the second MOSFET 13 and the D-BI 11. The second chip source S3, the second chip gate G3 of the first MOSFET 12, the third chip source S4 and the third chip gate G4 of the second MOSFET 13 are respectively electrically connected to the first device source S11, the first device gate G11, the second device source S12 and the second device gate G12 in the pin 502 by wire bonding.

[0105] In another embodiment of metal interconnection, the electrode fan-out metal layer of the D-BI 11, the second chip electrode of the first MOSFET 12 and the third chip electrode of the second MOSFET 13 are fan-out packaged, and metal interconnection is realized by the redistribution layer in the fan-out package. Referring to Figure 15 , Figure 15 is a corresponding structure diagram in the process flow of metal interconnection realized by the redistribution layer in the fan-out package according to the first embodiment of the present application.

[0106] In step S1121, the second packaging structure 15 is molded to obtain the second molded body 410.

[0107] Step S1122, drilling holes on the front side of the second plastic package 410, as shown in the figure, to obtain the first source hole 4101 passing through the second chip source S3 of the first MOSFET 12, the third gate hole 4102 passing through the second chip gate G3, the first gate hole 4103 passing through the first gate fan-out metal layer 322, the second gate hole 4104 passing through the second gate fan-out metal layer 323, the second source hole 4105 passing through the third chip source S4 of the second MOSFET 13, and the fourth gate hole 4106 passing through the third chip gate G4.

[0108] Step S1123, forming metal columns in the holes and the third redistribution layer 340 on the front side of the second plastic package 410 by electroplating. The third redistribution layer 340 includes the fourth gate fan-out metal layer 341, the fifth source fan-out metal layer 342, the sixth source fan-out metal layer 343, and the seventh gate fan-out metal layer 344. The fifth source fan-out metal layer 342 connects the second chip source S3 of the first MOSFET 12 and the first gate fan-out metal layer 322, thereby realizing the electrical connection between the second chip source S3 of the first MOSFET 12 and the first gate G1 of the D-BI 11. The sixth source fan-out metal layer 343 connects the third chip source S4 of the second MOSFET 13 and the second gate fan-out metal layer 323, thereby realizing the electrical connection between the third chip source S4 of the second MOSFET 13 and the second gate G2 of the D-BI 11.

[0109] Step S1124, connecting the four pins of the lead frame by wire bonding. Referring to Figure 16 , Figure 16 is a schematic diagram of the top structure of the device after metal interconnection according to the method shown in Figure 15 Embodiment One of the present application.

[0110] Step S113, plastic packaging the structure after metal interconnection. For example, using a molding process, the plastic packaging material such as epoxy resin is encapsulated around the chip, wire, etc., thereby protecting it. According to the actual scene of production equipment and production line, etc., transfer molding method, compression molding method, etc. can also be used. This step can also include the step of surface grinding the plastic packaging material, thereby exposing the flat electrode surface.

[0111] Step S114, electroplating, laser marking, cutting rib forming, removing flash, then the two-way normally closed device is obtained. Specifically, the electrode surface of the device is plated or electroplated with Ag, Au or sputtered with aluminum or other metals that can be soldered to facilitate electrical connection with other devices when applied. Marking on the surface of the plastic package of the device, for example, using laser or ink to print chip information on the surface of the chip, such as brand, model, batch, production cycle, version, origin, etc. Cutting the overall plastic package to remove the lead frame connecting rib, flash, etc. After the above processing, the two-way normally closed device is obtained.

[0112] By Figure 9 and Figure 13 It can be seen that the MOSFET in the embodiment is attached to the cascading metal layer on the surface of the first packaging structure 14, and the cascading metal layer is integrally arranged with the metal layer of the source S of the D-BI 11, so that the MOSFET can be transversely arranged above the D-BI 11 and the adjacent heat dissipation channel, which not only realizes the electrical connection relationship between the MOSFET back drain D and the D-BI 11 source S, but also provides a heat dissipation path for the MOSFET independent of the D-BI 11. Compared with the heat dissipation accumulation phenomenon caused by the existing technology of stacking the MOSFET on the HEMT active area, the overall heat dissipation of the device in the embodiment is better.

[0113] In the aforementioned step S102, when growing the metal post on the electrode surface of the front surface of the D-BI 11, first, a seed layer is formed on the upper surface of the D-BI 11, such as a layer of copper, which covers the electrode surface of the D-BI 11. Then a dry film is covered on the surface of the seed layer. The dry film is a kind of photosensitive material, which is usually composed of a photosensitive layer, a protective layer and a bottom layer. The photosensitive layer has the characteristic of being sensitive to light and will undergo a chemical reaction (dissolution or solidification) after being irradiated by ultraviolet light, so that a specific pattern can be formed by exposing and developing the dry film. Then, the specified position of the dry film is exposed by programming control of the exposure machine, and in this embodiment, the dry film on the electrode surface area is exposed. Then, using a developing solution (usually a dilute alkaline solution, such as Na2CO3 solution) to remove the exposed dry film to expose the electrode surface where the copper post needs to be grown. Then, electroplating copper or nickel or gold or other metals on the exposed area, and stopping the electroplating when the metal post reaches the required height, and using a special stripping solution (usually an alkaline solution) to remove the dry film remaining at other positions.

[0114] In addition, the method of forming the first redistribution layer 320 on the front surface of the first plastic package 400 in step S106 and the method of growing the metal post and forming the redistribution layer in other steps are similar, and will not be described again for the sake of simplicity.

[0115] Embodiment two

[0116] Referring to Figure 17 , Figure 17 is a part of the structure schematic diagram in the packaging method flow of the bidirectional normally-off device according to the second embodiment of the present application. In the second embodiment, the same method as that in the first embodiment is not described herein again. After obtaining the first packaging structure 14, the second embodiment further generates a second redistribution layer 330 on the back of the first packaging structure 14. The second redistribution layer 330 includes a first back fan-out metal layer 331 connected with the metal column 315 formed in the first hole 4011, a third back fan-out metal layer 333 connected with the D-BI 11 back, and a second back fan-out metal layer 332 connected with the metal column 316 formed in the second hole 4032. When the first packaging structure 14 is attached to the chip pads of the lead frame 500, the first area 401, the second area 402 and the third area 403 of the first packaging structure 14 are respectively attached to the first chip pad 5011, the second chip pad 5012 and the third chip pad 5013 which are insulated from each other through the second redistribution layer 330. As shown in Figure 18 Figure 18 is a structure schematic diagram of attaching the first packaging structure 14 to the lead frame according to the second embodiment of the present application.

[0117] Embodiment Three

[0118] Figure 19 is a flow chart of the packaging method of the bidirectional normally-off device according to the third embodiment of the present application, Figure 20 is a device packaging structure schematic diagram corresponding to part of the steps of the packaging method shown in Figure 19 The packaging method of the bidirectional normally-off device according to the third embodiment of the present application includes the following steps:

[0119] Step S201, providing the D-BI 11, the first substrate 61 and the second substrate 62 and performing pretreatment. The pretreatment includes brushing conductive adhesive 101 on the back of the D-BI 11, the first substrate 61 and the second substrate 62. In the present embodiment, the first substrate 61 and the second substrate 62 can be a direct plating copper (DPC) substrate, a ceramic substrate with a metal layer on the surface, a laminated resin plate, a sapphire substrate or other insulating material substrate, and a silicon substrate with a dielectric layer deposited on the surface with a metal layer on the surface. The upper and lower surfaces of the substrate are electrically insulated.

[0120] ​Step S202, metal balls or metal posts are planted on the electrode surface of the D-BI 11 and the metal layer of the substrate front surface, such as the first source metal post 311, the first gate metal post 312, the second gate metal post 313, and the second source metal post 314, the first substrate metal post 361, and the second substrate metal post 362.

[0121] Step S203, the D-BI 11, the first substrate 61, and the second substrate 62 are arranged horizontally on the temporary carrier 200.

[0122] Step S204, the current structure is molded to obtain the first molded body 400.

[0123] Step S205, the surface of the first molded body 400 is polished to expose the surface of the metal post.

[0124] Step S206, the first redistribution layer 320 is formed on the front surface of the first molded body 400 which exposes the surface of the metal post. At this time, the first packaging structure 14 is obtained. The first redistribution layer 320 includes the first source fan-out metal layer 321 connected to the first source metal post 311 and the first substrate metal post 361, the first gate fan-out metal layer 322 connected to the first gate metal post 312, the second gate fan-out metal layer 323 connected to the second gate metal post 313, and the second source fan-out metal layer 324 connected to the second source metal post 314 and the second substrate metal post 362. The first source fan-out metal layer 321 and the second source fan-out metal layer 324 exceed the body of the D-BI 11, the first source fan-out metal layer 321 covers at least part of the front surface of the first area 401, and the second source fan-out metal layer 324 covers at least part of the front surface of the third area 403.

[0125] Step S207, the temporary carrier 200 is removed, and the back of the first packaging structure 14 is attached to the lead frame 500.

[0126] Step S208, the first MOSFET 12 and the second MOSFET 13 are attached.

[0127] Step S209, metal interconnection is performed by wire bonding process through wire bonding. Among them, the second chip source S3 of the first MOSFET 12 and the first gate fan-out metal layer 322 are electrically connected by wire bonding to realize the cascade connection of the first MOSFET 12 and the D-BI 11, and the third chip source S4 of the second MOSFET 13 and the second gate fan-out metal layer 323 are electrically connected by wire bonding to realize the cascade connection of the second MOSFET 13 and the D-BI 11. The second chip source S3, the second chip gate G3 of the first MOSFET 12, the third chip source S4 and the third chip gate G4 of the second MOSFET 13 are respectively electrically connected with the first device source S11, the first device gate G11, the second device source S12 and the second device gate G12 in the pin 502.

[0128] Step S210, the structure body realizing metal interconnection is plastic encapsulated.

[0129] Step S211, electroplating, laser marking, cutting rib forming, and deburring, then a single bidirectional normally closed device is obtained.

[0130] In the embodiment, the substrates and their fan-out metal structures in the first area 401 and the third area 403 of the first packaging structure 14 respectively constitute the heat dissipation paths of the two MOSFETs, so that the heat dissipation paths of the MOSFETs are independent of the heat dissipation path of the D-BI 11, avoiding the heat superposition when the heat dissipation paths overlap in the traditional overmolding, thus improving the overall heat dissipation effect of the device.

[0131] Embodiment four

[0132] Figure 21 is the electrical schematic diagram of the bidirectional normally closed device according to the embodiment four of the present application. In the embodiment, the bidirectional normally closed device further comprises a first embedded circuit 70 and a second embedded circuit 71. Each embedded circuit can be a resistor, a capacitor, a diode or a combination of these elements, such as a parallel circuit of a resistor and a capacitor, a parallel circuit of a resistor and a diode, a reverse parallel circuit of two diodes, etc.

[0133] Figure 22is a partial packaging structure diagram of a bidirectional normally-off device according to the fourth embodiment of the present application. In this embodiment, the embedded circuit is integrated in the substrate, and the front metal layer and the back metal layer of the substrate are respectively two electrical connection points of the embedded circuit. After the first packaging structure 14 is formed according to the packaging method of the third embodiment, a second redistribution layer 330 is formed on the back of the first packaging structure 14. The second redistribution layer 330 includes a first back fan-out metal layer 331 connected with the back metal layer of the first substrate 61, a third back fan-out metal layer 333 connected with the back of the D-BI 11, and a second back fan-out metal layer 332 connected with the back metal layer of the second substrate 62. Then, a hole is drilled in the first plastic package 400, and the hole is plated with metal. A first front fan-out metal layer 325 and a second front fan-out metal layer 326 are formed on the front of the first plastic package 400, so that the other electrical connection point of the embedded circuit is led out from the back of the substrate to the front of the first packaging structure 14. After the first MOSFET 12 and the second MOSFET 13 are attached, one electrical connection point of the embedded circuit is connected with the MOSFET drain D and one source S of the D-BI 11, and the other electrical connection point of the embedded circuit is connected with the source S of the MOSFET 1 by wire bonding. For example, the first front fan-out metal layer 325 and the second chip source S3 are electrically connected by wire bonding, and the second front fan-out metal layer 326 and the third chip source S4 are electrically connected by wire bonding. The lead frame 500 in this embodiment is shown in Figure 12 . The lead frame 500 includes a first chip pad 5011, a second chip pad 5012, and a third chip pad 5013 which are insulated from each other. Thus, when the first packaging structure 14 is attached to the lead frame 500, the potentials on the back of the first packaging structure 14 are isolated from each other and do not interfere with each other. The other packaging procedures are the same as those in the third embodiment, and are not described herein.

[0134] Referring to Figure 23 , Figure 23 is a partial packaging structure diagram of another bidirectional normally-off device according to the fourth embodiment of the present application. In this embodiment, the back metal layer of the substrate is electrically connected with the chip pads of the lead frame 500 through the second redistribution layer 330, so that the other electrical connection point of the embedded circuit can be electrically connected with the source S of the MOSFET 1 by wire bonding the chip pads and the pins.

[0135] Embodiment Five

[0136] Figure 24 is a partial packaging structure diagram of a bidirectional normally-off device according to the fifth embodiment of the present application. In this embodiment, the electrical schematic diagram of the bidirectional normally-off device is shown in Figure 22 . In this embodiment, a first embedded circuit 70 and a second embedded circuit 71 are integrated in the substrate, and the substrate includes two front metal layers which are respectively two electrical connection points of the embedded circuit.

[0137] When the D-BI 11 and the substrate are respectively forward fan-out to obtain the first redistribution layer 320, the first source fan-out metal layer 321 and the second source fan-out metal layer 324 exceed the body of the D-BI 11, cover part of the surface of the front face of the first area 401 and part of the surface of the front face of the third area 403 respectively, and are respectively integrated with one fan-out metal layer of the substrate, and the first front fan-out metal layer 325 and the second front fan-out metal layer 326 are respectively insulated from other metal layers. The other packaging processes in the embodiment can refer to the foregoing embodiments, and will not be described here.

[0138] The embedded circuit on the substrate in the foregoing embodiment four and embodiment five includes two electrical connection points, however, it can be known that according to the specific circuit structure of the embedded circuit, a plurality of electrical connection points can be included, when a plurality of electrical connection points are included, the plurality of electrical connection points can be distributed on the front surface of the substrate, or can be distributed on the front face and the back face of the substrate at the same time, according to the need of electrical connection, the plurality of electrical connection points are fan-out to the front face of the first packaging structure 14, however, it can be obtained that the plurality of electrical connection points can also be fan-out to the back face of the first packaging structure 14, and electrically connected with part of the chip pads in the lead frame of the back face.

[0139] In another embodiment, Figure 21 The embedded circuit in the foregoing embodiment can also be located in the D-BI 11, and the required resistors, capacitors, diodes and other devices are made inside the D-BI 11. Since the MOSFET only occupies part of the surface of the front face of the D-BI 11, the resistors, capacitors, diode devices as discrete components can be pasted on the surface of the D-BI 11, and the electrical connection points are arranged, and when electrically connected, the electrical connection is realized by wire, metal strip / plate and the like.

[0140] Embodiment six

[0141] Figure 25is an electrical schematic diagram of a bidirectional normally closed device according to the embodiment six of the present application, in which the bidirectional normally closed device further comprises a third MOSFET 81 and a fourth MOSFET 82, and the connection relationship of the third MOSFET 81 and the fourth MOSFET 82 in the bidirectional normally closed device is different according to different application purposes. For example, the embodiment is applied to the diode characteristic, and thus the drain D and the source S of the third MOSFET 81 are connected with the drain D and the source S of the first MOSFET 12 respectively, and the gate of the third MOSFET 81 is connected with the source S of the third MOSFET 81 together, and similarly, the drain D and the source S of the fourth MOSFET 82 are connected with the drain D and the source S of the second MOSFET 13 respectively, and the gate of the fourth MOSFET 82 is connected with the source S of the fourth MOSFET 82 together. For another example, when the voltage resistance characteristic of the MOSFET is applied, the drain D and the source S of the third MOSFET 81 are connected with the drain D and the source S of the first MOSFET 12 respectively, and the gate of the third MOSFET 81 is floating. Alternatively, the gate of the third MOSFET 81 is used as another electrode of the bidirectional normally closed device. When the third MOSFET 81 and the fourth MOSFET 82 are fan-out packaged, the chip electrodes can be fan-out to the front surface and / or the back surface according to the connection relationship with other devices and the distribution of the chip electrodes.

[0142] Figure 26 is a partial packaging structure schematic diagram of the bidirectional normally closed device according to the embodiment six of the present application, in which metal balls or metal posts are planted on the electrode surface of the front surface of the third MOSFET 81, the D-BI 11 and the fourth MOSFET 82, and the patch process is used on the temporary carrier 200.

[0143] After the first plastic package 400 is obtained by plastic packaging the current structure, holes are drilled on the first plastic package 400, and then metal is electroplated in the holes to form the third drain metal post 381 and the fourth drain metal post 382.

[0144] Then, the first redistribution layer 320 is formed on the front surface of the first plastic package 400. Since the gate G and the source S of the third MOSFET 81 are electrically connected together, and the gate G and the source S of the fourth MOSFET 82 are electrically connected together, when the first redistribution layer 320 is formed, the fan-out metal layer of the fifth gate G5 of the third MOSFET 81 and the fan-out metal layer of the fifth source S5 are connected together to form the first front fan-out metal layer 325, and the fan-out metal layer of the sixth gate G6 of the fourth MOSFET 82 and the fan-out metal layer of the sixth source S6 are connected together to form the second front fan-out metal layer 326. The first source fan-out metal layer 321 and the third drain metal pillar 381 are connected together to form the first cascade metal layer, and the second source fan-out metal layer 324 and the fourth drain metal pillar 382 are connected together to form the second cascade metal layer.

[0145] Then, the second redistribution layer 330 is formed on the back surface, and the second redistribution layer 330 includes the first back fan-out metal layer 331 connected with the fifth drain D5 of the third MOSFET 81 and the third drain metal pillar 381, the third back fan-out metal layer 333 connected with the back surface of the D-BI 11, and the second back fan-out metal layer 332 connected with the sixth drain D6 of the fourth MOSFET 82 and the fourth drain metal pillar 382.

[0146] After the temporary carrier is removed, the first packaging structure 14 is obtained, and then the first packaging structure 14 is attached to the lead frame 500, and then the first MOSFET 12 and the second MOSFET 13 are attached, and then metal interconnection is performed by wire bonding to achieve the corresponding electrical connection relationship. For example, the first front fan-out metal layer 325 is connected with the second chip source S3 of the first MOSFET 12 by wire bonding, the second front fan-out metal layer 326 is connected with the third chip source S4 of the second MOSFET 13 by wire bonding, and so on, so as to achieve the Figure 25 electrical connection relationship shown in the figure. Finally, the process of plastic packaging and the like is performed, and since these processes are the same as those of other embodiments, they will not be described here.

[0147] Embodiment Seven

[0148] Figure 27is a schematic diagram of the structure of arranging D-BI 11, first substrate 61 and second substrate 62 on temporary carrier 200 according to embodiment seven of the present application. In this embodiment, first substrate 61 and second substrate 62 are integrated on the same insulating substrate 60, and their respective front metal layers are insulated from each other to ensure the isolation of the potentials thereon. In this structure, the embedded circuit in the foregoing embodiments can also be included. Similarly, third MOSFET 81 and fourth MOSFET 84 in embodiment six can be two enhancement mode transistors formed on the same insulating substrate. Other structures and packaging methods are the same as those in the foregoing embodiments and will not be described here.

[0149] Embodiment eight

[0150] Figure 28 is a schematic diagram of a partial packaging structure of a bidirectional normally-off device according to embodiment eight of the present application. In this embodiment, when forming first redistribution layer 320 on the front surface of first plastic package 400 exposing the surface of metal column, first substrate fan-out metal layer 327 electrically connected to first substrate metal column 361, first source fan-out metal layer 321 electrically connected to first source metal column 311, second source fan-out metal layer 324 electrically connected to second source metal column 314, and second substrate fan-out metal layer 328 electrically connected to second substrate metal column 362 are formed, respectively. In this embodiment, the drains D of the two MOSFETs are located on the back of the chip. Therefore, when mounting first MOSFET 12, part of second chip drain D3 of first MOSFET 12 is mounted on first source fan-out metal layer 321, and the other part is mounted on first substrate fan-out metal layer 327. Similarly, part of third chip drain D4 of second MOSFET 13 is mounted on second source fan-out metal layer 324, and the other part is mounted on second substrate fan-out metal layer 328. In a better embodiment, the mounting area of the MOSFET drain on the source fan-out metal layer is smaller than the mounting area of the substrate fan-out metal layer. For example, the mounting area of the substrate fan-out metal layer can be more than 3 times the mounting area of the source metal layer.

[0151] The wiring structure of separating the substrate fan-out metal layer from the source fan-out metal layer in this embodiment facilitates testing. That is, after packaging D-BI 11 and the two substrates to obtain first packaging structure 14, D-BI 11 and the two substrates can be tested independently to measure whether their respective functions are good. This is especially beneficial for testing when elements are integrated in the substrate or the substrate itself is a chip.

[0152] Secondly, the wiring structure separating the substrate fan-out metal layer and the source fan-out metal layer avoids mutual interference between different circuits. Since the main power circuit is between the D-BI 11 and the MOSFET, the working current of the whole device mainly flows through the main power circuit, and the current between the substrate and the MOSFET is much smaller than the current in the main power circuit. When the substrate fan-out metal layer and the source fan-out metal layer are separated, two independent circuits can be obtained, thereby effectively avoiding mutual interference between circuits.

[0153] In addition, the wiring structure in the embodiment has better heat dissipation. The heat dissipation path of the MOSFET in the embodiment is shown by arrows in the figure. When the substrate fan-out metal layer and the source fan-out metal layer are separated and the mounting area on the substrate fan-out metal layer is larger than that on the source metal layer, most of the heat of the MOSFET can be dissipated through the substrate fan-out metal layer and the substrate, thereby avoiding the partial heat of the MOSFET being conducted back to the D-BI 11 through the source metal layer when the substrate fan-out metal layer and the source fan-out metal layer are integrated.

[0154] The first redistribution layer structure of the embodiment is also applicable to other embodiments, which will not be described here.

[0155] Embodiment Nine

[0156] Figure 29 is a schematic diagram of a partial packaging structure of a bidirectional normally closed device according to the embodiment nine of the application. In the embodiment, the number of electrodes of the bidirectional normally closed device is six, and the electrical schematic diagram is as shown in Figure 1 After the first packaging structure 14 in step S109 according to the packaging method in the embodiment one, the first MOSFET 12 and the second MOSFET 13 are mounted according to step S111 to obtain the second packaging structure 15. Then, metal balls are planted on the surfaces of the electrodes of the first MOSFET 12 and the second MOSFET 13 and the surfaces of the first gate fan-out metal layer 322 and the second gate fan-out metal layer 323 in the first redistribution layer, or metal columns are grown. The method of obtaining the metal columns can be various according to actual requirements. For example, when the sizes of the metal columns are required to be the same, all the metal columns can be obtained at the same time. When the sizes of the metal columns are required to be different, a batch of metal columns with the same size can be grown first, then packaged, drilled, and then electroplated with metal to obtain another batch of metal columns with the same size. In the embodiment, the sizes of the metal columns are required to be the same. After the metal columns are obtained, the plastic package is performed, the surface of the plastic package is polished to expose the surfaces of the metal columns, and the fifth redistribution layer 350 is generated on the surfaces of the metal columns. The fifth redistribution layer 350 includes mutually insulated and separated metal layers connected with the metal columns. After subsequent processing, the metal layers are used as electrode pads of the bidirectional normally closed device. The subsequent processing includes, for example, depositing a passivation layer 90 on the current surface to protect the surface of the device.

[0157] In the embodiment, no lead frame is used, and the device electrodes are obtained through the electrode fan-out process. This method is also applicable to the bidirectional normally closed device with four device electrodes. For example, refer to Figure 30 , Figure 30 is a schematic diagram of a partial packaging structure of another bidirectional normally closed device according to Embodiment Nine of the present application. This embodiment takes the packaging structure in Embodiment One as an example. When no lead frame is used, after the first packaging structure 14 is obtained in step S109, the first MOSFET 12 and the second MOSFET 13 are attached to obtain the second packaging structure 15 according to step S111. Then, metal balls are planted on the surfaces of the electrodes of the first MOSFET 12 and the second MOSFET 13 and the surfaces of the first gate fan-out metal layer 322 and the second gate fan-out metal layer 323 in the first redistribution layer, and metal pillars are grown. After that, the device is molded, the surface of the molded body is polished to expose the surfaces of the metal pillars, and the fifth redistribution layer 350 is formed on the surfaces of the metal pillars. The four metal layers insulated from each other in the fifth redistribution layer 350 are used as the electrode pads of the bidirectional normally closed device.

[0158] The bidirectional normally closed device obtained through the packaging method provided by the present application has high integration and good heat dissipation effect. The device can be flexibly combined with passive devices such as capacitors and resistors or active devices such as diodes according to the needs, thereby improving the performance of the device. In addition, the device can be selected as a discrete chip or an integrated chip based on the needs of a product, so that the product design has high flexibility.

[0159] The above embodiments are only used to illustrate the present application, but not to limit the present application. Those skilled in the art can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should belong to the scope of the present application.

Claims

1. A packaging method for a bidirectional normally closed device, the bidirectional normally closed device comprising a first enhancement-mode semiconductor chip, a bidirectional depletion-mode semiconductor chip, and a second enhancement-mode semiconductor chip, wherein the bidirectional depletion-mode semiconductor chip comprises a plurality of first chip electrodes, the first enhancement-mode semiconductor chip comprises a plurality of second chip electrodes, and the second enhancement-mode semiconductor chip comprises a plurality of third chip electrodes, characterized in that, The packaging method of the bidirectional normally-off device comprises: Fan-out packaging electrodes of a bidirectional depletion-mode semiconductor chip to obtain a first packaging structure beyond a body of the bidirectional depletion-mode semiconductor chip, and forming a first redistribution layer on a front surface of the first packaging structure, the first packaging structure comprising a first region, a second region and a third region arranged horizontally, the bidirectional depletion-mode semiconductor chip being encapsulated in the second region, and the first region and the third region each comprising a heat dissipation channel; respectively mounting a first enhancement-mode semiconductor chip on the first cascade metal layer and a second enhancement-mode semiconductor chip on the second cascade metal layer to obtain a second packaging structure; and According to the number of electrodes required by the bidirectional normally-off device and the corresponding electrical connection relationship, the first chip electrode fan-out metal layer, the second chip electrode and the third chip electrode in the second packaging structure are subjected to electrode lead-out processing and encapsulation to obtain the bidirectional normally-off device.

2. The packaging method of a bidirectional normally-off device according to claim 1, wherein When the electrodes of the bidirectional depletion-mode semiconductor chip are fan-out packaged, after obtaining the first packaging structure beyond the body of the bidirectional depletion-mode semiconductor chip, metal pillars are respectively formed in the first region and the third region, which penetrate the first region and the third region; Correspondingly, when the first redistribution layer is formed on the front surface of the first packaging structure, the metal pillars in the first region are connected to the first cascade metal layer covering at least a part of the front surface of the first region, and the metal pillars in the third region are connected to the second cascade metal layer covering at least a part of the front surface of the third region; the metal pillars in the first region and the metal pillars in the third region form the heat dissipation channels in the first region and the third region, respectively.

3. The packaging method of a bidirectional normally-off device according to claim 1, wherein The step of fan-out packaging electrodes of a bidirectional depletion-mode semiconductor chip to obtain a first packaging structure beyond a body of the bidirectional depletion-mode semiconductor chip comprises: arranging the bidirectional depletion-mode semiconductor chip and two structures horizontally, the front surface and the back surface of the structures each comprising a metal layer; fan-out packaging the first chip electrode of the bidirectional depletion-mode semiconductor chip and the front metal layer and / or the back metal layer of the two structures arranged horizontally to obtain a first packaging structure, wherein the bidirectional depletion-mode semiconductor chip and the two structures are respectively encapsulated in the second region, the first region and the third region of the first packaging structure, respectively; and forming a first redistribution layer on a front surface of the first packaging structure, the first redistribution layer comprising a fan-out metal layer of the front metal layer of the structure in the first region covering at least a part of the front surface of the first region, a fan-out metal layer of the front metal layer of the structure in the third region covering at least a part of the front surface of the third region, and a first chip electrode fan-out metal layer of the bidirectional depletion-mode semiconductor chip; The structure and its fan-out metal structure inside the first area form a heat dissipation channel in the first area, the structure and its fan-out metal structure inside the third area form a heat dissipation channel in the third area, the fan-out metal layer of the front metal layer of the structure inside the first area at least covers part or all of the first cascade metal layer on the front surface of the first area, and the fan-out metal layer of the front metal layer of the structure inside the third area at least covers part or all of the second cascade metal layer on the front surface of the third area.

4. The packaging method of a bidirectional normally-off device according to claim 3, wherein When the structure includes a front metal layer and a back metal layer, the front metal layer of the structure is fanned out to the front surface, and the back metal layer of the structure is fanned out to the back surface during the fan-out packaging of the first chip electrode and the front metal layer and / or the back metal layer of the two structures of the horizontally arranged bidirectional depletion type semiconductor chip. Alternatively, the front metal layer and the back metal layer of the structure are respectively fanned out to the front surface.

5. The packaging method of a bidirectional normally-off device according to any one of claims 1 to 4, wherein When the first redistribution layer is formed on the front surface of the first packaging structure, the first chip electrode fan-out metal layer includes a first source fan-out metal layer, a second source fan-out metal layer, a first gate fan-out metal layer, and a second gate fan-out metal layer. The first source fan-out metal layer at least extends to the front surface of the first area to form the first cascade metal layer, and / or the second source fan-out metal layer at least extends to the front surface of the third area to form the second cascade metal layer. Alternatively, the first source fan-out metal layer is separated from the first cascade metal layer which at least covers the front surface of the first area, and correspondingly, when the first enhancement type semiconductor chip is mounted on the first cascade metal layer, the first enhancement type semiconductor chip is simultaneously mounted on the first source fan-out metal layer and the first cascade metal layer; and / or the second source fan-out metal layer is separated from the second cascade metal layer which at least covers the front surface of the third area, and correspondingly, when the second enhancement type semiconductor chip is mounted on the second cascade metal layer, the second enhancement type semiconductor chip is simultaneously mounted on the second source fan-out metal layer and the second cascade metal layer.

6. The packaging method of a bidirectional normally-off device according to claim 1, wherein After the first redistribution layer is formed on the front surface of the first packaging structure, further comprising: providing a lead frame, and mounting the first packaging structure on the chip pad of the lead frame; correspondingly, the steps of electrode lead-out processing of the first chip electrode fan-out metal layer, the second chip electrode, and the third chip electrode in the second packaging structure include: According to the electrode quantity requirements of the bidirectional normally-off device and the corresponding electrical connection relationship, the first chip electrode fan-out metal layer, the second chip electrode, the third chip electrode, and the corresponding device pins on the lead frame are metal interconnected.

7. The packaging method of a bidirectional normally-off device according to claim 6, wherein The step of metal interconnection includes: using a wire bonding process to perform metal interconnection through bonding wires, or using a ribbon bonding process to perform metal interconnection through metal strips, or using a press welding bridging process to perform metal interconnection through metal sheets.

8. The packaging method of a bidirectional normally-off device according to claim 1, wherein The steps of electrode lead-out processing of the first chip electrode fan-out metal layer, the second chip electrode, and the third chip electrode in the second packaging structure include: The first chip electrode fan-out metal layer, the second chip electrode of the first enhancement type semiconductor chip, and the third chip electrode of the second enhancement type semiconductor chip are subjected to one or more times of fan-out packaging, and the electrical connection relationship is realized through the metal columns and the redistribution layers formed during the fan-out packaging. The plurality of metal layers in the surface redistribution layer obtained after the last time of fan-out packaging respectively constitute device electrodes.

9. A bidirectional normally-off device, characterized by, The bidirectional normally-off device comprises: A first packaging structure comprises a first region, a second region and a third region arranged horizontally, a bidirectional depletion type semiconductor chip is encapsulated in the second region, and the first region and the third region respectively comprise heat dissipation channels; a first redistribution layer is formed on the front surface of the first packaging structure, and the first redistribution layer comprises a first cascade metal layer covering at least a part of the front surface of the first region, a first chip electrode fan-out metal layer of the bidirectional depletion type semiconductor chip, and a second cascade metal layer covering at least a part of the front surface of the third region; A first enhancement type semiconductor chip is attached to the first cascade metal layer, and the first enhancement type semiconductor chip comprises a plurality of second chip electrodes; A second enhancement type semiconductor chip is attached to the second cascade metal layer, and the second enhancement type semiconductor chip comprises a plurality of third chip electrodes; and An electrode lead-out structure is connected to the first chip electrode fan-out metal layer, the second chip electrode and the third chip electrode respectively to realize corresponding electrical connection relationship and obtain device electrodes meeting the quantity requirement.

10. The bidirectional normally-off device according to claim 9, wherein The first region and the third region respectively comprise metal columns, the metal columns in the first region are connected to the first cascade metal layer covering at least a part of the front surface of the first region, and the metal columns in the third region are connected to the second cascade metal layer covering at least a part of the front surface of the third region.

11. The bidirectional normally-off device according to claim 9, wherein The first region and the third region respectively comprise structures, the front surface and the back surface of each structure comprise metal layers, the front surface metal layer of the structure in the first region is connected to the first cascade metal layer through a fan-out metal structure, and the front surface metal layer of the structure in the third region is connected to the second cascade metal layer through a fan-out metal structure.

12. The bidirectional normally-off device according to claim 11, wherein, The first redistribution layer further comprises a first front surface fan-out metal layer of the back surface metal layer of each structure; The back surface of the first packaging structure comprises a second redistribution layer, and the second redistribution layer comprises a first back surface fan-out metal layer connected to the back surface metal layer of each structure; The first front surface fan-out metal layer of the back surface metal layer of each structure in the first redistribution layer is connected to the first back surface fan-out metal layer of the back surface metal layer of the corresponding structure in the second redistribution layer through a metal column.

13. The bidirectional normally-off device according to claim 11, wherein The structure is a substrate, a substrate integrated with an embedded circuit or an enhancement type semiconductor chip; When the structure is a substrate integrated with an embedded circuit, the front surface metal layer and / or the back surface metal layer of the structure are electrical connection points of the embedded circuit; When the structure is an enhancement type semiconductor chip, the front surface metal layer and / or the back surface metal layer of the structure are electrodes of the enhancement type semiconductor chip.

14. The bidirectional normally-off device according to claim 11, wherein, The two structures are located on the same insulating substrate and are separated from each other.

15. The bidirectional normally-off device of claim 9, wherein, The first enhanced semiconductor chip body and the bidirectional depletion semiconductor chip body are partially overlapped in the longitudinal direction; and / or, the second enhanced semiconductor chip body and the bidirectional depletion semiconductor chip body are partially overlapped in the longitudinal direction.

16. The bidirectional normally-off device according to any one of claims 9 to 15, wherein The first chip electrode fan-out metal layer includes a first source electrode fan-out metal layer, a second source electrode fan-out metal layer, a first gate electrode fan-out metal layer, and a second gate electrode fan-out metal layer. The first source electrode fan-out metal layer extends to at least the front surface of the first region to form the first cascade metal layer; or, the second source electrode fan-out metal layer extends to at least the front surface of the third region to form the second cascade metal layer. Alternatively, the first source electrode fan-out metal layer is separated from the first cascade metal layer covering at least the front surface of the first region, and the first enhanced semiconductor chip is simultaneously attached to the first source electrode fan-out metal layer and the first cascade metal layer; and / or, the second source electrode fan-out metal layer is separated from the second cascade metal layer covering at least the front surface of the third region; and the second enhanced semiconductor chip is simultaneously attached to the second source electrode fan-out metal layer and the second cascade metal layer.

17. The bidirectional normally-off device of claim 9, wherein, The electrode lead-out structure includes a lead frame and a metal interconnection structure, the first packaging structure is attached to the chip pad of the lead frame; and the metal interconnection structure is used to interconnect the first chip electrode fan-out metal layer, the second chip electrode, the third chip electrode, and the corresponding device pins on the lead frame to achieve the corresponding electrical connection relationship.

18. The bidirectional normally-off device of claim 9, wherein, The electrode lead-out structure includes the metal pillars and the redistribution layers obtained by one or more times of fan-out packaging of the first chip electrode fan-out metal layer, the second chip electrode, and the third chip electrode, wherein the multiple metal layers in the surface redistribution layer obtained by the last time of fan-out packaging respectively constitute the device electrodes.

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