Optical-mechanical-electrical co-packaging structure

Abstract

The invention discloses an optical-mechanical-electrical co-packaging structure, and relates to the technical field of semiconductors, the optical-mechanical-electrical co-packaging structure comprises an airtight sealing cover and a heightening grounding layer, and the airtight sealing cover and the heightening grounding layer construct a vacuum or airtight environment in a chip core area so as to meet the working requirements of an MEMS-silicon optical chip signal processing unit and break through the limitation of traditional open type packaging. A photoelectric conduction layer at the bottom of the chip forms a conductive and light guide channel through a doping and non-doping or heavy doping technical means to realize photoelectric signal co-integration transmission, an electrical interface and an optical interface are configured in a non-core area of the chip, environment construction and functions are independently processed, the stability of an airtight environment in the core area is ensured, and the reliability of the chip is improved. And the signal transmission efficiency and the integration level are improved, and the problem that the stability of an airtight environment is easily damaged by a traditional tube shell packaging scheme is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and specifically to an optomechanical and electrical co-packaging structure, and more particularly to an optomechanical and electrical co-packaging structure that integrates optical and electrical signal transmission functions and has a high-reliability protection mechanism. Background Art

[0002] Among traditional silicon photonic chip packaging technologies, co-packaging optoelectronics (CPO) effectively reduces packaging costs and power consumption by integrating network switching chips with optical modules, making it widely used in data center optical interconnects. However, for MEMS-silicon photonic chips, their internal signal processing units require a vacuum or airtight environment to ensure proper operation. Existing CPO technology, designed primarily for all-solid-state silicon photonic chips, uses open or semi-open packaging structures that cannot meet this requirement.

[0003] Existing solutions typically rely on external packaging methods such as tubes and shells to provide an airtight seal. Specifically, the tube and shell, formed through multiple precision machining processes, enclose the chip and are then welded or bonded to form a sealed cavity. However, the electrical connection between the tube and shell relies on wire bonds or solder balls, which are susceptible to variations in the thermal expansion coefficient of the materials and pressure (external pressure and vacuum pressure can easily compress the soldered mounting areas of the tube and shell), potentially compromising the seal. Summary of the Invention

[0004] The purpose of the present invention is to solve the problem that the optoelectronic co-packaging solution in the prior art is difficult to ensure the airtight environment stability of the MEMS chip.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: an opto-mechanical-electrical co-packaging structure, including an airtight sealing cover, a raised ground layer, and a photoelectric conductive layer covering the bottom of the chip, the chip being divided into a core area and a non-core area.

[0006] The raised ground layer is disposed between the airtight cover and the photoelectric conductive layer, so that the airtight cover covers the core area to form a vacuum or airtight environment.

[0007] The photoelectric conductive layer has a conductive channel for transmitting electrical signals and a light-guiding channel for transmitting light signals.

[0008] Specifically, the photoelectric conductive layer forms a conductive channel for transmitting electrical signals by being doped, and forms a light-conducting channel for transmitting optical signals by being undoped, thereby realizing co-integrated transmission of photoelectric signals.

[0009] The conductive channels distributed in the non-core area are configured with electrical interfaces, and the light-guiding channels distributed in the non-core area are configured with optical interfaces.

[0010] The photoconductive layer at the bottom of the chip can be understood as extending from the core region to the non-core region or from the non-core region to the core region.

[0011] The beneficial effects of the present invention are:

[0012] The optomechanical co-packaging structure of the present invention constructs a vacuum or airtight environment in the core area of ​​the chip through an airtight cover and a raised ground layer to meet the working requirements of the MEMS-silicon photonic chip signal processing unit, breaking through the limitations of traditional open packaging. On this basis, the photoelectric conductive layer at the bottom of the chip forms conductive and light-conducting channels through doping and undoping or heavy doping techniques to achieve co-integrated transmission of optoelectronic signals, and configures electrical and optical interfaces in the non-core area of ​​the chip to independently process the environment construction and function implementation, which not only ensures the stability of the airtight environment in the core area, but also improves the signal transmission efficiency and integration, avoiding the problem that traditional tube and shell packaging solutions easily destroy the stability of the airtight environment.

[0013] Furthermore, in an embodiment of the present invention, the chip uses a wafer as a substrate, and performs functional partitioning on the photoconductive layer whose top layer of the wafer is made of silicon material. The doped area is doped with high concentration through ion implantation or diffusion process to form an N-type or P-type conductive channel to transmit electrical signals, and the undoped area uses the optical transparency of the silicon layer as a waveguide to transmit optical signals.

[0014] Furthermore, in an embodiment of the present invention, the material of the raised ground layer includes silicon or metal, and has a thickness of 2-20 μm.

[0015] Furthermore, in an embodiment of the present invention, the raised grounding layer and the airtight sealing cover are electrically connected and mechanically fixed through a bonding process, the bottom of the raised grounding layer is electrically connected to the grounding end of the photoconductive layer through a bonding process, and the uneven structure at the bottom of the chip is filled to improve the bonding effect.

[0016] Furthermore, in an embodiment of the present invention, the airtight cover or the raised ground layer evacuates the core area during the bonding process to form a vacuum or airtight environment.

[0017] Furthermore, in an embodiment of the present invention, a signal processing unit is provided in the core area of ​​the chip, the signal processing unit is connected to an external circuit via the electrical interface, and the signal processing unit is connected to an external optical device via the optical interface.

[0018] Furthermore, in an embodiment of the present invention, a stopper layer structure is etched on the surface of the airtight cover, and the stopper layer is used to cooperate with the card slot structure of the chip to protect the signal processing unit in the core area when subjected to external impact.

[0019] Furthermore, in an embodiment of the present invention, the electrical interface includes a TSV through silicon via structure or a FlipChip flip chip bump structure.

[0020] The TSV through silicon via structure passes through the chip to achieve vertical electrical connection with the package base.

[0021] The FlipChip bump structure is arranged at the bottom of the chip and is interconnected with the package base through the bottom filling material.

[0022] Furthermore, in an embodiment of the present invention, the optical interface includes a grating coupling structure or an evanescent wave coupling structure.

[0023] The grating coupling structure is used to couple the optical signal of the chip to an external optical fiber array for transmission.

[0024] The evanescent wave coupling structure realizes optical signal transmission between the chip and an external optical fiber through near-field coupling.

[0025] Furthermore, in an embodiment of the present invention, the optomechanical co-packaging structure also includes a packaging base, the chip is fixed to the packaging base by patch glue, the electrical interface is electrically connected to the conductive circuit of the packaging base, and the optical interface is docked with the optical fiber interface of the packaging base. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the opto-mechanical-electrical co-packaging structure according to an embodiment of the present invention.

[0027] Figure 2 Schematic diagram of another opto-mechanical-electrical co-packaging structure according to an embodiment of the present invention.

[0028] Figure 3 Schematic diagram of an opto-mechanical-electrical co-packaging structure provided with TSV (Through Silicon Via) according to an embodiment of the present invention.

[0029] Figure 4 Schematic diagram of the connection between the flip chip bump structure and the package base according to an embodiment of the present invention.

[0030] Figure 5 Schematic diagram of the connection between another flip chip bump structure and a package base according to an embodiment of the present invention.

[0031] Figure 6 Schematic diagram of the optical fiber and grating coupling structure according to an embodiment of the present invention.

[0032] Figure 7 Schematic diagram of the optical fiber and evanescent wave coupling structure according to an embodiment of the present invention

[0033] 1. Raise the ground layer, 2. Airtight seal, 3. Photoconductive layer, 4. Signal processing unit, 5. Optical fiber, 6. Surface mount adhesive, 7. Package base, 8. Support auxiliary parts, 9. FlipChip bump structure. DETAILED DESCRIPTION

[0034] In order to clearly and completely describe the objectives and technical solutions of the present invention and make the advantages more clearly understood, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are part of the embodiments of the present invention, not all of them, and are only used to explain the embodiments of the present invention, not to limit the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] In the description of the present invention, it should be noted that the terms "center," "middle," "upper," "lower," "left," "right," "inner," "outer," "top," "bottom," "side," "vertical," "horizontal," and the like, indicating positions or location relationships, are based on the positions or location relationships shown in the accompanying drawings and are intended only to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present invention. Furthermore, the terms "one," "first," "second," "third," "fourth," "fifth," and "sixth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0037] For the purposes of simplicity and illustration, the principles of the embodiments are primarily described with reference to examples. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that these embodiments may not be limited to these specific details in practice. In some instances, well-known mechanical seal methods and structures used between the submarine center shaft and the hull are not described in detail to avoid unnecessarily obscuring the understanding of these embodiments. Furthermore, all embodiments may be used in combination with one another.

[0038] Example 1:

[0039] It should be noted that the drawings in the specification are the contents of the specification. The structural shapes, connection relationships, coordination relationships, and positional relationships that can be obtained without any doubt in the drawings in the specification should be understood as the contents of the specification.

[0040] An opto-mechanical-electrical co-packaging structure, such as Figure 1 or Figure 2 As shown, it includes an airtight cover 2, a raised ground layer 1 and a photoconductive layer 3 covering the bottom of the chip. The chip is divided into a core area and a non-core area.

[0041] The elevated grounding layer 1 is disposed between the airtight cover 2 and the photoconductive layer 3 , so that the airtight cover 2 covers the core area to form a vacuum or airtight environment.

[0042] The photoconductive layer has a conductive channel for transmitting electrical signals and a light-guiding channel for transmitting optical signals.

[0043] Specifically, the photoelectric conductive layer 3 forms a conductive channel to transmit electrical signals by doping, and forms a light-guiding channel to transmit optical signals by being undoped or heavily doped, thereby realizing co-integrated transmission of photoelectric signals.

[0044] The conductive channels distributed in the non-core area are configured with electrical interfaces, and the light-guiding channels distributed in the non-core area are configured with optical interfaces.

[0045] The chip is a MEMS-silicon photonic chip, and the photoelectric conductive layer 3 at the bottom of the chip can be understood as extending from the core area to the non-core area or from the non-core area to the core area.

[0046] The advantage of the present invention is that the optomechanical co-packaging structure constructs a vacuum or airtight environment in the core area of ​​the chip through the airtight sealing cover 2 and the raised ground layer 1 to meet the working requirements of the MEMS-silicon photonic chip signal processing unit 4, breaking through the limitations of traditional open packaging. On this basis, the photoelectric conductive layer 3 at the bottom of the chip forms conductive and light-conducting channels through doping and undoping technical means to realize the co-integrated transmission of photoelectric signals, and configures electrical and optical interfaces in the non-core area of ​​the chip to independently process the environment construction and function realization, which not only ensures the stability of the airtight environment in the core area, but also improves the signal transmission efficiency and integration, avoiding the problem that the traditional tube and shell packaging solution easily destroys the stability of the airtight environment.

[0047] The design of the present invention separates the construction of a vacuum / airtight environment from the realization of functions, which not only ensures the stability of the core working environment of the chip, but also improves the signal transmission efficiency and integration (continuing the advantage of traditional CPO technology in integrating network switching chips with optical modules). It also avoids the defect of traditional shell and tube packaging that is easily damaged by external factors. That is, it abandons the shell and tube packaging that is easily disturbed by external factors, avoids the damage to the sealing of the chip caused by thermal expansion and pressure of the material, and provides an innovative and practical solution for MEMS-silicon photonic chip packaging.

[0048] Another advantage of the present invention is that the traditional tube shell is replaced by the airtight cover 2, and the airtight cover 2 is made of the same material as the main body of the chip, forming a vacuum / airtight environment inside the chip without relying on external sealing components.

[0049] Another advantage of the present invention is that it integrates the functions of optical signal transmission, electrical signal interconnection, and mechanical support and protection within a single packaging structure, thereby simplifying the packaging level.

[0050] Specifically, if Figure 1 As shown, the chip uses a wafer as a substrate, and performs functional partitioning on the photoconductive layer 3 of the top layer of the wafer, which is silicon material, that is, a conductive channel pattern is processed on the top layer of the silicon material through existing ultraviolet lithography or electron beam lithography.

[0051] Next, the doped areas are doped with high concentrations through existing phosphorus (n-type) or boron (p-type) ion implantation or diffusion processes to form N-type or P-type conductive channels to transmit electrical signals. The undoped areas utilize the optical transparency of the silicon layer as waveguides to transmit optical signals.

[0052] Among them, no metal is introduced in the doping process, and the doping concentration is controlled at above 10 to the 19th power per cubic centimeter, ensuring that the conductive channel has excellent conductive properties.

[0053] Because silicon doped with phosphorus or boron remains a silicon-based material, it is a semiconductor doping modification rather than metallization. Therefore, the conductive path is pure silicon-based and can operate stably in high-temperature environments close to 1,000°C, meeting the needs of high-temperature applications. Existing metal conductive structures are susceptible to oxidation at high temperatures (e.g., above 200°C), affecting electrical connection reliability.

[0054] For high-temperature scenarios like 800°C, a metal-free doping process can increase the doping concentration in the conductive channel area by 10 to the 19th power per cubic centimeter, enhancing conductivity and high-temperature resistance. Furthermore, the spacing between the light-guiding channels is controlled to 3 microns, further reducing the impact of material diffusion on the signal at high temperatures.

[0055] Specifically, if Figure 1 or Figure 2As shown, the raised ground layer 1 is made of silicon or metal and has a thickness of 2-20μm. This thickness must be at least 10 times greater than the thickness of the thin silicon layer of the photoconductive layer. The core purpose of this design is to improve bonding performance by increasing the thickness of the raised ground layer: during the bonding process, ensuring reliable electrical connection between the raised ground layer and the ground terminal of the photoconductive layer is crucial. From a microscopic perspective, the surface of a material is not absolutely flat, but rather contains tiny bumps and depressions. When the ground layer is thin, these microscopic irregularities are more difficult to completely eliminate using existing processes, resulting in a smaller effective contact area with the ground terminal of the photoconductive layer. Increasing the ground layer thickness allows greater flexibility in adjusting and optimizing the surface morphology during deposition and polishing processes, making it easier to achieve high-precision flatness control. Furthermore, the thicker ground layer, due to its inherent rigidity, can more evenly transfer the bonding pressure to the contact surface with the ground terminal of the photoconductive layer, enabling bonding even in areas where surface irregularities would otherwise prevent close contact. This significantly increases the effective contact area between the two, increasing the number of paths for electron transmission, naturally reducing contact resistance, and improving the reliability of the electrical connection. At the same time, the thick layer of material has high rigidity and can serve as a support layer to buffer stress during the bonding process, reducing the risk of cracking in thin silicon due to concentrated pressure.

[0056] The present invention raises the thickness of the ground layer 1 not only to improve the reliability of the electrical connection, but also to provide airtight protection.

[0057] In the existing technology, raising the thickness of the ground layer in the bonding process is a common choice (such as 2-20μm and 10 times greater than the thin silicon layer). The technical issues have always focused on optimizing the electrical connection performance. For example, by thickening the ground layer to improve the surface flatness to increase the effective contact area with the photoconductive layer and reduce the contact resistance. The relevant process optimization and verification are all carried out around electrical indicators (such as contact resistance test and conductive reliability). Currently, the existing patents, papers and other documents in the semiconductor field have not explicitly mentioned the relationship between this thickness design and airtight protection.

[0058] Airtightness protection is an independent technical branch in existing technologies. Its conventional solutions rely on materials such as glass passivation layer, metal sealing ring, organic polymer packaging or interface chemical reactions, and have no direct correlation with the thickness of the ground layer.

[0059] For the first time, the present invention expands the thickness of the grounding layer from a single electrical parameter to a design element with mechanical buffering function. It achieves stress buffering through the physical increase of thickness and reduces airtightness defects such as interface microcracks. This technical effect cannot be directly deduced through the thickness selection of existing electrical connection processes.

[0060] Specifically, the raised ground layer 1 and the airtight sealing cover 2 are electrically connected and mechanically fixed through an existing bonding process (silicon-silicon bonding or metal-silicon bonding).

[0061] The bottom of the raised ground layer 1 is electrically connected to the ground end of the photoconductive layer 3 through a bonding process, and the uneven structure at the bottom of the chip is filled to improve the bonding effect.

[0062] The thickness (2-20μm) and material (silicon / metal) selection of the raised ground layer 1 can balance mechanical strength and electrical performance: the spacing between conductive channels is set to no less than 2um to avoid signal crosstalk and short circuit risks. Silicon material is suitable for high-precision bonding scenarios, and metal material is suitable for high conductivity and mechanical support requirements. The electrical interface and optical interface are located in the non-core area to avoid damage to the sealing structure of the core area, while facilitating external connection. The entire solution is implemented through existing standardized micro-nano processing technology (bonding), which is compatible with existing semiconductor production lines to ensure the feasibility of large-scale manufacturing.

[0063] The spacing between conductive channels is set to no less than 2um to avoid signal crosstalk and short circuit risks.

[0064] Specifically, during the bonding process of the airtight cover or the raised ground layer 1 , the core area is evacuated by existing vacuum equipment to form a vacuum or airtight environment.

[0065] Specifically, a signal processing unit 4 is provided in the core area of ​​the chip. The signal processing unit 4 is connected to an external circuit via an electrical interface, and the signal processing unit 4 is connected to an external optical device via an optical interface.

[0066] More specifically, if Figure 1 As shown, a stop layer structure is etched on the surface of the airtight cover 2, and the stop layer is used to cooperate with the card slot structure of the chip to protect the signal processing unit 4 in the core area when subjected to external impact.

[0067] Specifically, if Figure 3 、 Figure 4 、 Figure 5 As shown, the electrical interface includes a TSV through silicon via structure or a FlipChip bump structure 9 .

[0068] like Figure 3 As shown, TSV through holes are prepared by deep silicon etching (DRIE), and an insulating layer (such as silicon dioxide) is deposited on the inner wall and then filled with copper or polysilicon to form a vertical conductive channel; Figure 4 or Figure 5 As shown, the FlipChip bump structure 9 is fabricated on the bottom surface of the chip by electroplating process. The FlipChip bump structure 9 supports the array optical fiber 5 with a supporting auxiliary member 8.

[0069] The TSV through silicon via structure penetrates the chip to achieve vertical electrical connection with the package base 7 .

[0070] The FlipChip bump structure 9 is arranged at the bottom of the chip and is interconnected with the package base 7 through the bottom filling material.

[0071] Specifically, the optical interface includes a grating coupling structure or an evanescent wave coupling structure.

[0072] like Figure 6 As shown, the grating coupling structure is used to couple the optical signal of the chip to the external array optical fiber 5 for transmission.

[0073] like Figure 7 As shown, the evanescent wave coupling structure realizes optical signal transmission between the chip and another external array optical fiber 5 through near-field coupling.

[0074] Specifically, the optomechanical and electrical co-packaging structure also includes a packaging base 7, the chip is fixed to the packaging base 7 by patch glue 6, the electrical interface is electrically connected to the conductive circuit of the packaging base 7, and the optical interface is docked with the optical fiber 5 interface of the packaging base 7.

[0075] Example 2:

[0076] An opto-mechanical-electrical co-packaging structure differs from Example 1 in that the photoconductive layer 3 forms a light-guiding channel by heavy doping to transmit optical signals. The remaining features and technical effects of this embodiment are the same as those of Example 1.

[0077] The chip is a MEMS-silicon photonic chip, and the light-guiding channel area is heavily doped: a large amount of specific impurity atoms (such as gold, silver nanoparticles, semiconductor nanocrystals, etc.) are doped into the material of the light-guiding channel to change the optical properties of the light-guiding layer, such as the refractive index, so as to better guide the light, improve the light-guiding efficiency, and allow the light to propagate and distribute more effectively in the light-guiding layer.

[0078] Compared with the traditional semiconductor doping technology that only uses doping to make PN junctions or electrical contacts, this solution innovatively uses heavy doping as a conductor for light-guiding channels.

[0079] Example 3:

[0080] A method for preparing an opto-mechanical-electrical co-packaging structure, based on the opto-mechanical-electrical co-packaging structure of the above-mentioned embodiment 1 and embodiment 2, is as follows:

[0081] A suitable wafer is selected as the chip substrate, and the conductive channel pattern is precisely machined into the top silicon photoconductive layer 3 using ultraviolet lithography or electron beam lithography. Phosphorus or boron ion implantation or diffusion processes are then used to highly dope the corresponding areas. The doping concentration is strictly controlled to ensure good conductivity. The light-guiding channel area is then heavily doped as needed, with specific impurity atoms added to optimize light-guiding performance.

[0082] The prepared chip is then assembled with the airtight cover 2 and the raised grounding layer 1. First, the raised grounding layer 1 is connected to the airtight cover 2 through a silicon-silicon bonding or metal-silicon bonding process. During the bonding process, the core area of ​​the chip is vacuumed using a vacuum pump to form a vacuum or airtight environment. Then, the bottom of the raised grounding layer 1 is connected to the ground end of the photoconductive layer 3 at the bottom of the chip through a bonding process, and the spacing between the conductive channels is controlled to be no less than 2um. Next, an electrical interface (such as a TSV silicon through-hole structure or a FlipChip flip chip bump structure 9) and an optical interface (such as a grating coupling structure or an evanescent wave coupling structure) are prepared at the bottom of the chip.

[0083] Finally, the assembled chip is fixed on the package base 7 by patch glue 6 to ensure that the electrical interface is accurately electrically connected to the conductive circuit of the package base 7 and the optical interface is accurately docked with the interface of the optical fiber 5.

[0084] Although the above describes the illustrative specific embodiments of the present invention so that those skilled in the art can understand the present invention, the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, all inventions and creations based on the concepts of the present invention are protected.

Claims

1. An opto-mechanical-electrical co-packaging structure, characterized in that: It includes an airtight seal, a raised ground layer, and a photoconductive layer covering the bottom of the chip, and the chip is divided into a core area and a non-core area; The raised ground layer is disposed between the airtight cover and the photoconductive layer, so that the airtight cover covers the core area to form a vacuum or airtight environment; The photoelectric conductive layer has a conductive channel for transmitting electrical signals and a light-guiding channel for transmitting optical signals; The conductive channels distributed in the non-core area are configured with electrical interfaces, and the light-guiding channels distributed in the non-core area are configured with optical interfaces.

2. The opto-mechanical-electrical co-packaging structure according to claim 1, characterized in that: The chip uses a wafer as a substrate, and functionally partitions the photoelectric conductive layer whose top layer is made of silicon material. The doped areas are doped with high concentrations through ion implantation or diffusion processes to form N-type or P-type conductive channels to transmit electrical signals, and the undoped areas use the optical transparency of the silicon layer as waveguides to transmit optical signals.

3. The opto-mechanical-electrical co-packaging structure according to claim 1, characterized in that: The material of the raised ground layer includes silicon or metal, and the thickness is not less than 2 μm.

4. The opto-mechanical-electrical co-packaging structure according to claim 1, characterized in that: The raised grounding layer and the airtight sealing cover are electrically connected and mechanically fixed through a bonding process. The bottom of the raised grounding layer is electrically connected to the ground end of the photoconductive layer through a bonding process, and the uneven structure at the bottom of the chip is filled to improve the bonding effect.

5. The opto-mechanical-electrical co-packaging structure according to claim 1, characterized in that: The airtight cover or the raised ground layer evacuates the core area during the bonding process to form a vacuum or airtight environment.

6. The opto-mechanical-electrical co-packaging structure according to claim 1, characterized in that: A signal processing unit is provided in the core area of ​​the chip. The signal processing unit is connected to an external circuit via the electrical interface, and the signal processing unit is connected to an external optical device via the optical interface.

7. The opto-mechanical-electrical co-packaging structure according to claim 6, characterized in that: A stopper layer structure is etched on the surface of the airtight sealing cover, and the stopper layer is used to cooperate with the card slot structure of the chip to protect the signal processing unit in the core area when subjected to external impact.

8. The opto-mechanical-electrical co-packaging structure according to claim 1, characterized in that: The electrical interface includes a TSV through silicon via structure or a FlipChip flip chip bump structure; The TSV through silicon via structure penetrates the chip to achieve vertical electrical connection with the package base; The FlipChip bump structure is arranged at the bottom of the chip and is interconnected with the package base through the bottom filling material.

9. The opto-mechanical-electrical co-packaging structure according to claim 1, characterized in that: The optical interface includes a grating coupling structure or an evanescent wave coupling structure; The grating coupling structure is used to couple the optical signal of the chip to an external optical fiber array for transmission; The evanescent wave coupling structure realizes optical signal transmission between the chip and an external optical fiber through near-field coupling.

10. The opto-mechanical-electrical co-packaging structure according to claim 1, characterized in that: The optomechanical and electrical co-packaging structure further includes a packaging base, the chip is fixed to the packaging base by patch adhesive, the electrical interface is electrically connected to the conductive circuit of the packaging base, and the optical interface is docked with the optical fiber interface of the packaging base.

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