Capacitor structure

Abstract

The invention provides a capacitor structure. The capacitor structure comprises a substrate, a plurality of capacitor units, a first unit plate, a plurality of second unit plates and a plurality of through holes, a plurality of capacitor units are formed on the substrate. The first cell plate is disposed between the substrate and the plurality of capacitor cells, and the plurality of second cell plates are disposed on the plurality of capacitor cells, respectively. The through hole is arranged on the second unit plate. The plurality of capacitor units are connected in series.

Description

Technical Field

[0001] The present invention relates to a capacitor structure. Background Art

[0002] Integrated circuits (ICs) often include a variety of passive components. Capacitors are one of the more common passive components and are widely used in ICs for various applications.

[0003] In typical silicon capacitors, the capacitor's connecting conductors have high resistance, necessitating the reduction of their parasitic resistance. To improve this, the number of connecting conductors must be increased. However, increasing the number of connecting conductors increases the device area, hindering area design. Summary of the Invention

[0004] According to an embodiment of the present invention, a capacitor structure includes a substrate, a plurality of capacitor cells, a first unit plate, a plurality of second unit plates, and a plurality of through holes. The plurality of capacitor cells are formed on the substrate. The first unit plate is disposed between the substrate and the plurality of capacitor cells, and the plurality of second unit plates are respectively disposed on the plurality of capacitor cells. The plurality of through holes are disposed on the plurality of second unit plates.

[0005] According to another embodiment of the present invention, a capacitor structure includes at least one bottom cell plate, a plurality of top cell plates, a first through-hole, and a second through-hole. The capacitor cell is disposed on at least one bottom cell plate. The top cell plate is disposed on the capacitor cell. The first through-hole is disposed on one of the top cell plates, and the second through-hole is disposed on the other top cell plate, wherein the capacitor cell is connected in series between the first through-hole and the second through-hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] To provide a further understanding of the present invention, the accompanying drawings are included and incorporated in and constitute a part of this specification, and illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0007] Figure 1A A cross-sectional view of a capacitor structure according to some embodiments of the present invention is shown.

[0008] Figure 1B Shown Figure 1A Top view of the capacitor structure.

[0009] Figure 2 Cross-sectional views of capacitor structures according to other embodiments of the present invention are shown.

[0010] Figure 3 Cross-sectional views of capacitor structures according to other embodiments of the present invention are shown.

[0011] Figure 4A is a schematic cross-sectional view of a capacitor structure of an experimental example.

[0012] Figure 4B is a schematic cross-sectional view of a capacitor structure of a comparative example.

[0013] Figure 5 is a graph showing the voltage changes over time for the experimental example and the comparative example.

[0014] Figure 6 It is the impedance curve graph of the experimental example and the comparative example. DETAILED DESCRIPTION

[0015] The following invention provides many different embodiments or examples for realizing different features of the subject matter of the invention provided. Specific examples of components and arrangements are described below to simplify the invention. The above specific examples are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above a second feature may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various examples. The purpose of the above repetition is for simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for convenience, spatially relative terms such as "below" and "above" may be used herein to describe the relationship of one element or feature to another, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] As used herein, terms such as "first" and "second" describe various elements, components, regions, layers and / or sections, which should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Terms such as "first" and "second" when used herein do not imply an order or ranking unless the context clearly indicates.

[0018] Figure 1A A cross-sectional view of a capacitor structure according to some embodiments of the present invention is shown. Figure 1B Shown Figure 1A FIG. 1 is a top view of a capacitor structure with some parts omitted for clarity.

[0019] Please refer to Figure 1A The capacitor structure includes a substrate 100, a plurality of capacitor cells 102a-102b, a first unit plate 104, a plurality of second unit plates 106a-106b, and a plurality of through-holes 108a-108b. The substrate 100 is, for example, a semiconductor wafer or an insulator substrate. In some embodiments, the substrate 100 is composed of silicon or glass. The capacitor cells 102a-102b are formed above the substrate 100. In one embodiment, the capacitor cells 102a-102b can be formed in the substrate 100. In another embodiment, the capacitor cells 102a-102b can be formed above the substrate 100. For example, the capacitor cells 102a-102b can be formed in a middle-end-of-line (MEOL) region on the substrate 100. The first unit plate 104 is disposed between the substrate 100 and the plurality of capacitor cells 102a-102b. In some embodiments, the first unit plate 104 is configured as a single plate for connecting multiple capacitor units 102a-102b. The second unit plates 106a-106b are respectively disposed on the capacitor units 102a-102b. For example, the second unit plate 106a is disposed on the capacitor unit 102a, and the second unit plate 106b is disposed on the capacitor unit 102b. The through-holes 108a-108b are disposed on the second unit plates 106a-106b. In some embodiments, the second unit plate 106a includes a first surface 1061 and a second surface 1062, the first surface 1061 being attached to the capacitor unit 102a, and the second surface 1062 being attached to the through-hole 108a. In some embodiments, the second unit plate 106b includes a first surface 1061 and a second surface 1062, the first surface 1061 being attached to the capacitor unit 102b, and the second surface 1062 being attached to the through-hole 108b. For example, through-hole 108a can be directly attached to second unit board 106a, and through-hole 108b can be directly attached to second unit board 106b. In the present invention, the larger the second unit board 106a or 106b, the greater the number of through-holes 108a or 108b. Therefore, the resistance caused by through-holes 108a or 108b can be reduced. If the area of ​​second unit board 106a is larger than the area of ​​second unit board 106b, the number of through-holes 108a can be greater than the number of through-holes 108b. In addition, if the area of ​​second unit boards 106a-106b increases, the number of through-holes 108a-108b thereon can be adjusted (for example, increased to two or more through-holes) or remain unchanged.

[0020] For clarity, Figure 1B Only the through holes 108a-108b and the second unit plates 106a-106b are shown. Figure 1BWhen viewed from the top of the capacitor structure, each of the through-holes 108a-108b overlaps with each of the second unit plates 106a-106b. The top of the capacitor structure is the topmost portion of the capacitor structure in a top view, such as the through-holes 108a-108b. In some embodiments, the second unit plate 106a has a first surface area, a predetermined number of through-holes 108a (e.g., four through-holes 108a or more) are disposed on the second unit plate 106a and occupy a second surface area of ​​the second unit plate 106a, and the second surface area is at least half of the first surface area. Similarly, the second unit plate 106b has a first surface area, a predetermined number of through-holes 108b (e.g., four through-holes 108b or more) are disposed on the second unit plate 106b and occupy a second surface area of ​​the second unit plate 106b, and the second surface area is at least half of the first surface area. In other words, the vias 108a and 108b may be arranged to maximize their coverage on the second unit board 106a and the second unit board 106b, respectively, so as to minimize the resistance caused by the vias 108a and 108b.

[0021] Please refer to Figure 1A , first unit plate 104 is electrically connected to capacitor cells 102a-102b. In some embodiments, each of capacitor cells 102a-102b comprises a metal-insulator-metal (MIM) capacitor. In some embodiments, each of capacitor cells 102a-102b comprises a stacked capacitor. In some embodiments, each of capacitor cells 102a-102b comprises a crown-type capacitor.

[0022] In some embodiments, each capacitor cell 102a-102b includes a first conductor film (not shown) connected to the first cell plate 104, a second conductor film (not shown) connected to the second cell plates 106a-106b, and a dielectric layer (not shown) located between the first and second conductor films. In some embodiments, the capacitor cells 102a-102b may have a complex configuration to increase capacitance density.

[0023] exist Figure 1AIn the embodiment, the capacitor structure further includes a plurality of metal layers 110a-110b above the plurality of second unit plates 106a-106b, and each metal layer 110a-110b is connected to each second unit plate 106a-106b through a through-hole 108a-108b. For example, metal layer 110a is connected to second unit plate 106a through through-hole 108a, and metal layer 110b is connected to second unit plate 106b through through-hole 108b. In some embodiments, the plurality of metal layers 110a-110b are disposed over the plurality of through-holes 108a-108b, wherein through-hole 108a includes a first end 1081 attached to second unit plate 106a and a second end 1082 attached to metal layer 110a. Via 108b also includes a first end 1081 and a second end 1082. First end 1081 is attached to second unit plate 106b, and second end 1082 is attached to metal layer 110b. In some embodiments, metal layers 110a-110b are layers of a back-end-of-the-line (BEOL) structure, such as a first metal layer (M1). In some embodiments, metal layers 110a-110b are layers of a middle-of-the-line (MOL) structure, formed before the BEOL structure. In some embodiments, metal layers 110a-110b are copper layers or tungsten layers.

[0024] Compared to existing structures that connect capacitor cells in series by connecting vias to the bottom cell plate, the vias 108a-108b connected to the second cell plates 106a-106b are shorter than the vias connected to the bottom cell plate (e.g., the first cell plate 104). Therefore, the resistance of the vias 108a-108b connected to the second cell plates 106a-106b can be lower than the resistance of the vias 108a-108b connected to the bottom cell plate. Furthermore, the height h1 of the vias 108a-108b connected to the second cell plates 106a-106b is significantly shorter than the height of the vias 108a-108b connected to the bottom cell plate. For example, the height h1 of one of the plurality of vias 108a-108b is less than half the height h2 measured from the plurality of metal layers 110a-110b to the first cell plate 104. Therefore, the capacitor structure of the present invention has a better equivalent series resistance (ESR), thereby reducing resistance capacitance (RC) to improve operating speed. For example, in some embodiments, the RC of the capacitor structure can be less than 250ps.

[0025] In addition, compared with the above-mentioned conventional structure, the current loop in the capacitor structure of the present invention is smaller than that of the conventional structure, and thus the capacitor structure of the present invention has better equivalent series inductance (ESL).

[0026] Furthermore, since the through holes 108a-108b are formed on the top plates of the capacitor units 102a-102b, i.e., overlap with the capacitor units 102a-102b, this means that when the capacitor structure of the present invention and the existing capacitor structure have the same bottom plate area, the capacitor structure of the present invention can have a larger capacitance value than the existing capacitor structure. Alternatively, when the capacitor structure of the present invention is designed to have the same capacitance as the existing capacitor structure, the capacitor structure of the present invention can have a smaller area than the existing capacitor structure.

[0027] Figure 2 A cross-sectional view of a capacitor structure according to some embodiments of the present invention is shown.

[0028] Please refer to Figure 2 Capacitor structure 200 includes several bottom cell plates 202a-202b, several capacitor cells 204, several top cell plates 206a, 206b, and 206c, a first through-hole 208, and a second through-hole 210. Capacitor cells 204 are connected in series between first through-hole 208 and second through-hole 210. Capacitor cells 204 are disposed on bottom cell plates 202a-202b, while top cell plates 206a, 206b, and 206c are disposed on capacitor cells 204. In some embodiments, a substrate (not shown) is disposed beneath capacitor structure 200 to accommodate capacitor structure 200. In some embodiments, the substrate is composed of silicon or glass. Top cell plate 206a is connected to one of capacitor cells 204, bottom cell plate 202a is connected to two of capacitor cells 204, top cell plate 206b is connected to two of capacitor cells 204, bottom cell plate 202b is connected to two of capacitor cells 204, and top cell plate 206c is connected to one of capacitor cells 204. Each of the bottom cell plate 202 a , the top cell plate 206 b , and the bottom cell plate 202 b connects two capacitor cells 204 , and they do not connect the same two capacitor cells 204 .

[0029] like Figure 2As shown, first through-holes 208 are provided on top cell plate 206a, and second through-holes 210 are provided on top cell plate 206c. In some embodiments, top cell plate 206a includes a first surface 2061 and a second surface 2062, with first surface 2061 attached to one of capacitor cells 204 and second surface 2062 attached to first through-holes 208. In some embodiments, top cell plate 206c also includes a first surface 2061 and a second surface 2062, with first surface 2061 attached to one of capacitor cells 204 and second surface 2062 attached to second through-holes 210. Top cell plate 206a, connected to first through-holes 208, is located at one end of capacitor structure 200, while top cell plate 206c, connected to second through-holes 210, is located at the other end of capacitor structure 200. In some embodiments, when viewed from the top of capacitor structure 200, first through-holes 208 overlap with top cell plate 206a, and second through-holes 210 overlap with top cell plate 206c. In the present invention, the larger the top cell plate 206a or 206c, the more first through-holes 208 or second through-holes 210 there are. Therefore, the resistance caused by the first through-holes 208 or second through-holes 210 can be reduced. Furthermore, if the area of ​​the top cell plate 206a is larger than that of the top cell plate 206c, the number of first through-holes 208 can be greater than the number of second through-holes 210. Alternatively, if the areas of the top cell plates 206a and 206c increase, the number of first through-holes 208 and second through-holes 210 must also increase. In some embodiments, the bottom cell plates 202a-202b are electrically connected to the capacitor cells 204. In some embodiments, each capacitor cell 204 comprises a metal-insulator-metal (MIM) capacitor. In some embodiments, each capacitor cell 204 comprises a stacked capacitor. In some embodiments, each capacitor cell 204 comprises a crown-type capacitor.

[0030] Please refer again Figure 2Capacitor structure 200 further includes a first metal layer 212 disposed over top cell plate 206a and connected to first via 208, and a second metal layer 214 disposed over top cell plate 206c and connected to second via 210. In some embodiments, a height h3 of first via 208 is less than half of a height h4 measured from first metal layer 212 to bottom cell plate 202a, and a height h5 of second via 210 is less than half of a height h6 measured from second metal layer 214 to bottom cell plate 202b. In some embodiments, first metal layer 212 is disposed over first via 208, second metal layer 214 is disposed over second via 210, and first via 208 includes a first end 2081 and a second end 2082, wherein first end 2081 is attached to top cell plate 206a, and second end 2082 is attached to first metal layer 212. Second via 210 includes a first end 2101 and a second end 2102, wherein first end 2101 is attached to top unit plate 206c and second end 2102 is attached to second metal layer 214. In some embodiments, first metal layer 212 and second metal layer 214 are layers of a BEOL structure, such as a first metal layer (M1). In some embodiments, first metal layer 212 and second metal layer 214 are layers of a MEOL structure formed before the BEOL structure.

[0031] Figure 3 shows a cross-sectional view of a capacitor structure according to some embodiments of the present invention, wherein Figure 1A The symbols in the accompanying drawings represent identical or similar components.

[0032] Figure 1A The capacitor structure and Figure 3 The difference between the capacitor structures lies in the construction of the capacitor unit. Figure 3The capacitor cells 300 are disposed between the first unit plate 104 and the second unit plates 106a-106b, and each capacitor cell 300 includes a first conductor film 304, a second conductor film 306, and a dielectric layer 302 interposed therebetween. The first conductor film 304 is connected to the first unit plate 104. The second conductor film 306 is connected to the corresponding second unit plate of the second unit plates 106a-106b. The dielectric layer 302 is formed between the first conductor film 304 and the second conductor film 306. In some embodiments, the capacitor cells 300 can have a complex configuration to increase capacitance density; for example, the first conductor film 304 can have a crown-like, tubular, or wavy 3D shape, and the second conductor film 306 can also have a crown-like, tubular, or wavy 3D shape that complements the first conductor film 304. Furthermore, in a top view, the 3D shapes of the first conductor film 304 and the second conductor film 306 can be arranged in a rectangular array, or in some embodiments, a hexagonal array. In some embodiments, the first conductive film 304 and the second conductive film 306 are metal films, and the dielectric layer 302 is composed of a high-k dielectric material. For example, the high-k dielectric material may include at least one of La (lanthanum), Ha (hafnium), and Zr (zirconium) oxides, or other suitable materials.

[0033] In summary, the capacitor structure of the present invention has a better ESR and a larger capacitance value, thereby having a lower RC, and is therefore suitable for use in high-power density devices for high-performance computing (HPC) or AI applications. Therefore, the capacitor structure can be integrated with wafer-on-wafer (WoW) products or interposers. In addition, because the capacitor structure of the present invention can simultaneously have a high capacitance density and a smaller area, it can also adapt to device miniaturization. Therefore, the capacitor structure can be integrated into the system-on-chip (SoC) architecture of mobile products or Internet of Things (IoT) applications.

[0034] Several examples are listed below to verify the effects of the present invention, but these experiments and their results are not intended to limit the scope of application of the present invention.

[0035] Experimental example like Figure 4A As shown, the capacitor structure of the experimental example is Figure 3 The capacitor structure is the same.

[0036] Comparative Example Figure 4B is a schematic cross-sectional view of a capacitor structure of a comparative example. Figure 4B In the embodiment, the capacitor unit 300 and Figure 4A The capacitor cells in FIG. 1 are identical, but the second cell plates 106a-106b are connected in one layer, and the bottom cell plates 104a and 104b are separated from each other. Thus, metal layer 110a is connected to bottom cell plate 104a through via 108a', and metal layer 110b is connected to bottom cell plate 104b through via 108b'.

[0037] Dynamic IR performance (PDN and IPC) For dynamic IR simulation, it is assumed that the operating voltage is 1.2V and the allowed voltage variation is ±5% (i.e. 1.14V to 1.26V).

[0038] Figure 5 The graph is a graph showing the voltage change over time for the experimental example and the comparative example measured using dynamic IR simulation.

[0039] Please refer to Figure 5 ,The voltage variation of the experimental example is within the range of 1.14V to 1.26V, but the voltage variation of the comparative example is obviously beyond this range. Figure 5 The values ​​in are further described in Table 1 below.

[0040] Table 1

[0041] V p-p Can be from V max and V min The difference between them (in mV) is obtained.

[0042] V p-p The ratio can be calculated as 1-(122.5-70.4) / 122.5.

[0043] It can be seen from Table 1 that the voltage variation of the experimental example can be reduced to 0.57 times compared with the comparative example.

[0044] IPC impedance curve Figure 6 The simulated impedance curves of the experimental example and the comparative example are shown. Figure 6 As shown in the figure, the impedance of the experimental example at high frequencies is much lower than that of the comparative example. Therefore, the experimental example has a better ESR (equivalent series resistance).

[0045] Table 2 below lists the simulated values ​​of the IPC impedance curve.

[0046] Table 2

[0047] The above-mentioned improvement degree is obtained by the percentage of the difference between the experimental example and the comparative example to the value of the comparative example.

[0048] As can be seen from Table 2, the experimental example has improved results in ESR, ESL (equivalent series inductance) and RC (resistance and capacitance).

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A capacitor structure, characterized in that: include: substrate; A plurality of capacitor units are formed on the substrate; a first unit plate, disposed between the substrate and the plurality of capacitor units; a plurality of second unit plates, respectively disposed above the plurality of capacitor units; as well as A plurality of through holes are arranged above the plurality of second unit plates.

2. The capacitor structure according to claim 1, wherein: For one of the plurality of second unit plates, the second unit plate includes a first surface and a second surface, the first surface is attached to one of the plurality of capacitor cells, and the second surface is attached to one of the plurality of through-holes.

3. The capacitor structure according to claim 1, wherein: Also includes: A plurality of metal layers are disposed above the plurality of through holes; For one of the plurality of through holes, the through hole comprises a first end and a second end, the first end is attached to one of the plurality of second unit plates, and the second end is attached to one of the plurality of metal layers.

4. The capacitor structure according to claim 1, wherein: When viewed from a top of the capacitor structure, the plurality of through holes overlap with the plurality of second unit plates.

5. The capacitor structure according to claim 1, wherein: For one of the plurality of second unit plates, the second unit plate has a first surface area, a predetermined number of through holes are provided on the second unit plate and occupy a second surface area of ​​the second unit plate, and the second surface area is at least half of the first surface area.

6. The capacitor structure according to claim 1, wherein: The first unit plate is configured as a single plate for connecting the plurality of capacitor units.

7. The capacitor structure according to claim 1, wherein: Each of the capacitor units includes a metal-insulator-metal capacitor, a stacked capacitor, or a crown capacitor.

8. The capacitor structure according to claim 1, wherein: Each of the capacitor units comprises: a first conductor film connected to the first unit board; A second conductor film connected to corresponding second unit plates among the plurality of second unit plates; and A dielectric layer is formed between the first conductive film and the second conductive film.

9. The capacitor structure according to claim 1, wherein: Also includes: A plurality of metal layers are located above the plurality of second unit boards and are respectively connected to the plurality of second unit boards through the plurality of through holes.

10. The capacitor structure according to claim 9, wherein: A height of one of the plurality of through holes is less than half of a height measured from the plurality of metal layers to the first unit board.

11. A capacitor structure, characterized in that: include: at least one bottom unit plate; a plurality of capacitor units disposed above the at least one bottom unit plate; a plurality of top unit plates disposed above the plurality of capacitor units; a first through hole, provided on one of the plurality of top unit plates; as well as a second through hole provided on another one of the plurality of top unit plates; The plurality of capacitor units are connected in series between the first through-hole and the second through-hole.

12. The capacitor structure according to claim 11, wherein: For one of the plurality of top cell plates, the top cell plate includes a first surface and a second surface, the first surface is attached to one of the plurality of capacitor cells, and the second surface is attached to one of the first through-hole and the second through-hole.

13. The capacitor structure according to claim 11, wherein: One of the plurality of top cell plates connected to the first through-hole is located at one end of the capacitor structure, and another of the plurality of top cell plates connected to the second through-hole is located at another end of the capacitor structure.

14. The capacitor structure according to claim 13, wherein: The first through-hole overlaps the one of the plurality of top cell plates when viewed from a top of the capacitor structure.

15. The capacitor structure according to claim 13, wherein: The second through-hole overlaps the other one of the plurality of top cell plates when viewed from a top of the capacitor structure.

16. The capacitor structure according to claim 11, wherein: The at least one bottom cell plate is electrically connected to the plurality of capacitor cells.

17. The capacitor structure according to claim 11, wherein: Each of the plurality of capacitor units includes a metal-insulator-metal capacitor, a stacked capacitor, or a crown capacitor.

18. The capacitor structure according to claim 11, wherein: Also includes: a first metal layer disposed above the plurality of top unit plates and connected to the first through-holes; as well as A second metal layer is disposed above the plurality of top unit plates and connected to the second through holes.

19. The capacitor structure according to claim 18, wherein: The height of the first through hole is less than half of a height measured from the first metal layer to the at least one bottom unit plate.

20. The capacitor structure according to claim 18, wherein The height of the second through hole is less than half of a height measured from the second metal layer to the at least one bottom unit plate.

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