Method, device and equipment for regulating output electric power of inverter and storage medium

Abstract

The application provides an output electric power regulation method, device and equipment of an inverter and a storage medium, and particularly relates to the technical field of output electric power regulation of an inverter. The method comprises the following steps: a processor acquires a DC bus voltage of an nth switching mode of an inverter, a floating ground capacitor voltage at a k+1 moment of the nth switching mode and an inverter neutral point voltage at the k+1 moment of the nth switching mode; a cost value of the nth switching mode is calculated; the cost values of each two switching modes in the cost values of the first n switching modes are compared to obtain a minimum cost value; and the output electric power of the inverter is regulated according to the floating ground capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value. The method reduces the harmonic content of the output voltage of the inverter, reduces the fluctuation of the output voltage of the inverter, improves the stability of the output voltage of the inverter, and further improves the accuracy and stability of the output electric power of the inverter.

Description

Technical Field

[0001] This application relates to the field of inverter output power regulation technology, and in particular to an inverter output power regulation method, device, equipment and storage medium. Background Technology

[0002] With the rapid development of power electronics technology and the increasingly widespread use of renewable energy, a large amount of clean energy is constantly flowing into the power grid. As a key device connecting renewable energy to the power grid, inverters are showing a rapid growth trend in both type and quantity.

[0003] In the field of photovoltaic power supply applications, transformerless inverters (five-level active neutral clamped inverters) are gradually becoming a highly regarded type of inverter. These inverters not only effectively reduce system cost and weight but also improve energy conversion efficiency, bringing numerous advantages to the promotion and application of photovoltaic systems.

[0004] However, the voltage of the DC link capacitor and floating ground capacitor in the inverter often differs significantly from the set reference value, which leads to unstable output power of the inverter and affects the power generation efficiency and reliability of the entire photovoltaic system. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a method, device, equipment and storage medium for regulating the output power of an inverter, so as to solve the above problems, improve the stability of the output power of the inverter, and thus improve the power generation efficiency and reliability of the entire photovoltaic system.

[0006] In a first aspect, embodiments of this application provide a method for regulating the output power of an inverter, the method comprising:

[0007] The processor obtains the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 in the nth switching mode, and the inverter neutral point voltage at time k+1 in the nth switching mode.

[0008] The processor calculates the cost value of the nth switching mode based on the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 in the nth switching mode, and the inverter neutral point voltage at time k+1 in the nth switching mode; wherein, the cost value is used to characterize the difference between the floating ground capacitor voltage at time k+1 and the floating ground capacitor voltage at time k, and the difference between the inverter neutral point voltage at time k+1 and the inverter neutral point voltage at time k.

[0009] The processor compares the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain the minimum cost value;

[0010] The processor adjusts the inverter's output power based on the floating capacitor voltage and inverter neutral point voltage corresponding to the minimum cost value.

[0011] Preferably, the step of the processor calculating the cost value of the nth switching mode based on the DC bus voltage of the nth switching mode, the floating ground capacitor voltage at time k+1 of the nth switching mode, and the inverter neutral point voltage at time k+1 of the nth switching mode includes:

[0012] The cost of the nth switching mode is calculated using the following formula:

[0013]

[0014] in, Let n be the cost value of the nth switching mode. These are the weighting coefficients. The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. This represents the DC bus voltage for the nth switching mode of the inverter. Let be the floating ground capacitor voltage of one of phases a, b, and c at time k+1 of the nth switching mode.

[0015] Preferably, the formula for calculating the inverter neutral point voltage at time k+1 of the nth switching mode is as follows:

[0016]

[0017] in, The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. The inverter neutral point voltage at time k, used to indicate the nth switching mode. The output time of the w-th voltage vector of the inverter. This is the capacitance value of the DC link capacitor. This refers to the output current of phase a of the inverter. This refers to the output current of phase b of the inverter. This refers to the c-phase output current of the inverter. Let w be the neutral point current coefficient of phase a when the inverter outputs the w-th voltage vector. Let w be the neutral point current coefficient of phase b when the inverter outputs the w-th voltage vector. The neutral point current coefficient of phase a when the inverter outputs the w-th voltage vector.

[0018] Preferably, the formula for calculating the floating ground capacitor voltage at time k+1 of the nth switching mode is as follows:

[0019]

[0020] in, Let be the floating ground capacitor voltage at time k+1 of the nth switching mode. Let be the floating ground capacitor voltage at time k in the nth switching mode. Let be the output current of the inverter at time k in the nth switching mode. The output time of the w-th voltage vector of the inverter. This is the capacitance value of the floating capacitor. The floating ground capacitor current coefficient of phase x when the inverter outputs the w-th voltage vector.

[0021] Preferably, the method further includes:

[0022] The processor acquires the output status parameters of the inverter's a-phase bridge arm, the output status parameters of the inverter's b-phase bridge arm, and the output status parameters of the inverter's c-phase bridge arm.

[0023] The processor calculates the common-mode voltage of the inverter's output voltage vector w based on the inverter's a-phase bridge arm output state parameters, inverter's b-phase bridge arm output state parameters, inverter's c-phase bridge arm output state parameters, and the DC bus voltage of the inverter's nth switching mode.

[0024] The processor compares the common-mode voltage of every two voltage vectors among the first w voltage vectors output by the inverter to obtain the minimum common-mode voltage of the inverter.

[0025] The processor generates the inverter's output pulses based on the voltage vector sequence corresponding to the inverter's minimum common-mode voltage.

[0026] Preferably, the step of the processor calculating the common-mode voltage of the inverter output voltage vector w based on the output state parameters of the inverter's a-phase bridge arm, the output state parameters of the inverter's b-phase bridge arm, the output state parameters of the inverter's c-phase bridge arm, and the DC bus voltage of the inverter's nth switching mode includes:

[0027]

[0028] in, The common-mode voltage of the w-th voltage vector output by the inverter. This represents the DC bus voltage for the nth switching mode of the inverter. These are the output state parameters of phase a bridge arm of the inverter. These are the output state parameters of the b-phase bridge arm of the inverter. These are the output status parameters of the c-phase bridge arm of the inverter.

[0029] The inverter output power regulation method provided in this application has the following beneficial effects:

[0030] This application provides a method for regulating the output power of an inverter. In this method, the processor compares the cost values ​​of every two switching modes out of the first n switching modes to obtain the minimum cost value. The output power of the inverter is then regulated based on the floating ground capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value. This method determines the floating ground capacitor voltage and the inverter neutral point voltage through the minimum cost value, thereby determining the inverter's output power and maintaining its stability. This method also reduces the harmonic content of the inverter's output voltage, minimizes output voltage fluctuations, and improves the stability of the inverter's output voltage, thus enhancing the accuracy and stability of the inverter's output power.

[0031] Secondly, this application also provides an output power regulation device for an inverter, the device comprising:

[0032] The acquisition module is used to acquire the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 in the nth switching mode, and the inverter neutral point voltage at time k+1 in the nth switching mode.

[0033] The calculation module is used to calculate the cost value of the nth switching mode based on the DC bus voltage of the nth switching mode, the floating ground capacitor voltage at time k+1 of the nth switching mode, and the inverter neutral point voltage at time k+1 of the nth switching mode; wherein, the cost value is used to characterize the difference between the floating ground capacitor voltage at time k+1 and the floating ground capacitor voltage at time k, and the difference between the inverter neutral point voltage at time k+1 and the inverter neutral point voltage at time k.

[0034] The comparison module is used to compare the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain the minimum cost value;

[0035] The control module is used to adjust the output power of the inverter according to the floating ground capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value.

[0036] The inverter output power regulation device provided in this application embodiment has the same technical features as the inverter output power regulation method provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0037] Thirdly, this application provides a computing device, including a memory and a processor;

[0038] The memory stores one or more computer programs, the one or more computer programs including instructions; when the instructions are executed by the processor, the computing device performs the method as described in any one of the first aspects.

[0039] Fourthly, this application provides a computer-readable storage medium for storing a computer program for performing the method as described in any one of the first aspects.

[0040] Fifthly, this application provides a computer program product comprising one or more computer instructions, wherein when the computer instructions are executed by a computer, the computer performs the method as described in any one of the first aspects.

[0041] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application are realized and obtained through the structures particularly pointed out in the description and the accompanying drawings.

[0042] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] Figure 1 This application provides a schematic flowchart of an inverter output power regulation method according to an embodiment of the present application.

[0045] Figure 2 This is a schematic diagram of the inverter structure provided in an embodiment of this application;

[0046] Figure 3 A voltage vector diagram provided for an embodiment of this application;

[0047] Figure 4 This is a partial voltage vector diagram provided for an embodiment of this application;

[0048] Figure 5 A waveform diagram of the inverter output voltage vector provided in the embodiments of this application;

[0049] Figure 6A schematic diagram of the output power regulation device for an inverter provided in this application embodiment;

[0050] Figure 7 This is a schematic diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0052] To facilitate understanding of this embodiment, the embodiments of this application will be described in detail below.

[0053] This application provides a method for regulating the output power of an inverter, such as... Figure 1 As shown, Figure 1 This is a schematic flowchart illustrating an inverter output power regulation method provided in an embodiment of this application. The method includes the following steps:

[0054] S101, the processor obtains the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 in the nth switching mode, and the inverter neutral point voltage at time k+1 in the nth switching mode.

[0055] Specifically, such as Figure 2 As shown, Figure 2 This is a schematic diagram of an inverter structure provided in an embodiment of this application. The inverter includes: a floating ground capacitor Cf, a DC link capacitor, a first switching element S1, a second switching element S2, a third switching element S3, a fourth switching element S4, a fifth switching element S5, a sixth switching element S6, a seventh switching element S7, an eighth switching element S8, a ninth switching element S9, a tenth switching element S10, an eleventh switching element S11, and a twelfth switching element S12; wherein, the DC link capacitor includes: a first DC link capacitor C1 and a second DC link capacitor C2.

[0056] The source of the first switching element S1 is connected to the positive terminal of the DC bus voltage Udc and the first terminal of the first DC link capacitor C1, respectively. The drain of the first switching element S1 is connected to the source of the second switching element S2, and the drain of the second switching element S2 is connected to the source of the fifth switching element S5 and the source of the tenth switching element S10, respectively.

[0057] The drain of the seventh switching element S7 is connected to the negative terminal of the DC bus voltage Udc and the first terminal of the second DC link capacitor C2. The source of the seventh switching element S7 is connected to the drain of the eighth switching element S8. The drain of the eighth switching element S8 is connected to the drain of the fourth switching element S4 and the drain of the eleventh switching element S11.

[0058] The drain of the ninth switching element S9 is connected to the second terminal of the first DC link capacitor C1, the second terminal of the second DC link capacitor C2, and the source of the third switching element S3. The source of the ninth switching element S9 is connected to the drain of the tenth switching element S10, and the drain of the third switching element S3 is connected to the source of the fourth switching element S4.

[0059] The drain of the fifth switching element S5 is connected to the first terminal of the floating ground capacitor Cf and the source of the sixth switching element S6. The drain of the sixth switching element S6 is connected to the output voltage U0 of the inverter and the source of the twelfth switching element S12. The drain of the twelfth switching element S12 is connected to the second terminal of the floating ground capacitor Cf and the source of the eleventh switching element S11.

[0060] The output voltage of the inverter corresponding to each of the above switching modes has a mapping relationship. As shown in Table 1, Table 1 is a switching mode table provided in the embodiments of this application.

[0061] Table 1:

[0062]

[0063] In Table 1, 1 indicates that the IGBT is in the on state, 0 indicates that the IGBT is in the off state, and Mode represents each switching mode. Each arm of the inverter has eight switching modes, but the inverter's output voltage has five parameters: -2E, -E, 0, E, and 2E. Therefore, the inverter's output voltage needs to be switched by different switching modes to avoid unwanted output voltages. The switching modes corresponding to the same inverter output voltage are called redundancy modes. As can be seen from Table 1, when the inverter's output voltage is E or -E, there are two redundancy modes. However, redundancy modes have opposite effects on the floating ground capacitor voltage. Therefore, different redundancy modes can be selected to balance the floating ground capacitor voltage and keep it stable.

[0064] The aforementioned DC bus voltage is obtained by using voltmeters connected in parallel to the positive and negative terminals of the DC bus voltage.

[0065] The formula for calculating the inverter neutral point voltage at time k+1 in the above nth switching mode is as follows:

[0066]

[0067] in, The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. The inverter neutral point voltage at time k, used to indicate the nth switching mode. The output time of the w-th voltage vector of the inverter. This is the capacitance value of the DC link capacitor. This refers to the output current of phase a of the inverter. This refers to the output current of phase b of the inverter. This refers to the c-phase output current of the inverter. Let w be the neutral point current coefficient of phase a when the inverter outputs the w-th voltage vector. Let w be the neutral point current coefficient of phase b when the inverter outputs the w-th voltage vector. The neutral point current coefficient of phase a when the inverter outputs the w-th voltage vector.

[0068] In the above-mentioned inverter, the DC bus voltage and DC link current are constant in the nth switching mode. The inverter neutral point voltage at time k in the nth switching mode is equal to twice the current flowing through the first DC link capacitor at time k in the nth switching mode, and also equal to twice the current flowing through the second DC link capacitor at time k in the nth switching mode. Therefore, the relationship between the DC link current and the current flowing through the first DC link capacitor at time k in the nth switching mode, and the current flowing through the second DC link capacitor at time k in the nth switching mode, can be expressed as:

[0069]

[0070] in, This is the DC link current. Let be the current flowing through the first DC link capacitor at time k in the nth switching mode. Let be the current flowing through the second DC link capacitor at time k in the nth switching mode. This is the capacitance value of the first DC link capacitor. This is the capacitance value of the second DC link capacitor.

[0071] More specifically, the DC link current is calculated using the following formula:

[0072]

[0073] in, This is the DC link current. This refers to the output current of phase a of the inverter. This refers to the output current of phase b of the inverter. This is the c-phase output current of the inverter.

[0074] Referring to Table 1, the mapping relationship between the neutral point current coefficients of phase a, phase b, and phase c when the inverter outputs the w-th voltage vector and the switching mode is the same.

[0075] Right now

[0076] ;

[0077] in, It is in switch mode.

[0078] The formula for calculating the floating capacitor voltage at time k+1 in the above nth switching mode is as follows:

[0079]

[0080] in, Let be the floating ground capacitor voltage at time k+1 of the nth switching mode. Let be the floating ground capacitor voltage at time k in the nth switching mode. Let be the output current of the inverter at time k in the nth switching mode. The output time of the w-th voltage vector of the inverter. This is the capacitance value of the floating capacitor. The floating ground capacitor current coefficient of phase x when the inverter outputs the w-th voltage vector.

[0081] The current coefficient flowing through the floating ground capacitor when the inverter outputs its w-th voltage vector can be represented by a function that describes the relationship between the inverter's output current at time k in the n-th switching mode and the current flowing through the floating ground capacitor at time k in the n-th switching mode. ;

[0082] in, Let be the current flowing through the floating capacitor at time k in the nth switching mode. Let be the output current of the inverter at time k in the nth switching mode.

[0083] Referring to Table 1, the floating ground capacitor current coefficient of phase x when the inverter outputs the w-th voltage vector is calculated using the following formula:

[0084]

[0085] in, It is in switch mode.

[0086] S102, the processor calculates the cost value of the nth switching mode based on the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 of the nth switching mode, and the neutral point voltage of the inverter at time k+1 of the nth switching mode.

[0087] The cost value is used to characterize the difference between the floating ground capacitor voltage at time k+1 and the floating ground capacitor voltage at time k, as well as the difference between the inverter neutral point voltage at time k+1 and the inverter neutral point voltage at time k.

[0088] Specifically, the cost of the nth switching mode is calculated using the following formula:

[0089]

[0090] in, Let n be the cost value of the nth switching mode. These are the weighting coefficients. The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. This represents the DC bus voltage for the nth switching mode of the inverter. Let be the floating ground capacitor voltage of one of phases a, b, and c at time k+1 of the nth switching mode.

[0091] S103, the processor compares the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain the minimum cost value.

[0092] Specifically, the cost value is a quantitative indicator that comprehensively considers multiple factors affecting the inverter's output voltage, namely the difference between the floating ground capacitor voltage at time k+1 and the floating ground capacitor voltage at time k, and the difference between the inverter neutral point voltage at time k+1 and the inverter neutral point voltage at time k.

[0093] Differences in floating ground capacitor voltage and inverter neutral point voltage at different times directly affect the inverter's output voltage, thus influencing the harmonic content of the output voltage. Harmonics in the inverter's output voltage can adversely affect load equipment, such as causing overheating and reducing equipment lifespan. The minimum cost switching mode corresponds to the floating ground capacitor voltage and inverter neutral point voltage, minimizing the harmonic content of the inverter's output voltage and improving output voltage quality.

[0094] S104, the processor adjusts the inverter's output power based on the floating capacitor voltage and inverter neutral point voltage corresponding to the minimum cost value.

[0095] Specifically, the floating ground capacitor voltage and inverter neutral point voltage corresponding to the switching mode with the minimum cost value obtained above minimize the harmonic content of the inverter's output voltage, thereby minimizing the inverter's output power loss. During inverter operation, different switching modes generate different power losses, such as switching losses and conduction losses. The minimum cost value means that the total system loss is likely to be the lowest under that switching mode.

[0096] With this configuration, when the inverter output voltage is controlled using the floating ground capacitor voltage and inverter neutral point voltage corresponding to the minimum cost value, the harmonic content of the inverter output voltage is reduced, the stability of the inverter output voltage is improved, and thus the power loss of the inverter output power is effectively reduced, thereby improving the efficiency of the inverter output power.

[0097] This application provides a method for regulating the output power of an inverter. In this method, the processor compares the cost values ​​of every two switching modes out of the first n switching modes to obtain the minimum cost value. The inverter's output power is then regulated based on the floating ground capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value. This method determines the floating ground capacitor voltage and the inverter neutral point voltage through the minimum cost value, thereby determining the inverter's output power and maintaining its stability. Compared to existing technologies that use complex calculations to determine the inverter's output voltage vector based on its time, this method simplifies the calculation process. The floating ground capacitor voltage and the inverter neutral point voltage used to regulate the inverter's output power can be determined simply by comparing the minimum cost value. This method reduces the harmonic content of the inverter's output voltage, decreases output voltage fluctuations, and improves the stability of the inverter's output voltage, thus improving the accuracy and stability of the inverter's output power.

[0098] In one implementation, the processor acquires the output state parameters of the inverter's a-phase bridge arm, the output state parameters of the inverter's b-phase bridge arm, and the output state parameters of the inverter's c-phase bridge arm. Based on the output state parameters of the inverter's a-phase bridge arm, the output state parameters of the inverter's b-phase bridge arm, the output state parameters of the inverter's c-phase bridge arm, and the DC bus voltage of the inverter's nth switching mode, the processor calculates the common-mode voltage of the inverter's output voltage vector w.

[0099] Specifically, the formula for calculating the common-mode voltage of the w-th voltage vector at the inverter output is as follows:

[0100]

[0101] in, The common-mode voltage of the w-th voltage vector output by the inverter. This represents the DC bus voltage for the nth switching mode of the inverter. These are the output state parameters of phase a bridge arm of the inverter. These are the output state parameters of the b-phase bridge arm of the inverter. These are the output status parameters of the c-phase bridge arm of the inverter.

[0102] The processor compares the common-mode voltage of every two voltage vectors in the first w voltage vectors of the inverter output to obtain the minimum common-mode voltage of the inverter, and generates the output pulse of the inverter based on the voltage vector sequence corresponding to the minimum common-mode voltage of the inverter.

[0103] More specifically, the output state parameters of the a-phase bridge arm, b-phase bridge arm, and c-phase bridge arm of the inverter mentioned above take values ​​ranging from {0, 1, 2, 3, 4}. The inverter's output voltage, i.e., the redundant vector voltage, includes the a-phase output voltage, b-phase output voltage, and c-phase output voltage, such as... Figure 3 As shown, Figure 3 This is a voltage vector diagram provided for an embodiment of this application. The calculation formulas for the above-mentioned phase a output voltage, phase b output voltage, and phase c output voltage are as follows:

[0104]

[0105] in, The output voltage of phase a, This is the output voltage of phase b. This is the output voltage of phase c. These are the output state parameters of phase a bridge arm of the inverter. These are the output state parameters of the b-phase bridge arm of the inverter. Here, E represents the output state parameters of the c-phase bridge arm of the inverter, and E represents the input voltage of the inverter.

[0106] As shown above, the formula for calculating the inverter's output voltage is as follows:

[0107]

[0108] in, Where is the output voltage of the inverter, and E is the input voltage of the inverter. These are the output state parameters of phase a bridge arm of the inverter. These are the output state parameters of the b-phase bridge arm of the inverter. These are the output state parameters of the c-phase bridge arm of the inverter. The imaginary unit, It is a natural constant.

[0109] like Figure 4 As shown, Figure 4This is a partial voltage vector diagram provided for an embodiment of this application. Triangle A represents the vector in the line voltage coordinate system, and triangle B represents the redundant vector in the transition conventional coordinate system. The reference vector voltage is calculated according to the following formula:

[0110]

[0111] in, For reference vector voltage, The vector voltage at the first point of the vector in the line voltage coordinate system. The output time of the first vector voltage in the line voltage coordinate system. The vector voltage at the second point in the line voltage coordinate system is the vector voltage. The output time of the vector voltage at the second point of the vector in the line voltage coordinate system. Let be the vector voltage at the third point in the line voltage coordinate system. The output time of the vector voltage at the third point of the vector in the line voltage coordinate system.

[0112] The output time of the vector voltage at the first point of the vector in the line voltage coordinate system, the output time of the vector voltage at the second point of the vector in the line voltage coordinate system, and the output time of the vector voltage at the third point of the vector in the line voltage coordinate system are calculated according to the following formula:

[0113]

[0114] in, The output time of the vector voltage at the first point of the vector in the line voltage coordinate system. The output time of the vector voltage at the second point of the vector in the line voltage coordinate system. The output time of the vector voltage at the third point of the vector in the line voltage coordinate system. Let be the distance between the second point of the reference vector voltage to the vector in the line voltage coordinate system and the third point of the reference vector voltage to the vector in the line voltage coordinate system. Let be the distance between the first point of the reference vector voltage vector in the line voltage coordinate system and the third point of the reference vector voltage vector in the line voltage coordinate system. The distance between the first point of the reference vector voltage to the line voltage coordinate system and the third point of the reference vector voltage to the line voltage coordinate system is given.

[0115] In triangle A above, the formulas for calculating the first point, the second point, and the third point of the vector in the line voltage coordinate system are as follows:

[0116]

[0117] in, The first point of the vector in the line voltage coordinate system. The second point of the vector in the line voltage coordinate system. The third point of the vector in the line voltage coordinate system. This is the down-rounded value of the vector voltage at the first point of the vector in the line voltage coordinate system. This is the down-rounded value of the vector voltage at the second point in the line voltage coordinate system. This is the down-rounded value of the vector voltage at the third point of the vector in the line voltage coordinate system.

[0118] The formulas for calculating the distances between the lines connecting the second and third points of the reference vector voltage to the line voltage coordinate system, the first and third points of the reference vector voltage to the line voltage coordinate system, and the first and third points of the reference vector voltage to the line voltage coordinate system are as follows:

[0119]

[0120] in, Let be the distance between the second point of the reference vector voltage to the vector in the line voltage coordinate system and the third point of the reference vector voltage to the vector in the line voltage coordinate system. Let be the distance between the first point of the reference vector voltage vector in the line voltage coordinate system and the third point of the reference vector voltage vector in the line voltage coordinate system. Let be the distance between the first point of the reference vector voltage vector in the line voltage coordinate system and the third point of the reference vector voltage vector in the line voltage coordinate system. The vector voltage at the first point of the vector in the line voltage coordinate system. The vector voltage at the second point in the line voltage coordinate system is the vector voltage. Let be the vector voltage at the third point in the line voltage coordinate system. This is the down-rounded value of the vector voltage at the first point of the vector in the line voltage coordinate system. This is the down-rounded value of the vector voltage at the second point in the line voltage coordinate system. This is the down-rounded value of the vector voltage at the third point of the vector in the line voltage coordinate system.

[0121] In triangle B above, the formulas for calculating the first point, the second point, and the third point of the redundant vector in the transitioned traditional coordinate system are as follows:

[0122]

[0123] in, This is the first point of the redundant vector in the traditional coordinate system after the transition. The second point of the redundant vector in the traditional coordinate system after the transition. The third point of the redundant vector in the traditional coordinate system after the transition. This is the rounded-down value of the redundant vector voltage at the first point of the redundant vector in the transitioned traditional coordinate system. This is the rounded-down value of the redundant vector voltage at the second point of the redundant vector in the traditional coordinate system after the transition. This is the down-rounded value of the redundant vector voltage at the third point of the redundant vector in the traditional coordinate system after the transition.

[0124] The formulas for calculating the distances between the reference redundant vector voltage and the second and third points of the redundant vector in the transitioned traditional coordinate system, the distances between the reference redundant vector voltage and the first and third points of the redundant vector in the transitioned traditional coordinate system, and the distances between the reference redundant vector voltage and the third point of the redundant vector in the transitioned traditional coordinate system are as follows:

[0125]

[0126] in, Let the distance between the second point of the reference redundant vector voltage to the redundant vector in the transitioned traditional coordinate system and the third point of the reference redundant vector voltage to the redundant vector in the transitioned traditional coordinate system be the distance. Let the distance between the first point of the reference redundant vector voltage in the transitioned traditional coordinate system and the third point of the reference redundant vector voltage in the transitioned traditional coordinate system be the distance between the two points. Let the distance between the first point of the reference redundant vector voltage in the transitioned traditional coordinate system and the third point of the reference redundant vector voltage in the transitioned traditional coordinate system be the distance between the two points. The redundant vector voltage at the first point of the redundant vector in the traditional coordinate system after the transition. The redundant vector voltage at the second point of the redundant vector in the traditional coordinate system after the transition. The redundant vector voltage at the third point of the redundant vector in the traditional coordinate system after the transition. This is the rounded-down value of the redundant vector voltage at the first point of the redundant vector in the transitioned traditional coordinate system. This is the rounded-down value of the redundant vector voltage at the second point of the redundant vector in the traditional coordinate system after the transition. This is the down-rounded value of the redundant vector voltage at the third point of the redundant vector in the traditional coordinate system after the transition.

[0127] As shown in Table 2, Table 2 is a comparison table of inverter common mode voltage and voltage vector sequence provided in the embodiments of this application.

[0128] Table 2:

[0129]

[0130] like Figure 5 As shown in Table 2, Figure 5 This is a waveform diagram of the inverter output voltage vector provided in an embodiment of this application. In triangle A, four voltage vector sequences can be obtained. To suppress the inverter common-mode voltage within the expected range, the common-mode voltages of every two voltage vectors output by the inverter are compared among the common-mode voltages of the first w voltage vectors, to obtain the minimum inverter common-mode voltage. For example, when the sequence number is 3 or 4, the inverter common-mode voltage is Udc / 6, which is the minimum inverter common-mode voltage. Therefore, the voltage vector sequence corresponding to the inverter common-mode voltage when the sequence number is 3 or 4 is selected as the qualified sequence, and the inverter output pulse is generated based on the qualified sequence.

[0131] In this method, the voltage vector sequence corresponding to the minimum common-mode voltage can significantly reduce high-frequency common-mode current components, thereby reducing system radiation and conducted interference. By comparing the common-mode voltages of every two voltage vectors from the first w voltage vectors of the inverter output, this method can accurately pinpoint the combination of switching modes of the inverter that generates the minimum common-mode voltage. This directly reduces the inverter's leakage current to ground and shaft current, extends the inverter's lifespan, improves the stability of the inverter's output pulses, and provides a stable and reliable power supply to the downstream loads.

[0132] Based on the above method embodiments, this application also provides an inverter output power regulation device, such as... Figure 6 As shown, Figure 6 This is a schematic diagram of an inverter output power regulation device provided in an embodiment of this application. The device includes: an acquisition module 61, a calculation module 62, a comparison module 63, and a control module 64. The functions of each module are as follows:

[0133] The acquisition module 61 is used to acquire the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 in the nth switching mode, and the inverter neutral point voltage at time k+1 in the nth switching mode.

[0134] The calculation module 62 is used to calculate the cost value of the nth switching mode based on the DC bus voltage of the nth switching mode, the floating ground capacitor voltage at time k+1 of the nth switching mode, and the inverter neutral point voltage at time k+1 of the nth switching mode; wherein, the cost value is used to characterize the difference between the floating ground capacitor voltage at time k+1 and the floating ground capacitor voltage at time k, and the difference between the inverter neutral point voltage at time k+1 and the inverter neutral point voltage at time k.

[0135] Comparison module 63 is used to compare the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain the minimum cost value;

[0136] The control module 64 is used to regulate the output power of the inverter according to the floating capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value.

[0137] Preferably, the calculation module 62 is specifically used to calculate the cost value of the nth switching mode according to the following formula:

[0138]

[0139] in, Let n be the cost value of the nth switching mode. These are the weighting coefficients. The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. This represents the DC bus voltage for the nth switching mode of the inverter. Let be the floating ground capacitor voltage of one of phases a, b, and c at time k+1 of the nth switching mode.

[0140] Preferably, the formula for calculating the inverter neutral point voltage at time k+1 of the nth switching mode is as follows:

[0141]

[0142] in, The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. The inverter neutral point voltage at time k, used to indicate the nth switching mode. The output time of the w-th voltage vector of the inverter. This is the capacitance value of the DC link capacitor. This refers to the output current of phase a of the inverter. This refers to the output current of phase b of the inverter. This refers to the c-phase output current of the inverter. Let w be the neutral point current coefficient of phase a when the inverter outputs the w-th voltage vector. Let w be the neutral point current coefficient of phase b when the inverter outputs the w-th voltage vector. The neutral point current coefficient of phase a when the inverter outputs the w-th voltage vector.

[0143] Preferably, the formula for calculating the floating ground capacitor voltage at time k+1 of the nth switching mode is as follows:

[0144]

[0145] in, Let be the floating ground capacitor voltage at time k+1 of the nth switching mode. Let be the floating ground capacitor voltage at time k in the nth switching mode. Let be the output current of the inverter at time k in the nth switching mode. The output time of the w-th voltage vector of the inverter. This is the capacitance value of the floating capacitor. The floating ground capacitor current coefficient of phase x when the inverter outputs the w-th voltage vector.

[0146] Preferably, the acquisition module 61 is further used to acquire the output state parameters of the a-phase bridge arm of the inverter, the output state parameters of the b-phase bridge arm of the inverter, and the output state parameters of the c-phase bridge arm of the inverter.

[0147] The calculation module 62 is also used to calculate the common-mode voltage of the inverter output voltage vector w based on the output state parameters of the inverter's a-phase bridge arm, the output state parameters of the inverter's b-phase bridge arm, the output state parameters of the inverter's c-phase bridge arm, and the DC bus voltage of the inverter's nth switching mode.

[0148] Comparison module 63 is also used to compare the common-mode voltage of every two voltage vectors of the inverter output in the common-mode voltage of the first w voltage vectors of the inverter output, and to obtain the minimum common-mode voltage of the inverter.

[0149] The control module 64 is also used to generate the inverter's output pulses based on the voltage vector sequence corresponding to the inverter's minimum common-mode voltage.

[0150] Preferably, the calculation module 62 is specifically used to calculate the common-mode voltage of the w-th voltage vector of the inverter output according to the following formula:

[0151]

[0152] in, The common-mode voltage of the w-th voltage vector output by the inverter. This represents the DC bus voltage for the nth switching mode of the inverter. These are the output state parameters of phase a bridge arm of the inverter. These are the output state parameters of the b-phase bridge arm of the inverter. These are the output status parameters of the c-phase bridge arm of the inverter.

[0153] The inverter output power regulation device provided in this application embodiment has the same technical features as the inverter output power regulation method provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0154] This application also provides a computing device. For example... Figure 7 As shown in the figure, this is a schematic diagram of a computing device provided in an embodiment of this application. The computing device 400 includes a bus 401, a processor 402, a communication interface 403, and a memory 404. The processor 402, the memory 404, and the communication interface 403 communicate with each other via the bus 401.

[0155] Bus 401 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0156] The processor 402 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0157] Communication interface 403 is used for communication with external devices. Memory 404 may include volatile memory, such as random access memory (RAM). Memory 404 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0158] The memory 404 stores executable code, and the processor 402 executes the executable code to perform the aforementioned inverter output power regulation method.

[0159] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium capable of being stored by a computing device, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to perform the above-described method.

[0160] This application also provides a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this application are generated.

[0161] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center via wired (e.g., coaxial cable, fiber optic) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0162] When the computer program product is executed by a computer, the computer executes any of the aforementioned inverter output power regulation methods. The computer program product can be a software installation package; when any of the aforementioned inverter output power regulation methods is required, the computer program product can be downloaded and executed on the computer.

[0163] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0164] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application.

Claims

1. A method for regulating the output power of an inverter, characterized in that, The method includes: The processor obtains the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 in the nth switching mode, and the inverter neutral point voltage at time k+1 in the nth switching mode. The processor calculates the cost value of the nth switching mode based on the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 in the nth switching mode, and the inverter neutral point voltage at time k+1 in the nth switching mode; wherein, the cost value is used to characterize the difference between the floating ground capacitor voltage at time k+1 and the floating ground capacitor voltage at time k, and the difference between the inverter neutral point voltage at time k+1 and the inverter neutral point voltage at time k. The processor compares the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain the minimum cost value; The processor adjusts the output power of the inverter according to the floating capacitor voltage and inverter neutral point voltage corresponding to the minimum cost value; The step of the processor calculating the cost value of the nth switching mode based on the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 of the nth switching mode, and the neutral point voltage of the inverter at time k+1 of the nth switching mode includes: The cost of the nth switching mode is calculated using the following formula: in, Let n be the cost value of the nth switching mode. These are the weighting coefficients. The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. This represents the DC bus voltage for the nth switching mode of the inverter. Let be the floating ground capacitor voltage of one of phases a, b, and c at time k+1 of the nth switching mode.

2. The inverter output power regulation method according to claim 1, characterized in that, The formula for calculating the inverter neutral point voltage at time k+1 in the nth switching mode is as follows: in, The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. The inverter neutral point voltage at time k, used to indicate the nth switching mode. The output time of the common-mode voltage of the w-th voltage vector of the inverter. This is the capacitance value of the DC link capacitor. This refers to the output current of phase a of the inverter. This refers to the output current of phase b of the inverter. This refers to the c-phase output current of the inverter. Let w be the neutral point current coefficient of phase a when the inverter outputs the w-th voltage vector. Let w be the neutral point current coefficient of phase b when the inverter outputs the w-th voltage vector. The neutral point current coefficient of phase c when the inverter outputs the w-th voltage vector.

3. The inverter output power regulation method according to claim 1, characterized in that, The formula for calculating the floating capacitor voltage at time k+1 in the nth switching mode is as follows: in, Let be the floating ground capacitor voltage at time k+1 of the nth switching mode. Let be the floating ground capacitor voltage at time k in the nth switching mode. Let be the output current of the inverter at time k in the nth switching mode. The output time of the common-mode voltage of the w-th voltage vector of the inverter. This is the capacitance value of the floating capacitor. The floating ground capacitor current coefficient of phase x when the inverter outputs the w-th voltage vector.

4. The inverter output power regulation method according to claim 1, characterized in that, The method further includes: The processor acquires the output status parameters of the inverter's a-phase bridge arm, the output status parameters of the inverter's b-phase bridge arm, and the output status parameters of the inverter's c-phase bridge arm. The processor calculates the common-mode voltage of the inverter's output voltage vector w based on the inverter's a-phase bridge arm output state parameters, inverter's b-phase bridge arm output state parameters, inverter's c-phase bridge arm output state parameters, and the DC bus voltage of the inverter's nth switching mode. The processor compares the common-mode voltage of every two voltage vectors in the common-mode voltage of the first w voltage vectors of the inverter output to obtain the minimum common-mode voltage of the inverter. The processor generates the inverter's output pulses based on the voltage vector sequence corresponding to the inverter's minimum common-mode voltage.

5. The inverter output power regulation method according to claim 4, characterized in that, The step of the processor calculating the common-mode voltage of the inverter's output voltage vector w based on the inverter's a-phase bridge arm output state parameters, the inverter's b-phase bridge arm output state parameters, the inverter's c-phase bridge arm output state parameters, and the DC bus voltage of the inverter's nth switching mode includes: in, The common-mode voltage of the w-th voltage vector output by the inverter. This represents the DC bus voltage for the nth switching mode of the inverter. These are the output state parameters of phase a bridge arm of the inverter. These are the output state parameters of the b-phase bridge arm of the inverter. These are the output status parameters of the c-phase bridge arm of the inverter.

6. An output power regulation device for an inverter, characterized in that, The device includes: The acquisition module is used to acquire the DC bus voltage of the inverter in the nth switching mode, the floating ground capacitor voltage at time k+1 in the nth switching mode, and the inverter neutral point voltage at time k+1 in the nth switching mode. The calculation module is used to calculate the cost value of the nth switching mode based on the DC bus voltage of the nth switching mode, the floating ground capacitor voltage at time k+1 of the nth switching mode, and the inverter neutral point voltage at time k+1 of the nth switching mode; wherein, the cost value is used to characterize the difference between the floating ground capacitor voltage at time k+1 and the floating ground capacitor voltage at time k, and the difference between the inverter neutral point voltage at time k+1 and the inverter neutral point voltage at time k. The comparison module is used to compare the cost values ​​of every two switching modes among the cost values ​​of the first n switching modes to obtain the minimum cost value; The control module is used to adjust the output power of the inverter according to the floating ground capacitor voltage and the inverter neutral point voltage corresponding to the minimum cost value; The calculation module is specifically used to calculate the cost value of the nth switching mode according to the following formula: in, Let n be the cost value of the nth switching mode. These are the weighting coefficients. The inverter neutral point voltage used to indicate the (k+1)th time of the nth switching mode. This represents the DC bus voltage for the nth switching mode of the inverter. Let be the floating ground capacitor voltage of one of phases a, b, and c at time k+1 of the nth switching mode.

7. A computing device, characterized in that, Including memory and processor; The memory stores one or more computer programs, the one or more computer programs including instructions; when the instructions are executed by the processor, the computing device performs the method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program for performing the method as described in any one of claims 1 to 5.

9. A computer program product, characterized in that, The computer program product includes one or more computer instructions, which, when executed by a computer, perform the method as described in any one of claims 1 to 5.

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