Sampling circuit, chip, slave device and communication system

Abstract

The invention provides a sampling circuit, a chip, slave equipment and a communication system, and relates to the technical field of unibus communication. The sampling circuit provided by the invention comprises a falling edge detection circuit, a rising edge detection circuit and a synchronous circuit, the falling edge detection circuit and the rising edge detection circuit are respectively connected with the synchronous circuit; the falling edge detection circuit is used for generating a falling edge synchronization signal based on the synchronization clock signal when the falling edge of the single bus signal is detected; the rising edge detection circuit is used for generating a rising edge synchronization signal based on the synchronization clock signal when the rising edge of the single bus signal is detected; the synchronous circuit is used for outputting a single-bus synchronous signal according to the falling edge synchronous signal and the rising edge synchronous signal, and the frequency of the synchronous clock signal is lower than that of the single-bus signal. According to the sampling circuit provided by the invention, under the scene that a low-frequency clock is adopted to synchronously sample a high-frequency single-bus signal, synchronous sampling is effectively carried out on the single-bus signal, and the problem of missing sampling of the single-bus signal is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of single bus communication, and in particular to a sampling circuit, a chip, a slave device and a communication system. Background Art

[0002] In the field of single-bus communication technology, since the single-bus communication protocol only transmits data on a single line, the transmission rate is relatively low. To improve data transmission rate and efficiency, the single-bus communication protocol has an overdrive mode, which increases the overall data transmission rate by increasing the speed of the single bus and optimizing the transmission protocol.

[0003] However, in 1-wire overspeed mode, because the 1-wire signal sent by the master device is at a higher frequency and the clock frequency of the slave devices on the 1-wire is lower, the slave device's synchronization circuit uses a low-frequency clock to synchronously sample the high-frequency 1-wire signal, which may cause missed samples. For example, the high-frequency 1-wire signal may have become invalid before the low-frequency clock arrives. Summary of the Invention

[0004] In order to solve the problem of missed sampling when synchronously sampling a single bus signal in a single bus overspeed mode in the related art, the present application provides a sampling circuit, chip, slave device and communication system, which can effectively perform synchronous sampling of the single bus signal in the scenario of synchronous sampling of the high-frequency single bus signal using a low-frequency clock, thereby avoiding the problem of missed sampling of the single bus signal.

[0005] In a first aspect, an embodiment of the present application provides a sampling circuit, comprising:

[0006] A falling edge detection circuit, a rising edge detection circuit and a synchronization circuit; the falling edge detection circuit and the rising edge detection circuit are respectively connected to the synchronization circuit;

[0007] The falling edge detection circuit is used to generate a falling edge synchronization signal based on the synchronization clock signal when detecting the falling edge of the single bus signal;

[0008] The rising edge detection circuit is used to generate a rising edge synchronization signal based on the synchronization clock signal when detecting the rising edge of the single bus signal;

[0009] The synchronization circuit is used to output a single bus synchronization signal according to the falling edge synchronization signal and the rising edge synchronization signal; wherein the frequency of the synchronization clock signal is lower than the frequency of the single bus signal.

[0010] In a second aspect, an embodiment of the present application provides a chip, comprising: the sampling circuit as described in the first aspect; wherein the chip is applied to a slave device.

[0011] In a third aspect, an embodiment of the present application provides a slave device for communicating with a host device via a single bus communication protocol, characterized in that it includes: a sampling circuit as described in the first aspect; wherein the falling edge detection circuit and the rising edge detection circuit of the sampling circuit are used to receive a single bus signal from the host device.

[0012] In a fourth aspect, an embodiment of the present application provides a communication system, including:

[0013] A host device and a slave device, wherein the host device communicates with the slave device via a single bus communication protocol; the slave device comprises the sampling circuit according to the first aspect;

[0014] The falling edge detection circuit and the rising edge detection circuit of the sampling circuit are used to receive a single bus signal from a host device.

[0015] In an embodiment of the present application, a sampling circuit includes: a falling edge detection circuit, a rising edge detection circuit and a synchronization circuit; the falling edge detection circuit and the rising edge detection circuit are respectively connected to the synchronization circuit; the falling edge detection circuit is used to generate a falling edge synchronization signal based on a synchronization clock signal when a falling edge of a single bus signal is detected; the rising edge detection circuit is used to generate a rising edge synchronization signal based on the synchronization clock signal when a rising edge of a single bus signal is detected; the synchronization circuit is used to output a single bus synchronization signal based on the falling edge synchronization signal and the rising edge synchronization signal; wherein the frequency of the synchronization clock signal is lower than the frequency of the single bus signal. In this way, in the scenario where a low-frequency clock is used to synchronously sample a high-frequency single-bus signal, the present application first generates a falling edge synchronization signal based on the synchronization clock signal when the falling edge of the single-bus signal is detected by the falling edge detection circuit, and generates a rising edge synchronization signal based on the synchronization clock signal when the rising edge of the single-bus signal is detected by the rising edge detection circuit. Then, a single-bus synchronization signal is generated based on the falling edge synchronization signal and the rising edge synchronization signal. This can effectively synchronously sample the single-bus signal and ensure the validity of the sampled single-bus synchronization signal. Compared with the related art that uses a synchronization circuit to directly synchronously sample the single-bus signal itself through the sampling clock, this avoids the problem of missed sampling when synchronously sampling a high-frequency single-bus signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the embodiments of the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 A structural schematic diagram of a sampling circuit provided in an embodiment of the present application;

[0018] Figure 2 A structural schematic diagram of another sampling circuit provided in an embodiment of the present application;

[0019] Figure 3 A timing diagram of a sampling circuit provided in an embodiment of the present application;

[0020] Figure 4 A structural schematic diagram of a falling edge detection circuit in a sampling circuit provided in an embodiment of the present application;

[0021] Figure 5 A timing diagram of a falling edge detection circuit provided in an embodiment of the present application;

[0022] Figure 6 A structural schematic diagram of a rising edge detection circuit in a sampling circuit provided in an embodiment of the present application;

[0023] Figure 7 A timing diagram of a rising edge detection circuit provided in an embodiment of the present application;

[0024] Figure 8 A schematic structural diagram of a chip provided in an embodiment of the present application;

[0025] Figure 9 A schematic structural diagram of a slave device provided in an embodiment of the present application;

[0026] Figure 10 A structural diagram of a communication system provided in an embodiment of the present application;

[0027] Figure 11 A timing diagram of a sampling circuit in a slave device provided in an embodiment of the present application.

[0028] Description of reference numerals:

[0029] 100 - sampling circuit; 110 - falling edge detection circuit; 1101 - inverter circuit; 1102 - first D flip-flop; 1103 - second D flip-flop; 1104 - third D flip-flop; 1105 - fourth D flip-flop; 1106 - second XOR gate circuit; 120 - rising edge detection circuit; 1201 - fifth D flip-flop; 1202 - sixth D flip-flop; 1203 - seventh D flip-flop; 1204 - eighth D flip-flop; 1205 - third XOR gate circuit; 130 - synchronization circuit; 1301 - first XOR gate circuit; one_wire - single bus signal; one_wire_n - single bus inverted signal; one_wire_a1 - single bus falling edge signal; clk - synchronization clock Clock signal; nedg_q1-first falling edge synchronization signal; nedg_q2-second falling edge synchronization signal; nedg_q3-third falling edge synchronization signal; nedg_pulse-falling edge single pulse signal; one_wire_a2-single bus rising edge signal; psdg_q1-first rising edge synchronization signal; psdg_q2-second rising edge synchronization signal; psdg_q3-third rising edge synchronization signal; psdg_pulse-rising edge single pulse signal; one_sync-single bus synchronization signal; samp_flag-sampling flag signal; one_shift[7:0]-receiving register; 200-chip; 10-slave device; 20-host device. DETAILED DESCRIPTION

[0030] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly refer to one or more of the features. Throughout the description of this application, unless otherwise specified, "plurality" means two or more. Furthermore, "and / or" in the specification and claims refers to at least one of the connected entities, and the character " / " generally indicates an "or" relationship between the connected entities.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0033] As described in the background art, since the single-bus communication protocol has only one line to transmit data, the transmission rate is relatively low. In order to improve the data transmission rate and efficiency, the single-bus communication protocol has an overspeed mode, which improves the overall data transmission rate by increasing the rate of the single-bus signal, optimizing the transmission protocol, etc. However, in overspeed mode, since the frequency of the single-bus signal sent by the host device is relatively high and the clock frequency of the slave device on the bus is relatively low, the synchronization circuit of the slave device uses a low-frequency clock to sample the high-frequency single-bus signal, which may cause missed sampling problems. For example, before the low-frequency clock in the slow clock domain arrives, the high-frequency single-bus signal may have become invalid. In addition, if the clock frequency of the sampling circuit is increased and a higher clock frequency is used to synchronously sample the single-bus data signal, the power consumption of the slave device may increase, affecting the stability and reliability of the system.

[0034] Therefore, for slave devices operating in 1-wire overspeed mode, when using a low-frequency clock to synchronously sample a high-frequency 1-wire signal, missed sampling may occur, causing functional errors. This missed sampling problem primarily occurs when a slow clock domain samples a fast clock domain signal. The high-frequency asynchronous signal becomes invalid before the slow clock domain's low-frequency clock arrives.

[0035] In related technologies, the following three methods can usually be used to achieve synchronous sampling of asynchronous signals:

[0036] First, a synchronizer is used to synchronously sample asynchronous signals. A synchronizer can be understood as asynchronous signal sampling logic consisting of two flip-flops. The first-stage flip-flop may enter a metastable state when sampling the asynchronous signal, but after a delay of one clock cycle, when the second-stage flip-flop samples its output signal, it has recovered to a stable state, preventing the second-stage flip-flop from entering a metastable state, thereby preventing the metastable state from propagating throughout the circuit. However, when using a low-frequency clock in the slow clock domain to synchronously sample an asynchronous signal in the fast clock domain, the synchronizer may cause missed sampling. Before the low-frequency clock in the slow clock domain arrives, the asynchronous signal in the fast clock domain (such as a single bus signal) has already failed, resulting in data loss and functional errors.

[0037] Second, a handshake mechanism is used to synchronize the sampling of asynchronous signals. The handshake mechanism can be understood as adding feedback hold logic to the asynchronous signal within the asynchronous clock domain. The asynchronous signal is not invalidated until the destination clock domain confirms that the asynchronous signal has been synchronously sampled. However, although the handshake mechanism can synchronize signals in different clock domains, it requires additional request and feedback logic on the sender and receiver, which is not allowed for single-bus communication protocols.

[0038] Third, FIFO (First In First Out) is used to synchronously sample asynchronous signals. FIFO consists of a dual-port memory and a set of control logic. One port of the dual-port memory is used to write to the memory, while the other port is used to read from the memory. Reading and writing can be performed simultaneously, and the read / write clocks can be completely different clocks, thereby achieving synchronization of signals in different clock domains. However, since FIFO requires clock signals from two clock sources as FIFO input, this is not allowed in the single-bus communication protocol.

[0039] Based on this, in single-bus overspeed mode, the above-mentioned related technologies have difficulty in achieving the function of synchronously sampling the single-bus signal in single-bus overspeed mode using a low-frequency clock as the synchronization clock. In order to solve the problem of missed sampling when synchronously sampling the single-bus signal in single-bus overspeed mode in the related technologies, the sampling circuit provided in the embodiment of the present application can effectively synchronously sample the single-bus signal in overspeed mode based on the synchronization clock signal of the slave device that is much lower than the single-bus frequency without changing the circuit structure of the host device and the single-bus communication protocol, thereby obtaining a synchronized single-bus synchronization signal.

[0040] Furthermore, after the 1-wire bus signal passes through the sampling circuit of this application, it can also generate corresponding rising-edge pulse signals and falling-edge pulse signals. Due to the characteristics of the 1-wire bus communication protocol, any communication begins with a falling edge initiated by the host. Subsequent circuits can sample the 1-wire bus synchronization signal based on the falling-edge pulse signal, and classify and analyze the 1-wire bus signal based on the rising-edge pulse signal and the falling-edge pulse signal.

[0041] It is understandable that for a slave device operating in a single bus overspeed mode, when a low-frequency clock is used to synchronously sample a high-frequency single bus signal, a metastable problem may occur, causing functional errors. Among them, the metastable problem is an inherent problem that exists when an asynchronous signal is input into the destination clock domain. It is a physical problem of the interaction of asynchronous clock signals caused by the inherent design mechanism of the synchronization circuit. Based on this, the embodiment of the present application can also perform three-level trigger synchronization on the single bus falling edge signal (or single bus rising edge signal) to obtain a stable falling edge synchronization signal (or rising edge synchronization signal) to avoid the propagation of the metastable problem in the circuit.

[0042] In addition, the sampling circuit provided in the embodiment of the present application can also be generally applied to general synchronous circuits of asynchronous signals, and the present application does not impose any specific restrictions on the application scenarios of the sampling circuit.

[0043] In addition, the sampling circuit provided in the embodiment of the present application can also be set on the chip, and the chip can be applied to the slave device, and the slave device effectively samples the single bus signal from the host device through the sampling circuit. The chip, slave device, and host device provided in the embodiment of the present application can be commonly used for related devices and chips of the single bus protocol. For example, it can be applied to the field of consumables, the chip can be a consumable chip, the slave device can be a consumable device, and the host device can be a printer. The consumable device can communicate with the printer through the consumable chip. When its communication protocol is a single bus communication protocol, the sampling circuit provided in the present application can be applied to the consumable chip, consumable device, and printer.

[0044] The technical solution provided by the present invention is described in detail below with reference to the accompanying drawings.

[0045] like Figure 1 As shown, an embodiment of the present application provides a sampling circuit 100 for synchronously sampling a single bus signal, which may include:

[0046] Falling edge detection circuit 110, rising edge detection circuit 120 and synchronization circuit 130; falling edge detection circuit 110 and rising edge detection circuit 120 are respectively connected to synchronization circuit 130;

[0047] The falling edge detection circuit 110 is used to generate a falling edge synchronization signal based on the synchronization clock signal when a falling edge of the single bus signal is detected;

[0048] The rising edge detection circuit 120 is used to generate a rising edge synchronization signal based on the synchronization clock signal when detecting the rising edge of the single bus signal;

[0049] The synchronization circuit 130 is configured to output a single bus synchronization signal according to the falling edge synchronization signal and the rising edge synchronization signal; wherein the frequency of the synchronization clock signal is lower than the frequency of the single bus signal.

[0050] In the embodiment of the present application, the single bus signal can be understood as the sampling object of the sampling circuit, the synchronous clock signal is the sampling clock in the sampling circuit, and the single bus synchronous signal can be understood as the sampling result of the sampling circuit, which is the synchronous signal after the single bus signal is synchronized with the sampling clock.

[0051] In the embodiment of the present application, the frequency of the synchronous clock signal is lower than the frequency of the single bus signal, which can be understood as the need to use a low-frequency clock to synchronously sample the single bus signal in the fast clock domain.

[0052] For example, to avoid loss of sampled single-bus data information, the frequency of the synchronous clock signal used for sampling can be in the range of 500 kHz to 600 kHz, and the period can be in the range of 1.66 μs to 2 μs. For example, the frequency of the synchronous clock signal is 500 kHz, and the period is 2 μs. For another example, the frequency of the synchronous clock signal is 600 kHz, and the period is 1.66 μs.

[0053] In practical applications, the 1-wire bus signal can come from a host device in overspeed mode. When the host device sends data "0" in overspeed mode, the corresponding low-level width of the 1-wire bus signal can be 0.25us. When the host device sends data "1" in overspeed mode, the corresponding low-level width of the 1-wire bus signal can be 6us.

[0054] From this, we can see that when the host device sends data "0" in overdrive mode, the low-level width corresponding to the single-bus signal (for example, 0.25us) is much lower than the period of the synchronous clock signal (for example, 1.66us-2us). Correspondingly, since frequency and period are reciprocal to each other, when the single-bus signal carries data "0", the frequency of the synchronous clock signal is lower than the frequency of the single-bus signal. In this case, the present application can use a low-frequency synchronous clock signal to sample the data "0" of the high-frequency single-bus signal.

[0055] In an embodiment of the present application, when the frequency of the synchronous clock signal is lower than the frequency of the single bus signal, the present application uses a low-frequency clock to synchronously sample the high-frequency single bus signal.

[0056] In the scenario of synchronously sampling a high-frequency single-bus signal using a low-frequency clock, the present application first generates a falling-edge synchronization signal based on the synchronization clock signal when a falling-edge detection circuit detects the falling edge of the single-bus signal, and generates a rising-edge synchronization signal based on the synchronization clock signal when a rising-edge detection circuit detects the rising edge of the single-bus signal. Then, a single-bus synchronization signal is generated based on the falling-edge synchronization signal and the rising-edge synchronization signal. This effectively synchronously samples the single-bus signal and ensures the validity of the sampled single-bus synchronization signal. Furthermore, compared with the related art that uses a synchronization circuit to directly synchronously sample the single-bus signal itself using a sampling clock, this avoids the problem of missed sampling when synchronously sampling a high-frequency single-bus signal.

[0057] According to the sampling circuit provided by the embodiment of the present application, it includes a falling edge detection circuit, a rising edge detection circuit and a synchronization circuit; the falling edge detection circuit and the rising edge detection circuit are respectively connected to the synchronization circuit; the falling edge detection circuit is used to generate a falling edge synchronization signal based on a synchronization clock signal when a falling edge of a single bus signal is detected; the rising edge detection circuit is used to generate a rising edge synchronization signal based on the synchronization clock signal when a rising edge of the single bus signal is detected; the synchronization circuit is used to output a single bus synchronization signal based on the falling edge synchronization signal and the rising edge synchronization signal; wherein the frequency of the synchronization clock signal is lower than the frequency of the single bus signal. In this way, in the scenario where a low-frequency clock is used to synchronously sample a high-frequency single-bus signal, the present application first generates a falling edge synchronization signal based on the synchronization clock signal when the falling edge of the single-bus signal is detected by the falling edge detection circuit, and generates a rising edge synchronization signal based on the synchronization clock signal when the rising edge of the single-bus signal is detected by the rising edge detection circuit. Then, a single-bus synchronization signal is generated based on the falling edge synchronization signal and the rising edge synchronization signal. This can effectively synchronously sample the single-bus signal and ensure the validity of the sampled single-bus synchronization signal. Compared with the related art that uses a synchronization circuit to directly synchronously sample the single-bus signal itself through the sampling clock, this avoids the problem of missed sampling when synchronously sampling a high-frequency single-bus signal.

[0058] In a specific embodiment, Figure 2 As shown, in the sampling circuit, the falling edge detection circuit 110 may include: an inverter circuit 1101, a first D flip-flop 1102, a second D flip-flop 1103, a third D flip-flop 1104 and a fourth D flip-flop 1105;

[0059] Among them, the input end of the inverter circuit 1101 is used to receive a single bus signal, and the output end of the inverter circuit 1101 is connected to the clock pin of the first D flip-flop 1102; the inverting output end of the first D flip-flop 1102 is connected to the input end of the first D flip-flop 1102, and the output end of the first D flip-flop 1102 is connected to the input end of the second D flip-flop 1103; the clock pin of the second D flip-flop 1103, the clock pin of the third D flip-flop 1104 and the clock pin of the fourth D flip-flop 1105 are all used to receive a synchronous clock signal, the output end of the second D flip-flop 1103 is connected to the input end of the third D flip-flop 1104, and the output end of the third D flip-flop 1104 is connected to the input end of the fourth D flip-flop 1105.

[0060] exist Figure 2In the example, one_wire is a single bus signal, and clk is a synchronous clock signal, which can be understood as the sampling clock of sampling circuit 100. The single bus signal one_wire first passes through inverter circuit 1101 and outputs a single bus inverse signal one_wire_n. The single bus inverse signal one_wire_n can serve as the clock terminal of the first D flip-flop 1102. The inverse output terminal (i.e., the Q pin) of the first D flip-flop 1102 serves as the input terminal (i.e., the D pin) of the first-stage flip-flop. The output terminal (i.e., the Q pin) of the first D flip-flop 1102 serves as the input terminal (i.e., the D pin) of the second D flip-flop 1103, and so on, all the way to the fourth D flip-flop 1105.

[0061] In the embodiment of the present application, the frequency of the synchronous clock signal is lower than the frequency of the single bus signal. It can be seen that the low level width of the single bus signal one_wire is smaller than the period of the synchronous clock signal clk. Figure 3 As shown, the low-level width of the single-bus signal one_wire has a one-to-one correspondence with the type of the single-bus signal. For example, the low-level width of the single-bus signal one_wire when writing data "1" is smaller than the low-level width of the single-bus signal one_wire when writing data "0". The low-level width of the single-bus signal one_wire when writing data "1" is smaller than the period of the synchronous clock signal clk, indicating that the frequency of the single-bus signal when writing data "1" is higher than the frequency of the synchronous clock signal.

[0062] like Figure 5 As shown, in falling edge detection circuit 110, each time a falling edge occurs in single-bus signal one_wire, falling edge signal one_wire_a1 is negated. Subsequently, the sampling synchronization clock signal clk synchronizes the falling edge signal one_wire_a1 through three stages of triggers. The outputs of the last two stages of triggers are then passed through an exclusive-OR gate to generate a falling edge single pulse signal nedg_pulse. Because three stages of trigger synchronization have been performed on the falling edge signal one_wire_a1, the second and third falling edge synchronization signals nedg_q2 and nedg_q3 output by the last two stages of triggers are stable, thus avoiding metastability issues.

[0063] In a specific embodiment, Figure 2 As shown, the rising edge detection circuit 120 may include: a fifth D flip-flop 1201 , a sixth D flip-flop 1202 , a seventh D flip-flop 1203 and an eighth D flip-flop 1204 ;

[0064] Among them, the clock pin of the fifth D flip-flop 1201 is used to receive a single bus signal, the inverting output terminal of the fifth D flip-flop 1201 is connected to the input terminal of the fifth D flip-flop 1201, and the output terminal of the fifth D flip-flop 1201 is connected to the input terminal of the sixth D flip-flop 1202; the clock pin of the sixth D flip-flop 1202, the clock pin of the seventh D flip-flop 1203 and the clock pin of the eighth D flip-flop 1204 are all used to receive a synchronous clock signal, the output terminal of the sixth D flip-flop 1202 is connected to the input terminal of the seventh D flip-flop 1203, and the output terminal of the seventh D flip-flop 1203 is connected to the input terminal of the eighth D flip-flop 1204.

[0065] like Figure 2 As shown, in the rising edge detection circuit 120, the single bus signal one_wire can be used as the clock terminal of the first-stage flip-flop (i.e., the fifth D flip-flop 1201), and the inverting output terminal of the first-stage flip-flop can be used as the input terminal of the first-stage flip-flop. The output terminal of the first-stage flip-flop can be used as the input terminal of the second-stage flip-flop, and so on, all the way to the fourth-stage flip-flop (i.e., the eighth D flip-flop 1204).

[0066] like Figure 7 As shown, in rising edge detection circuit 120, because the frequency of the synchronous clock signal is lower than that of the single-bus signal, the low-level width of the single-bus signal one_wire is significantly shorter than the period of the synchronous clock signal clk. Each time a rising edge occurs in the single-bus signal one_wire, the single-bus rising-edge signal one_wire_a2 is negated. The synchronous clock signal clk, used for sampling, then synchronizes the single-bus rising-edge signal one_wire_a2 with three stages of triggers. The outputs of the last two stages of triggers are then passed through an exclusive-OR gate to generate a rising-edge single pulse signal psdg_pulse. Because the single-bus rising-edge signal one_wire_a2 has undergone three stages of trigger synchronization, the second rising-edge synchronization signal psdg_q2 and the third rising-edge synchronization signal psdg_q3 output by the last two stages of triggers are stable, thus avoiding metastability issues.

[0067] like Figure 2 As shown, in the sampling circuit provided in the present application, the synchronization circuit 130 may include: a first XOR gate circuit 1301;

[0068] The first input terminal of the first XOR gate circuit 1301 is connected to the output terminal of the fourth D flip-flop 1205 , and the second input terminal of the first XOR gate circuit 1301 is connected to the output terminal of the eighth D flip-flop 1204 .

[0069] exist Figure 2In the figure, one_wire is a single bus signal, clk is a synchronous clock signal, and one_sync is a synchronous signal obtained by sampling the single bus signal one_wire with the synchronous clock. Synchronization circuit 130 performs an exclusive OR operation on the third falling-edge synchronization signal nedg_q3 and the third rising-edge synchronization signal psdg_q3 output by the last-stage flip-flops of rising-edge detection circuit 110 and falling-edge detection circuit 120 to generate the single bus synchronization signal one_sync.

[0070] For example, in Figure 2 In the embodiment, the falling edge synchronization signal may include: a first falling edge synchronization signal nedg_q1, a second falling edge synchronization signal nedg_q2 and a third falling edge synchronization signal nedg_q3; the inverter circuit 1101 is used to output the single bus inversion signal one_wire_n according to the single bus signal one_wire, the first D flip-flop 1102 is used to output the single bus falling edge signal one_wire_a1 at the inverting output end according to the single bus inversion signal one_wire_n, the second D flip-flop 1103 is used to output the first falling edge synchronization signal nedg_q1 according to the synchronization clock signal clk and the single bus falling edge signal one_wire_a1, the third D flip-flop 1104 is used to output the second falling edge synchronization signal nedg_q2 according to the synchronization clock signal clk and the first falling edge synchronization signal nedg_q1, and the fourth D flip-flop 1105 is used to output the third falling edge synchronization signal nedg_q3 according to the synchronization clock signal clk and the second falling edge synchronization signal nedg_q2.

[0071] exist Figure 2 In the embodiment, the rising edge synchronization signal includes: a first rising edge synchronization signal psdg_q1, a second rising edge synchronization signal psdg_q2 and a third rising edge synchronization signal psdg_q3; the fifth D flip-flop 1201 is used to output the single bus rising edge signal one_wire_a2 at the inverting output terminal according to the single bus signal one_wire, the sixth D flip-flop 1202 is used to output the first rising edge synchronization signal psdg_q1 according to the synchronization clock signal clk and the single bus rising edge signal one_wire_a2, the seventh D flip-flop 1203 is used to output the second rising edge synchronization signal psdg_q2 according to the synchronization clock signal clk and the first rising edge synchronization signal psdg_q1, and the eighth D flip-flop 1204 is used to output the third rising edge synchronization signal psdg_q3 according to the synchronization clock signal clk and the second rising edge synchronization signal psdg_q2.

[0072] exist Figure 2In the embodiment, the first XOR gate circuit 1301 is used to output the single bus synchronization signal one_sync according to the third falling edge synchronization signal nedg_q3 and the third rising edge synchronization signal psdg_q3.

[0073] like Figure 3 As shown, the falling edge signal one_wire_a1 and the rising edge signal one_wire_a2 of the single-bus signal one_wire are inverted at the falling and rising edges, respectively. In single-bus overspeed mode, when the single-bus signal one_wire is written "1", the single-bus synchronization signal one_sync is not pulled low. When writing "0", the single-bus synchronization signal one_sync is synchronized to the corresponding low level. According to the single-bus communication protocol, when receiving data, the slave device samples the synchronized single-bus synchronization signal one_sync after detecting the falling edge of the single-bus signal. When the master device's one_wire signal is written "1", the slave device detects the falling edge and samples one_sync as high, correctly sampling the data "1". When the master device's one_wire signal is written "0", the slave device detects the falling edge and samples one_sync as low, correctly sampling the data "0".

[0074] In another specific embodiment, the sampling circuit provided by the present application can also output a falling edge single pulse signal. For example, Figure 4 As shown, the falling edge detection circuit 110 may further include: a second XOR gate circuit 1106; the first input terminal of the second XOR gate circuit 1106 is connected to the output terminal of the third D flip-flop 1104, and the second input terminal of the second XOR gate circuit 1106 is connected to the output terminal of the fourth D flip-flop 1105.

[0075] Among them, the falling edge single pulse signal nedg_pulse can be understood as a single-cycle pulse signal that detects the falling edge of the single bus signal one_wire; the second falling edge synchronization signal nedg_q2 output from the output end of the third D flip-flop 1104 and the third falling edge synchronization signal nedg_q3 output from the output end of the fourth D flip-flop 1105 are passed through the second XOR gate circuit 1106 to obtain the falling edge single pulse signal nedg_pulse.

[0076] like Figure 4 As described above, in the falling edge detection circuit, the second XOR gate circuit 1106 is used to output a falling edge single pulse signal nedg_pulse according to the second falling edge synchronization signal nedg_q2 and the third falling edge synchronization signal nedg_q3; the falling edge single pulse signal nedg_pulse is used to sample the single bus synchronization signal one_sync.

[0077] For example, in single-bus overspeed mode, when the single-bus signal one_wire writes "1", the single-bus synchronization signal one_sync will not be pulled low. When writing "0", the single-bus synchronization signal one_sync will be synchronized to the corresponding low level. According to the single-bus communication protocol, during the data reception phase, after detecting the falling edge of the single-bus signal, the slave starts sampling the synchronized single-bus synchronization signal one_sync. When the master device's one_wire signal writes "1", the slave detects the falling edge (that is, based on the falling edge single pulse signal nedg_pulse being high), and starts sampling one_sync at a high level, and can correctly sample the "1" data. When the master device's one_wire signal writes "0", the slave device detects the falling edge (that is, based on the falling edge single pulse signal nedg_pulse being high), and samples one_sync at a low level, and can correctly sample the "0" data.

[0078] In addition, if Figure 5 As shown, since the single bus falling edge signal one_wire_a1 has been synchronized with three levels of triggers, the second falling edge synchronization signal nedg_q2 and the third falling edge synchronization signal nedg_q3 output by the last two levels of triggers are stable. Furthermore, the falling edge single pulse signal nedg_pulse obtained by performing an XOR operation on the second falling edge synchronization signal nedg_q2 and the third falling edge synchronization signal nedg_q3 is also stable, which can avoid the metastable problem.

[0079] In another specific embodiment, the sampling circuit provided by the present application can also output a rising edge single pulse signal. For example, Figure 6 As shown, the rising edge detection circuit 120 further includes: a third XOR gate circuit 1205;

[0080] A first input terminal of the third XOR gate circuit 1205 is connected to the output terminal of the seventh D flip-flop 1203 , and a second input terminal of the third XOR gate circuit 1205 is connected to the output terminal of the eighth D flip-flop 1204 .

[0081] Among them, the rising edge single pulse signal psdg_pulse can be understood as a single-cycle pulse signal that detects the rising edge of the single bus signal one_wire; the second rising edge synchronization signal psdg_q2 output from the output end of the seventh D flip-flop 1203 and the third falling edge synchronization signal psdg_q3 output from the output end of the eighth D flip-flop 1204 are passed through the third XOR gate circuit 1205 to obtain the rising edge single pulse signal psdg_pulse.

[0082] like Figure 6As shown, in the rising edge detection circuit 120, the third XOR gate circuit 1205 is used to output a rising edge single pulse signal psdg_pulse according to the second rising edge synchronization signal psdg_q2 and the third rising edge synchronization signal psdg_q3; the rising edge single pulse signal psdg_pulse and the falling edge single pulse signal nedg_pulse are used for classification analysis of the single bus signal one_wire.

[0083] It can be understood that the present application can determine the width of the single bus synchronization signal one_sync according to the falling edge single pulse signal nedg_pulse and the rising edge single pulse signal psdg_pulse, and further determine the type of the single bus signal one_wire.

[0084] For example, the present application can start sampling and counting the single-wire synchronization signal one_sync when the falling-edge single-pulse signal nedg_pulse is at a high level; end sampling and counting the single-wire synchronization signal one_sync when the rising-edge single-pulse signal psdg_pulse is at a high level, and obtain a count value. The count value is used to obtain the width of the single-wire synchronization signal one_sync, and the single-wire signal one_wire is classified and analyzed based on the width of the single-wire synchronization signal one_sync.

[0085] Among them, the width of the single bus synchronization signal one_sync has a one-to-one correspondence with the type of the single bus signal one_wire. The type of the single bus signal one_wire includes but is not limited to writing data "1" in overspeed mode, writing data "0" in overspeed mode, writing data "1" in normal mode, writing data "0" in normal mode, reset pulse, etc.

[0086] In addition, if Figure 7 As shown, since the single bus rising edge signal one_wire_a2 has been synchronized with three levels of triggers, the second rising edge synchronization signal psdg_q2 and the third rising edge synchronization signal psdg_q3 output by the last two levels of triggers are stable. Furthermore, the rising edge single pulse signal psdg_pulse obtained by performing an XOR operation on the second rising edge synchronization signal psdg_q2 and the third rising edge synchronization signal psdg_q3 is also stable, which can avoid the metastable problem.

[0087] Based on the concept similar to the sampling circuit provided in the embodiment of the present application, the embodiment of the present application can also provide a chip. Figure 8 As shown, the chip 200 provided in the embodiment of the present application may include the sampling circuit 100 provided in any of the above embodiments.

[0088] Based on the concept similar to the sampling circuit provided in the embodiment of the present application, the embodiment of the present application also provides a slave device. Figure 9 As shown, the chip 200 can be applied to a slave device 10 . The slave device 10 provided in the embodiment of the present application can include the sampling circuit 100 provided in any of the above embodiments.

[0089] Based on a concept similar to the sampling circuit provided in the embodiment of the present application, the embodiment of the present application also provides a communication system. Figure 10 As shown, the communication system provided by the embodiment of the present application may include a host device 20 and a slave device 10, wherein the host device 20 communicates with the slave device 10 via a single bus communication protocol; wherein the host device 20 may send a single bus signal to the slave device 10 so that the sampling circuit 100 samples the single bus signal.

[0090] Among them, such as Figure 9 As shown, the sampling circuit 100 may be provided on a chip 200 .

[0091] Among them, such as Figure 9 and Figure 10 As shown, the slave device 10 provided in an embodiment of the present application can be used to communicate with the host device 20 through a single bus communication protocol, wherein the slave device 10 may include: a sampling circuit 100 provided in any of the above embodiments; wherein the falling edge detection circuit 110 and the rising edge detection circuit 120 of the sampling circuit 100 are used to receive the single bus signal from the host device 20.

[0092] For example, in practical applications, Figure 11 As shown, the master device 20 continuously transmits data 8'h55, and the slave device 10 synchronously samples the single bus signal one_wire and receives the data 8'h55 in the receive register one_shift[7:0] (where "55" in hexadecimal corresponds to "01010101" in binary). When the single bus signal one_wire is written as 1, its low-level width corresponds to 0.25µs, and when it is written as 0, its low-level width corresponds to 6µs. The period of the synchronous clock signal clk used for sampling can be 1.66µs.

[0093] exist Figure 11 In the receiving register one_shift[7:0], the numbers are all expressed in hexadecimal. Of course, this application can use other bases and perform base conversion, which is not specifically limited here.

[0094] like Figure 11As shown in the figure, when a single-bus signal is written, single-cycle pulse signals (i.e., nedg_pulse and psdg_pulse) are generated on the falling and rising edges of the single-bus signal. Based on the falling single-edge pulse signal nedg_pulse, the slave device begins collecting 1 bit of data. The sampling flag signal samp_flag is set high two sampling cycles after the falling single-edge pulse signal nedg_pulse. Based on the sampling flag signal samp_flag, the slave device stores the sampled single-bus signal in the receive register one_shift[7:0]. At this time, if the single-bus synchronization signal one_sync is high, it indicates that the master is sending "1" data; if the single-bus synchronization signal one_sync is low, it indicates that the master is sending "0" data.

[0095] In summary, the sampling circuit provided in the present application can accurately and synchronously sample the single bus signal when the clock frequency of the slave device is much lower than the frequency of the single bus signal in the single bus overspeed mode.

[0096] In addition, the above-described scheme is a case where the master device writes data "0" or "1" and the slave device reads data "0" or "1". In actual applications, this application may also include a case where the slave device writes data "0" or "1" and the master device reads data "0" or "1".

[0097] For example, the master device sends a read enable low-level pulse with a width of 0.25µs. During the 1-wire protocol phase where the master device reads data, the master typically pulls the 1-wire bus low and waits for at least 0.25µs before releasing the bus and handing it over to the slave device. The slave device then writes data "0" or "1" via the 1-wire bus signal, and the master device waits for the slave device to pull the bus low for 0.25µs before reading the data from the 1-wire bus.

[0098] Specifically, when a slave device writes data "0" or "1" via a single bus signal, if the slave device sends data "0," it can continue to pull the single bus low after sending the data "0," extending the low-level width corresponding to the data "0" and ensuring that the host device can effectively read the single bus data "0." If the slave device sends data "1," it can pull the single bus high when the host device releases the single bus (i.e., immediately pull the single bus high after the host device releases the single bus) to avoid loss of single bus data information read by the host device.

[0099] It can be understood that the chip, slave device and communication system provided in the embodiments of the present application can realize all the functions of the sampling circuit and achieve the same technical effects. To avoid repetition, they will not be described here.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the present invention.

Claims

1. A sampling circuit, characterized in that: include: Falling edge detection circuit, rising edge detection circuit and synchronization circuit; The falling edge detection circuit and the rising edge detection circuit are respectively connected to the synchronization circuit; The falling edge detection circuit is used to generate a falling edge synchronization signal based on the synchronization clock signal when detecting the falling edge of the single bus signal; The rising edge detection circuit is used to generate a rising edge synchronization signal based on the synchronization clock signal when detecting the rising edge of the single bus signal; The synchronization circuit is used to output a single bus synchronization signal according to the falling edge synchronization signal and the rising edge synchronization signal; wherein the frequency of the synchronization clock signal is lower than the frequency of the single bus signal.

2. The sampling circuit according to claim 1, wherein: The falling edge detection circuit includes: an inverter circuit, a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; The input end of the inverter circuit is used to receive the single bus signal, and the output end of the inverter circuit is connected to the clock pin of the first D flip-flop; the inverting output end of the first D flip-flop is connected to the input end of the first D flip-flop, and the output end of the first D flip-flop is connected to the input end of the second D flip-flop; the clock pin of the second D flip-flop, the clock pin of the third D flip-flop, and the clock pin of the fourth D flip-flop are all used to receive a synchronous clock signal, the output end of the second D flip-flop is connected to the input end of the third D flip-flop, and the output end of the third D flip-flop is connected to the input end of the fourth D flip-flop.

3. The sampling circuit according to claim 2, wherein: The rising edge detection circuit includes: a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop and an eighth D flip-flop; Among them, the clock pin of the fifth D flip-flop is used to receive the single bus signal, the inverting output end of the fifth D flip-flop is connected to the input end of the fifth D flip-flop, and the output end of the fifth D flip-flop is connected to the input end of the sixth D flip-flop; the clock pin of the sixth D flip-flop, the clock pin of the seventh D flip-flop and the clock pin of the eighth D flip-flop are all used to receive a synchronous clock signal, the output end of the sixth D flip-flop is connected to the input end of the seventh D flip-flop, and the output end of the seventh D flip-flop is connected to the input end of the eighth D flip-flop.

4. The sampling circuit according to claim 3, wherein: The synchronization circuit includes: a first XOR gate circuit; The first input terminal of the first XOR gate circuit is connected to the output terminal of the fourth D flip-flop, and the second input terminal of the first XOR gate circuit is connected to the output terminal of the eighth D flip-flop.

5. The sampling circuit according to claim 4, characterized in that: The falling edge synchronization signal includes: a first falling edge synchronization signal, a second falling edge synchronization signal and a third falling edge synchronization signal; in the falling edge detection circuit, the inverter circuit is used to output a single bus inversion signal according to the single bus signal, the first D flip-flop is used to output a single bus falling edge signal at the inversion output end according to the single bus inversion signal, the second D flip-flop is used to output a first falling edge synchronization signal according to the synchronous clock signal and the single bus falling edge signal, the third D flip-flop is used to output a second falling edge synchronization signal according to the synchronous clock signal and the first falling edge synchronization signal, and the fourth D flip-flop is used to output a third falling edge synchronization signal according to the synchronous clock signal and the second falling edge synchronization signal; The rising edge synchronization signal includes: a first rising edge synchronization signal, a second rising edge synchronization signal and a third rising edge synchronization signal; in the rising edge detection circuit, the fifth D flip-flop is used to output a single bus rising edge signal at the inverting output terminal according to the single bus signal, the sixth D flip-flop is used to output a first rising edge synchronization signal according to the synchronous clock signal and the single bus rising edge signal, the seventh D flip-flop is used to output a second rising edge synchronization signal according to the synchronous clock signal and the first rising edge synchronization signal, and the eighth D flip-flop is used to output a third rising edge synchronization signal according to the synchronous clock signal and the second rising edge synchronization signal; In the synchronization circuit, the first XOR gate circuit is used to output a single bus synchronization signal according to the third falling edge synchronization signal and the third rising edge synchronization signal.

6. The sampling circuit according to claim 5, characterized in that: The falling edge detection circuit further includes: a second XOR gate circuit; The first input terminal of the second XOR gate circuit is connected to the output terminal of the third D flip-flop, and the second input terminal of the second XOR gate circuit is connected to the output terminal of the fourth D flip-flop.

7. The sampling circuit according to claim 6, characterized in that: In the falling edge detection circuit, the second XOR gate circuit is used to output a falling edge single pulse signal according to the second falling edge synchronization signal and the third falling edge synchronization signal; the falling edge single pulse signal is used to sample the single bus synchronization signal.

8. The sampling circuit according to claim 7, wherein: The rising edge detection circuit further includes: a third XOR gate circuit; The first input terminal of the third XOR gate circuit is connected to the output terminal of the seventh D flip-flop, and the second input terminal of the third XOR gate circuit is connected to the output terminal of the eighth D flip-flop.

9. The sampling circuit according to claim 8, characterized in that: In the rising edge detection circuit, the third XOR gate circuit is used to output a rising edge single pulse signal based on the second rising edge synchronization signal and the third falling edge synchronization signal; the rising edge single pulse signal and the falling edge single pulse signal are used for classification analysis of the single bus signal.

10. A chip, characterized in that: include: The sampling circuit according to any one of claims 1 to 9, wherein the chip is applied to a slave device.

11. A slave device for communicating with a host device via a single bus communication protocol, characterized in that: include: The sampling circuit according to any one of claims 1 to 9, wherein the falling edge detection circuit and the rising edge detection circuit of the sampling circuit are used to receive a single bus signal from a host device.

12. A communication system, characterized in that: include: A host device and a slave device, wherein the host device communicates with the slave device via a single bus communication protocol; the slave device comprises the sampling circuit according to any one of claims 1 to 9; The falling edge detection circuit and the rising edge detection circuit of the sampling circuit are used to receive a single bus signal from a host device.

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