Successive approximation analog-to-digital converter linearity correction circuit and correction method

Abstract

The invention provides a linearity correction circuit and a linearity correction method for a successive approximation analog-to-digital converter, which are applied to the technical field of semiconductor integrated circuit design and are used for multiplexing part of capacitors in an analog-to-digital converter capacitor array to inject jitter noise so as to improve the linearity of an SAR ADC under small input amplitude and improve the linearity of the SAR ADC under small input amplitude in a sampling stage. An input signal is coupled to an upper pole plate of the DAC capacitor array, and meanwhile, a lower pole plate of the multiplexing capacitor unit is connected to a reference voltage controlled by a dither signal; after a phase is sampled and before the phase is converted, a lower pole plate of a multiplexing capacitor unit is switched to a fixed reference voltage, random jitter noise is injected at the moment, after the voltage of a top pole plate of a capacitor array is established stably, a comparator is enabled, successive approximation conversion is started, and the jitter noise is injected by multiplexing part of capacitors in the existing CDAC capacitor array, so that the random jitter noise is generated. The random jitter noise injection by using an extra capacitor array is avoided, the circuit design is simplified, the circuit cost and power consumption are reduced, and the linearity of the SAR ADC is improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit design, and in particular to a successive approximation analog-to-digital converter linearity correction circuit and correction method. Background Art

[0002] In current wireless communication transceiver link systems, a receiving link generally uses a Successive Approximation Analog-to-Digital Converter (SAR ADC) for analog-to-digital conversion.

[0003] However, SAR ADC has extremely high requirements on linearity under low input signal amplitude, especially in the digital predistortion (DPD) mode scenario. This is because at low input amplitude, the impact of capacitor array mismatch on linearity is most serious, thus affecting the overall performance of the ADC.

[0004] To improve the linearity of a SAR ADC, linearity calibration is usually required. Traditional SAR ADC linearity calibration solutions typically inject a set of dither noise into the capacitor array. By injecting a dither signal generated by a pseudo-random number, the mismatch of the capacitor array can be dispersed. Although this can improve linearity, this traditional solution has the following disadvantages:

[0005] First, the additional dither injection capacitor array not only increases the hardware cost, but also increases the complexity of the logic control circuit;

[0006] Second, complex logic control circuits are required to manage the dither injection process, further increasing the design cost;

[0007] Third, additional circuit elements will lead to increased area and power consumption.

[0008] Based on this, a new linearity correction scheme for successive approximation analog-to-digital converters is needed. Summary of the Invention

[0009] In view of this, the embodiments of this specification provide a successive approximation analog-to-digital converter linearity correction circuit and correction method, which injects dither noise (dither) by reusing the existing CDAC capacitor array, avoiding the additional addition of a dither injection capacitor array, thereby simplifying the dither injection control logic and reducing hardware cost and design complexity.

[0010] The embodiments of this specification provide the following technical solutions:

[0011] In a first aspect, an embodiment of the present disclosure provides a successive approximation analog-to-digital converter linearity correction circuit, comprising:

[0012] A sampling module is used to sample and hold an input signal, the sampling module comprising: a sampling switch connected between the input signal and the capacitor array of the analog-to-digital converter;

[0013] The sampling module is configured as follows: during a sampling phase, the sampling switch is in a closed state to couple the input signal to the analog-to-digital converter capacitor array; from the end of the sampling phase to the beginning of the conversion phase, the sampling switch is in an open state to maintain the charge on the analog-to-digital converter capacitor array;

[0014] An analog-to-digital converter capacitor array includes a plurality of capacitor units, wherein some of the capacitor units are used as multiplexed capacitor units for jitter noise injection;

[0015] The capacitor unit is configured as follows: in the sampling phase: in the non-multiplexed capacitor unit, the bottom plate of the highest-order capacitor is connected to the first reference voltage, and the bottom plates of the remaining capacitors are connected to the second reference voltage; the bottom plates of the multiplexed capacitor units at both ends of the differential are respectively connected to the second reference voltage or the first reference voltage controlled by the pseudo-random number and the inverse of the pseudo-random number; after the sampling phase and before the conversion phase, the bottom plate of the multiplexed capacitor unit is switched to the second reference voltage to inject jitter noise; the connection state of the bottom plates of the remaining capacitors remains unchanged; wherein the voltage value of the second reference voltage is higher than the voltage value of the first reference voltage;

[0016] a dynamic comparator connected to the output end of the capacitor array of the analog-to-digital converter, for comparing the voltage difference between the output nodes and converting the voltage difference into a digital signal output;

[0017] The register logic module of the successive approximation analog-to-digital converter is connected to the output end of the dynamic comparator and is used to control the switching of the capacitor array of the analog-to-digital converter according to the output result of the dynamic comparator to approximate the input signal bit by bit and generate a digital output code.

[0018] The embodiments of this specification are applied in a communication transceiver link system. By reusing some capacitor units in the existing analog-to-digital converter capacitor array (CDAC capacitor array), they are reused as jitter noise injection capacitors. The jitter noise injection capacitors are used to inject random jitter noise controlled by pseudo-random numbers to break up the capacitor array mismatch and improve linearity. This significantly improves the linearity and overall performance of the SAR ADC, while simplifying the circuit design and reducing power consumption.

[0019] In combination with the first aspect, in one possible implementation, the sampling switch includes: a non-inverting input switch and an inverting input switch, the non-inverting input switch is connected between the positive input signal and the positive end top plate node of the analog-to-digital converter capacitor array, and the inverting input switch is connected between the negative input signal and the negative end top plate node of the analog-to-digital converter capacitor array.

[0020] In this implementation, by adopting a sampling switch design with a non-inverting input switch and an inverting input switch, the positive and negative input signals can be accurately sampled respectively, which helps to reduce signal cross-interference and significantly improves the accuracy of signal sampling and the overall performance of the SAR ADC.

[0021] In combination with the first aspect, in one possible implementation, the pseudo-random number is a binary number, which is used to control the bottom plate level of the positive-end multiplexed capacitor unit in the analog-to-digital converter capacitor array; the inverse of the pseudo-random number is used to control the bottom plate level of the negative-end multiplexed capacitor unit in the analog-to-digital converter capacitor array.

[0022] In this implementation, pseudo-random numbers and their complements are used to control the bottom plate levels of the positive and negative multiplexed capacitors in the capacitor array of an analog-to-digital converter (CDAC). This allows for effective injection of dither noise without adding additional hardware cost, helping to break up capacitor array mismatches and significantly enhancing the linearity of the successive approximation analog-to-digital converter (SAR ADC). This eliminates the need for dedicated dither injection circuits, simplifies circuit design, and effectively reduces power consumption and area.

[0023] With reference to the first aspect, in one possible implementation, the level switching timing of the pseudo-random number is synchronized with the edge of the sampling clock;

[0024] After the sampling phase ends and before the comparator clock enable signal takes effect, the bottom plate voltage of the reused capacitor is switched from a level controlled by a pseudo-random number to a second reference voltage, and random jitter noise is injected after the top plate voltage of the capacitor array is established and stabilized.

[0025] In this implementation, timing control is used to precisely control the jitter noise injection into the SAR ADC, simplifying the design and ensuring that the jitter noise injection matches the SAR ADC sampling and conversion process. This optimizes the linearity of the SAR ADC at low input amplitudes and avoids errors caused by voltage instability during the conversion process, ensuring the accuracy of the conversion results.

[0026] With reference to the first aspect, in a possible implementation, the multiplexed capacitor unit includes capacitor units C5 to C8 in the analog-to-digital converter capacitor array.

[0027] In this implementation, random jitter noise is injected in the analog domain to randomize and break up the harmonics introduced by capacitor array mismatch. Then, after the conversion, the code value of the injected random jitter noise is subtracted in the digital domain. This reduces the error caused by capacitor mismatch and significantly improves the linearity of the SAR ADC without adding additional hardware burden.

[0028] In conjunction with the first aspect, in a possible implementation, the successive approximation analog-to-digital converter linearity correction circuit further includes: a boundary protection circuit;

[0029] The boundary protection circuit is connected to the output end of the register logic module of the successive approximation analog-to-digital converter, and is used to forcibly set the output code according to the output result of the dynamic comparator.

[0030] This implementation can prevent the SAR ADC output code polarity from flipping when a large-amplitude signal is input and a dither is injected simultaneously, significantly enhancing the robustness of the SAR ADC when processing out-of-band input signals, improving the reliability of the conversion results, and optimizing the overall performance.

[0031] In combination with the first aspect, in one possible implementation, when the comparison results of the preset number of times in each conversion cycle of the register logic module of the successive approximation analog-to-digital converter are all 0, the boundary protection circuit forces the output code to be set to all 0; when the comparison results of the preset number of times in each conversion cycle of the register logic module of the successive approximation analog-to-digital converter are added to the weight of the multiplexed capacitor injected with jitter noise to be all 1, or a carry occurs in the highest bit, the boundary protection circuit forces the output code to be set to all 1.

[0032] In this implementation, the sensitivity of the boundary protection circuit is adjusted according to actual needs, so that changes in the input signal are handled more robustly, output errors caused by signal fluctuations are reduced, and functional errors introduced by SAR ADC due to changes in input signal amplitude are avoided.

[0033] In a second aspect, an embodiment of the present specification further provides a method for correcting a linearity correction circuit of a successive approximation analog-to-digital converter, which is implemented based on the linearity correction circuit of the successive approximation analog-to-digital converter described in the first aspect or any one of the first aspects. The method for correcting the linearity correction circuit of the successive approximation analog-to-digital converter includes:

[0034] During a sampling phase, the sampling switch is closed to transfer the input signal to the analog-to-digital converter capacitor array for sampling; wherein the analog-to-digital converter capacitor array includes a plurality of capacitor units, some of which are used as multiplexed capacitor units for jitter noise injection;

[0035] Connecting the bottom plates of the multiplexed capacitor units at both ends of the differential to a second reference voltage or a first reference voltage controlled by a pseudo-random number and the inverse of the pseudo-random number; connecting the bottom plate of the highest-order capacitor in the non-multiplexed capacitor to the first reference voltage, and connecting the bottom plates of the remaining capacitors to the second reference voltage;

[0036] Between the end of the sampling phase and the beginning of the conversion phase, the sampling switch is turned off, and the bottom plate of the reused capacitor unit is switched to a second reference voltage to inject jitter noise; wherein the voltage value of the second reference voltage is higher than the voltage value of the first reference voltage;

[0037] In a conversion phase, a dynamic comparator is used to compare the voltage difference between the output nodes of the capacitor array of the analog-to-digital converter, and the voltage difference is converted into a digital signal output;

[0038] According to the output result of the dynamic comparator, a register logic module of a successive approximation analog-to-digital converter is used to control the switching of the analog-to-digital converter capacitor array to approximate the input signal bit by bit and generate a digital output code.

[0039] The embodiments of this specification are applied in a wireless communication transceiver link system. By multiplexing jitter noise injection capacitors to inject random jitter noise controlled by pseudo-random numbers, the impact of capacitor array mismatch on conversion linearity is effectively reduced, and the linearity of the ADC at low input amplitudes is improved. During the conversion stage, the dynamic comparator and the register logic module of the successive approximation analog-to-digital converter work together to accurately approximate the input signal bit by bit and generate an accurate digital output code. This not only improves the linearity of the SAR ADC at low input amplitudes, such as in digital pre-distortion (DPD) mode scenarios, but also simplifies circuit design, reduces power consumption, and eliminates the need for additional hardware support, thereby achieving cost-effective, high-performance analog-to-digital conversion.

[0040] In conjunction with the second aspect, in a possible implementation, the level switching timing of the pseudo-random number is synchronized with the edge of the sampling clock;

[0041] After the sampling phase ends and before the comparator clock enable signal takes effect, the bottom plate voltage of the reused capacitor is switched from a level controlled by a pseudo-random number to a second reference voltage, and random jitter noise is injected after the top plate voltage of the capacitor array is established and stabilized.

[0042] In this implementation, accurate injection and effective utilization of jitter noise can be ensured without requiring additional clock synchronization circuits or complex control logic, thus simplifying circuit design and improving the linearity of the SARADC without adding additional hardware burden.

[0043] In conjunction with the second aspect, in a possible implementation, the correction method of the successive approximation analog-to-digital converter linearity correction circuit further includes: a boundary protection step:

[0044] When the comparison results of the register logic module of the successive approximation analog-to-digital converter for a preset number of times in each conversion cycle are all 0, the boundary protection circuit forcibly sets the output code to all 0s;

[0045] When the comparison results of the preset number of times in each conversion cycle of the register logic module of the successive approximation analog-to-digital converter are added to the weight of the reused capacitor injected with jitter noise to obtain all 1s, or a carry occurs in the highest bit, the boundary protection circuit forces the output code to be set to all 1s.

[0046] In this implementation, by monitoring the comparison results a preset number of times within the conversion cycle and adjusting the sensitivity of the boundary protection circuit according to actual needs, it is possible to prevent the output code from erroneously flipping in polarity when the input signal approaches the quantization limit of the ADC. This ensures the accuracy and reliability of the SAR ADC output, enhances the robustness of the SAR ADC under extreme conditions, simplifies the circuit design, implements the boundary protection function without the need for additional hardware, and reduces the overall complexity and cost of the system.

[0047] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0048] This application reuses part of the capacitor array of the existing analog-to-digital converter and injects jitter noise controlled by pseudo-random numbers to disperse the harmonic energy introduced by capacitor mismatch, thereby effectively improving the linearity of the SAR ADC without increasing additional hardware costs. At the same time, it also simplifies the circuit design and reduces circuit power consumption and area. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 This is a schematic diagram of a linearity correction circuit for a successive approximation analog-to-digital converter in this application;

[0051] Figure 2 This is a schematic diagram of the bottom plate connection method of the sampling phase dither injection capacitor in this application;

[0052] Figure 3This is a schematic diagram of the bottom plate connection method of the phase conversion dither injection capacitor in this application;

[0053] Figure 4 This is a schematic diagram of the dither injection timing of the CDAC array in this application. DETAILED DESCRIPTION

[0054] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0055] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0056] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0057] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0058] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples, however, one skilled in the art will appreciate that the examples can be practiced without these specific details.

[0059] In wireless communications, audio processing, and other high-precision analog signal processing fields, the requirements for ADC linearity are becoming increasingly stringent. Especially in applications such as digital pre-distortion (DPD), ADC linearity directly affects the overall performance of the system.

[0060] Successive approximation analog-to-digital converters (SAR ADCs) are widely used in current Wi-Fi communication transceiver systems. Especially when operating in digital predistortion (DPD) mode, the signal amplitude processed by the ADC is typically very small. Because the core conversion element of a SAR ADC is the analog-to-analog converter capacitor array (CDAC), manufacturing mismatches in the capacitor array are inevitable at low input signal amplitudes, severely affecting the ADC's linearity and causing signal distortion, which in turn severely impacts the performance of the communication system (e.g., increased bit error rates).

[0061] To improve linearity, traditional calibration schemes typically require additional hardware, such as a dedicated dither noise injection capacitor array. By injecting pseudo-random numbers into this array of capacitors, the CDAC capacitor mismatch is broken up, thereby achieving the goal of improving linearity.

[0062] In view of this, the inventors discovered through research and improvement exploration that the existing calibration scheme requires the introduction of an additional dither injection capacitor array. On the one hand, the additional capacitor array occupies valuable chip area and increases hardware costs; on the other hand, additional control logic is required to manage the injection, switching and calculation of this set of dither capacitors, which increases the complexity of circuit design and verification. In addition, the additional capacitors will also introduce additional parasitic capacitance or noise, increasing the design cost of SARADC.

[0063] Based on this, the embodiment of this specification proposes a successive approximation analog-to-digital converter linearity correction circuit: the overall idea is: reuse part of the capacitors in the analog-to-digital converter capacitor array to inject jitter noise, thereby improving the linearity of the SARADC under small input amplitudes. In the sampling phase, the input signal is coupled to the upper plate of the DAC capacitor array, and at the same time, the lower plate of the reused part of the capacitor array is connected to the high and low levels controlled by the dither signal; after the sampling phase and before the conversion phase, the lower plate of the reused capacitor unit is switched to a fixed reference voltage, thereby injecting jitter noise voltage into the upper plate of the capacitor array, and after the jitter noise voltage is established and stabilized, successive approximation conversion is performed. By reusing the existing CDAC capacitor array to inject jitter noise, the use of an additional capacitor array to inject random jitter noise is avoided, which simplifies the circuit design, reduces cost and power consumption, and improves the linearity of the SAR ADC.

[0064] Some capacitor units in the digital-to-analog converter (DAC) capacitor array are used as reused capacitors to inject dither noise, thereby improving the linearity of the SAR ADC at small input amplitudes. During the sampling phase, the input signal is coupled to the DAC capacitor array, and the lower plate of the reused capacitor array is connected to the high and low voltage levels controlled by the dither signal. After the sampling phase before the conversion phase, the lower plate of the reused capacitor unit is switched to a high level to inject dither noise voltage into the upper plate of the capacitor array. After the dither noise voltage is established and stabilized, successive approximation conversion is performed. By reusing the existing CDAC capacitor array to inject dither noise, the use of an additional capacitor array is avoided, simplifying the circuit design, reducing cost and power consumption, and improving the linearity of the SAR ADC.

[0065] The following describes the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0066] like Figure 1 As shown, the embodiment of this specification provides a successive approximation analog-to-digital converter linearity correction circuit, including:

[0067] A sampling module is used to sample and hold an input signal, the sampling module comprising: a sampling switch connected between the input signal and the capacitor array of the analog-to-digital converter;

[0068] The sampling module is configured as follows: during a sampling phase, the sampling switch is in a closed state to couple the input signal to the analog-to-digital converter capacitor array; from the end of the sampling phase to the beginning of the conversion phase, the sampling switch is in an open state to maintain the charge on the analog-to-digital converter capacitor array;

[0069] An analog-to-digital converter capacitor array includes a plurality of capacitor units, wherein some of the capacitor units are used as multiplexed capacitor units for jitter noise injection;

[0070] The capacitor unit is configured as follows: in the sampling phase: in the non-multiplexed capacitor unit, the bottom plate of the highest-order capacitor is connected to the first reference voltage, and the bottom plates of the remaining capacitors are connected to the second reference voltage; the bottom plates of the multiplexed capacitor units at both ends of the differential are respectively connected to the second reference voltage or the first reference voltage controlled by the pseudo-random number and the inverse of the pseudo-random number; after the sampling phase and before the conversion phase, the bottom plate of the multiplexed capacitor unit is switched to the second reference voltage to inject jitter noise; the connection state of the bottom plates of the remaining capacitors remains unchanged; wherein the voltage value of the second reference voltage is higher than the voltage value of the first reference voltage;

[0071] a dynamic comparator connected to the output end of the capacitor array of the analog-to-digital converter, for comparing the voltage difference between the output nodes and converting the voltage difference into a digital signal output;

[0072] The register logic module of the successive approximation analog-to-digital converter is connected to the output end of the dynamic comparator and is used to control the switching of the capacitor array of the analog-to-digital converter according to the output result of the dynamic comparator to approximate the input signal bit by bit and generate a digital output code.

[0073] In this application, any bit capacitor can be selected for dither noise (dither injection), avoiding the need to add an additional capacitor array for dither injection, greatly simplifying the dither injection control logic and reducing circuit design costs.

[0074] During implementation, sampling is performed first. During the sampling phase, the sampling switch is closed to couple the input signal to the corresponding node of the DAC capacitor array and convert it into charge stored on the DAC capacitor array.

[0075] At this stage, some capacitor units are selected as multiplexed capacitor units for injecting dither noise. The bottom plates of these multiplexed capacitor units are connected to high and low levels controlled by pseudo-random numbers (and their inverse codes) to inject dither noise. In non-multiplexed capacitor units, the bottom plate of the highest-order capacitor is connected to a low level, and the bottom plates of the remaining capacitors are connected to a high level, thereby improving the linearity of the ADC.

[0076] After the sampling phase ends before the conversion phase begins, the sampling switch opens to isolate the input signal and maintain the charge on the DAC capacitor array. At this time, the bottom plate of the reused capacitor unit is switched to a fixed voltage (VREFP), injecting the jitter noise voltage into the top plate of the capacitor array. The bottom plates of the remaining capacitors remain connected unchanged.

[0077] Then, during the conversion phase, the dynamic comparator begins to operate, comparing the voltage difference between the output nodes of the DAC capacitor array. The successive approximation analog-to-digital converter's register logic (SAR logic) controls the switching of the DAC capacitor array based on the dynamic comparator's output, approximating the digital representation of the input signal bit by bit. After a series of comparisons and adjustments, the SAR logic module ultimately generates and outputs an output code representing the digital value of the input signal plus the injected jitter noise. This code is then used to feed the comparator's output back to the bottom plate of the DAC capacitor array to generate the residual signal for the next comparison.

[0078] The present application improves linearity by multiplexing the DAC capacitor array to inject dither signals, thereby improving the performance of the ADC, avoiding the addition of an additional capacitor array for dither injection, greatly simplifying the dither injection control logic, and reducing circuit design costs.

[0079] In some embodiments, the sampling switch includes: a non-inverting input switch and an inverting input switch, wherein the non-inverting input switch is connected between the positive input signal and the positive end top plate node of the analog-to-digital converter capacitor array, and the inverting input switch is connected between the negative input signal and the negative end top plate node of the analog-to-digital converter capacitor array.

[0080] The non-inverting input switch SW1 is directly connected to the positive input signal and the positive top plate node of the DAC capacitor array, and the inverting input switch SW2 is directly connected to the negative input signal and the negative top plate node of the DAC capacitor array.

[0081] In the implementation, during the sampling phase, as Figure 2 As shown, the non-inverting input switch SW1 and the inverting input switch SW2 are both closed, and the SP node and the IP node are connected together through the non-inverting input switch SW1, allowing the input signal to charge the positive end top plate node of the DAC capacitor array, thereby storing the voltage value of the input signal; the SN node and the IN node are connected together through the inverting input switch SW2, allowing the input signal to charge the negative end top plate node of the DAC capacitor array, also storing the voltage value of the input signal.

[0082] After the sampling phase ends and before the conversion phase begins, if Figure 3 As shown, the non-inverting input switch SW1 and the inverting input switch SW2 are both disconnected, the SP node and the IP node are disconnected through the non-inverting input switch SW1, and the SN node and the IN node are disconnected through the inverting input switch SW2, so as to isolate the input signal and maintain the charge on the DAC capacitor array.

[0083] In some embodiments, the pseudo-random number is a binary number, which is used to control the bottom plate level of the positive-end multiplexed capacitor unit in the analog-to-digital converter capacitor array; the inverse of the pseudo-random number is used to control the bottom plate level of the negative-end multiplexed capacitor unit in the analog-to-digital converter capacitor array.

[0084] The pseudo-random number is usually generated by a linear feedback shift register. In implementation, during the sampling phase, the bottom plate of the positive-end multiplexing capacitor unit is connected to a voltage level controlled by the pseudo-random number; the bottom plate of the negative-end multiplexing capacitor unit is connected to a voltage level controlled by the inverse of the pseudo-random number, but in the opposite direction to the positive end.

[0085] In some embodiments, the level switching timing of the pseudo-random number is synchronized with the edge of the sampling clock;

[0086] After the sampling phase ends and before the comparator clock enable signal takes effect, the bottom plate voltage of the reused capacitor is switched from a level controlled by a pseudo-random number to a second reference voltage, and random jitter noise is injected after the top plate voltage of the capacitor array is established and stabilized.

[0087] After the sampling phase ends and before the comparator clock enable signal takes effect, the stable establishment of the bottom and top plate voltages of the reuse capacitor is completed.

[0088] Specifically, the clock CLKS controls the entire SAR ADC operating cycle, including the sampling phase and the conversion phase. On the rising edge of CLKS, the sampling switch closes, the sampling phase begins, and the input signal is coupled to the CDAC capacitor array; on the falling edge of CLKS, the sampling switch opens, ending the sampling phase and starting the conversion phase. At this time, the charge on the CDAC capacitor array is maintained for the conversion process.

[0089] In implementation, see Figure 4The timing diagram shows that when the sampling clock CLKS is high, the top plate short (SP / SN) of the CDAC capacitor array is connected to the common-mode voltage. The common-mode voltage can be any differential voltage. It is only used as an illustration here. At this stage, the input signal is coupled to the CDAC capacitor array through the sampling switch, and the capacitor begins to charge and store the voltage value of the input signal; when the CLKS falling edge arrives, the sampling phase ends and the conversion phase begins. The bottom plate voltage of the capacitor unit used for dither injection switches from the high and low levels controlled by the pseudo-random number to a fixed reference voltage (such as VREFP or VREFN). Due to the switching of the dither injection capacitor bottom plate voltage, the top plate SP / SN node of the CDAC capacitor array begins to establish a differential voltage associated with the dither code value. After switching to the fixed reference voltage, it takes a certain amount of time for the voltage of the top plate SP / SN of the capacitor array to stabilize, that is, the establishment is completed. Once the SP / SN voltage is established, the comparator clock COMP_CLK_EN is enabled to start SAR In the successive approximation conversion of the ADC, the SAR logic determines the digital output code bit by bit based on the output result of the dynamic comparator. The SAR logic controls the switching of the CDAC capacitor array to approximate the voltage value of the input signal.

[0090] In some embodiments, the multiplexed capacitor unit includes capacitor units C5 to C8 in the analog-to-digital converter capacitor array.

[0091] In implementation, capacitor units C5 to C8 in the DAC capacitor array are selected for injecting dither signals, which ensures that the injected dither signals are evenly distributed across the entire ADC input range, thereby effectively dispersing the errors caused by capacitor mismatch and improving linearity.

[0092] In some embodiments, the successive approximation analog-to-digital converter linearity correction circuit further includes: a boundary protection circuit;

[0093] The boundary protection circuit is connected to the output end of the register logic module of the successive approximation analog-to-digital converter, and is used to forcibly set the output code according to the output result of the dynamic comparator, thereby avoiding the polarity reversal of the ADC output code value when the input exceeds the swing.

[0094] In some embodiments, when the comparison results of the register logic module of the successive approximation analog-to-digital converter for a preset number of times in each conversion cycle are all 0, the boundary protection circuit forces the output code to be set to all 0; when the comparison results of the register logic module of the successive approximation analog-to-digital converter for a preset number of times in each conversion cycle are added to the weight of the reused capacitor injected with jitter noise to be all 1, or when a carry occurs in the highest bit, the boundary protection circuit forces the output code to be set to all 1.

[0095] In implementation, the preset number of times can be set to 10 times. When the SAR ADC compares all 0s in 10 times per cycle, the SAR ADC output code is forced to be all 0s. When the SAR ADC compares all 10 times per cycle and the dither adds the corresponding weights, the 10-bit data is all 1s, or there is a carry in the highest bit after the weighted addition, the SAR ADC output code value is forced to be all 1s. Through the boundary protection circuit, the ADC ensures the correct polarity of the ADC output code value in the case of over-rail input.

[0096] The following is another example of a linearity correction circuit for a successive approximation analog-to-digital converter, which is a schematic illustration formed by combining the aforementioned examples.

[0097] The schematic diagram of the bottom plate connection of the sampling phase dither injection capacitor is as follows Figure 2 As shown, in the sampling phase, the sampling switch is closed, the SP node and the IP node are connected together through the switch SW1, the SN node and the IN node are connected together through the switch SW2, and the upper plate of the capacitor samples the input signal, wherein the lower plates of the capacitors C5 to C8 of the upper capacitor array are connected to the high and low levels controlled by the 4-bit pseudo-random number Prbs<3:0>, wherein the lower plates of the capacitors C5 to C8 of the lower capacitor array are connected to the high and low levels controlled by the inverse (Prbsb<3:0>) of the 4-bit pseudo-random number Prbs<3:0>, and the bottom plates of the other capacitors are all connected to VREFP except for the bottom plate of the highest-bit capacitor connected to VREFN.

[0098] The diagram of the bottom plate connection of the dither injection capacitor in the conversion phase is as follows Figure 3 As shown, after the sampling phase ends and before the conversion phase begins, the sampling switch is disconnected, the SP node and the IP node are disconnected through the switch SW1, the SN node and the IN node are disconnected through the switch SW2, and the upper plate of the capacitor holds the input signal. At this time, the lower plates of the capacitors C5 to C8 of the upper capacitor array are connected to the fixed high level VREFP, and the lower plates of the capacitors C5 to C8 of the lower capacitor array are connected to the fixed high level VREFP. Except for the bottom plate of the highest capacitor connected to VREFN, the bottom plates of the remaining capacitors are all connected to VREFP.

[0099] Specific timings such as Figure 4As shown, when the sampling clock CLKS is high, the top plate of CDAC is shorted to the common mode voltage (can be connected to any differential voltage). After the falling edge of CLKS arrives, since the voltage on the bottom plate of the dither injection capacitor switches from the high and low levels controlled by the pseudo-random number to the fixed reference voltage, the SP / SN node on the top plate of the differential capacitor array will begin to establish a differential voltage associated with the dither code value. After a delay, when the SP / SN voltage on the top plate of the capacitor array is established, the comparator clock COMP_CLK_EN is enabled and the successive approximation conversion of the SAR ADC begins.

[0100] Based on the same inventive concept, the present application further provides a correction method for a successive approximation analog-to-digital converter linearity correction circuit, which is implemented based on the successive approximation analog-to-digital converter linearity correction circuit described in any one of the above embodiments. The correction method for the successive approximation analog-to-digital converter linearity correction circuit includes:

[0101] During a sampling phase, the sampling switch is closed to transfer the input signal to the analog-to-digital converter capacitor array for sampling; wherein the analog-to-digital converter capacitor array includes a plurality of capacitor units, some of which are used as multiplexed capacitor units for jitter noise injection;

[0102] Connecting the bottom plates of the multiplexed capacitor units at both ends of the differential to a second reference voltage or a first reference voltage controlled by a pseudo-random number and the inverse of the pseudo-random number; connecting the bottom plate of the highest-order capacitor in the non-multiplexed capacitor to the first reference voltage, and connecting the bottom plates of the remaining capacitors to the second reference voltage;

[0103] Between the end of the sampling phase and the beginning of the conversion phase, the sampling switch is turned off, and the bottom plate of the reused capacitor unit is switched to a second reference voltage to inject jitter noise; wherein the voltage value of the second reference voltage is higher than the voltage value of the first reference voltage;

[0104] In a conversion phase, a dynamic comparator is used to compare the voltage difference between the output nodes of the capacitor array of the analog-to-digital converter, and the voltage difference is converted into a digital signal output;

[0105] According to the output result of the dynamic comparator, a register logic module of a successive approximation analog-to-digital converter is used to control the switching of the analog-to-digital converter capacitor array to approximate the input signal bit by bit and generate a digital output code.

[0106] In some embodiments, the level switching timing of the pseudo-random number is synchronized with the edge of the sampling clock;

[0107] After the sampling phase ends and before the comparator clock enable signal takes effect, the bottom plate voltage of the reused capacitor is switched from a level controlled by a pseudo-random number to a second reference voltage, and random jitter noise is injected after the top plate voltage of the capacitor array is established and stabilized.

[0108] In some embodiments, the correction method of the successive approximation analog-to-digital converter linearity correction circuit further includes: a boundary protection step:

[0109] When the comparison results of the register logic module of the successive approximation analog-to-digital converter for a preset number of times in each conversion cycle are all 0, the boundary protection circuit forcibly sets the output code to all 0s;

[0110] When the comparison results of the preset number of times in each conversion cycle of the register logic module of the successive approximation analog-to-digital converter are added to the weight of the reused capacitor injected with jitter noise to obtain all 1s, or a carry occurs in the highest bit, the boundary protection circuit forces the output code to be set to all 1s.

[0111] The successive approximation analog-to-digital converter linearity correction scheme proposed in this application not only improves the linearity of the SAR ADC at small amplitudes, but also injects dither in the analog domain by reusing the existing CDAC sampling capacitors, avoiding the use of an additional dither capacitor array to inject random jitter noise. This greatly simplifies the dither injection circuit, reduces circuit cost and design complexity, and also adds a boundary protection function to the ADC output code value to avoid polarity reversal of the ADC output code value when the input exceeds the swing.

[0112] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0113] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A successive approximation analog-to-digital converter linearity correction circuit, characterized in that: include: A sampling module is used to sample and hold an input signal, the sampling module comprising: a sampling switch connected between the input signal and the capacitor array of the analog-to-digital converter; The sampling module is configured as follows: during a sampling phase, the sampling switch is in a closed state to couple the input signal to the digital-to-analog conversion capacitor array of the analog-to-digital converter; from the end of the sampling phase to the beginning of the conversion phase, the sampling switch is in an open state to maintain the charge on the digital-to-analog conversion capacitor array of the analog-to-digital converter; A digital-to-analog conversion capacitor array of an analog-to-digital converter includes a plurality of capacitor units, wherein some of the capacitor units are used as multiplexed capacitor units for jitter noise injection; The capacitor unit is configured as follows: in the sampling phase: in the non-multiplexed capacitor unit, the bottom plate of the highest-order capacitor is connected to the first reference voltage, and the bottom plates of the remaining capacitors are connected to the second reference voltage; the bottom plates of the multiplexed capacitor units at both ends of the differential are respectively connected to the second reference voltage or the first reference voltage controlled by the pseudo-random number and the inverse of the pseudo-random number; after the sampling phase and before the conversion phase, the bottom plate of the multiplexed capacitor unit is switched to the second reference voltage to inject jitter noise; the connection state of the bottom plates of the remaining capacitors remains unchanged; wherein the voltage value of the second reference voltage is higher than the voltage value of the first reference voltage; a dynamic comparator connected to the output end of the capacitor array of the analog-to-digital converter, for comparing the voltage difference between the output nodes and converting the voltage difference into a digital signal output; The register logic module of the successive approximation analog-to-digital converter is connected to the output end of the dynamic comparator and is used to control the switching of the capacitor array of the analog-to-digital converter according to the output result of the dynamic comparator to approximate the input signal bit by bit and generate a digital output code.

2. The successive approximation analog-to-digital converter linearity correction circuit according to claim 1, wherein: The sampling switch includes: a non-inverting input switch and an inverting input switch. The non-inverting input switch is connected between the positive input signal and the positive end upper plate node of the analog-to-digital converter capacitor array, and the inverting input switch is connected between the negative input signal and the negative end upper plate node of the analog-to-digital converter capacitor array.

3. The successive approximation analog-to-digital converter linearity correction circuit according to claim 1, wherein: The pseudo-random number is a binary number, which is used to control the bottom plate level of the positive-end multiplexed capacitor unit in the analog-to-digital converter capacitor array; the inverse code of the pseudo-random number is used to control the bottom plate level of the negative-end multiplexed capacitor unit in the analog-to-digital converter capacitor array.

4. The successive approximation analog-to-digital converter linearity correction circuit according to claim 3, wherein: The level switching timing of the pseudo-random number is synchronized with the edge of the sampling clock; After the sampling phase ends and before the comparator clock enable signal takes effect, the bottom plate voltage of the reused capacitor is switched from a level controlled by a pseudo-random number to a second reference voltage, and random jitter noise is injected after the top plate voltage of the capacitor array is established and stabilized.

5. The successive approximation analog-to-digital converter linearity correction circuit according to claim 1, wherein: The multiplexed capacitor unit includes capacitor units C5 to C8 in the analog-to-digital converter capacitor array.

6. The successive approximation analog-to-digital converter linearity correction circuit according to claim 1, wherein: The successive approximation analog-to-digital converter linearity correction circuit further includes: a boundary protection circuit; The boundary protection circuit is connected to the output end of the register logic module of the successive approximation analog-to-digital converter, and is used to forcibly set the output code according to the output result of the dynamic comparator.

7. The successive approximation analog-to-digital converter linearity correction circuit according to claim 6, wherein: When the comparison results of the register logic module of the successive approximation analog-to-digital converter for a preset number of times in each conversion cycle are all 0, the boundary protection circuit forces the output code to be set to all 0; when the comparison results of the register logic module of the successive approximation analog-to-digital converter for a preset number of times in each conversion cycle are added to the weight of the multiplexed capacitor injected with jitter noise to be all 1, or a carry occurs in the highest bit, the boundary protection circuit forces the output code to be set to all 1.

8. A method for correcting a linearity correction circuit of a successive approximation analog-to-digital converter, characterized in that: Based on the successive approximation analog-to-digital converter linearity correction circuit according to any one of claims 1 to 7, the correction method of the successive approximation analog-to-digital converter linearity correction circuit includes: During a sampling phase, the sampling switch is closed to transfer the input signal to the analog-to-digital converter capacitor array for sampling; wherein the analog-to-digital converter capacitor array includes a plurality of capacitor units, some of which are used as multiplexed capacitor units for jitter noise injection; Connecting the bottom plates of the multiplexed capacitor units at both ends of the differential to a second reference voltage or a first reference voltage controlled by a pseudo-random number and the inverse of the pseudo-random number; connecting the bottom plate of the highest-order capacitor in the non-multiplexed capacitor to the first reference voltage, and connecting the bottom plates of the remaining capacitors to the second reference voltage; Between the end of the sampling phase and the beginning of the conversion phase, the sampling switch is turned off, and the bottom plate of the reused capacitor unit is switched to a second reference voltage to inject jitter noise; wherein the voltage value of the second reference voltage is higher than the voltage value of the first reference voltage; In a conversion phase, a dynamic comparator is used to compare the voltage difference between the output nodes of the capacitor array of the analog-to-digital converter, and the voltage difference is converted into a digital signal output; According to the output result of the dynamic comparator, a register logic module of a successive approximation analog-to-digital converter is used to control the switching of the analog-to-digital converter capacitor array to approximate the input signal bit by bit and generate a digital output code.

9. The method for correcting the linearity correction circuit of a successive approximation analog-to-digital converter according to claim 8, wherein: The level switching timing of the pseudo-random number is synchronized with the edge of the sampling clock; After the sampling phase ends and before the comparator clock enable signal takes effect, the bottom plate voltage of the reused capacitor is switched from a level controlled by a pseudo-random number to a second reference voltage, and random jitter noise is injected after the top plate voltage of the capacitor array is established and stabilized.

10. The method for correcting the linearity correction circuit of a successive approximation analog-to-digital converter according to claim 8, wherein: The correction method of the successive approximation analog-to-digital converter linearity correction circuit further includes: a boundary protection step: When the comparison results of the register logic module of the successive approximation analog-to-digital converter for a preset number of times in each conversion cycle are all 0, the boundary protection circuit forcibly sets the output code to all 0s; When the comparison results of the preset number of times in each conversion cycle of the register logic module of the successive approximation analog-to-digital converter are added to the weight of the reused capacitor injected with jitter noise to obtain all 1s, or a carry occurs in the highest bit, the boundary protection circuit forces the output code to be set to all 1s.

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