Inductive memory processor stacked package structure and its fabrication method

Abstract

This invention discloses an inductive memory processor stacked package structure and its fabrication method. The SOC chip in the package structure has pads and a first electromagnetic coil on its front side. The HBM chip includes a memory chip and multiple vertically stacked DRAM chips electrically connected to the back of the memory chip. Conductive bumps and a second electromagnetic coil are formed on the front side of the memory chip. The SOC chip is mounted on the front side of the substrate, with the SOC chip facing upwards. The HBM chip is stacked on the front side of the SOC chip, and the second electromagnetic coil corresponds to the position of the first electromagnetic coil. The electromagnetic induction area does not exceed 40 μm. The pads of the SOC chip are electrically connected to the substrate, and the conductive bumps of the HBM chip are electrically connected to the substrate. The molding compound encapsulates the front side of the substrate, at least covering the SOC chip, the HBM chip, and all electrically connected parts. This invention provides an inductive memory processor stacked package structure and its fabrication method with higher packaging density and improved electrical performance transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to an inductor-based memory processor stacked packaging structure and its fabrication method. Background Technology

[0002] With the development of cloud computing and mobile internet technologies, the demand for servers in data centers and other similar facilities has surged, leading to a growing need for high-capacity, high-bandwidth, and low-power storage devices. To meet this demand, manufacturers have launched multi-layer stacked memory packaging products based on 3D stacking technology. These products vertically interconnect multiple memory chips via through-silicon vias (TSVs), leveraging the advantages of high density and short vertical interconnect distances to significantly improve data transmission speeds.

[0003] However, existing multi-layer stacked memories have some problems in the packaging process.

[0004] First, when using copper-tin bumps or micro-bumps, due to the deformability of tin during reflow, the spacing between bumps and the height of tin need to be strictly controlled to prevent short circuits between bumps.

[0005] Secondly, traditional packaging methods such as flip-chip structures or wire bonding can easily lead to stress concentration at the chip electrodes, which can damage the fragile Low-K dielectric layer and affect the reliability of the chip.

[0006] Furthermore, existing fan-out wafer-level packaging technology can only solve the problem of single-sided chip stacking. Due to the limitations of wafer size, it cannot maximize the processing size, which is not conducive to improving production capacity and reducing manufacturing costs.

[0007] Therefore, finding a new packaging solution that can overcome these defects has become an important direction for current technological development. Summary of the Invention

[0008] To address the aforementioned issues, this invention provides an inductor-based memory processor stacked packaging structure with higher packaging density and improved electrical performance transmission efficiency, as well as a method for its fabrication.

[0009] In a first aspect, the present invention discloses a method for fabricating an inductive memory processor stacked package structure, the method comprising the following steps:

[0010] S1. After forming pads and the first electromagnetic coil on the front side of the SOC wafer, grind it into a single SOC chip.

[0011] S2. Conductive bumps and a second electromagnetic coil are formed on the front side of the memory chip, and multiple vertically stacked DRAM chips are electrically connected to the back side of the memory chip to form an HBM chip.

[0012] S3. Provide a substrate, mount the SOC chip on the front side of the substrate with the SOC chip facing up; stack the HBM chip on the front side of the SOC chip, with the second electromagnetic coil corresponding to the position of the first electromagnetic coil; form an electromagnetic induction area between the second electromagnetic coil and the first electromagnetic coil, the electromagnetic induction area not exceeding 40μm; the pads of the SOC chip are electrically connected to the substrate, and the conductive bumps of the HBM chip are electrically connected to the substrate.

[0013] S4. The front side of the substrate is encapsulated using molding compound, which covers at least the SOC chip, HBM chip, and all electrical connection parts to form an inductor-memory processor stacked package structure.

[0014] Secondly, the present invention discloses an inductive memory processor stacked package structure prepared using the above-described preparation method, comprising a SOC chip, an HBM chip, a substrate, and a molding compound. The SOC chip has pads and a first electromagnetic coil on its front side. The HBM chip includes a memory chip and multiple vertically stacked DRAM chips electrically connected to the back side of the memory chip. Conductive bumps and a second electromagnetic coil are formed on the front side of the memory chip. The SOC chip is mounted on the front side of the substrate, with the front side of the SOC chip facing upwards. The HBM chip is stacked on the front side of the SOC chip, and the second electromagnetic coil corresponds to the position of the first electromagnetic coil. The electromagnetic induction area does not exceed 40 μm. The pads of the SOC chip are electrically connected to the substrate, and the conductive bumps of the HBM chip are electrically connected to the substrate. The molding compound encapsulates the front side of the substrate, at least covering the SOC chip, the HBM chip, and each electrically connected portion.

[0015] Thirdly, the present invention also discloses another method for fabricating an inductive memory processor stacked package structure, which replaces steps S3-S4 in the fabrication method described in the first aspect with the following steps:

[0016] S3' Attach the single SOC chip from step S1 to the front of the first PMIC chip, electrically connect the pads to the first PMIC chip, and then encapsulate it to form an SOC package; attach the HBM chip from step S2 to the front of the second PMIC chip, electrically connect the conductive bumps to the second PMIC chip, and then encapsulate it to form an HBM package.

[0017] S4' Attach the SOC package to the front side of the substrate with the front side of the SOC package facing up; stack the HBM package on the front side of the SOC package, with the second electromagnetic coil corresponding to the position of the first electromagnetic coil.

[0018] S5' A heat dissipation cover is provided on the front side of the substrate. The heat dissipation cover covers the SOC package and the HBM package to form an inductor memory processor stacked package structure.

[0019] Fourthly, this invention discloses an inductor memory processor stacked package structure prepared using the above-described method, comprising a SOC package, an HBM package, a substrate, and a heat sink. The SOC package includes a SOC chip, a first PMIC chip, and a first molding compound. The SOC chip has pads and a first electromagnetic coil on its front side. The SOC chip is mounted on the front side of the first PMIC chip, and the pads are electrically connected to the first PMIC chip. The first molding compound encapsulates the SOC chip and the electrical connection portion. The HBM package includes an HBM chip, a second PMIC chip, and a second molding compound. The HBM chip includes a memory chip and multiple vertically stacked DRAM chips electrically connected to the back side of the memory chip. Conductive bumps and a second electromagnetic coil are formed on the front side of the memory chip. The HBM chip is mounted on the front side of the second PMIC chip, and the conductive bumps are electrically connected to the second PMIC chip. The second molding compound encapsulates the HBM chip and the electrical connection portion. The SOC package is mounted on the front side of the substrate, with the front side of the SOC package facing upwards. The HBM package is stacked on the front of the SOC package, and the second electromagnetic coil corresponds to the position of the first electromagnetic coil; a heat dissipation cover is provided on the front of the substrate, which covers the SOC package and the HBM package.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] This invention achieves information exchange between the SOC chip and the HBM chip through face-to-face inductance communication between inductor coils, effectively enhancing transmission efficiency.

[0022] This invention employs an innovative inductor-based memory processor stacking packaging process and structure, which simplifies the hybrid bonding and thermoforming processes, optimizes the packaging process, improves production efficiency, and reduces production costs. Attached Figure Description

[0023] Figure 1 This is a side view of the SOC chip in Embodiment 1 of the present invention;

[0024] Figure 2 This is a schematic diagram of the front structure of the SOC chip in Embodiment 1 of the present invention;

[0025] Figure 3 This is a side view of the memory chip in Embodiment 1 of the present invention;

[0026] Figure 4 This is a schematic diagram of the front structure of the memory chip in Embodiment 1 of the present invention;

[0027] Figure 5 This is a schematic diagram of the HBM chip structure in Embodiment 1 of the present invention;

[0028] Figure 6This is a schematic diagram of the SOC chip mounted face-up on the front of the substrate in Embodiment 1 of the present invention;

[0029] Figure 7 In order to be in Figure 6 A schematic diagram of the structure of a SOC chip with an HBM chip stacked on top of it;

[0030] Figure 8 This is a schematic diagram of the stacked packaging structure of the inductor storage processor in Embodiment 1 of the present invention;

[0031] Figure 9 This is a schematic diagram of the SOC package structure in Embodiment 2 of the present invention;

[0032] Figure 10 This is a schematic diagram of the HBM package structure in Embodiment 2 of the present invention;

[0033] Figure 11 This is a schematic diagram of the structure of the SOC package and the HBM package stacked on the substrate in Embodiment 2 of the present invention;

[0034] Figure 12 This is a schematic diagram of the stacked packaging structure of the inductor storage processor in Embodiment 2 of the present invention.

[0035] Labeling: 1. Single SOC chip; 101. SOC wafer; 102. Pad; 103. First electromagnetic coil; 104. First alignment mark; 2. Memory chip; 201. Conductive bump; 202. Second electromagnetic coil; 203. Second alignment mark; 3. DRAM chip; 4. HBM chip; 5. Substrate; 6. Molding package; 7. First PMIC chip; 8. First molding package; 9. SOC package; 10. Second PMIC chip; 12. HBM package; 11. Second molding package; 13. Heat sink. Detailed Implementation

[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0037] Example 1

[0038] This embodiment discloses an inductor storage processor stacked packaging structure and its fabrication method.

[0039] The fabrication method of this inductor-based memory processor stacked package structure includes the following steps:

[0040] S1. After forming pads 102 and the first electromagnetic coil 103 on the front side of the SOC wafer 101, it is ground into a single SOC chip 1.

[0041] The specific process is as follows:

[0042] like Figure 1 and Figure 2 As shown, a SOC wafer 101 is provided. Using a series of bumping processes such as photolithography and electroplating, bonding pads 102 for wirebond bonding and a first electromagnetic coil 103 are formed on the front side of the SOC wafer 101. Through a grinding process, the SOC wafer 101 is divided into individual SOC chips 1. The bonding pads 102 are used for wirebond bonding. The first electromagnetic coil 103 plays an important role in the chip's signal transmission and functional implementation; its material, number of turns, and other parameters are determined according to the specific requirements of the chip.

[0043] Meanwhile, to facilitate alignment in the subsequent TCB thermocompression bonding process, a first alignment mark 104 is specially set on the front side of the SOC wafer 101, which helps to achieve precise chip alignment during the TCB thermocompression bonding process and ensures the quality and accuracy of thermocompression bonding.

[0044] S2. Conductive bumps 201 and a second electromagnetic coil 202 are formed on the front side of the memory chip 2, and multiple vertically stacked DRAM chips 3 are electrically connected to the back side of the memory chip 2 to form an HBM chip 4.

[0045] The specific process is as follows:

[0046] like Figure 3 , Figure 4 and Figure 5 As shown, a memory chip 2 is provided. Conductive bumps 201 (C4 bump) and a second electromagnetic coil 202 are formed on the front side of the memory chip 2 using a bumping process. A second alignment mark 203 for TCB (Thermo-Contact Bump) is also present. When the HBM chip 4 is stacked on the SOC chip 1 using the TCB thermo-bonding process, alignment is achieved using the first alignment mark 104 and the second alignment mark 203. The shapes of the first alignment mark 104 and the second alignment mark 203 can be freely designed, as long as they allow for alignment. Multiple layers of vertically stacked DRAM chips 3 are connected to the back side of the memory chip 2 using TSV (Thermo-Contact Vessel) technology. The figure shows two layers of DRAM chips 3. In actual implementation, the number of stacked DRAM chips 3 can be set according to circuit requirements.

[0047] By utilizing TSV technology, high-precision alignment and electrical connection between different layers of the multi-layer vertically stacked DRAM chip 3 were achieved, thereby ensuring the overall functionality and reliability of the HBM chip 4.

[0048] The conductive bump 201 is fabricated as a C4 bump. The electrical connection achieved through the C4 bump can effectively improve the chip's integration and performance.

[0049] S3. Provide a substrate 5, mount the SOC chip 1 on the front side of the substrate 5 with the front side of the SOC chip 1 facing upwards; stack the HBM chip 4 on the front side of the SOC chip 1, with the second electromagnetic coil 202 corresponding to the position of the first electromagnetic coil 103; an electromagnetic induction area is formed between the second electromagnetic coil 202 and the first electromagnetic coil 103, and the electromagnetic induction area does not exceed 40μm; the pads 102 of the SOC chip 1 are electrically connected to the substrate 5, and the conductive bumps 201 of the HBM chip 4 are electrically connected to the substrate 5.

[0050] The electromagnetic induction region refers to the distance between the second electromagnetic coil 202 on the HBM chip 4 and the first electromagnetic coil 103 on the SOC chip 1. The first electromagnetic coil 103 and the second electromagnetic coil 202 are stacked to form a mutual inductance region. This electromagnetic induction region should preferably not exceed 40µm, otherwise efficient mutual inductance communication cannot be achieved.

[0051] Specifically, such as Figure 6 As shown, a DAF is first attached to the back of the SOC chip 1, and then it is mounted upright on the front of the substrate 5. The pads 102 of the SOC chip 1 are electrically connected to the substrate 5 using a wirebonding process. Figure 7 As shown, HBM chip 4 is stacked on the front side of SOC chip 1 using TCB thermoforming process.

[0052] S4. A molding compound is used to mold the front side of the substrate 5, forming a molding portion 6. The molding portion 6 at least covers the SOC chip 1, the HBM chip 4, and all electrical connection points. The molding compound is heated and pressurized to tightly bond the chips together, ensuring stable performance during subsequent operation and reducing performance fluctuations or failures caused by loose connections. This results in a molding compound that... Figure 8 The inductor storage processor stacked package structure is shown.

[0053] The inductive memory processor stacked package structure prepared by the above-described method includes a SOC chip 1, an HBM chip 4, a substrate 5, and a molding compound 6. The SOC chip 1 has pads 102 and a first electromagnetic coil 103 on its front side. The HBM chip 4 includes a memory chip 2 and a multilayer vertically stacked DRAM chip 3 electrically connected to the back side of the memory chip 2. Conductive bumps 201 and a second electromagnetic coil 202 are formed on the front side of the memory chip 2. The SOC chip 1 is mounted on the front side of the substrate 5 with the front side of the SOC chip 1 facing upwards. The HBM chip 4 is stacked on the front side of the SOC chip 1, and the second electromagnetic coil 202 corresponds to the position of the first electromagnetic coil 103. The electromagnetic induction area does not exceed 40 μm. The pads 102 of the SOC chip 1 are electrically connected to the substrate 5, and the conductive bumps 201 of the HBM chip 4 are electrically connected to the substrate 5. The molding compound 6 molds the front side of the substrate 5, covering at least the SOC chip 1, the HBM chip 4, and each electrically connected part.

[0054] Example 2

[0055] This embodiment discloses another inductive storage processor stacked packaging structure and its fabrication method.

[0056] The difference between the fabrication method of the inductor storage processor stacked package structure disclosed in this embodiment and that in Embodiment 1 is that steps S3-S4 in the fabrication method disclosed in Embodiment 1 are replaced with the following steps:

[0057] S3' Attach the single SOC chip 1 from step S1 to the front of the first PMIC chip 7, and electrically connect the pad 102 to the first PMIC chip 7 using the wirebond process. After molding, a SOC package 9 is formed, that is, the first molding part 8 after molding molds the SOC chip 1 and the electrical connection part, and the surfaces of the first electromagnetic coil 103 and the first alignment mark 104 need to be exposed.

[0058] In step S2, the HBM chip 4 is mounted on the front side of the second PMIC chip 10. The conductive bumps 201 are electrically connected to the second PMIC chip 10. After molding, an HBM package 12 is formed, that is, the second molding part 11 molds the HBM chip 4 and the electrical connection parts, and the surface of the conductive bumps 201 needs to be exposed. The structure of the SOC package 9 is as follows. Figure 9 As shown, the structure of the HBM package 12 is as follows: Figure 10 As shown.

[0059] In this embodiment, the conductive bump 201 does not need to be made into a C4 bump; a bump of normal height is sufficient.

[0060] S4', as Figure 11 As shown, the SOC package 9 is mounted on the front side of the substrate 5 with the front side of the SOC package 9 facing upwards; the HBM package 12 is stacked on the front side of the SOC package 9, and the second electromagnetic coil 202 corresponds to the position of the first electromagnetic coil 103.

[0061] S5' A heat sink 13 is provided on the front side of the substrate 5. The heat sink 13 covers the SOC package 9 and the HBM package 12, forming a structure as shown in Figure 15. Figure 12 The inductor storage processor stacked package structure is shown.

[0062] The inductor memory processor stacked package structure prepared by the above preparation method includes a SOC package 9, an HBM package 12, a substrate 5, and a heat sink 13. The SOC package 9 includes a SOC chip 1, a first PMIC chip 7, and a first molding compound 8. The front side of the SOC chip 1 has a pad 102 and a first electromagnetic coil 103. The SOC chip 1 is mounted on the front side of the first PMIC chip 7, and the pad 102 is electrically connected to the first PMIC chip 7. The first molding compound 8 molds the SOC chip 1 and the electrical connection portion. The HBM package 12 includes an H The system comprises a BM chip 4, a second PMIC chip 10, and a second molding compound 11. The HBM chip 4 includes a memory chip 2 and a DRAM chip 3 electrically connected to multiple vertically stacked layers on the back of the memory chip 2. Conductive bumps 201 and a second electromagnetic coil 202 are formed on the front of the memory chip 2. The HBM chip 4 is mounted on the front of the second PMIC chip 10, and the conductive bumps 201 are electrically connected to the second PMIC chip 10. The second molding compound 11 encapsulates the HBM chip 4 and the electrically connected parts. A SOC package 9 is mounted on the front of the substrate 5, with the front of the SOC package 9 facing upwards. An HBM package 12 is stacked on the front of the SOC package 9, and the second electromagnetic coil 202 corresponds to the position of the first electromagnetic coil 103. A heat sink 13 is provided on the front of the substrate 5, covering the SOC package 9 and the HBM package 12.

[0063] The above descriptions are merely some embodiments of the present invention. It should be noted that those skilled in the art can make other modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method for fabricating an inductive storage processor stacked package structure, characterized in that, The method includes the following steps: S1. After forming pads and the first electromagnetic coil on the front side of the SOC wafer, grind it into a single SOC chip. S2. Conductive bumps and a second electromagnetic coil are formed on the front side of the memory chip, and multiple vertically stacked DRAM chips are electrically connected on the back side of the memory chip to form an HBM chip; the memory chip and the DRAM chip are electrically connected through TSV, and the conductive bumps are C4 conductive bumps; S3. Provide a substrate, mount the SOC chip on the front side of the substrate with the SOC chip facing up; stack the HBM chip on the front side of the SOC chip, with the second electromagnetic coil corresponding to the position of the first electromagnetic coil; form an electromagnetic induction area between the second electromagnetic coil and the first electromagnetic coil, the electromagnetic induction area not exceeding 40μm; the pads of the SOC chip are electrically connected to the substrate, and the conductive bumps of the HBM chip are electrically connected to the substrate. S4. The front side of the substrate is encapsulated with molding compound, which covers at least the SOC chip, HBM chip and all electrical connection parts to form an inductor-memory processor stacked package structure. The inductive memory processor stacked package structure prepared according to the above method includes a SOC chip, an HBM chip, a substrate, and a molding compound. The SOC chip has pads and a first electromagnetic coil on its front side. The HBM chip includes a memory chip and multiple vertically stacked DRAM chips electrically connected to the back of the memory chip. Conductive bumps and a second electromagnetic coil are formed on the front side of the memory chip. The SOC chip is mounted on the front side of the substrate with the front side of the SOC chip facing upwards. The HBM chip is stacked on the front side of the SOC chip, and the second electromagnetic coil corresponds to the position of the first electromagnetic coil. The electromagnetic induction area does not exceed 40 μm. The pads of the SOC chip are electrically connected to the substrate, and the conductive bumps of the HBM chip are electrically connected to the substrate. The molding compound encapsulates the front side of the substrate, at least covering the SOC chip, the HBM chip, and all electrical connection parts.

2. The method according to claim 1, characterized in that, In step S1, a first alignment mark is also provided on the front side of the SOC wafer.

3. The method according to claim 2, characterized in that, The HBM chip also has a second alignment mark on the front side of the memory chip. When the HBM chip is stacked on the SOC chip through the TCB hot-press bonding process, the first alignment mark and the second alignment mark are used for alignment.

4. The method according to claim 3, characterized in that, The pads of the SOC chip are electrically connected to the substrate via wire bonding.

5. The method according to claim 1, characterized in that, Replace steps S3-S4 with the following steps: S3' Attach the single SOC chip from step S1 to the front of the first PMIC chip, electrically connect the pads to the first PMIC chip, and then encapsulate it to form an SOC package; attach the HBM chip from step S2 to the front of the second PMIC chip, electrically connect the conductive bumps to the second PMIC chip, and then encapsulate it to form an HBM package. S4' Attach the SOC package to the front side of the substrate with the front side of the SOC package facing up; stack the HBM package on the front side of the SOC package, with the second electromagnetic coil corresponding to the position of the first electromagnetic coil. S5' A heat dissipation cover is provided on the front side of the substrate. The heat dissipation cover covers the SOC package and the HBM package to form an inductor memory processor stacked package structure.

6. Inductor-based memory processor stacked package structure, The method according to claim 5 is used to prepare the product, characterized in that, The system includes a SOC package, an HBM package, a substrate, and a heat sink. The SOC package includes a SOC chip, a first PMIC chip, and a first molding compound. The SOC chip has pads and a first electromagnetic coil on its front side. The SOC chip is mounted on the front side of the first PMIC chip, and the pads are electrically connected to the first PMIC chip. The first molding compound encapsulates the SOC chip and the electrical connection points. The HBM package includes an HBM chip, a second PMIC chip, and a second molding compound. The HBM chip includes a memory chip and multiple vertically stacked DRAM chips electrically connected to the back side of the memory chip. Conductive bumps and a second electromagnetic coil are formed on the front side of the memory chip. The HBM chip is mounted on the front side of the second PMIC chip, and the conductive bumps are electrically connected to the second PMIC chip. The second molding compound encapsulates the HBM chip and the electrical connection points. The SOC package is mounted on the front side of the substrate, with the front side of the SOC package facing upwards. The HBM package is stacked on the front side of the SOC package, and the second electromagnetic coil corresponds to the position of the first electromagnetic coil. A heat sink is provided on the front side of the substrate, covering the SOC package and the HBM package.

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