Glass passivation protection TVS (Transient Voltage Suppressor) device and preparation method thereof

Abstract

The invention discloses a glass passivation protection TVS (Transient Voltage Suppressor) device and a preparation method thereof, and relates to the technical field of semiconductor device manufacturing, the device adopts a sandwich structure formed by a substrate layer and conducting layers on two sides, a special groove is formed in the edge of one side opposite to the conducting type, and a protection system of an oxide layer, a multi-layer composite passivation layer (an SIPOS layer and an MTO layer), an LTO layer and a glass layer is constructed. The preparation method comprises the steps of arranging the conductive layer, oxidizing, etching the groove, depositing the passivation layer, performing electrophoretic deposition on the glass layer, performing low-temperature oxidation to form the LTO layer and the like. The invention provides four structural schemes of P-type two-way symmetry, N-type two-way symmetry, P-type one-way asymmetry and N-type one-way asymmetry, through the optimization of an electrophoretic deposition process and the improvement of a multi-layer composite protection layer, the reliability and the electrical performance of the TVS chip are effectively improved, the glass layer is uniform, compact and bubble-free, the electric leakage is controlled to be below 0.1 mu A, and the TVS chip has high reliability. The breakdown voltage of the semiconductor device reaches more than 20V (P-type substrate) and more than 36V (N-type substrate), the production cost is reduced, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a TVS device with glass passivation protection and a preparation method thereof. Background Art

[0002] Transient voltage suppressor (TVS) chips are core components for circuit protection, and their reliability and electrical performance are directly related to the stability of electronic systems. Traditional glass passivation films have large thickness (30-40 μm), which causes bubbles and cracks and reduces device reliability. The Chinese invention patent "PN junction protection method for silicon mesa semiconductor devices" with announcement number CN102779764B proposes using a passivation layer (SIPOS) film superimposed on a glass passivation film to replace the traditional single glass passivation film to improve the passivation effect. Although this process can effectively protect the glass layer after cracks appear, this process cannot avoid the appearance of bubbles and cracks in the glass layer, and the protection is not comprehensive enough, and the calcination passivation process is too cumbersome. In recent years, researchers have proposed a variety of improvements to TVS devices. One is to combine the photoresist method and the resistance method to grow a glass layer in a specific area, which can avoid impurities and bubbles and improve the density and high-temperature resistance of the glass layer. However, due to the direct contact between the passivation layer and the substrate layer, it causes problems such as increased leakage and unstable breakdown voltage. Another is to set an oxide layer between the substrate layer and the passivation layer (except for the electrophoretic glass layer area) to achieve insulation during electrophoresis and reduce leakage problems. However, since the thermal expansion coefficient and thermal conductivity of the oxide layer SiO2 are significantly lower than those of silicon, it hinders the conduction of heat from the substrate layer to the passivation layer, causing local thermal stress accumulation and increased temperature rise, which can easily cause cracks, thermal failure and other problems.

[0003] The two aforementioned improvement approaches create a fundamental conflict between insulation and heat dissipation requirements: while the presence of an oxide layer enhances insulation and suppresses leakage, it significantly increases thermal resistance, leading to increased device temperature rise. While excluding an oxide layer improves heat dissipation, it sacrifices insulation and significantly impacts device performance. Existing technologies are unable to strike a balance between insulation and heat dissipation performance, resulting in TVS devices still facing a technical bottleneck of coexisting leakage risks and thermal failure risks in high-reliability scenarios.

[0004] Therefore, an innovative design is urgently needed to break through the limitations of existing technologies. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a TVS device with glass passivation protection and a preparation method thereof.

[0006] The object of the present invention is achieved through the following technical solutions:

[0007] <First Aspect>

[0008] The present invention provides a TVS device with glass passivation protection, comprising a substrate layer, wherein the substrate layer is of a first conductivity type, and further comprising:

[0009] Two conductive layers located on the upper and lower sides of the substrate layer respectively form a sandwich structure, and at least one of the two conductive layers has a conductivity type opposite to that of the substrate layer;

[0010] On the side of the opposite conductivity type, grooves are opened at the four edges of the device, the bottom of the grooves extends into the substrate layer, and the bottom of the grooves gradually deepens from the inside to the outside; the central area outside the conductive layer of the opposite conductivity type is covered with a nickel-gold layer, and the outer area adjacent to the central area is covered with an oxide layer; a continuous passivation layer is covered outside the oxide layer and the groove, the passivation layer located outside the oxide layer is planar, and the passivation layer located outside the groove is arc-shaped; the passivation layer is composed of a SIPOS layer located in the inner layer and an MTO layer located in the outer layer; an LTO layer and a glass layer are covered outside the passivation layer, the glass layer is covered at the corner position of the passivation layer, the LTO layer is covered at the planar area and the arc-shaped bottom area of ​​the passivation layer, the LTO layer and the glass layer are in contact with each other, and the outer side of the LTO layer covering the planar area ends before the corner position of the passivation layer.

[0011] As an embodiment, the corner position of the passivation layer is formed by the outer edge of the passivation layer plane and the arc connected thereto.

[0012] As an embodiment, when the conductivity type of one of the conductive layers is the same as the conductivity type of the substrate layer, the outer side of the conductive layer with the same conductivity type is covered with a nickel-gold layer.

[0013] As an embodiment, the nickel-gold layer has a structure of nickel inside and gold outside.

[0014] As an embodiment, the area where the LTO layer and the glass layer contact each other is a transition zone, where the edge of the LTO layer covers the edge of the glass layer, and the length of the transition zone is 10 μm to 100 μm.

[0015] As an embodiment, when the substrate layer is a P-type substrate, the conductive layers on both sides are N-type doped regions.

[0016] As an embodiment, when the substrate layer is a P-type substrate, the conductive layer on one side is an N-type doped region, and the conductive layer on the other side is a P-type main expansion region.

[0017] As an embodiment, when the substrate layer is an N-type substrate, the conductive layers on both sides are P-type doped regions.

[0018] As an embodiment, when the substrate layer is an N-type substrate, the conductive layer on one side is a P-type doped region, and the conductive layer on the other side is an N-type main expansion region.

[0019] As an embodiment, the TVS device has a size of 30 mil to 600 mil.

[0020] In some embodiments, the TVS device has a size of 70-80 mil.

[0021] As an embodiment, the substrate layer has a thickness of 240 to 320 μm and a resistivity of 0.0020 to 10 Ω·cm.

[0022] In some embodiments, the substrate layer has a thickness of 300 μm and a resistivity of 0.042-0.048 Ω·cm.

[0023] In some embodiments, the substrate layer has a resistivity of 0.042-0.044 Ω·cm.

[0024] In some embodiments, the substrate layer has a resistivity of 0.046-0.048 Ω·cm.

[0025] As an embodiment, the thickness of the conductive layer is 0.3 μm to 1.2 μm.

[0026] In some embodiments, the thickness of the first conductive layer is 0.3 μm to 0.8 μm, and the thickness of the second conductive layer is 0.3 μm to 0.5 μm.

[0027] As an embodiment, the groove has a depth of 20 μm to 150 μm and a width of 200 μm to 500 μm.

[0028] In some embodiments, the groove has a depth of 60 μm to 70 μm and a width of 270 μm to 300 μm.

[0029] As an embodiment, the oxide layer is in the form of a rounded rectangular ring with a thickness of The ring edge width is 10μm to 100μm.

[0030] In some embodiments, the thickness of the oxide layer is The ring edge width is 20μm to 30μm.

[0031] As an embodiment, the thickness of the passivation layer is

[0032] In some embodiments, the thickness of the passivation layer is

[0033] As an embodiment, the thickness of the table glass layer is 5 μm to 25 μm.

[0034] In some embodiments, the thickness of the mesa glass layer is 8 μm to 12 μm.

[0035] As an embodiment, the height of the glass layer from the arc-shaped bottom of the passivation layer is 20 μm to 150 μm.

[0036] In some embodiments, the height of the glass layer from the arc-shaped bottom of the passivation layer is 60 μm to 70 μm.

[0037] As an embodiment, the width of the LTO layer is 10 μm to 100 μm.

[0038] In some embodiments, the width of the LTO layer is 20 μm to 30 μm.

[0039] As an embodiment, the thickness of the nickel layer in the nickel-gold layer is 0.3-0.8 μm, and the thickness of the gold layer is 0.3-0.5 μm.

[0040] In some embodiments, the thickness of the nickel layer in the nickel-gold layer is 0.4 μm, and the thickness of the gold layer is 0.4 μm.

[0041] <Second Aspect>

[0042] The present invention provides a method for preparing a TVS device with glass passivation protection, comprising the following steps:

[0043] First, conductive layers are provided on both sides of the substrate layer to obtain a sandwich structure, wherein at least one side of the substrate layer is provided with a first conductive layer of a conductivity type opposite to that of the substrate layer, and at most one side of the substrate layer is provided with a second conductive layer of a conductivity type opposite to that of the substrate layer;

[0044] second, performing oxidation treatment on the surface of the first conductive layer to obtain an oxide layer;

[0045] Third, a groove is etched on the surface of the oxide layer;

[0046] Fourth, a passivation layer is deposited on the surface of the oxide layer and the trench;

[0047] Fifth, a glass layer is formed on the surface of the passivation layer at the corner position between the oxide layer and the groove, thereby obtaining a chip having the glass layer covering the corner position of the passivation layer surface;

[0048] Sixth, the chip processed in the fifth step is subjected to a low temperature oxidation treatment to obtain a chip having an LTO layer covering the surface of the passivation layer except for the glass layer;

[0049] Seventh, etching a lead hole in the middle of the LTO layer of the chip processed in step 6 to a depth where the first conductive layer is exposed;

[0050] Eighth, plating a nickel-gold layer on the conductive layers provided on both sides of the chip processed in the seventh step;

[0051] Ninth, inspect, cut and separate the chips to obtain the TVS devices.

[0052] As an embodiment, in the first step, conductive layers are respectively provided on both sides of the substrate layer, and first conductive layers are respectively provided on both sides of the substrate layer.

[0053] In some embodiments, the substrate layer is a P-type substrate, and the first conductive layer is an N-type doped region.

[0054] In some embodiments, the substrate layer is an N-type substrate, and the first conductive layer is a P-type doped region.

[0055] As an embodiment, in the first step, conductive layers are respectively provided on both sides of the substrate layer, with the first conductive layer being provided on one side of the substrate layer and the second conductive layer being provided on the other side.

[0056] In some embodiments, the substrate layer is a P-type substrate, the first conductive layer is an N-type doped region, and the second conductive layer is a P-type main expansion region.

[0057] In some embodiments, the substrate layer is an N-type substrate, the first conductive layer is a P-type doped region, and the second conductive layer is an N-type main expansion region.

[0058] As an embodiment, the sheet resistance of the sandwich structure is ≤2.5Ω / □, and the PN junction depth is 20 to 80 μm.

[0059] In some embodiments, the sheet resistance of the sandwich structure is 2.1Ω / □, and the PN junction depth is 45-46μm.

[0060] As an embodiment, in the second step, the oxidation treatment is: the sandwich structure is heated at 1000-1200°C, 2-3 L / min nitrogen and 1-5 L / min oxygen are introduced, and the surface of the first conductive layer is formed. oxide layer.

[0061] In some embodiments, the oxidation treatment is as follows: the sandwich structure is oxidized at 1100°C with 2L / min nitrogen and 5L / min oxygen for 0.75h to obtain a thickness of oxide layer.

[0062] As an embodiment, before the second step, the sandwich structure is sandblasted, cleaned, and sequentially cleaned in SC1 cleaning solution and SC2 cleaning solution.

[0063] In some embodiments, the sandblasting process is to use diamond abrasive to remove the front and back surfaces of the NPN structure after step S10, with a thickness of 1 to 4 μm.

[0064] In some embodiments, the cleaning process is to first place the sandblasted sample in deionized water for ultrasonic cleaning, then soak it in an alkaline cleaning solution, and finally soak it in a hydrofluoric acid solution.

[0065] In some embodiments, the ammonium hydroxide-hydrogen peroxide-water cleaning solution is prepared according to a mass ratio of ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:9.2, and the hydrochloric acid-hydrogen peroxide-water cleaning solution is prepared according to a mass ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:9.2.

[0066] As an embodiment, in the third step, the etching steps of the trench are: obtaining a trench pattern by photolithography in one step and removing the oxide layer on the trench area; etching to open the trench; removing the edges; and removing the photoresist.

[0067] In some embodiments, the etching to form the grooves is performed by immersing the sample after the first photolithography in a second mixed acid solution for etching, wherein the second mixed acid solution is prepared according to a mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 5:4:4.

[0068] In some embodiments, edge removal is performed by sequentially immersing the grooved sample in a first mixed acid solution and an ammonium fluoride etching solution to remove the exposed oxide layer at the edge of the chip after the groove is opened. The first mixed acid solution is prepared according to a mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 18:1:1.

[0069] As an embodiment, in the fourth step, the deposition parameters of the passivation layer are: depositing the oxygen-doped polysilicon passivation layer at 500-800°C, and the thickness of the passivation layer is controlled at

[0070] In some embodiments, the deposition parameters of the passivation layer are 650°C, 420 min, and the thickness is passivation layer.

[0071] As an embodiment, before the fourth step, the chip obtained in the third step is cleaned in SC1 cleaning solution and SC2 cleaning solution in sequence.

[0072] As an implementation plan, in the fifth step, first, secondary photolithography is performed to form the dicing lanes and the table glass edge area, and then an electrophoretic method is used to form a uniform glass powder coating on the table glass edge area. Finally, the chip is placed at 570-830°C, nitrogen is introduced to burn off the photoresist on the chip surface, and then the glass is passivated with oxygen to form a uniform and dense glass layer.

[0073] In some embodiments, in the fifth step, the secondary photolithography is: coating photoresist on the surface of the passivation layer, and then developing the photoresist at the corners of the passivation layer and the side portions of the grooves through secondary photolithography to obtain the mesa glass edge area.

[0074] As an embodiment, in the sixth step, the low temperature oxidation treatment is: the chip obtained in the fifth step is oxidized at 360-500°C to form a thickness of LTO layer.

[0075] As an embodiment, in the seventh step, the lead hole area is photoetched three times on the surface of the LTO layer, and then the LTO layer, passivation layer, and oxide layer corresponding to the lead hole area are removed in sequence by wet etching, and finally the photoresist is removed.

[0076] In some embodiments, in the seventh step, the chip after three photolithography processes is immersed in an ammonium fluoride etching solution to remove the LTO layer corresponding to the lead hole area, and the chip is taken out and rinsed with deionized water to remove the residual etching solution.

[0077] In some embodiments, in the seventh step, the chip with the LTO layer corresponding to the lead hole area removed is immersed in a first mixed acid solution to remove the passivation layer corresponding to the lead hole area.

[0078] In some embodiments, in the seventh step, the chip with the passivation layer corresponding to the lead hole area removed is immersed in an ammonium fluoride etching solution to remove the oxide layer corresponding to the lead hole area.

[0079] As an embodiment, in the eighth step, the plating of the nickel-gold layer includes two steps: nickel plating treatment, alloy treatment and back gold treatment.

[0080] As an embodiment, the nickel plating is performed by electroplating or chemical plating.

[0081] In some embodiments, the nickel plating process adopts chemical nickel plating, the plating solution components include nickel chloride, ammonium chloride, diammonium hydrogen citrate, citric acid, and sodium hypophosphite, and the plating temperature is 87-97°C.

[0082] As an embodiment, the alloy treatment is as follows: treating the nickel-plated chip at 520-560° C., with a nitrogen flow of 20-30 L / min, for 25-35 min.

[0083] In some embodiments, the nickel layer in the nickel-gold layer is obtained by nickel plating and alloying, repeating the nickel plating and alloying, and then performing nickel plating again.

[0084] In some embodiments, the back-gold treatment is to place the chip in a gold chloride solution and immerse it at 90-100° C. to obtain a gold layer of 0.3-0.5 μm.

[0085] Compared with the prior art, the present invention has the following beneficial effects:

[0086] The present invention provides a glass-passivated TVS device and a preparation method thereof. Four TVS device implementation schemes are provided, including a P-type bidirectional symmetrical structure, an N-type bidirectional symmetrical structure, a P-type unidirectional asymmetric structure, and an N-type unidirectional asymmetric structure. By optimizing the electrophoretic deposition process and improving the multi-layer composite protective layer, these devices offer significant advantages in improving TVS chip reliability, electrical performance, and production efficiency.

[0087] 1) The electrophoresis process provides efficient and precise protection, achieving improved uniformity and efficiency, and effectively reducing costs

[0088] In the present invention, after the passivation layer (MTO+SIPOS) is deposited, a secondary photolithography followed by electrophoretic deposition of the glass layer is adopted, and the electric field principle is used to evenly coat the glass powder on the designated chip position. This overcomes the defects of uneven glass thickness and cumbersome manual operation in the traditional scraping method, and is not only highly efficient but also has low production costs. In addition, the glass has good uniformity and can ensure the reliability of the chip.

[0089] 2) Optimize the density of the glass layer to eliminate the hidden dangers of bubbles

[0090] In the present invention, while ensuring the uniform thickness of the glass layer, the glass powder is sintered to form a dense and bubble-free glass layer by optimizing the calcination. Compared with the traditional process, the glass layer prepared by the present invention does not produce bubbles and simplifies the calcination process.

[0091] 3) Multi-layer composite structure to build a comprehensive protection system

[0092] The composite protective layer formed from the chip surface upwards realizes gradient protection from the chip surface to the metallization layer. The planar area is double-insulated and isolated by the oxide layer and the MTO layer to suppress leakage; the MTO+SIPOS composite passivation layer in the groove area enhances the uniformity of the electric field and improves the voltage resistance; the dense and bubble-free glass layer isolates external impurities; the LTO layer enhances impact resistance; the metal layer optimizes the conductive performance and reduces the contact resistance.

[0093] 4) Leakage control and electrical performance improvement

[0094] This invention utilizes a passivation layer (MTO+SIPOS) and a secondary photolithography-based electrophoretic glass layer to stabilize the chip while also protecting it from adverse external environments. This solves numerous drawbacks, such as instability in the reverse characteristic curve and high reverse leakage current. This ensures excellent stability and reliability in high-temperature environments, making the chip adaptable to a variety of environments and improving its practicality. In addition to ensuring reliable performance, this process also controls leakage current to below 0.1μA, with a breakdown voltage of over 20V (for TVS devices with P-type substrates) and over 38V (for TVS devices with N-type substrates). BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0096] Figure 1 Schematic diagrams of substrates used in Examples 5 to 8 of the present invention, wherein (a) corresponds to a P-type substrate, and (b) corresponds to an N-type substrate;

[0097] Figure 2 Schematic diagrams of the sandwich structures prepared in Examples 5 to 8 of the present invention, wherein (a) is an NPN structure, (b) is a PNP structure, (c) is an NPP structure, and (d) is a PNN structure;

[0098] Figure 3 Comparative photographs of chips with and without an oxide layer during a single photolithography step in Example 5 of the present invention and a comparative example, wherein (a) corresponds to Example 5, and (b) corresponds to the comparative example;

[0099] Figure 4 Schematic diagrams of the chips with grooves prepared in Examples 5 to 8 of the present invention, wherein (a) corresponds to Example 5, (b) corresponds to Example 6, (c) corresponds to Example 7, and (d) corresponds to Example 8;

[0100] Figure 5 Schematic diagrams of chips with passivation layers deposited thereon prepared in Examples 5 to 8 of the present invention, wherein (a) corresponds to Example 5, (b) corresponds to Example 6, (c) corresponds to Example 7, and (d) corresponds to Example 8;

[0101] Figure 6 Schematic diagrams of chips with glass layers deposited thereon prepared in Examples 5 to 8 of the present invention, wherein (a) corresponds to Example 5, (b) corresponds to Example 6, (c) corresponds to Example 7, and (d) corresponds to Example 8;

[0102] Figure 7Schematic diagrams of chips deposited with LTO layers prepared in Examples 5 to 8 of the present invention, wherein (a) corresponds to Example 5, (b) corresponds to Example 6, (c) corresponds to Example 7, and (d) corresponds to Example 8;

[0103] Figure 8 Schematic diagrams of TVS devices prepared in Examples 5 to 8 of the present invention, wherein (a) corresponds to Example 5, (b) corresponds to Example 6, (c) corresponds to Example 7, and (d) corresponds to Example 8;

[0104] Figure 9 Microscopic observation photos of the glass layer of the TVS devices prepared in Examples 5 to 8 of the present invention, wherein (a) corresponds to Example 5, (b) corresponds to Example 6, (c) corresponds to Example 7, and (d) corresponds to Example 8;

[0105] Figure 10 The leakage current test results of the TVS devices prepared in Examples 5 to 8 of the present invention are shown, wherein (a) corresponds to Example 5, (b) corresponds to Example 6, (c) corresponds to Example 7, and (d) corresponds to Example 8;

[0106] Figure 11 1 and 2 are reverse characteristic curves of the TVS devices prepared in Examples 5 to 8 of the present invention, wherein (a) corresponds to Example 5, (b) corresponds to Example 6, (c) corresponds to Example 7, and (d) corresponds to Example 8. DETAILED DESCRIPTION

[0107] The present invention will be described in detail below with reference to the examples. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that those skilled in the art may make several adjustments and improvements without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0108] This specific embodiment provides a TVS device with glass passivation protection and a preparation method thereof. P-type and N-type substrates, unidirectional sheets and bidirectional sheets are used as substrates for preparing TVS devices, and are specifically introduced through Examples 1 to 4.

[0109] Example 1

[0110] This embodiment provides a P-type bidirectional symmetrical TVS device with glass passivation protection, including a P-type substrate and:

[0111] N-type doped regions located on the upper and lower sides of the P-type substrate;

[0112] Trenches are opened on the edges of the upper and lower sides of the device, with the bottom of the trench located in the P-type substrate layer, and the bottom of the trench gradually deepens from the inside to the outside;

[0113] Above the upper N-type doped region, the central region is covered with a nickel-gold layer, with nickel on the inner layer and gold on the outer layer; the outer region adjacent to the central region is covered with an oxide layer;

[0114] A continuous passivation layer is covered on the oxide layer and the trench. The passivation layer above the oxide layer is planar, and the passivation layer on the trench is arc-shaped, similar to the structure of the Chinese character "厂" in a longitudinal section;

[0115] The passivation layer is composed of a SIPOS layer on the inner layer and an MTO layer on the outer layer;

[0116] An LTO layer and a glass layer are covered above the passivation layer:

[0117] The glass layer is covered at the corner position of the passivation layer. The corner position is formed by the outer edge of the planar part of the passivation layer and the upper arc connected thereto;

[0118] The LTO layer is covered on the planar region and the bottom arc region of the passivation layer. The outer side of the LTO layer covering the planar region stops before the corner position;

[0119] The LTO layer and the glass layer contact each other to form a transition region, and the connection position of the two is in the way that the glass layer is below and the LTO layer is above. The size of the transition region in the planar position is 1.23 ± 0.01 mm, and the size of the transition region in the arc position is 0.078 ± 0.005 mm;

[0120] Nickel-gold layer, oxide layer, passivation layer and glass layer are symmetrically provided on the outer sides of the trench under the P-type substrate and the N-type doped region.

[0121] Embodiment 2

[0122] This embodiment provides a glass-passivated protected N-type bidirectional symmetric structure TVS device, including an N-type substrate, and further including:<00​​​​​​​​​​​​​​

[0128] The passivation layer is composed of an inner SIPOS layer and an outer MTO layer;

[0129] An LTO layer and a glass layer are covered above the passivation layer:

[0130] The glass layer is covered at the corner position of the passivation layer, and the corner position is formed by the outer edge of the passivation layer plane and the upper arc connected thereto;

[0131] The LTO layer is covered on the planar area and the bottom area of the arc of the passivation layer, and the outer side of the LTO layer covering the planar area stops before the corner position;

[0132] The LTO layer and the glass layer contact each other to form a transition zone, and the connection position of the two is such that the glass layer is below and the LTO layer is above. The size of the transition zone in the planar position is 1.53 ± 0.01 mm, and the size of the transition zone in the arc position is R0.1 ± 0.005 mm;

[0133] Nickel-gold layers, oxide layers, passivation layers and glass layers are symmetrically arranged outside the grooves and P-type doping regions on the lower side of the N-type substrate.

[0134] Embodiment 3

[0135] This embodiment provides a P-type unidirectional asymmetric structure TVS device with glass passivation protection, including a P-type substrate, and further including:

[0136] An N-type doping region on the upper side of the P-type substrate;

[0137] A P-type main diffusion region on the lower side of the P-type substrate;

[0138] Grooves are provided at the four peripheral edges on the upper side of the device, and the bottom of the grooves is located in the P-type substrate layer, and the bottom of the grooves gradually deepens from the inside to the outside;

[0139] Above the upper N-type doping region, a nickel-gold layer is covered in the central region, with nickel on the inner layer and gold on the outer layer; an oxide layer is covered in the outer region adjacent to the central region;

[0140] An oxide layer is sequentially arranged around the upper N-type doping region;

[0141] A continuous passivation layer is covered on the oxide layer and the grooves. The passivation layer above the oxide layer is planar, and the passivation layer on the grooves is arc-shaped, which is similar to a "factory" character structure in the longitudinal section;

[0142] The passivation layer is composed of an inner SIPOS layer and an outer MTO layer; <着ID=46>

[0143] An LTO layer and a glass layer are covered above the passivation layer:

[0144] A glass layer is covered on the corner position of the passivation layer, and the corner position is formed by the outer edge of the plane of the passivation layer and the upper arc connected thereto;

[0145] An LTO layer is covered on the planar area and the bottom area of the arc of the passivation layer, and the outer side of the LTO layer covering the planar area stops before the corner position;

[0146] The LTO layer and the glass layer contact each other to form a transition zone, and the connection position of the two is such that the glass layer is below and the LTO layer is above. The size of the transition zone in the planar position is 1.23 ± 0.01 mm, and the size of the transition zone in the arc position is 0.078 ± 𝟘.𝟘𝟘𝟝 mm;

[0147] A nickel-gold layer is covered on the lower side of the P-type main diffusion region.

[0148] Example 4

[0149] This example provides a glass-passivated protected N-type unidirectional asymmetric structure TVS device, including an N-type substrate, and further including:

[0150] A P-type doping region located on the upper side of the N-type substrate;

[0151] An N-type main diffusion region located on the lower side of the N-type substrate;

[0152] Grooves are provided on the four peripheral edges on the upper side of the device, and the bottom of the grooves is located in the N-type substrate layer, and the bottom of the grooves gradually deepens from the inside to the outside;

[0153] Above the upper-side P-type doping region, a nickel-gold layer is covered in the central region, with nickel on the inner layer and gold on the outer layer; an oxide layer is covered in the outer region adjacent to the central region;

[0154] An oxide layer is sequentially provided around the upper-side P-type doping region;

[0155] A continuous passivation layer is covered on the oxide layer and the grooves. The passivation layer above the oxide layer is planar, and the passivation layer above the grooves is arc-shaped, which is similar to a "factory" character structure in the longitudinal section;

[0156] The passivation layer is composed of a SIPOS layer on the inner layer and an MTO layer on the outer layer;

[0157] An LTO layer and a glass layer are covered above the passivation layer:

[0158] A glass layer is covered on the corner position of the passivation layer, and the corner position is formed by the outer edge of the plane of the passivation layer and the upper arc connected thereto;

[0159] An LTO layer is covered on the planar area and the bottom area of the arc of the passivation layer, and the outer side of the LTO layer covering the planar area stops before the corner position;

[0160] The LTO layer and the glass layer contact each other to form a transition zone, and the connection position between the two is such that the glass layer is at the bottom and the LTO layer is at the top. The size of the transition zone in the flat position is 1.53±0.01mm, and the size of the transition zone in the curved position is R0.1±0.005mm;

[0161] The lower side of the N-type main expansion region is covered with a nickel-gold layer.

[0162] Example 5

[0163] This embodiment provides a method for preparing a P-type bidirectional symmetrical TVS device with glass passivation protection, comprising the following steps:

[0164] S1. Silicon wafer inspection

[0165] Take a 5-inch P-type substrate with a thickness of 240 to 320 μm (300 μm in this embodiment) and a resistivity of 0.0020 to 10 Ω·cm (0.042 Ω·cm in this embodiment). Figure 1 As shown in (a).

[0166] S2, surface acid corrosion

[0167] Prepare a first mixed acid solution according to the mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 18:1:1, and prepare a hydrofluoric acid solution according to the mass ratio of hydrofluoric acid: pure water = 1:1;

[0168] First, the substrate in step S1 is immersed in the first mixed acid solution at room temperature for 25 to 35 seconds (28 seconds in this embodiment) to remove the damaged layer on the substrate surface; then the substrate is immersed in a hydrofluoric acid solution at room temperature of 25±5°C for 2 to 4 minutes (3 minutes in this embodiment) to remove the silicon powder and oxide layer on the substrate surface.

[0169] S3, pre-expansion processing

[0170] Prepare SC1 solution at a mass ratio of ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:9.2, and prepare SC2 solution at a mass ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:9.2;

[0171] First, the substrate treated in step S2 is immersed in SC1 solution at 50-60°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove organic pollutants and impurities on the substrate surface; then the substrate is immersed in SC2 solution at 45-65°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove metal ions on the substrate surface.

[0172] S4, pre-expansion processing

[0173] Use diffusion equipment and materials to perform N-type doping on both sides of the S3-treated substrate;

[0174] The diffusion equipment is a high-temperature furnace and a quartz tube, and the materials are oxygen, nitrogen and phosphorus oxychloride;

[0175] The process conditions are as follows: diffusion temperature 1000-1200° C. (1200° C. in this embodiment), time 6-8 h (7 h in this embodiment), nitrogen 1.5-4 L / min (4 L / min in this embodiment), oxygen 0.5-1 L / min (0.5 L / min in this embodiment);

[0176] A substrate in which N-doping is performed on the upper and lower sides of a P-type substrate is obtained.

[0177] S5, pre-expansion post-processing

[0178] Prepare hydrofluoric acid solution by mixing hydrofluoric acid and water in a mass ratio of 1:1;

[0179] The substrate after the S4 treatment is cleaned with a hydrofluoric acid solution for 8 to 12 minutes (10 minutes in this embodiment) to remove surface diffusion source impurities and diffusion reaction byproducts.

[0180] S6, pre-expansion test

[0181] Test the sheet resistance of pre-expanded silicon wafers.

[0182] When the tested substrate resistance is 250-450 mΩ / □, proceed to the next step.

[0183] In this embodiment, the sheet resistance of the substrate after the S5 process is 330 mΩ / □.

[0184] S7, main expansion pre-processing

[0185] Prepare SC1 solution and SC2 solution again, as shown in step S3;

[0186] The substrate that has passed the S6 inspection is immersed in SC1 solution at 50-60°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove organic pollutants and impurities on the substrate surface; then the substrate is immersed in SC2 solution at 45-65°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove metal ions on the substrate surface.

[0187] S8, main expansion processing

[0188] Use diffusion equipment and materials to perform main diffusion treatment on the surface of the substrate after S7 treatment;

[0189] The diffusion equipment is a high-temperature furnace and silicon carbide tube, and the materials are oxygen and nitrogen;

[0190] Process conditions: in a furnace tube at 1100-1280°C (1250°C in this embodiment), nitrogen at 2-3 L / min and oxygen at 1 L / min, and the main expansion is performed to the corresponding cut-off voltage (18 V in this embodiment);

[0191] An NPN structure is obtained in which the upper and lower sides of a P-type substrate are covered with N-type doping regions.

[0192] S9, main expansion post-processing

[0193] Prepare hydrofluoric acid solution, as shown in step S5;

[0194] The NPN structure after S8 treatment is cleaned with hydrofluoric acid for 8 to 12 minutes (10 minutes in this embodiment) to remove surface diffusion source impurities and diffusion reaction byproducts.

[0195] S10, inspection after main expansion

[0196] Test the sheet resistance and PN junction depth of the NPN structure after S9 processing.

[0197] When the junction depth is between 20 and 80 μm and the sheet resistance is ≤ 2.5 Ω, proceed to the next step;

[0198] In this embodiment, the sheet resistance of the NPN structure after the S9 process is 2.1Ω / □, and the PN junction depth is 46μm.

[0199] S11, sandblasting

[0200] Use diamond blasting to remove the front and back surfaces of the NPN structure after step S10, with a thickness of 1 to 4 μm;

[0201] The process parameters of sandblasting in this embodiment are: belt speed 16.5 mm / s, sandblasting pressure 0.05 MPa, and removal thickness of 1.5 μm on both sides.

[0202] S12, cleaning after sandblasting

[0203] Prepare hydrofluoric acid solution as in step S5, and prepare alkaline cleaning solution according to the ratio of sodium hydroxide: deionized water = 4kg:20L;

[0204] First, the NPN structure after S11 treatment is placed in deionized water for ultrasonic cleaning for 30 minutes; then it is immersed in an alkaline cleaning solution at 45-55°C (50°C in this embodiment) for 5 minutes to remove the residual corundum on the surface of the substrate; and then immersed in a hydrofluoric acid solution for 4-6 minutes (5 minutes in this embodiment) to remove the surface alkaline solution and oxide layer.

[0205] S13, oxidation pretreatment

[0206] Prepare SC1 solution and SC2 solution again, as shown in step S3;

[0207] The NPN structure after S12 treatment is immersed in SC1 solution at 50-60°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove organic pollutants and impurities on the surface; then the NPN structure is immersed in SC2 solution at 45-65°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove surface metal ions.

[0208] S14, oxidation treatment

[0209] The surface of the NPN structure after S13 treatment is oxidized using diffusion equipment and materials;

[0210] The diffusion equipment is a high-temperature furnace and a quartz tube, and the materials are oxygen and nitrogen;

[0211] Process parameters: Place the NPN structure after S13 treatment in a constant temperature zone of 1000-1200°C (1100°C in this embodiment), introduce 2-3 L / min (2 L / min in this embodiment) nitrogen and 1-5 L / min (5 L / min in this embodiment) oxygen to generate The oxidation time in this embodiment is 0.75h and the thickness of the oxide layer is

[0212] After oxidation treatment, the substrate Figure 2 As shown in (a), a double-sided oxidation structure is obtained in which the N-type doped region and the oxide layer are sequentially covered on the upper and lower sides of the P-type substrate.

[0213] S15, one-shot lithography

[0214] After the double-sided oxidation structure is processed in step S14, a trench pattern is formed on the edges of the upper and lower surfaces, and the oxide layer on the trench area is removed. Figure 3 As shown in (a), it can be seen that there is an oxide layer during the first photolithography, and no floating glue or acid drilling occurs during the etching and grooving process, and the chip is neat and without deformation;

[0215] Process parameters: photoresist thickness 8±3 μm, exposure light intensity 12-20 mW (15 mW in this embodiment), development time 9 min, rinse time 6 min, ammonium fluoride etching solution (reagent grade in this embodiment) temperature 40±2° C., etching time 6 min;

[0216] The equipment involved includes glue coating machine, double-sided exposure machine, developer and rinse machine, oxide layer etching machine, and the materials involved include photoresist, developer, rinse solution, and ammonium fluoride etching solution.

[0217] S16, open the chip in the corrosion groove

[0218] Prepare a second mixed acid solution according to the mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 5:4:4;

[0219] The double-sided oxide structure after step S15 is immersed in a second mixed acid solution for 0.5 to 10 minutes (340 seconds in this embodiment) to etch the silicon surface without photoresist protection to open a groove. The target depth of the groove is 65 to 70 μm. In this embodiment, the depth of the groove exceeds the PN junction by 20 μm, forming a chip prototype.

[0220] After processing, the double-sided oxidation structure of the chip with grooves is Figure 4 As shown in (a), the bottom of the trench is located in the P-type substrate layer.

[0221] S17, De-edging

[0222] Prepare a first mixed acid solution, as shown in S2;

[0223] First, the chip treated in step S16 is immersed in the first mixed acid solution for 30 to 60 seconds (60 seconds in this embodiment), and then immersed in an ammonium fluoride etching solution (reagent grade in this embodiment) at 38 to 42° C. (40° C. in this embodiment) for 1 to 3 minutes (2 minutes in this embodiment) to remove the oxide layer exposed at the edge of the chip after the double-sided oxide structure is grooved, and to prepare for the subsequent deposition of glass powder at the corner position.

[0224] S18, remove photoresist

[0225] First, the chip treated in step S17 is immersed in sulfuric acid (concentration of 98%) at 70-120° C. (120° C. in this embodiment) for 45 minutes to remove the photoresist on the chip surface; then immersed in hydrogen peroxide for 0.8-1.2 minutes (1 minute in this embodiment); then ultrasonically cleaned with deionized water for 30 minutes; finally, immersed in ammonium fluoride etching solution (reagent grade in this embodiment) for 20 seconds.

[0226] S19, RCA cleaning

[0227] Prepare SC1 solution and SC2 solution, as shown in step S3;

[0228] The chip treated in step S18 is immersed in SC1 solution at 50-60°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove organic pollutants and impurities on the chip surface and grooves; then the substrate is immersed in SC2 solution at 45-65°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove metal ions on the chip surface and grooves.

[0229] S20, passivation layer deposition

[0230] The chip after being cleaned in step S19 is heated at 500 - 800 °C (650 °C in this embodiment) to form an oxygen-doped polysilicon passivation layer (MTO + SIPOS). The thickness of the passivation layer is In this embodiment, the deposition time is 420 min, and the thickness of the prepared passivation layer is

[0231] The chip after being processed in step S20 is as Figure 5 (a) shown. The passivation layer covers the oxide layers and trenches on the upper and lower sides. The cross-sectional shape of the passivation layer is similar to the shape formed by connecting two "factory" characters facing each other.

[0232] S21, secondary lithography

[0233] On the chip obtained in step S20, scribe lanes and the mesa glass edge regions are lithographed;

[0234] Process parameters: the thickness of the photoresist is 10 ± 3 μm (10 μm in this embodiment), the exposure light intensity is 12 - 20 mW (12 mW in this embodiment), the development time is 9 min, and the rinsing time is 6 min;

[0235] The equipment involved includes a spin coater, a single-sided exposure machine, a development and rinsing machine. The materials involved include photoresist, developer, and rinsing solution.

[0236] In this embodiment, the photoresist selectively covers the passivation layer, and the corner positions of the "factory" character structure of the passivation layer are exposed (not covered with photoresist). The top plane and the bottom of the arc-shaped trench except for the corner positions are covered with photoresist. That is, the corner positions are the mesa glass edge regions.

[0237] S22, electrophoresis [[ID=I]]

[0238] A suspension is prepared according to the ratio of acetone: nitric acid: glass powder = 10 L: 2 mL: 30 g. Using an electrophoresis machine, charged particles move directionally under the action of an electric field, and glass powder is coated on the corner positions of the passivation layer on both the front and back sides of the chip after secondary lithography to form a uniform glass powder coating layer. In this embodiment, the voltage is 280 V, the current is 200 mA, the electrophoresis time is 1 min, and the electrode spacing is 6 cm.

[0239] S23, firing

[0240] The chip after being processed in step S22 is heated at 570 - 830 °C (820 °C in this embodiment). First, nitrogen is introduced at 10 L / min for 2 min to burn off the photoresist on the chip surface, and then oxygen is introduced at 3 - 7 L / min (7 L / min in this embodiment) for 90 min for glass passivation to form a uniform and dense glass layer.

[0241] The chip after step S23 is as follows Figure 6 As shown in (a), the glass layer covers the corners of the passivation layer.

[0242] S24, low temperature oxidation treatment

[0243] The chip after step S23 is oxidized at 360-500°C (430°C in this embodiment) to form a thickness of (This embodiment is ) silicon dioxide film (LTO) is used to resist tin flowing into the glass edge area and external physical impact.

[0244] The chip after step S24 is as follows Figure 7 As shown in (a), the passivation layer (except the area outside the glass layer) is covered with an LTO layer, and the area where the LTO layer and the glass layer contact each other is the transition zone. The size of the transition zone in the plane position is 1.23±0.01mm, and the size of the transition zone in the arc position is 0.078±0.005mm.

[0245] S25, three-stage lithography

[0246] Photolithography of lead hole areas on both the front and back sides of the chip processed in step S24;

[0247] Process parameters: photoresist thickness 12±3 μm (12 μm in this embodiment), exposure light intensity 12-20 mW (15 mW in this embodiment), development time 9 min, rinse time 6 min;

[0248] The equipment involved includes glue coating machine, single-sided exposure machine, developer and rinse machine, oxide layer etching machine, and the materials involved include photoresist, developer, and rinse solution.

[0249] S26, wet etching

[0250] As shown in step S2, a first mixed acid solution is prepared;

[0251] The LTO at the lead is removed by soaking in an ammonium fluoride etching solution (reagent grade in the present embodiment) at 38 to 42° C. (40° C. in the present embodiment) for 1 to 3 minutes (2 minutes in the present embodiment), and the chip is removed and rinsed with deionized water to remove the residual ammonium fluoride etching solution. The chip is then soaked in a first mixed acid solution at -1 to -3° C. (-2° C. in the present embodiment) for 2 to 4 minutes (3 minutes in the present embodiment) to remove the SIPOS, and then soaked in an ammonium fluoride etching solution (reagent grade in the present embodiment) at 38 to 42° C. (40° C. in the present embodiment) for 2 to 4 minutes (3 minutes in the present embodiment) to remove the oxide layer at the lead.

[0252] S27, remove photoresist

[0253] First, immerse the chip processed in step S26 in sulfuric acid (concentration: 98%) at 70 - 120°C (120°C in this embodiment) for 45 min to remove the photoresist on the chip surface; then soak it in hydrogen peroxide for 0.8 - 1.2 min (1 min in this embodiment); and then ultrasonically clean it with deionized water for 30 min.

[0254] Obtain a chip with the LTO layer, passivation layer, and oxidation layer etched in the middle of the upper and lower sides, that is, the exposed areas in the middle of the upper and lower sides of the chip are N - type doping regions.

[0255] After etching, the shape where the two "factory" characters are connected opposite to each other in the longitudinal section of the passivation layer is disconnected, forming two symmetrical "factory" shapes.

[0256] S28, Metallization

[0257] Perform nickel plating on the N - type doping regions exposed on the upper and lower sides of the chip processed in step S27. Use the electroless nickel plating method. The components of the plating solution are nickel chloride, ammonium chloride, diammonium hydrogen citrate, citric acid, and sodium hypophosphite. The process temperature is 87 - 97°C (92°C in this embodiment).

[0258] S29, Alloying

[0259] Place the chip processed in step S28 in an atmospheric furnace. The process temperature is 520 - 560°C (540°C in this embodiment), the time is 25 - 35 min (30 min in this embodiment), and the nitrogen flow rate is 20 - 30 L / min (25 L / min in this embodiment) to form a good ohmic contact between silicon and the metal.

[0260] S30, Repeat Metallization and Alloying

[0261] Repeat steps S28 and S29 once, and then repeat step S28 to obtain a chip with a plating thickness of 0.3 - 0.8 μm (0.4 μm in this embodiment).

[0262] S31, Back - gold plating

[0263] Put the chip processed in step S30 into a gold chloride solution for back - gold plating. The process temperature is 90 - 100°C (95°C in this embodiment) to obtain a gold layer with a thickness of 0.3 - 0.5 μm (0.4 μm in this embodiment).

[0264] The chip processed in step S31 is as Figure 8 shown in (a), obtaining a chip with N - type doping regions covered with nickel - gold layers in the middle of the upper and lower sides.

[0265] S32, Test and Dicing

[0266] Inspect the performance of the die, cut and separate the chips, and select good products for packaging.

[0267] Example 6

[0268] This embodiment provides a method for preparing an N-type bidirectional symmetrical TVS device with glass passivation protection. The steps are basically the same as those in Example 5, except that:

[0269] In step S1, the P-type substrate is replaced with an N-type substrate. In this embodiment, the N-type substrate has a resistivity of 0.047Ω·cm. Figure 1 (b) shown.

[0270] In step S4, the materials are oxygen, nitrogen and a boron source. The boron source is evenly applied to both sides of the substrate, baked at 180-200°C (180°C in this embodiment) for 15-30 seconds (15 seconds in this embodiment), and then pre-expansion treatment is performed;

[0271] The process conditions of the pre-expansion treatment are: diffusion temperature 1000-1180° C. (1150° C. in this embodiment), time 4-7 h (7 h in this embodiment), nitrogen 9-11 L / min (9 L / min in this embodiment), oxygen 0.2-0.4 L / min (0.4 L / min in this embodiment); the boron source in this embodiment is a boron latex source;

[0272] A substrate with P doping performed on the upper and lower sides of an N-type substrate is obtained.

[0273] In step S6, the sheet resistance of the substrate in this embodiment is 1.8Ω / □.

[0274] In step S8, the corresponding cutoff voltage in this embodiment is 33V, and a PNP structure with P-type doping regions covering the upper and lower sides of an N-type substrate is obtained.

[0275] In step S10 , the sheet resistance of the PNP structure in this embodiment is 2.1Ω / □, and the PN junction depth is 45μm.

[0276] The PNP structure after oxidation treatment in step S14 is as follows Figure 2 (b) shown.

[0277] The double-sided oxide structure with grooves after the S16 step is as follows Figure 4 As shown in (b), the bottom of the trench is located in the N-type substrate layer, and the bottom of the trench gradually deepens from the inside to the outside.

[0278] The thickness of the passivation layer after step S20 is Chip such as Figure 5 (b) shown.

[0279] The chip after step S23 is as follows Figure 6 (b) shown.

[0280] The chip after step S24 is as follows Figure 7 (b) shown.

[0281] After the processing in step S27, the exposed areas in the middle of the upper and lower sides of the chip are P-type doped areas.

[0282] In step S28, the exposed P-type doped regions on the upper and lower sides of the chip processed in step S27 are subjected to nickel plating. The parameters are as in Example 5.

[0283] The chip after step S31 is as follows Figure 8 As shown in (b), a chip is obtained in which the middle parts of the upper and lower sides are P-type doped regions covered with a nickel-gold layer.

[0284] Example 7

[0285] This embodiment provides a method for preparing a P-type unidirectional asymmetric TVS device with glass passivation protection. The steps are basically the same as those in Example 5, except that:

[0286] In step S4, the process conditions are the same, but N-type doping is performed only on the front side of the P-type substrate to obtain an N-doped substrate on the front side of the P-type substrate.

[0287] In step S6, the sheet resistance of the substrate is 350 mΩ / □.

[0288] After step S6 and before step S7, two steps of sandblasting and cleaning are added, specifically:

[0289] Sandblasting: Use diamond abrasive to remove the back surface of the P-type unidirectional substrate, removing 20 to 30 μm (25 μm in this embodiment). The sandblasting process parameters are a belt speed of 16.5 mm / s and a sandblasting pressure of 1.1 MPa.

[0290] Cleaning after sandblasting: the same as step S12 in Example 5.

[0291] In step S8, a boron latex source is first evenly applied to the back of the P-type substrate, and baked at 180-200°C (180°C in this embodiment) for 15-30s (30s in this embodiment), and then the main expansion treatment is performed. The process conditions of the main expansion treatment are consistent with those of step S8 in Example 5. The corresponding cutoff voltage in this embodiment is 18V, and an NPP structure is obtained in which the front side of the P-type substrate is covered with an N-type doped region and the back side is covered with a P-type main expansion region.

[0292] In step S10, the sheet resistance of the NPP structure is 2.1Ω and the PN junction depth is 45μm.

[0293] The double-sided oxidation structure after the oxidation treatment in step S14 is as follows Figure 2 (c) shown.

[0294] In step S15, a groove area is photoetched on the front side of the double-sided oxidation structure processed in step S14, and the oxide layer on the groove area is removed; the equipment, materials and process parameters refer to step S15 in Example 5, but the double-sided exposure machine in the equipment involved is replaced by a single-sided exposure machine.

[0295] After the S16 step, the chip with double-sided oxidation structure with grooves on the front side is processed. Figure 4 As shown in (c), the bottom of the trench is located in the P-type substrate layer, and the bottom of the trench gradually deepens from the inside to the outside.

[0296] The thickness of the passivation layer after step S20 is Chip such as Figure 5 As shown in (c), the oxide layer and the groove on the front side of the chip are covered with a passivation layer, and the cross-sectional shape of the passivation layer is referred to Example 5 (only the front side is provided with a passivation layer).

[0297] In step S21, scribe lines and mesa glass edge areas are photoetched on the corners of the front passivation layer of the chip obtained in step S20. The process parameters are the same as those of step S21 in Example 5.

[0298] In step S22, a uniform glass powder coating is formed at the corners of the passivation layer on the front side of the chip.

[0299] The chip after step S23 is as follows Figure 6 As shown in (c), the corners of the chip's front passivation layer are covered with a glass layer.

[0300] The chip after step S24 is as follows Figure 7 As shown in (c), the chip front passivation layer (except the area of ​​the glass layer) is covered with an LTO layer.

[0301] In step S25, a lead hole area is photoetched on the front side of the chip processed in step S24. The process parameters refer to step S25 of embodiment 5.

[0302] The exposed area in the middle of the front side of the chip after processing in step S27 is an N-type doped area.

[0303] In step S28, the N-type doped region exposed on the front side and the P-type main expansion region on the back side of the chip processed in step S27 are subjected to nickel plating. The parameters are as in Example 5.

[0304] The chip after step S31 is as follows Figure 8 As shown in (c), a chip with an N-type doped area in the middle of the front and a P-type main expansion area on the back is obtained, both of which are covered with a nickel-gold layer.

[0305] Example 8

[0306] This embodiment provides a method for preparing an N-type unidirectional asymmetric TVS device with glass passivation protection. The steps are basically the same as those in Example 6, except that:

[0307] In step S4, the process conditions are the same, but N-type doping is performed only on the back side of the N-type substrate, thereby obtaining a substrate with P doping on the front side of the N-type substrate.

[0308] In step S6, the sheet resistance of the substrate is 350 mΩ / □.

[0309] After step S6 and before step S7, two steps of sandblasting and cleaning are also included, which are consistent with the steps between step S6 and step S7 in Example 7.

[0310] In step S8, a boron latex source is first evenly applied to the back of the N-type substrate, and then baking and main expansion treatment are performed. The parameters are the same as step S8 of Example 7. In this embodiment, the corresponding cutoff voltage is 33V, and a PNN structure is obtained in which the front side of the N-type substrate is covered with a P-type doped region and the back side is covered with an N-type main expansion region.

[0311] In step S10, the sheet resistance of the PNN structure is 2.1Ω and the PN junction depth is 45μm.

[0312] The double-sided oxidation structure after the oxidation treatment in step S14 is as follows Figure 2 (d) shown.

[0313] In step S15, a trench area is photoetched on the front side of the double-sided oxidation structure processed in step S14, and the oxide layer on the trench area is removed; the equipment, materials and process parameters refer to step S15 of embodiment 7.

[0314] After the S16 step, the chip with double-sided oxidation structure with grooves on the front side is processed. Figure 4 As shown in (d), the bottom of the trench is located in the N-type substrate layer, and the bottom of the trench gradually deepens from the inside to the outside.

[0315] The thickness of the passivation layer after step S20 is Chip such as Figure 5 As shown in (d), the oxide layer and the groove on the front side of the chip are covered with a passivation layer, and the cross-sectional shape of the passivation layer is referred to Example 7.

[0316] In step S21, scribe lines and mesa glass edge areas are photoetched on the corners of the front passivation layer of the chip obtained in step S20. The process parameters refer to step S21 of Example 5.

[0317] In step S22, a uniform glass powder coating is formed at the corners of the passivation layer on the front side of the chip.

[0318] The chip after step S23 is as follows Figure 6 As shown in (d), the corners of the chip's front passivation layer are covered with a glass layer.

[0319] The chip after step S24 is as follows Figure 7 As shown in (d), the chip front passivation layer (except the area of ​​the glass layer) is covered with an LTO layer.

[0320] In step S25, a lead hole area is photoetched on the front side of the chip processed in step S24. The process parameters refer to step S25 of embodiment 5.

[0321] The exposed area in the middle of the front side of the chip after processing in step S27 is a P-type doped area.

[0322] In step S28, the P-type doped region exposed on the front side of the chip processed in step S27 and the N-type main expansion region on the back side are subjected to nickel plating. The parameters are as in Example 5.

[0323] The chip after step S31 is as follows Figure 8 As shown in (d), a chip is obtained in which the middle part of the front side is a type doped region and the back side N-type main expansion region is covered with a nickel-gold layer.

[0324] Comparative Example

[0325] This comparative example provides a method for preparing a TVS device without an oxide layer. The steps are basically the same as those in Example 5, except that:

[0326] The oxidation treatment in step S14 is not performed.

[0327] That is to say, when the photolithography is carried out once, there is no oxide layer in the groove, and it is easy to produce floating glue or acid drilling during the etching and grooving process, resulting in serious deformation of the chip, such as Figure 3 As shown in (b), it has a great impact on the reliability performance of the chip.

[0328] Application performance testing:

[0329] (1) Glass layer inspection of TVS devices prepared in Examples 5 to 8

[0330] Inspection steps: Observe the inside of the glass at 50 times the magnification through a microscope to check for bubbles, and carefully observe the surface and interior of the glass to check for impurities such as dust, sand, and metal chips.

[0331] Test results: Figure 9 As shown, there are no bubbles inside the glass layer and the density is excellent.

[0332] (2) Reverse leakage current detection of TVS devices prepared in Examples 5 to 8

[0333] Testing steps: Use the TK-188D instrument to test the leakage current (IR1 / 2). IR1 represents the leakage current of the chip when a specific reverse voltage is applied in the direction of the marking surface; IR2 represents the leakage current of the chip when the same reverse voltage is applied in the opposite direction.

[0334] Test results: Figure 10 As shown, the details are as follows:

[0335] Example 5: TVS P-type bidirectional 70mil size, 18V cut-off voltage, leakage current (IR1 / 2) can reach a level of <0.1uA.

[0336] Example 6: TVS N-type bidirectional 80mil size, 33V cut-off voltage, leakage current (IR1 / 2) can reach a level of <0.1uA.

[0337] Example 7: TVS P-type unidirectional 70mil size, 18V cut-off voltage, leakage current (IR1 / 2) can reach a level of <0.1uA.

[0338] Example 8: TVS N-type unidirectional 80mil size, 33V cut-off voltage, leakage current (IR1 / 2) can reach a level of <0.1uA.

[0339] (3) Reverse characteristic curves of TVS devices prepared in Examples 5 to 8

[0340] Testing steps: Use Taiwan TK-188D instrument to test the reverse characteristic distribution (breakdown voltage), where VBR1 represents the breakdown voltage when the specified test current passes through the chip in the direction of the marking surface; VBR2 represents the breakdown voltage when the specified test current passes through the chip in the opposite direction.

[0341] Test results: Figure 11 As shown, the details are as follows:

[0342] Example 5: TVS P-type bidirectional 70mil size, 18V cut-off voltage, measured breakdown voltage (VBR1 / 2) 20.67V-20.99V, in line with the breakdown voltage (VBR1 / 2) standard range of 20.07V-22.03V, with good uniformity.

[0343] Example 6: TVS N-type bidirectional 80mil size, 33V cut-off voltage, measured breakdown voltage (VBR1 / 2) 38.47V-38.97V, in line with the breakdown voltage (VBR1 / 2) range of 36.83V-40.47V, with good uniformity.

[0344] Example 7: TVS P-type unidirectional 70mil size, 18V cut-off voltage, measured breakdown voltage (VBR1 / 2) 20.79V-20.97V, in line with the breakdown voltage (VBR1 / 2) range of 20.07V-22.03V, with good uniformity.

[0345] Example 8: TVS N-type unidirectional 80mil size, 33V cut-off voltage, measured breakdown voltage (VBR1 / 2) 39.01V-39.27V, in line with the breakdown voltage (VBR1 / 2) range of 36.83V-40.47V, with good uniformity.

[0346] (4) Temperature shock test of TVS devices prepared in Examples 5 to 8

[0347] Test results: The prepared TVS device can withstand temperature shocks from -55°C to 150°C and can operate stably.

[0348] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various variations or modifications within the scope of the claims, which do not affect the essence of the present invention.

[0349] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various variations or modifications within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A TVS device with glass passivation protection, characterized in that: The method comprises a substrate layer, wherein the substrate layer is of a first conductive type, and further comprises: Two conductive layers located on the upper and lower sides of the substrate layer respectively form a sandwich structure, and at least one of the two conductive layers has a conductivity type opposite to that of the substrate layer; On the side of the opposite conductivity type, grooves are opened at the four edges of the device, the bottom of the grooves extends into the substrate layer, and the bottom of the grooves gradually deepens from the inside to the outside; the central area outside the conductive layer of the opposite conductivity type is covered with a nickel-gold layer, and the outer area adjacent to the central area is covered with an oxide layer; a continuous passivation layer is covered outside the oxide layer and the groove, the passivation layer located outside the oxide layer is planar, and the passivation layer located outside the groove is arc-shaped; the passivation layer is composed of a SIPOS layer located in the inner layer and an MTO layer located in the outer layer; an LTO layer and a glass layer are covered outside the passivation layer, the glass layer is covered at the corner position of the passivation layer, the LTO layer is covered at the planar area and the arc-shaped bottom area of ​​the passivation layer, the LTO layer and the glass layer are in contact with each other, and the outer side of the LTO layer covering the planar area ends before the corner position of the passivation layer.

2. The TVS device according to claim 1, wherein: When the conductivity type of one of the conductive layers is the same as that of the substrate layer, the outer side of the conductive layer with the same conductivity type is covered with a nickel-gold layer.

3. The TVS device according to claim 1, wherein: It also includes one or more of the following technical features: A1. When the substrate layer is a P-type substrate, the conductive layers on both sides are N-type doped regions; B1. When the substrate layer is a P-type substrate, the conductive layer on one side is an N-type doped region, and the conductive layer on the other side is a P-type main expansion region; C1. When the substrate layer is an N-type substrate, the conductive layers on both sides are P-type doped regions; D1. When the substrate layer is an N-type substrate, the conductive layer on one side is a P-type doped region, and the conductive layer on the other side is an N-type main expansion region.

4. The TVS device according to claim 1, wherein: It also includes one or more of the following technical features: A2. The TVS device size is 30mil to 600mil; B2, the substrate layer has a thickness of 240 to 320 μm and a resistivity of 0.0020 to 10 Ω·cm; C2, the thickness of the conductive layer is 0.3 μm to 1.2 μm; D2, the groove depth is 20μm to 150μm, and the width is 200μm to 500μm; E2, the oxide layer is in the shape of a rounded rectangular ring with a thickness of The ring edge width is 10μm to 100μm; F2, the thickness of the passivation layer is G2, the thickness of the table glass layer is 5μm to 25μm; H2, the height of the glass layer from the arc-shaped bottom of the passivation layer is 20 μm to 150 μm; I2. The width of the LTO layer is 10 μm to 100 μm; G2. In the nickel-gold layer, the thickness of the nickel layer is 0.3-0.8 μm, and the thickness of the gold layer is 0.3-0.5 μm.

5. The method for preparing a TVS device according to any one of claims 1 to 4, characterized in that: The following steps are involved: First, conductive layers are provided on both sides of the substrate layer to obtain a sandwich structure, wherein at least one side of the substrate layer is provided with a first conductive layer of a conductivity type opposite to that of the substrate layer, and at most one side of the substrate layer is provided with a second conductive layer of a conductivity type opposite to that of the substrate layer; second, performing oxidation treatment on the surface of the first conductive layer to obtain an oxide layer; Third, a groove is etched on the surface of the oxide layer; Fourth, a passivation layer is deposited on the surface of the oxide layer and the trench; Fifth, a glass layer is formed on the surface of the passivation layer at the corner position between the oxide layer and the groove, thereby obtaining a chip having the glass layer covering the corner position of the passivation layer surface; Sixth, the chip processed in the fifth step is subjected to a low temperature oxidation treatment to obtain a chip having an LTO layer covering the surface of the passivation layer except for the glass layer; Seventh, etching a lead hole in the middle of the LTO layer of the chip processed in step 6 to a depth where the first conductive layer is exposed; Eighth, plating a nickel-gold layer on the conductive layers provided on both sides of the chip processed in the seventh step; Ninth, inspect, cut and separate the chips to obtain the TVS devices.

6. The preparation method according to claim 5, characterized in that It also includes one or more of the following technical features: A3. In the first step, conductive layers are provided on both sides of the substrate layer, and first conductive layers are provided on both sides of the substrate layer; B3. In the first step, conductive layers are provided on both sides of the substrate layer, with the first conductive layer provided on one side of the substrate layer and the second conductive layer provided on the other side; C3. The sheet resistance of the sandwich structure is ≤2.5Ω / □, and the PN junction depth is 20-80μm.

7. The preparation method according to claim 5, characterized in that In the second step, the oxidation treatment is as follows: the sandwich structure is heated at 1000-1200°C and introduced with 2-3 L / min nitrogen and 1-5 L / min oxygen to generate a oxide layer.

8. The preparation method according to claim 5, characterized in that In the fourth step, the deposition parameters of the passivation layer are: depositing the oxygen-doped polysilicon passivation layer at 500-800°C, and the thickness of the passivation layer is controlled at 9. The preparation method according to claim 5, characterized in that In the fifth step, first, the dicing lines and the table glass edge area are formed through secondary photolithography, and then a uniform glass powder coating is formed on the table glass edge area by electrophoresis. Finally, the chip is placed at 570-830°C, nitrogen is introduced to burn off the photoresist on the chip surface, and then the glass is passivated with oxygen to form a uniform and dense glass layer.

10. The preparation method according to claim 5, characterized in that In the sixth step, the low temperature oxidation treatment is to perform oxidation treatment on the chip obtained in the fifth step at 360-500°C to form a thickness of LTO layer.

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