Semiconductor devices and methods for fabricating semiconductor devices

Abstract

This application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a drain structure, a substrate structure, an epitaxial layer, a gate structure, a dielectric layer, and a source structure arranged sequentially along a first direction. The epitaxial layer is located on one side of the substrate structure, and the doping type of the epitaxial layer is the same as that of the substrate structure. The epitaxial layer includes a JFET region, a first implantation region, and a second implantation region. The JFET region and the second implantation region are respectively located on the side of the first implantation region away from the substrate structure. The orthogonal projection of the JFET region onto the substrate structure at least partially overlaps with the orthogonal projection of the first implantation region onto the substrate structure. The second implantation regions are spaced apart along a second direction, and the JFET region is located between two adjacent second implantation regions. The surface of the JFET region away from the substrate structure is in contact with the gate structure. This solves the technical problem of low reliability of the gate structure in semiconductor devices.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a semiconductor device and a method for fabricating the semiconductor device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) have become an essential component of power electronics due to their excellent performance characteristics, such as low on-resistance, high operating frequency, and high breakdown voltage, playing an irreplaceable role, especially in industries such as electric vehicles, rail transportation, and smart grids. However, there is a trade-off between the JFET resistance and the reliability of the gate structure. While reducing the JFET resistance can lower the device's on-resistance and thus improve efficiency, it also means that the gate structure will be subjected to greater voltage stress, increasing the risk of device failure. Conversely, increasing the JFET resistance to protect the gate structure will lead to an increase in on-resistance, thereby increasing chip area and raising costs.

[0003] To address the aforementioned issues, this application provides a semiconductor device designed to overcome the limitations of existing technologies and improve the overall performance of the device.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main objective of this application is to provide a semiconductor device and a method for fabricating a semiconductor device, so as to solve the problem of low reliability of the gate structure of semiconductor devices in the prior art.

[0006] To achieve the above objectives, according to one aspect of this application, a semiconductor device is provided, comprising a drain structure, a substrate structure, an epitaxial layer, a gate structure, a dielectric layer, and a source structure arranged sequentially along a first direction. The epitaxial layer is located on one side of the substrate structure, and the doping type of the epitaxial layer is the same as that of the substrate structure. The epitaxial layer includes a JFET region, a first implantation region, and a second implantation region. The doping type of the first implantation region is different from that of the epitaxial layer. The JFET region and the second implantation region are respectively located on the side of the first implantation region away from the substrate structure. The orthographic projection of the JFET region onto the substrate structure at least partially overlaps with the orthographic projection of the first implantation region onto the substrate structure. The second implantation regions are spaced apart along a second direction, and the JFET region is located between two adjacent second implantation regions. The surface of the JFET region on the side away from the substrate structure contacts the gate structure. The first direction is the thickness direction of the device, and the second direction is perpendicular to the first direction.

[0007] Optionally, in the third direction, the first injection zone is spaced apart, and the third direction is perpendicular to the first direction and the second direction, respectively.

[0008] Optionally, the second implantation region includes a first sub-implantation region and a second sub-implantation region. In the first direction, the second sub-implantation region is at least partially located on the side of the first sub-implantation region close to the substrate structure. In the second direction, the second sub-implantation region is at least partially located on the side of the first sub-implantation region close to the JFET region. The doping type of the first sub-implantation region is the same as the doping type of the epitaxial layer, and the doping type of the first sub-implantation region is different from the doping type of the second sub-implantation region.

[0009] Optionally, the semiconductor device further includes: a third implantation region located within the epitaxial layer, wherein in the first direction, the third implantation region is in contact with the source structure, and in the second direction, the third implantation region is located on the side of the second implantation region away from the JFET region and is in contact with the second implantation region, wherein the doping type of the first implantation region and the doping type of the third implantation region are the same, and the doping concentration of the third implantation region is greater than the doping concentration of the first implantation region.

[0010] Optionally, in the second direction, the third injection region at least partially overlaps with the first injection region, and the third injection region is staggered on both sides of the JFET region.

[0011] Optionally, in the first direction, the depth of the third injection region is a first depth, the depth of the second injection region is a second depth, and the first depth is greater than or equal to the second depth.

[0012] Optionally, in the first direction, there is a gap between the first injection region and the second injection region.

[0013] Optionally, the width of the JFET region in the second direction is a first width, and the width of the first injection region in the second direction is a second width, wherein the second width is greater than or equal to the first width.

[0014] Optionally, the gate structure includes: a gate dielectric layer located on a portion of the surface of the epitaxial layer away from the substrate structure; and a gate located on the side of the gate dielectric layer away from the epitaxial layer.

[0015] According to another aspect of this application, a method for fabricating the aforementioned semiconductor device is provided, comprising: providing a substrate structure; forming a first pre-epitaxial layer on one side of the substrate structure; processing a portion of the first pre-epitaxial layer to form a first implantation region, thereby obtaining a pre-structure, wherein the doping type of the first implantation region is different from the doping type of the first pre-epitaxial layer, and one end of the first implantation region is in contact with the substrate structure; forming a second pre-epitaxial layer on the exposed surface of the pre-structure, and performing ion implantation on the second pre-epitaxial layer to obtain second implantation regions spaced apart in a second direction, wherein a JFET region is formed between two second implantation regions, and the orthographic projection of the JFET region on the substrate structure is at least equal to the orthographic projection of the first implantation region on the substrate structure. The doping types of the first implantation region and the JFET region are different. The first implantation region, the second implantation region, and the JFET region are located within the epitaxial layer. The doping type of the JFET region is the same as that of the epitaxial layer. The second direction is perpendicular to the thickness direction of the substrate structure. A gate structure is formed on a portion of the surface of the epitaxial layer away from the substrate structure. A dielectric layer is formed on the surface of the gate structure away from the epitaxial layer and on a portion of the surface of the epitaxial layer away from the substrate structure. A source structure is formed on the surface of the dielectric layer away from the gate structure and on a portion of the surface of the epitaxial layer away from the substrate structure. A drain structure is formed on the side of the substrate structure away from the epitaxial layer.

[0016] The present application provides a semiconductor device in which the orthographic projection of the JFET region on the substrate structure at least partially overlaps with the orthographic projection of the first injection region on the substrate structure. In other words, the first injection region is provided directly below the JFET region, so that the drain voltage of the drain structure does not directly pass through the JFET region to the gate structure, but passes through the first injection region to the JFET region and then to the gate structure. The first injection region can further reduce the drain voltage, thereby protecting the gate structure and improving the reliability of the gate structure. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown;

[0019] Figure 2 A schematic diagram of the structure of another semiconductor device provided according to an embodiment of this application is shown;

[0020] Figure 3 A schematic diagram of the structure of another semiconductor device provided according to an embodiment of this application is shown;

[0021] Figure 4 It shows Figure 3 Top view;

[0022] Figure 5 A schematic diagram of the structure of yet another semiconductor device provided according to an embodiment of this application is shown;

[0023] Figure 6 A schematic diagram of the structure of another semiconductor device provided according to an embodiment of this application is shown;

[0024] Figure 7 A schematic diagram of the structure of another semiconductor device provided according to an embodiment of this application is shown;

[0025] Figure 8 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0026] Figure 9 A schematic diagram of the fabrication process of a semiconductor device according to an embodiment of this application is shown.

[0027] The above figures include the following reference numerals:

[0028] 10. Substrate structure; 11. Epitaxial layer; 111. First pre-epitaxial layer; 112. Groove; 113. Second pre-epitaxial layer; 12. First implantation region; 13. JFET region; 14. Second implantation region; 141. First sub-implantation region; 142. Second sub-implantation region; 15. Gate structure; 151. Gate dielectric layer; 152. Gate; 16. Dielectric layer; 17. Source structure; 18. Drain structure; 19. Third implantation region. Detailed Implementation

[0029] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0030] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0033] As described in the background section, the reliability of the gate structure of semiconductor devices in the prior art is not high. In order to solve the above problems, the embodiments of this application provide a semiconductor device and a method for fabricating a semiconductor device.

[0034] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0035] Figures 1 to 7 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application. For example... Figures 1 to 7 As shown, the structure includes a drain structure 18, a substrate structure 10, an epitaxial layer 11, a gate structure 15, a dielectric layer 16, and a source structure 17 arranged sequentially along a first direction D1. The epitaxial layer 11 is located on one side of the substrate structure 10, and the doping type of the epitaxial layer 11 is the same as that of the substrate structure 10. The epitaxial layer 11 includes a JFET region 13, a first implantation region 12, and a second implantation region 14. The doping type of the first implantation region 12 is different from that of the epitaxial layer 11. The JFET region 13 and the second implantation region 14 are respectively located on the upper... The first injection region 12 is located on the side away from the substrate structure 10; the orthographic projection of the JFET region 13 on the substrate structure 10 at least partially overlaps with the orthographic projection of the first injection region 12 on the substrate structure 10; the second injection regions 14 are spaced apart along the second direction D2, the JFET region 13 is located between two adjacent second injection regions 14, and the surface of the JFET region 13 on the side away from the substrate structure 10 is in contact with the gate structure 15; the first direction D1 is the thickness direction of the device, and the second direction D2 is perpendicular to the first direction D1.

[0036] Specifically, the first injection region, the JFET region, and the second injection region are all located within the epitaxial layer. The doping concentration of the epitaxial layer is lower than that of the substrate structure. The JFET region is located between the source and drain structures. Due to the doping concentration gradient, a certain electric field is formed here, affecting the flow of charge carriers and controlling the drain current when the MOSFET is off. In the second direction mentioned above, the two second injection regions are located on both sides of the JFET region. The gate structure can be made of metal or conductive material and does not directly contact the source or drain. The key function of the gate is to control the conduction state of the channel. When an appropriate voltage (relative to the source) is applied to the gate structure, it generates an electric field in the channel region between the source and drain structures, thereby changing the conductivity of the channel region and controlling the MOSFET's conduction or cutoff. For NMOS, the MOSFET conducts when the gate voltage is higher than the threshold voltage; for PMOS, the MOSFET conducts when the gate voltage is lower than the threshold voltage. The dielectric layer can be made of insulating material to isolate the gate structure and the source structure. The source structure described above is where current begins to flow in a MOSFET. Its main function is to provide free electrons or holes (depending on the device type, i.e., NMOS or PMOS), which will flow through the channel. The material of the source structure can be at least one of Ti, Ni, Al, and Cu. The drain is where current ends to flow in a MOSFET, and it has the same doping type as the source structure. The main function of the drain is to receive and collect the carriers provided by the source from the channel. When the MOSFET is in the on state, a channel is formed between the source and drain, and current can flow in this channel. The level of the drain voltage also affects the operating mode of the MOSFET, such as operating in the saturation region, cutoff region, or linear region. The source structure, drain structure, and gate structure work together to enable the MOSFET to act as an effective current controller, realizing functions such as signal amplification, logic operation, and power control. The material of the drain structure described above can be at least one of Ni, Ti, Al, Cu, and Ag.

[0037] This embodiment provides a semiconductor device in which the orthographic projection of the JFET region on the substrate structure at least partially overlaps with the orthographic projection of the first injection region on the substrate structure. In other words, the first injection region is provided directly below the JFET region, so that the drain voltage of the drain structure does not directly pass through the JFET region to the gate structure, but instead passes through the first injection region to the JFET region and then to the gate structure. The first injection region can further reduce the drain voltage, thereby protecting the gate structure and improving the reliability of the gate structure.

[0038] In the specific implementation process, such as Figure 4As shown, the first injection regions 12 are spaced apart on the third direction D3, and the third direction D3 is perpendicular to both the first direction and the second direction D2. This arrangement can further reduce the on-resistance of the semiconductor device.

[0039] like Figure 4 As shown, the distance between two adjacent first implantation regions 12 is also related to the doping concentration of the epitaxial layer, decreasing as the doping concentration of the epitaxial layer increases. As the doping concentration of the epitaxial layer 11 increases, the JFET resistance decreases, and the influence of the drain voltage on the gate structure increases. By reducing the distance, the gate structure can be further better protected. Furthermore, the shape of the first implantation region 12 is not limited to... Figure 4 The bar shape can also be hexagonal, circular, or other shapes.

[0040] In the specific implementation process, such as Figure 2 As shown, the second implantation region 14 includes a first sub-implantation region 141 and a second sub-implantation region 142. In the first direction D1, the second sub-implantation region 142 is at least partially located on the side of the first sub-implantation region 141 closest to the substrate structure 10. In the second direction D2, the second sub-implantation region 142 is at least partially located on the side of the first sub-implantation region 141 closest to the JFET region 13. The doping type of the first sub-implantation region 141 is the same as that of the epitaxial layer 11, while the doping type of the first sub-implantation region 141 is different from that of the second sub-implantation region 142. The second sub-implantation region 142 can serve as a well region to control the channel turn-off, thereby further improving the reliability and stability of the semiconductor device.

[0041] Specifically, in the first direction, the second sub-implantation region is at least partially located on the side of the first sub-implantation region closest to the substrate structure. That is, the second sub-implantation region can be divided into two parts: one part is located between the first sub-implantation region and the epitaxial layer, and the other part is located between the first sub-implantation region and the JFET region.

[0042] In the above implementation process, such as Figure 3 and Figure 4As shown, the semiconductor device further includes a third implantation region 19 located within the epitaxial layer 11. In the first direction D1, the third implantation region 19 is in contact with the source structure 17. In the second direction D2, the third implantation region 19 is located on the side of the second implantation region 14 away from the JFET region 13, and is in contact with the second implantation region 14. The doping type of the first implantation region 12 is the same as that of the third implantation region 19, and the doping concentration of the third implantation region 19 is greater than that of the first implantation region 12. The provision of the third implantation region 19 can further reduce the on-resistance of the semiconductor device.

[0043] Specifically, the depth of the third injection region can be the same as or different from the depth of the second injection region and the JFET region. Figure 4 yes Figure 3 Top view, Figure 3 It is along Figure 4 The cross-sectional view obtained along the AA' direction, as shown below. Figure 4 As shown, in the second direction D2, the aforementioned third injection regions 19 are arranged alternately.

[0044] like Figure 4 As shown, in the second direction D2, the third injection region 19 at least partially overlaps with the first injection region 12, and the third injection region 19 is staggered on both sides of the JFET region. The more uniform distribution of the first injection region 12 and the third injection region 19 improves the uniformity of charge distribution and further enhances the stability of the power semiconductor device.

[0045] In order to further reduce the on-resistance of semiconductor devices, in the first direction, the depth of the third injection region is the first depth, the depth of the second injection region is the second depth, and the first depth is greater than or equal to the second depth.

[0046] Specifically, the first depth is the distance between the surface of the third injection region closest to the substrate structure and the surface furthest from the substrate structure; the second depth is the distance between the surface of the second injection region closest to the substrate structure and the surface furthest from the substrate structure. The second depths of the second injection regions on both sides of the JFET region may be the same or different. In the first direction, the depth of the JFET region is the third depth, the first depth is greater than or equal to the third depth, and the second and third depths may be equal or unequal.

[0047] like Figure 3As shown, the second injection region 14 and the third injection region 19 are in contact along the second direction D2. This arrangement increases the contact area between the second injection region 14 and the third injection region 19, thereby further reducing the on-resistance of the semiconductor device.

[0048] In another embodiment, such as Figure 5 As shown, in the first direction D1, the first injection region 12 is in contact with the JFET region 13; in the second direction D2, the width of the first injection region 12 can be greater than or equal to the width of the JFET region 13, or it can be less than the width of the JFET region 13. When the width of the first injection region 12 is greater than or equal to the width of the JFET region 13, the first injection region 12 is in contact with both the JFET region 13 and the second injection region 14. When the width of the first injection region 12 is less than the width of the JFET region 13, the first injection region 12 is in contact with only the JFET region 13.

[0049] In some embodiments, such as Figure 3 As shown, in the second direction D2, there is a gap between the first injection region 12 and the third injection region 19. This arrangement can further reduce the on-resistance of the semiconductor device.

[0050] In other words, in the second direction, there is a gap between the first implantation region and the JFET region, and the epitaxial layers on both sides of the first implantation region are interconnected. Those skilled in the art can set the size of the above gap according to the actual situation.

[0051] In other embodiments, the size of the predetermined interval decreases as the doping concentration of the epitaxial layer increases. As the doping concentration of the epitaxial layer increases, the JFET resistance decreases, and the influence of the drain voltage on the gate structure increases. By reducing the size of the predetermined interval, the gate structure can be further better protected.

[0052] like Figure 6 As shown, the width of the JFET region 13 in the second direction D2 is a first width W1, and the width of the first injection region 12 in the second direction D2 is a second width W2, wherein the second width W2 is greater than or equal to the first width W1. This configuration increases the size of the first injection region, thereby improving its blocking capability, further reducing the drain voltage, and further enhancing the protection effect of the gate structure.

[0053] like Figure 7As shown, the gate structure 15 includes: a gate dielectric layer 151 located on a portion of the surface of the epitaxial layer 11 away from the substrate structure 10; and a gate 152 located on the side of the gate dielectric layer 151 away from the epitaxial layer 11. The gate structure 15, including the gate dielectric layer 151 and the gate 152, can improve the stability of the gate structure 15, thereby further improving the switching speed and reliability of the semiconductor device.

[0054] Specifically, the gate can be made of polycrystalline silicon or a metal material, such as intrinsic polycrystalline silicon or doped polycrystalline silicon. The gate dielectric layer can be made of silicon oxide, silicon nitride, or a high-k dielectric material.

[0055] This application also provides a method for fabricating a semiconductor device. Figure 8 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 8 As shown, the method includes:

[0056] Step S201, provide the substrate structure 10, to obtain as follows Figure 9 The structure shown in (a);

[0057] Specifically, the material of the aforementioned substrate structure can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, and sapphire, etc.

[0058] Step S202: A first pre-epipolar layer 111 is formed on one side of the substrate structure 10, resulting in... Figure 9 The structure shown in (b);

[0059] Specifically, the doping type of the first pre-epitaxial layer is the same as that of the substrate structure, and the doping concentration of the first pre-epitaxial layer is less than that of the substrate structure. The first pre-epitaxial layer can be formed on one side of the substrate structure by epitaxial growth.

[0060] Step S203: A portion of the first pre-epilithographic layer 111 is processed to form a first implantation region 12, resulting in a pre-structure. The doping type of the first implantation region 12 differs from that of the first pre-epilithographic layer 111. One end of the first implantation region 12 contacts the substrate structure 10, resulting in... Figure 9 The structure shown in (d);

[0061] Specifically, the first implantation region can be formed either by ion implantation or by trench etching followed by backfilling. The specific steps for trench etching followed by backfilling are as follows: Part of the first preparatory epitaxial layer 111 is removed to form a groove 112, resulting in... Figure 9The structure shown in (c) is obtained by forming a first injection region 12 in the groove 112, resulting in a preparatory structure, as shown in the figure. Figure 9 The structure shown in (d);

[0062] Step S204: A second pre-epipolar layer 113 is formed on the exposed surface of the pre-structure, resulting in the following... Figure 9 The structure shown in (e) is used, and ion implantation is performed on the second pre-epitaxial layer 113 to obtain second implantation regions 14 spaced apart in the second direction D2. A JFET region 13 is formed between the two second implantation regions 14. The orthogonal projection of the JFET region 13 on the substrate structure 10 at least partially overlaps with the orthogonal projection of the first implantation region 12 on the substrate structure 10. The doping type of the first implantation region 12 is different from that of the JFET region 13. The first implantation region 12, the second implantation region 14, and the JFET region 13 are located within the epitaxial layer 11. The doping type of the JFET region 13 is the same as that of the epitaxial layer 11. The second direction D2 is perpendicular to the thickness direction of the substrate structure 10, resulting in the structure shown in (e). Figure 9 The structure shown in (f);

[0063] Specifically, a first pre-epitaxial layer can be formed on the exposed surface of the pre-structure by epitaxial growth.

[0064] Step S205: A gate structure 15 is formed on a portion of the surface of the epitaxial layer 11 away from the substrate structure 10, resulting in... Figure 9 The structure shown in (g);

[0065] The gate structure described above can be made of metal or conductive material and does not directly contact the source or drain. The key function of the gate is to control the conduction state of the channel. When an appropriate voltage (relative to the source) is applied to the gate structure, it generates an electric field in the channel region between the source and drain structures, thereby changing the conductivity of the channel region and thus controlling the MOSFET's on or off state. For NMOS, the MOSFET conducts when the gate voltage is higher than the threshold voltage; for PMOS, the MOSFET conducts when the gate voltage is lower than the threshold voltage.

[0066] Step S206: A dielectric layer 16 is formed on the surface of the gate structure 15 away from the epitaxial layer 11 and on a portion of the surface of the epitaxial layer 11 away from the substrate structure 10, to obtain... Figure 9 The structure shown in (h);

[0067] Specifically, the material of the aforementioned dielectric layer can be an insulating material, used to isolate the aforementioned gate structure and source structure.

[0068] Step S207: A source structure 17 is formed on the surface of the dielectric layer 16 away from the gate structure 15 and on a portion of the surface of the epitaxial layer 11 away from the substrate structure 10, resulting in... Figure 9 The structure shown in (i);

[0069] Specifically, the aforementioned source structure is the location where current begins to flow in a MOSFET. Its main function is to provide free electrons or holes (depending on the device type, i.e., NMOS or PMOS), which will flow through the channel. The material of the aforementioned source structure can be at least one of Ti, Ni, Al, and Cu.

[0070] In step S208, a drain structure 18 is formed on the side of the substrate structure 10 away from the epitaxial layer 11, resulting in the following: Figure 1 The structure shown.

[0071] Specifically, the drain is the point where current flow ends in a MOSFET, and it has the same doping type as the source structure. The main function of the drain is to receive and collect charge carriers provided by the source from the channel. When the MOSFET is in the on state, a channel is formed between the source and drain, and current can flow in this channel. The level of the drain voltage also affects the operating mode of the MOSFET, such as operating in the saturation region, cutoff region, or linear region. The source structure, drain structure, and gate structure work together to enable the MOSFET to act as an effective current controller, realizing functions such as signal amplification, logic operation, and power control. The material of the drain structure can be at least one of Ni, Ti, Al, Cu, and Ag.

[0072] This embodiment provides a method for fabricating a semiconductor device in which the orthogonal projection of the JFET region on the substrate structure at least partially overlaps with the orthogonal projection of the first injection region on the substrate structure. In other words, the first injection region is provided directly below the JFET region, so that the drain voltage of the drain structure does not directly pass through the JFET region to the gate structure, but instead passes through the first injection region, reaches the JFET region, and then reaches the gate structure. The first injection region can further reduce the drain voltage, thereby protecting the gate structure and improving the reliability of the gate structure.

[0073] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0074] 1) In the semiconductor device of this application, the orthogonal projection of the JFET region on the substrate structure and the orthogonal projection of the first injection region on the substrate structure at least partially overlap. That is, the first injection region is provided directly below the JFET region, so that the drain voltage of the drain structure does not directly pass through the JFET region to the gate structure, but passes through the first injection region, reaches the JFET region and then reaches the gate structure. The first injection region can further reduce the drain voltage, achieve the effect of protecting the gate structure, and thus improve the reliability of the gate structure.

[0075] 2) In the semiconductor device fabrication method of this application, the orthogonal projection of the JFET region on the substrate structure and the orthogonal projection of the first injection region on the substrate structure at least partially overlap. That is, the first injection region is provided directly below the JFET region, so that the drain voltage of the drain structure does not directly pass through the JFET region to the gate structure, but passes through the first injection region, reaches the JFET region and then reaches the gate structure. The first injection region can further reduce the drain voltage, achieve the effect of protecting the gate structure, and thus improve the reliability of the gate structure.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises a drain structure, a substrate structure, an epitaxial layer, a gate structure, a dielectric layer and a source structure arranged in sequence along a first direction, The epitaxial layer is located on one side of the substrate structure, the doping type of the epitaxial layer is the same as the doping type of the substrate structure, the epitaxial layer comprises a JFET region, a first implanted region and a second implanted region, the doping type of the first implanted region is different from the doping type of the epitaxial layer, the JFET region and the second implanted region are respectively located on the side of the first implanted region away from the substrate structure, one end of the first implanted region is in contact with the substrate structure, and the other end of the first implanted region is not in contact with the second implanted region. The orthographic projection of the JFET region on the substrate structure at least partially overlaps the orthographic projection of the first implanted region on the substrate structure. The second implanted region is spaced apart along a second direction, the JFET region is located between two adjacent second implanted regions, and the surface of the JFET region away from the substrate structure is in contact with the gate structure. The first direction is the thickness direction of the device, and the second direction is perpendicular to the first direction, The semiconductor device further comprises: A third implanted region located in the epitaxial layer, in the first direction, the third implanted region is in contact with the source structure, in the second direction, the third implanted region is located on the side of the second implanted region away from the JFET region, and the third implanted region is in contact with the second implanted region, the doping type of the first implanted region is the same as the doping type of the third implanted region, the doping concentration of the third implanted region is greater than the doping concentration of the first implanted region, in the first direction, the depth of the third implanted region is a first depth, the depth of the second implanted region is a second depth, the first depth is equal to the second depth, In the first direction, there is a spacing between the first implanted region and the second implanted region.

2. The semiconductor device according to claim 1, wherein In a third direction, the first implanted regions are spaced apart, and the third direction is perpendicular to the first direction and the second direction.

3. The semiconductor device of claim 1, wherein The second implanted region comprises a first sub-implanted region and a second sub-implanted region, in the first direction, the second sub-implanted region is at least partially located on the side of the first sub-implanted region close to the substrate structure, in the second direction, the second sub-implanted region is at least partially located on the side of the first sub-implanted region close to the JFET region, the doping type of the first sub-implanted region is the same as the doping type of the epitaxial layer, and the doping type of the first sub-implanted region is different from the doping type of the second sub-implanted region.

4. The semiconductor device of claim 1, wherein In the second direction, the third implanted region at least partially overlaps the first implanted region, and the third implanted region is arranged on both sides of the JFET region.

5. The semiconductor device of claim 1, wherein The width of the JFET region in the second direction is a first width, and the width of the first implanted region in the second direction is a second width, and the second width is greater than or equal to the first width.

6. The semiconductor device of claim 1, wherein The gate structure comprises: A gate dielectric layer located on part of the surface of the epitaxial layer away from the substrate structure. a gate electrode formed on a portion of the surface of the epitaxial layer away from the substrate structure.

7. A method of manufacturing a semiconductor device, characterized by A semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is prepared by a method comprising: providing a substrate structure; forming a first preliminary epitaxial layer on one side of the substrate structure; treating a portion of the first preliminary epitaxial layer to form a first implanted region, thereby obtaining a preliminary structure, wherein the first implanted region has a different doping type from the first preliminary epitaxial layer, and one end of the first implanted region is in contact with the substrate structure; forming a second preliminary epitaxial layer on the exposed surface of the preliminary structure, and performing ion implantation on the second preliminary epitaxial layer to form second implanted regions spaced apart in a second direction, wherein a JFET region is formed between two of the second implanted regions, the orthographic projection of the JFET region on the substrate structure at least partially overlaps the orthographic projection of the first implanted region on the substrate structure, the doping type of the first implanted region is different from the doping type of the JFET region, the first implanted region, the second implanted regions, and the JFET region are located in the epitaxial layer, the doping type of the JFET region is the same as the doping type of the epitaxial layer, and the second direction is perpendicular to the thickness direction of the substrate structure; forming a gate electrode structure on a portion of the surface of the epitaxial layer away from the substrate structure; forming a dielectric layer on the surface of the gate electrode structure away from the epitaxial layer, and on a portion of the surface of the epitaxial layer away from the substrate structure; forming a source electrode structure on the surface of the dielectric layer away from the gate electrode structure, and on a portion of the surface of the epitaxial layer away from the substrate structure; forming a drain electrode structure on the side of the substrate structure away from the epitaxial layer.

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