Electrode structure, semiconductor device and semiconductor device manufacturing method
By adopting a three-layer electrode structure in semiconductor light-emitting devices, using high temperature to attract H atoms of Mg-H complex and combining it with high work function metals, the problem of ohmic contact between p-GaN and p-type electrode interface is solved, achieving a balance between conductivity and current uniformity, and improving the performance of the device.
Patent Information
- Application Number
- CN202510847895.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-23
- Publication Date
- 2025-09-26
AI Technical Summary
It is difficult to form an effective ohmic contact between p-GaN and p-type electrode interfaces in semiconductor light-emitting devices with existing technologies, and traditional electrodes cannot achieve both conductivity and current uniformity.
A three-layer electrode structure is employed, with the first electrode layer positioned within a recess in the semiconductor material, contacting the semiconductor material; the second electrode layer positioned above the semiconductor material, contacting the first electrode layer; and the third electrode layer covering the side of the second electrode layer facing away from the semiconductor material. The first electrode layer is made of Ti, Ni, Pd, or a TiW alloy; the second electrode layer is made of Pt, W, Ta, or a NiCr alloy; and the third electrode layer is made of ITO, AZO, GZO, or a metal mesh. High temperatures attract hydrogen atoms from Mg-H complexes, increasing the hole concentration in p-GaN. High-work-function metals are also used to reduce the interfacial barrier difference.
It achieves good ohmic contact and current uniformity in semiconductor light-emitting devices, improves device efficiency, increases the hole concentration of p-GaN and reduces the interface barrier difference.
Smart Images
Figure CN120711902A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electrodes, and in particular to an electrode structure, a semiconductor device, and a method for manufacturing a semiconductor device. Background Art
[0002] Conventional semiconductor light-emitting devices mainly include electrodes (top layer), upper ITO (Indium Tin Oxide) layer, N-GaN (Gallium Nitride) layer, MQW (Multiple Quantum Wells) multiple quantum wells, P-GaN layer, P+-GaN layer, lower ITO layer, bonding metal and substrate, and are formed by stacking the above components.
[0003] In the above structure, achieving good ohmic contact between the p-GaN and p-type electrode interface is one of the key objectives for optimizing the electrical performance of semiconductor light-emitting devices. The difficulty in creating a low-contact-resistance p-type electrode lies in the following: p-GaN material uses Mg as the p-type dopant, but Mg easily forms a Mg-H complex with hydrogen in the metal organic chemical vapor deposition (MOCVD) reaction source, making it difficult to form effective p-type doping. Furthermore, the work function of p-GaN is 7.5 eV, while metals or metal systems with work functions higher than 7.5 eV are extremely limited, making it difficult to form an interface with a low barrier height.
[0004] Currently, industry researchers have proposed a variety of ohmic contact electrode systems commonly used for p-GaN materials, such as ITO, Ni / Au, Ti / Au, Pt / Au, Pd / Au, Pt / Ni / Au, and Pd / Ni / Au. However, traditional p-type electrodes such as ITO and Ni / Au cannot address issues such as conductivity, ohmic contact, and current uniformity. Summary of the Invention
[0005] The purpose of this application is to provide an electrode structure, a semiconductor device and a method for manufacturing a semiconductor device.
[0006] According to a first aspect of an embodiment of the present application, an electrode structure is provided for connecting to a semiconductor material, the electrode structure comprising:
[0007] a first electrode layer, the first electrode layer being arranged in the groove on the semiconductor material and being in contact with the semiconductor material;
[0008] a second electrode layer, wherein the second electrode layer is disposed on the semiconductor material and is in contact with the first electrode layer;
[0009] A third electrode layer covers a side of the second electrode layer facing away from the semiconductor material.
[0010] It should be noted that the semiconductor material is the above-mentioned P + -GaN layer, using a high-doping concentration P-type GaN layer. The first electrode layer can be Ti (titanium), Ni (nickel), Pd (palladium) or TiW (titanium-tungsten) alloy. As long as it can combine with H and has a lower formation enthalpy than Mg-H, it can attract p at high temperatures. + The H atoms of the Mg-H complex in p-GaN cause Mg to form an effective P-type doping in GaN, thereby increasing the hole concentration of p-GaN. The second electrode layer can be Pt (platinum), W (tungsten), Ta (tantalum) and NiCr alloy. The third electrode layer can be ITO, AZO (aluminum-doped zinc oxide), GZO (gallium-doped zinc oxide), or a metal grid (such as Ag nanowires). In addition, the electrode structure proposed in this application can be used in the above-mentioned semiconductor light-emitting devices, and can also be used in other semiconductor devices.
[0011] In the three-layer electrode structure of the first electrode layer, the second electrode layer and the third electrode layer, the first electrode layer has a lower formation enthalpy with H than Mg-H, and can attract p at high temperature. + The H atoms of the Mg-H complex in the p-GaN form effective p-type doping of Mg in the GaN, thereby increasing the hole concentration in the p-GaN and improving the efficiency of the semiconductor light-emitting device. The second electrode layer, as a high-work function metal, can reduce the potential barrier difference between the p-GaN and electrode interfaces, and the third electrode layer acts as a current spreading layer to evenly distribute the current at the interface.
[0012] In summary, the three-layer electrode structure of the first electrode layer, the second electrode layer and the third electrode layer can form a good ohmic contact with P-GaN while taking into account current uniformity.
[0013] In one embodiment, the first electrode layer includes a plurality of electrode layer units, a plurality of grooves corresponding to the first electrode layer units are provided on the semiconductor material, and the plurality of electrode layer units are spaced apart and arranged in the plurality of grooves.
[0014] Based on the above configuration, the multiple grooves arranged at intervals can increase the contact area between the first electrode layer and the semiconductor material on the one hand, and can also make the distribution of the first electrode layer and the semiconductor material more uniform on the other hand.
[0015] In one embodiment, the height of the electrode layer unit is set to be the same as the depth of the groove.
[0016] Based on the above arrangement, the electrode layer unit and the semiconductor material form a smooth outward contact surface, ie, without protrusions or depressions, which facilitates contact between the second electrode layer and the electrode layer unit and also makes the second electrode layer smoother.
[0017] In one embodiment, the electrode layer unit is arranged in a trapezoidal shape, and the trapezoid includes a first bottom surface and a second bottom surface, the first bottom surface is larger than the second bottom surface, and the second bottom surface is arranged in contact with the second electrode layer.
[0018] Because the trapezoidal structure has a larger base and a smaller top, the contact surface between the electrode layer unit and the semiconductor material is larger, thereby generating more holes. Furthermore, the contact surface between the electrode layer unit and the second electrode layer is smaller, while conversely, the contact surface between the second electrode layer and the semiconductor material is larger. This results in a higher hole concentration in the semiconductor material and a greater reduction in the barrier difference between the P-GaN and electrode interfaces.
[0019] In one embodiment, the electrode layer unit is spherical, and one end of the sphere facing away from the bottom of the groove is in contact with the second electrode layer.
[0020] Based on the above configuration, under the same volume, the spherical shape can increase the contact surface between the electrode layer unit and the semiconductor material. At the same time, the exposed surface of the electrode layer unit is a spherical contact point, which makes the contact surface between the electrode layer unit and the second electrode layer smaller. Conversely, the contact surface between the second electrode layer and the semiconductor material is larger. This in turn increases the hole concentration in the semiconductor material and greatly reduces the barrier difference between the P-GaN and electrode interfaces.
[0021] In one embodiment, the electrode layer unit further includes a first substructure and a second substructure connected to each other, the cross section of the first substructure is larger than the cross section of the second substructure, and the end of the second substructure facing away from the first substructure is arranged in contact with the second electrode layer.
[0022] Based on this configuration, the first substructure can be made larger and the second substructure smaller, achieving a larger contact surface with the semiconductor material and a smaller contact surface with the second electrode layer. Furthermore, the depth, length, and volume of the first and second substructures can be designed based on practical needs to achieve a balance between performance and functionality.
[0023] According to a second aspect of the embodiments of the present application, a semiconductor device is provided, comprising the electrode structure as described in any one of the above embodiments.
[0024] According to a third aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising:
[0025] providing a substrate;
[0026] forming a semiconductor material and a first electrode layer that cooperate with each other on a substrate;
[0027] forming a second electrode layer on a side of the first electrode layer facing away from the substrate;
[0028] Disposing a third electrode layer on a side of the second electrode layer facing away from the first electrode layer;
[0029] The first electrode layer is embedded in the semiconductor material, and one end of the first electrode layer facing away from the substrate is in contact with the second electrode layer.
[0030] It should be noted that the above semiconductor device manufacturing method also includes manufacturing electrodes, upper ITO layer, N-GaN layer and MQW multiple quantum well, etc. The above manufacturing processes are all existing technologies and will not be described in detail in this application.
[0031] Through the above arrangement, a three-layer electrode structure of a first electrode layer, a second electrode layer, and a third electrode layer can be formed on the semiconductor material. The first electrode layer has a lower formation enthalpy with H than Mg-H, and can attract p at high temperature. + The H atoms of the Mg-H complex in p-GaN enable Mg to form effective P-type doping in GaN, thereby increasing the hole concentration of p-GaN. The second electrode layer, as a high work function metal, can reduce the barrier difference between the P-GaN and electrode interface. The third electrode layer acts as a current spreading layer to evenly distribute the current at the interface.
[0032] In addition, the three-layer electrode structure of the first electrode layer, the second electrode layer and the third electrode layer can form a good ohmic contact with P-GaN and take into account the current uniformity. + -GaN grooves can increase the contact area between the first electrode layer and the P-GaN, further increasing the hole concentration of the p-GaN.
[0033] In one embodiment, forming a semiconductor material and a first electrode layer that cooperate with each other on a substrate includes:
[0034] forming a semiconductor material on the substrate;
[0035] Etching a plurality of grooves in the semiconductor material;
[0036] A first electrode layer is formed in the groove, wherein the first electrode layer includes a plurality of electrode layer units, and shapes of the plurality of electrode layer units match the plurality of grooves.
[0037] In the above-mentioned manufacturing method, a plurality of grooves can be first etched into the semiconductor material, and then the first electrode layer can be formed within the grooves. This method is suitable for grooves with uniform cross-sections and can be directly produced using a conventional mask. This process is mature, efficient, and low-cost.
[0038] In one embodiment, forming a semiconductor material and a first electrode layer that cooperate with each other on a substrate includes:
[0039] forming a first semiconductor unit on the substrate;
[0040] forming a first electrode layer on the first semiconductor unit;
[0041] Etching on the first electrode layer to form a plurality of electrode layer units;
[0042] A second semiconductor unit is formed on the first semiconductor unit, wherein the second semiconductor unit wraps around the sides of the plurality of electrode layer units, and the second semiconductor unit is combined with the first semiconductor unit to form a semiconductor material.
[0043] In the above manufacturing method, a portion of semiconductor material, namely a first semiconductor unit, can be first made, then a desired electrode layer unit pattern can be formed on the first semiconductor unit, and finally the side of the electrode layer unit can be wrapped with another portion of semiconductor material.
[0044] This manufacturing method not only allows for the production of grooves with uniform cross-sections, but also allows for the production of electrode layer units with varying cross-sections. For example, this can increase the area at the bottom of the groove and reduce the contact surface with the second electrode layer. This method can cover a wider range of applications and can accommodate the trapezoidal and spherical electrode layer units described in the above embodiments.
[0045] In one embodiment, the groove is in a trapezoidal shape, and the trapezoid includes a first bottom surface and a second bottom surface, the first bottom surface is larger than the second bottom surface, and the second bottom surface is arranged away from the substrate; and / or
[0046] The groove is spherical, and one end of the sphere facing away from the substrate is in contact with the second electrode layer.
[0047] Because the trapezoidal structure has a larger base and a smaller top, the contact surface between the electrode layer unit and the semiconductor material is larger, thereby generating more holes. In addition, the contact surface between the electrode layer unit and the second electrode layer is smaller, while the contact surface between the second electrode layer and the semiconductor material is larger.
[0048] Under the same volume, the spherical shape can make the contact area between the electrode layer unit and the semiconductor material larger. At the same time, the surface of the electrode layer unit exposed to the outside is a point of the sphere, so that the contact area between the electrode layer unit and the second electrode layer will be smaller. Conversely, the contact area between the second electrode layer and the semiconductor material will be larger.
[0049] The beneficial technical effects brought about by the technical solutions provided by the embodiments of the present application are:
[0050] By providing a first electrode layer, a second electrode layer, and a third electrode layer, wherein the first electrode layer is arranged in a groove on the semiconductor material and is in contact with the semiconductor material, the second electrode layer is arranged on the semiconductor material and is in contact with the first electrode layer, and the third electrode layer covers the side of the second electrode layer facing away from the semiconductor material.
[0051] In the three-layer electrode structure of the first electrode layer, the second electrode layer and the third electrode layer, the first electrode layer has a lower formation enthalpy with H than Mg-H, and can attract p at high temperature. + The H atoms of the Mg-H complex in the p-GaN form effective p-type doping of Mg in the GaN, thereby increasing the hole concentration in the p-GaN and improving the efficiency of the semiconductor light-emitting device. The second electrode layer, as a high-work function metal, can reduce the potential barrier difference between the p-GaN and electrode interfaces, and the third electrode layer acts as a current spreading layer to evenly distribute the current at the interface. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0053] Figure 1 Schematic diagram of the structure of a semiconductor device according to an embodiment of the present application.
[0054] Figure 2 Schematic diagram of the structure of another semiconductor device according to an embodiment of the present application.
[0055] Figure 3 1 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application.
[0056] Figure 4 Schematic diagram of the structure of another semiconductor device according to an embodiment of the present application.
[0057] Figure 5 Schematic diagram of the structure of another semiconductor device according to an embodiment of the present application.
[0058] Figure 6 FIG. 1 is a flowchart of a semiconductor device fabrication process according to an embodiment of the present application.
[0059] Description of Reference Numerals
[0060] Electrode structure 10
[0061] Semiconductor Materials 100
[0062] Groove 110
[0063] First semiconductor material 100A
[0064] The second semiconductor material 100B
[0065] The third semiconductor material 100C
[0066] First semiconductor unit 120
[0067] The second semiconductor unit 130
[0068] First electrode layer 200
[0069] Electrode layer unit 210
[0070] First bottom surface 211
[0071] Second bottom surface 212
[0072] First substructure 210A
[0073] Second substructure 210B
[0074] Second electrode layer 300
[0075] The third electrode layer 400
[0076] Light-emitting layer 500
[0077] Bonding Metal 600
[0078] Substrate 700
[0079] Semiconductor device 20 DETAILED DESCRIPTION
[0080] Here, the technical solutions in the embodiments (or "implementations") of the present application will be clearly and completely described in conjunction with the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0081] If there are terms related to directional indications or positional relationships in the embodiments of this application (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationship, movement, etc. between the components in a specific posture (as shown in the accompanying drawings); if the specific posture changes, the directional indication or positional relationship will also change accordingly. In addition, the terms "first" and "second" in the embodiments of this application are only used for the purpose of convenience of description and should not be understood as indicating or implying relative importance.
[0082] Conventional semiconductor light emitting devices mainly include an electrode (top layer), an upper ITO (Indium Tin Oxide) layer 400, an N-GaN (Gallium Nitride) layer 100A, an MQW (Multiple Quantum Wells) layer 500, a P-GaN layer 100B, and a P + -GaN layer 100C, lower ITO layer, bonding metal 600 and substrate 700 and other components, and is formed by stacking the above components.
[0083] The electrode (top layer) is one of the main entrances for current into the device, usually in contact with the N-GaN layer, for injecting electrons. In some designs, two different electrodes may be included, corresponding to the anode and cathode, respectively, to facilitate the efficient input and output of current.
[0084] The upper ITO layer 400 acts as a transparent conductive layer, primarily distributing current evenly. In the top structure, it ensures that current is evenly distributed across the N-GaN layer 100A, improving light extraction efficiency and reducing efficiency drops caused by current concentration.
[0085] The N-GaN layer 100A is a layer of GaN material doped with donor impurities, which provides free electrons. When a forward voltage is applied to the device, these electrons flow to the MQW multi-quantum well 500 region, where they recombine with holes to emit light.
[0086] The MQW multi-quantum well 500 is composed of alternating thin layers of semiconductor materials (such as InGaN / GaN). The quantum well structure confines electrons and holes in a very small space, increasing the probability of their recombination, thereby efficiently generating photons. This area is where the actual light emission occurs.
[0087] The P-GaN layer 100B is a P-type doped GaN layer that provides holes. Under forward bias, these holes move to the MQW region and recombine with electrons from the N-GaN layer to emit light.
[0088] P + The -GaN layer 100C is a highly doped P-type GaN layer, typically located above the P-GaN layer and close to the underlying ITO layer. Its purpose is to enhance hole injection efficiency and reduce contact resistance, thereby improving overall device performance.
[0089] The lower ITO layer is similar to the upper ITO layer, but is usually located at the bottom of the device and serves as a transparent electrode on the other side, helping to evenly distribute the current across the P + -GaN layer and helps in light extraction.
[0090] The bonding metal 600 is used to achieve electrical connections. Especially in flip chip technology, the bonding metal also plays a role in heat conduction and helps dissipate heat, which is crucial for maintaining the long-term stability and efficiency of the LED.
[0091] In GaN-based LEDs, substrate 700 is commonly made of sapphire (Al2O3), SiC, or silicon (Si). It provides a physical foundation for epitaxial growth. The choice of substrate 700 affects crystal quality, cost, and compatibility with subsequent processing techniques.
[0092] These components are stacked together through semiconductor manufacturing processes such as epitaxial growth and deposition to form a complete functional unit. In this structure, current enters from one electrode, passes through the ITO layer, N-GaN layer, MQW layer, P-GaN layer, and finally reaches the other electrode. During this process, electrons and holes recombine within the MQW region, releasing energy that is emitted as light. This sophisticated design maximizes luminous efficiency, optimizes current distribution, and improves thermal management.
[0093] In the above structure, achieving good ohmic contact between the p-GaN and p-type electrode interface is one of the key objectives for optimizing the electrical performance of semiconductor light-emitting devices. The difficulty in creating a low-contact-resistance p-type electrode lies in the following: p-GaN material uses Mg as the p-type dopant, but Mg easily forms a Mg-H complex with hydrogen in the metal organic chemical vapor deposition (MOCVD) reaction source, making it difficult to form effective p-type doping. Furthermore, the work function of p-GaN is 7.5 eV, while metals or metal systems with work functions higher than 7.5 eV are extremely limited, making it difficult to form an interface with a low barrier height.
[0094] Currently, industry researchers have proposed a variety of ohmic contact electrode systems commonly used for p-GaN materials, such as ITO, Ni / Au, Ti / Au, Pt / Au, Pd / Au, Pt / Ni / Au, and Pd / Ni / Au. However, traditional p-type electrodes such as ITO and Ni / Au cannot address issues such as conductivity, ohmic contact, and current uniformity.
[0095] This application proposes an electrode structure 10, referring to Figure 1-Figure 5 As shown, the electrode structure 10 is used to connect to the semiconductor material 100 , and includes a first electrode layer 200 , a second electrode layer 300 and a third electrode layer 400 .
[0096] Among them, the first electrode layer 200 is arranged in the groove 110 on the semiconductor material 100 and is arranged in contact with the semiconductor material 100, the second electrode layer 300 is arranged on the semiconductor material 100, and the second electrode layer 300 is arranged in contact with the first electrode layer 200, and the third electrode layer 400 covers the side of the second electrode layer 300 facing away from the semiconductor material 100.
[0097] It should be noted that the semiconductor material 100 is the above-mentioned P + -GaN layer, using a high-doping concentration P-type GaN layer. The first electrode layer 200 can be Ti (titanium), Ni (nickel), Pd (palladium) or TiW (titanium-tungsten) alloy. As long as it can combine with H and has a lower formation enthalpy than Mg-H, it can attract p-type GaN at high temperatures. + -The H atoms of the Mg-H complex in GaN cause Mg to form an effective P-type doping in GaN, thereby increasing the hole concentration of p-GaN, which is within the protection scope of this application. The second electrode layer 300 can be Pt (platinum), W (tungsten), Ta (tantalum) and NiCr alloy. The third electrode layer 400 can be ITO, AZO (aluminum-doped zinc oxide), GZO (gallium-doped zinc oxide), or a metal grid (such as Ag nanowires). In addition, the electrode structure 10 proposed in this application can be used not only in the above-mentioned semiconductor light-emitting devices, but also in other semiconductor devices.
[0098] In the three-layer electrode structure of the first electrode layer 200, the second electrode layer 300 and the third electrode layer 400, the first electrode layer 200 has a lower formation enthalpy with H than Mg-H, and can attract p at high temperature. + The H atoms of the Mg-H complex in the p-GaN form effective p-type doping of Mg in the GaN, thereby increasing the hole concentration in the p-GaN and improving the efficiency of the semiconductor light-emitting device. The second electrode layer 300, as a high-work-function metal, can reduce the potential barrier difference between the p-GaN and electrode interfaces. The third electrode layer 400 acts as a current spreading layer to evenly distribute the current at the interface.
[0099] In summary, the three-layer electrode structure of the first electrode layer 200 , the second electrode layer 300 and the third electrode layer 400 can form a good ohmic contact with P-GaN while taking into account current uniformity.
[0100] In one embodiment, reference Figure 1-Figure 5 As shown, the first electrode layer 200 includes a plurality of electrode layer units 210 , a plurality of grooves 110 corresponding thereto are provided on the semiconductor material 100 , and the plurality of electrode layer units 210 are spaced apart and arranged in the plurality of grooves 110 .
[0101] Based on the above configuration, the multiple grooves 110 arranged at intervals can increase the contact area between the first electrode layer 200 and the semiconductor material 100 on the one hand, and can also make the distribution of the first electrode layer 200 and the semiconductor material 100 more uniform on the other hand.
[0102] In one embodiment, continue to refer to Figure 1-Figure 5 As shown, the height of the electrode layer unit 210 is set to be the same as the depth of the groove 110. That is, the electrode layer unit 210 just fills the groove 110 and is in contact with the second electrode layer 300.
[0103] Based on the above configuration, the electrode layer unit 210 and the semiconductor material 100 form a smooth outward contact surface, ie, without protrusions or depressions, which facilitates contact between the second electrode layer 300 and the electrode layer unit 210 and also makes the second electrode layer 300 more flat.
[0104] In one embodiment, reference Figure 2 As shown, the electrode layer unit 210 is arranged in a trapezoidal shape, and the trapezoid includes a first bottom surface 211 and a second bottom surface 212. The first bottom surface 211 is larger than the second bottom surface 212, and the second bottom surface 212 is arranged in contact with the second electrode layer 300. It should be noted that the above-mentioned trapezoidal shape is a graphic pattern in cross section, and can actually be set to a cylindrical shape with a larger top and a smaller bottom, or a square shape with a larger top and a smaller bottom.
[0105] Because the trapezoidal structure has a larger base and a smaller top, the contact surface between the electrode layer unit 210 and the semiconductor material 100 is larger, thereby generating more holes. Furthermore, the contact surface between the electrode layer unit 210 and the second electrode layer 300 is smaller, while conversely, the contact surface between the second electrode layer 300 and the semiconductor material 100 is larger. This results in a higher hole concentration in the semiconductor material 100 and significantly reduces the barrier difference between the P-GaN and electrode interfaces.
[0106] In one embodiment, reference Figure 3 As shown, the electrode layer unit 210 is spherical, and the end of the sphere facing away from the bottom of the groove 110 is in contact with the second electrode layer 300. That is, the sphere can be completely buried in the semiconductor material 100, leaving a contact point on the outside to contact the second electrode layer 300.
[0107] Based on the above configuration, under the same volume, the spherical shape can increase the contact area between the electrode layer unit 210 and the semiconductor material 100. At the same time, the exposed surface of the electrode layer unit 210 is a spherical contact point, which makes the contact area between the electrode layer unit 210 and the second electrode layer 300 smaller. Conversely, the contact area between the second electrode layer 300 and the semiconductor material 100 is larger. This further increases the hole concentration in the semiconductor material 100 and greatly reduces the barrier difference between the P-GaN and electrode interfaces.
[0108] In one embodiment, reference Figure 4 As shown, the electrode layer unit 210 further includes a first substructure 210A and a second substructure 210B connected to each other. The cross-section of the first substructure 210A is larger than the cross-section of the second substructure 210B, and the end of the second substructure 210B facing away from the first substructure 210A is arranged in contact with the second electrode layer 300. It should be noted that the cross-section of the first substructure 210A is larger than the cross-section of the second substructure 210B, that is, the volume of the first substructure 210A is larger than that of the second substructure 210B.
[0109] Based on the above configuration, the volume of the first substructure 210A can be increased, while the volume of the second substructure 210B can be decreased, thereby achieving a larger contact surface with the semiconductor material 100 and a smaller contact surface with the second electrode layer 300. Furthermore, the depth, length, and volume of the first substructure 210A and the second substructure 210B can be designed based on practical needs to achieve a balance between performance and functionality.
[0110] refer to Figure 6 As shown, in one embodiment, the present application further proposes a method for manufacturing a semiconductor device, comprising:
[0111] S1: providing a substrate;
[0112] S2: forming a semiconductor material 100 and a first electrode layer 200 that cooperate with each other on a substrate;
[0113] S3: forming a second electrode layer 300 on a side of the first electrode layer 200 facing away from the substrate;
[0114] S4: disposing a third electrode layer 400 on a side of the second electrode layer 300 facing away from the first electrode layer 200;
[0115] The first electrode layer 200 is embedded in the semiconductor material 100, and the end of the first electrode layer 200 facing away from the substrate is in contact with the second electrode layer 300. That is, a groove 110 is provided on the semiconductor material 100, and the first electrode layer 200 is disposed in the groove 110 and connected to the second electrode layer 300.
[0116] It should be noted that the above semiconductor device manufacturing method also includes manufacturing electrodes, upper ITO layer, N-GaN layer and MQW multiple quantum well, etc. The above manufacturing processes are all existing technologies and will not be described in detail in this application.
[0117] Through the above configuration, a three-layer electrode structure consisting of a first electrode layer 200, a second electrode layer 300, and a third electrode layer 400 can be formed on the semiconductor material 100. The first electrode layer 200 has a lower formation enthalpy with H than Mg-H, and can attract p at high temperatures. + The H atoms of the Mg-H complex in p-GaN enable Mg to form effective P-type doping in GaN, thereby increasing the hole concentration of p-GaN. The second electrode layer 300, as a high work function metal, can reduce the barrier difference between the P-GaN and the electrode interface. The third electrode layer 400 acts as a current spreading layer to evenly distribute the current at the interface.
[0118] In addition, the three-layer electrode structure of the first electrode layer 200, the second electrode layer 300 and the third electrode layer 400 can form a good ohmic contact with P-GaN and take into account the current uniformity. + In the groove 110 of the p-GaN, the contact area between the first electrode layer 200 and the p-GaN can be increased, and the hole concentration of the p-GaN can be further increased.
[0119] In one embodiment, reference Figure 1 As shown, forming a semiconductor material 100 and a first electrode layer 200 that cooperate with each other on a substrate includes:
[0120] S21A: forming a semiconductor material 100 on a substrate;
[0121] S22A: Etching a plurality of grooves 110 on the semiconductor material 100;
[0122] S23A: forming a first electrode layer 200 in the groove 110 , wherein the first electrode layer 200 includes a plurality of electrode layer units 210 , and shapes of the plurality of electrode layer units 210 match the plurality of grooves 110 .
[0123] In the above manufacturing method, a plurality of grooves 110 may be formed by etching the semiconductor material 100 first, and then the first electrode layer 200 may be formed in the grooves 110. Figure 1 As shown, this manufacturing method is suitable for grooves 110 with uniform cross-sections, and can be directly manufactured using a conventional mask. This process is mature, efficient, and low-cost.
[0124] In one embodiment, reference Figure 5As shown, the semiconductor material 100 and the first electrode layer 200 formed on the substrate in cooperation with each other may also be configured to include:
[0125] S21B: forming a first semiconductor unit 120 on the substrate;
[0126] S22B: forming a first electrode layer 200 on the first semiconductor unit 120;
[0127] S23B: Etching to form a plurality of electrode layer units 210 on the first electrode layer 200;
[0128] S24B: forming a second semiconductor unit 130 on the first semiconductor unit 120 , wherein the second semiconductor unit 130 wraps around the sides of the plurality of electrode layer units 210 , and the second semiconductor unit 130 and the first semiconductor unit 120 are combined to form the semiconductor material 100 .
[0129] In the above manufacturing method, a portion of semiconductor material 100, namely the first semiconductor unit 120, can be first produced, and then the desired electrode layer unit 210 pattern can be formed on the first semiconductor unit 120, and finally the side of the electrode layer unit 210 can be wrapped with another portion of semiconductor material 100.
[0130] This manufacturing method can not only produce grooves 110 with uniform cross-sections, but also produce electrode layer units 210 with varying cross-sections. For example, the area at the bottom of the groove 110 can be increased, reducing the contact surface with the second electrode layer 300. In other words, this manufacturing method can cover a wider range of types and can accommodate the trapezoidal and spherical electrode layer units 210 described in the above embodiments.
[0131] In one embodiment, reference Figure 2 As shown, the shape of the groove 110 is a trapezoid, and the trapezoid includes a first bottom surface 211 and a second bottom surface 212 . The first bottom surface 211 is larger than the second bottom surface 212 , and the second bottom surface 212 is arranged away from the substrate.
[0132] Because the trapezoidal structure has a larger base and a smaller top, the contact surface between the electrode layer unit 210 and the semiconductor material 100 is larger, thereby generating more holes. Furthermore, the contact surface between the electrode layer unit 210 and the second electrode layer 300 is smaller, while the contact surface between the second electrode layer 300 and the semiconductor material 100 is larger.
[0133] In one embodiment, reference Figure 3 As shown, the groove 110 is spherical, and the end of the sphere facing away from the substrate is in contact with the second electrode layer 300 .
[0134] Based on the above configuration, under the same volume, the spherical shape can make the contact area between the electrode layer unit 210 and the semiconductor material 100 larger, and the surface of the electrode layer unit 210 exposed to the outside is a point of the sphere, so that the contact area between the electrode layer unit 210 and the second electrode layer 300 will be smaller. Conversely, the contact area between the second electrode layer 300 and the semiconductor material 100 will be larger.
[0135] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application shall be included in the scope of protection of this application.
Claims
1. An electrode structure for connecting to a semiconductor material, characterized in that: The electrode structure comprises: a first electrode layer, the first electrode layer being arranged in the groove on the semiconductor material and being in contact with the semiconductor material; a second electrode layer, wherein the second electrode layer is disposed on the semiconductor material and is in contact with the first electrode layer; A third electrode layer covers a side of the second electrode layer facing away from the semiconductor material.
2. The electrode structure according to claim 1, wherein: The first electrode layer includes a plurality of electrode layer units, a plurality of grooves corresponding to the first electrode layer units are provided on the semiconductor material, and the plurality of electrode layer units are spaced apart and arranged in the plurality of grooves.
3. The electrode structure according to claim 2, wherein: The height of the electrode layer unit is set to be the same as the depth of the groove.
4. The electrode structure according to claim 2, wherein: The electrode layer unit is arranged in a trapezoidal shape, and the trapezoid includes a first bottom surface and a second bottom surface, the first bottom surface is larger than the second bottom surface, and the second bottom surface is arranged in contact with the second electrode layer.
5. The electrode structure according to claim 2, wherein: The electrode layer unit is spherical, and one end of the sphere facing away from the bottom of the groove is in contact with the second electrode layer.
6. The electrode structure according to claim 2, wherein: The electrode layer unit further includes a first substructure and a second substructure connected to each other, the cross section of the first substructure is larger than the cross section of the second substructure, and the end of the second substructure facing away from the first substructure is arranged in contact with the second electrode layer.
7. A semiconductor device comprising the electrode structure according to any one of claims 1 to 6.
8. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a semiconductor material and a first electrode layer that cooperate with each other on a substrate; forming a second electrode layer on a side of the first electrode layer facing away from the substrate; Disposing a third electrode layer on a side of the second electrode layer facing away from the first electrode layer; The first electrode layer is embedded in the semiconductor material, and one end of the first electrode layer facing away from the substrate is in contact with the second electrode layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein: Forming a semiconductor material and a first electrode layer that cooperate with each other on a substrate includes: forming a semiconductor material on the substrate; Etching a plurality of grooves in the semiconductor material; A first electrode layer is formed in the groove, wherein the first electrode layer includes a plurality of electrode layer units, and shapes of the plurality of electrode layer units match the plurality of grooves.
10. The method for manufacturing a semiconductor device according to claim 8, wherein: Forming a semiconductor material and a first electrode layer that cooperate with each other on a substrate includes: forming a first semiconductor unit on the substrate; forming a first electrode layer on the first semiconductor unit; Etching on the first electrode layer to form a plurality of electrode layer units; A second semiconductor unit is formed on the first semiconductor unit, wherein the second semiconductor unit wraps around the sides of the plurality of electrode layer units, and the second semiconductor unit is combined with the first semiconductor unit to form a semiconductor material.
11. The method for manufacturing a semiconductor device according to any one of claims 9 or 10, wherein: The groove is in a trapezoidal shape, and the trapezoid includes a first bottom surface and a second bottom surface, the first bottom surface is larger than the second bottom surface, and the second bottom surface is arranged away from the substrate; and / or The groove is spherical, and one end of the sphere facing away from the substrate is in contact with the second electrode layer.