A transistor reliability test system and method with nanosecond-level delay

Abstract

A transistor reliability testing system and method with nanosecond-level delay is disclosed, belonging to the field of transistor testing technology. The testing system consists of three parts: a voltage stress value and stress duration control module, a current control module, and a hard-switching transient and on-resistance testing module. These modules are used to control the drain voltage stress value and duration of the transistor under test; the current magnitude during hard-switching testing; and the on-time. The testing system processes signals through hardware circuitry, converting a single-channel input pulse signal into two inverted pulse signals with a "dead time," thus improving the safety of the testing system. Only one pulse signal needs to be input to each of the three modules to flexibly adjust the drain voltage stress duration, current, and on-time of the transistor under test. Simulation and experiments demonstrate that the measurement delay from the end of drain voltage stress to the switch to test state is on the order of nanoseconds, which is of great significance for real-time monitoring of performance degradation after transistor drain voltage stress.

Description

Technical Field

[0001] This invention belongs to the field of transistor testing, specifically relating to a transistor reliability testing system and method with nanosecond-level delay. This system and method can realize the switching characteristics and dynamic on-resistance testing of transistors with nanosecond-level delay under arbitrary drain voltage stress values, drain voltage stress durations, and load currents. Background Technology

[0002] The double-pulse circuit can be used to study the hard-switching characteristics of a transistor when it is simultaneously subjected to drain voltage stress and load current. The double-pulse circuit test method involves applying two consecutive pulses to the gate of the transistor under test (TUT), causing the TUT to switch on and off twice consecutively. When the transistor is on, the high-voltage power supply charges the load inductor; when the transistor is off, the current in the load inductor freewheels through the diode and gradually discharges. Controlling the first turn-on duration of the TUT allows for precise control of the current at the end of the first power inductor charging. The first turn-on duration of the TUT is typically 2 to 10 microseconds. The TUT is then turned off for approximately 1 to 3 microseconds before being turned on again. During the second turn-on, the TUT simultaneously experiences a significant switching of drain voltage and drain current, constituting a hard-switching process. Studying the transient process of the second turn-on and the on-resistance during the second conduction allows for analysis of the drain voltage stress degradation.

[0003] Traditional dual-pulse circuits cannot control the drain voltage stress time of transistors, and the switch from the end of the drain voltage stress to the measurement state generally involves a long measurement delay. This delay includes the time for the transistor to be turned on for the first time (typically 2 to 10 microseconds) and the time for the transistor to be turned off for the first time, during which the inductor current freewheels through the Schottky diode (typically 1 to 3 microseconds). According to relevant literature, for example, Kailun Zhong published a paper titled "..." in the IEEE Transactions on Industrial Electronics journal in August 2022, pages 8387-8395. I G - and V GS -DependentDynamic R ONThe papers "Characterization of Commercial High-Voltage p-GaN Gate Power HEMTs" and "Review of Pulse Test Setup for the Switching Characterization of GaN Power Devices" published by Guangze Zu in IEEE Transactions on Electron Devices (pp. 3003-3013) in June 2022 point out that for novel transistors fabricated from certain new materials (gallium nitride, silicon carbide, gallium oxide, etc.), drain voltage stress can cause internal defects to trap carriers, threshold voltage drift, and on-resistance degradation. After the drain voltage stress is removed, the internal defects gradually release carriers. Depending on the type of defect, the time constant for carrier release can be on the order of microseconds, milliseconds, or seconds. For defects with a time constant on the order of microseconds, a measurement delay of several microseconds (e.g., 3 to 13 microseconds) can lead to inaccurate measurement results, making it impossible to display the true state of the transistor after drain voltage stress in real time. Obviously, the data measured by the traditional dual-pulse circuit cannot reflect the instantaneous switching characteristics and on-resistance of the transistor under test after drain voltage stress. Summary of the Invention

[0004] The purpose of this invention is to provide a transistor reliability testing system and method with a measurement delay on the order of nanoseconds after drain voltage stress. The testing system is based on a traditional double-pulse circuit, but addresses the problem of a long delay (typically 3 to 13 microseconds) between the end of drain voltage stress and the start of measurement of the transistor's turn-on transients and on-resistance in traditional double-pulse testing circuits. This invention discloses a novel testing system and method. This testing system can test the transistor's switching transients and on-resistance under arbitrary drain voltage stress values, drain voltage stress durations, and load currents, provided the measurement delay is on the order of nanoseconds.

[0005] This invention's system consists of three modules. Each module requires only one externally input pulse signal. The system has built-in logic processing capabilities, which can convert one pulse signal into two pulse signals, including a dead time, through hardware circuitry (for enhanced security). The dead time is also flexibly adjustable. This transistor reliability testing system includes two circuit structures: the first structure's power module contains five NMOS power transistors, its advantage being that only NMOS technology is involved in integrating this power circuit. The second structure's power module contains five NMOS power transistors and two PMOS transistors, its advantage being that it does not require an isolated gate driver chip and an isolated power supply, allowing for easier integration into a single power chip. The appropriate circuit structure can be flexibly selected according to actual needs.

[0006] To achieve the above objectives, the specific technical solution adopted is as follows:

[0007] The first objective of this invention is to provide a transistor reliability testing system with nanosecond-level delay, including a voltage stress value and stress duration control module, a current control module, and a hard-switching transient and on-resistance testing module. Each of the voltage stress value and stress duration control module, the current control module, and the hard-switching transient and on-resistance testing module includes two parts: a logic circuit and a power circuit.

[0008] The voltage stress value and stress duration control module is used to control the drain voltage stress value and drain voltage stress duration of the transistor under test; the current control module is used to control the current magnitude during the hard switching test of the transistor under test; and the hard switching transient and on-resistance test module is used to control the on-time of the transistor under test after hard switching.

[0009] Furthermore, the logic circuit portion of the voltage stress value and stress duration control module of the present invention includes an NMOS transistor, a resistor, a capacitor, a Schottky diode, and a gate driver chip; the power circuit portion of the voltage stress value and stress duration control module includes an NMOS power transistor / or a PMOS and an NMOS power transistor, a power resistor, and a Zener diode; the logic circuit converts an input pulse signal into two inverted pulse signals with a "dead time", and inputs the two pulse signals into the power circuit; the power circuit controls the conduction status of the half-bridge circuit of the module based on the two pulse signals, thereby controlling the midpoint voltage of the bridge arm.

[0010] Furthermore, the logic circuit portion of the current control module of the present invention includes a gate driver chip; the power circuit portion of the current control module includes an NMOS power transistor, a Schottky diode, and a power inductor; the logic circuit converts an input pulse signal into a pulse signal with "the ability to output a large transient current" and inputs the pulse signal into the power circuit; the power circuit controls the conduction status of the NMOS power transistor based on the pulse signal, thereby controlling the current of the power inductor.

[0011] Furthermore, the logic circuit portion of the hard-switching transient and on-resistance testing module of the present invention includes an NMOS transistor, a resistor, a capacitor, a Schottky diode, and a gate driver chip; the power circuit portion of the hard-switching transient and on-resistance testing module includes an NMOS power transistor / or a PMOS and an NMOS power transistor, a power resistor, and a Zener diode; the logic circuit converts one input pulse signal into two inverted pulse signals with a "dead time", and inputs the two pulse signals into the power circuit; the power circuit controls the conduction status of the half-bridge circuit of the module based on the two pulse signals, thereby controlling whether the transistor under test is turned on and the drain connection position of the transistor under test.

[0012] Furthermore, the logic circuit portion of the voltage stress value and stress duration control module includes NMOS transistors. Q A3 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 Among them, NMOS transistors Q A3 gate connection V A0 Terminal, NMOS transistor Q A3 Drain connection resistor R 1 and R 2, one end of the resistor R The other end of 1 and V CC Connection; Resistor R The other end of 2 is connected to a capacitor. C One end of 1 and the gate driver chip U A1 The input terminal IN, capacitor C The other end of 1 is connected to an NMOS transistor. Q A3 Source and gate driver chips UA1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 Terminal; resistor R 3 One end connected V A0 Terminal, resistor R The other end of 3 is connected to a resistor. R One end of 4, resistor R The other end of 4 is connected to a capacitor. C One end of 2 and the Schottky diode D 5's anode, and with the gate driver chip U A2 Connect the input terminal IN to the Schottky diode. D 5 Cathode connection resistor R 3 and resistance R 4 common connection terminals; capacitor C The other end of 2 is connected to the gate driver chip. U A2 GND1, the ground terminal, is the gate driver chip. U A2 The output terminal OUT and the ground terminal GND2 are respectively V GA2 End and V SA2 end;

[0013] The power circuit section of the voltage stress value and stress duration control module includes NMOS power transistors. Q A1 and Q A2 Among them, NMOS power transistors Q A2 The source of the NMOS power transistor Q A1 The drain connection forms a common terminal with V SA2 Connection, NMOS power transistor Q A2 drain connection V DD Terminal, its gate is connected V GA2 NMOS power transistor Q A1 Its source is grounded, and its gate is connected to... V GA1 .

[0014] Furthermore, the logic circuit portion of the current control module includes a gate driver chip. UB1 Gate driver chip U B1 IN input terminal connection V B0 The output terminal OUT is V GB0 end;

[0015] The power circuit section of the current control module includes NMOS power transistors. Q B0 Schottky diode D 1 and D 2. Power Inductor L Among them, NMOS transistors Q B0 Drain and power inductor L one end and Schottky diode D 1 and D The two anodes are connected to the common terminal, power inductor L The other end and the Schottky diode D The NMOS transistor of the cathode and voltage stress value and stress duration control module of 1 Q A1 drain and NMOS transistor Q A2 The source pole and V SA2 The common connection terminals are connected; NMOS transistors Q B0 The source and voltage stress value and stress duration control module of the NMOS transistor Q A1 The source terminals are connected; NMOS transistor Q B0 gate connection V GB0 end.

[0016] Furthermore, the logic circuit portion of the hard-switching transient and on-resistance testing module includes NMOS transistors. Q C3 ,resistance R 5- R 8. Capacitors C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 Among them, NMOS transistors Q C3 gate connection V C0 Terminal, NMOS transistorQ C3 Drain connection resistor R 5 and R One end of 6, resistor R The other end of 5 and V CC Connection; Resistor R The other end of 6 is connected to a capacitor. C 3 and the gate driver chip U C2 The input terminal IN, capacitor C The other end of 3 is connected to an NMOS transistor. Q C3 Source and gate driver chips U C2 GND1, the ground terminal, is the gate driver chip. U C2 The output terminal OUT is V GC2 Terminal, gate driver chip U C2 The grounding terminal GND2 is V SC2 Terminal; resistor R 7 one end connected V C0 Terminal, resistor R The other end of the resistor is connected R One end of the 8, resistor R The other end of 8 is connected to a capacitor. C One end of 4 and the Schottky diode D The anode of 6, and the gate driver chip U C1 Connect the input terminal IN to the Schottky diode. D 6 Cathode connection resistor R 7 and resistance R 8 common connection terminals; capacitor C The other end of 4 is connected to the gate driver chip. U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end;

[0017] The power circuit section of the hard-switching transient and on-resistance test module includes NMOS power transistors. Q C1 and Q C2 Among them, NMOS transistors Q C2 The source of the NMOS transistor QC1 The drain connection forms a common terminal with the Schottky diode of the current control module. D 2 cathodes are connected and with V SC2 Connection; NMOS transistor Q C2 The drain and current control module's Schottky diode D 1. Cathode, Power Inductor L And the NMOS transistor in the voltage stress value and stress duration control module. Q A1 drain of NMOS transistor Q A2 The source pole, V SA2 The common connection terminals are connected; NMOS transistors Q C2 gate connection V GC2 NMOS power transistor Q C1 The NMOS transistor in the source connection current control module Q B0 The source of the NMOS transistor and the voltage stress value and stress duration control module Q A1 The source of the NMOS power transistor Q C1 gate connection V GC1 The NMOS transistor mentioned above Q B0 The source and NMOS transistor Q C1 The source common connection terminal of the NMOS transistor Q C2 The source of the NMOS transistor Q C1 Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two cathodes.

[0018] Furthermore, the power circuit portion of the voltage stress value and stress duration control module of the present invention also includes a PMOS transistor. Q A3 Power resistor R 9 and R 10 Zener diode D 3; among which, NMOS transistor Q A1 The source of the NMOS transistor Q A2The common terminal of the NMOS transistor is grounded after the source is connected. Q A2 Drain and resistor R One end of 9 is connected to the resistor. R The other end of 9 is connected to a Zener diode. D 3. Anode and resistor R 10 One end, and with the PMOS transistor Q A3 The gate of the PMOS transistor is connected to the gate. Q A3 The drain of the NMOS transistor Q A1 The drains are connected; Zener diode D 3 Cathode and resistor R 10 The other end is connected to the PMOS transistor Q A3 The source terminals are connected, and connected V DD ;

[0019] The logic circuit of the voltage stress value and stress duration control module includes NMOS transistors. Q A4 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 Among them, NMOS transistors Q A4 gate connection V A0 Terminal, NMOS transistor Q A4 Drain connection resistor R 1 and R 2, one end of the resistor R The other end of 1 and V CC Connection; Resistor R The other end of 2 is connected to a capacitor. C One end of 1 and the gate driver chip U A1 The input terminal IN, capacitor C The other end of 1 is connected to an NMOS transistor. Q A4 Source and gate driver chips U A1The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 Terminal; resistor R 3 One end connected V A0 Terminal, resistor R The other end of 3 is connected to a resistor. R One end of 4, resistor R The other end of 4 is connected to a capacitor. C One end of 2 and the Schottky diode D 5's anode, and with the gate driver chip U A2 Connect the input terminal IN to the Schottky diode. D 5 Cathode connection resistor R 3 and resistance R 4 common connection terminals; capacitor C The other end of 2 is connected to the gate driver chip. U A2 The ground terminal GND, gate driver chip U A2 The output terminal OUT is V GA2 end.

[0020] Furthermore, the logic circuit portion of the current control module includes a gate driver chip. U B1 Gate driver chip U B1 IN input terminal connection V B0 The output terminal OUT is V GB0 end;

[0021] The power circuit section of the current control module includes NMOS power transistors. Q B0 Schottky diode D 1 and D 2. Power Inductor L Among them, NMOS transistors Q B0 Drain and power inductor L one end and Schottky diode D 1 and D The two anodes are connected to a common connection terminal. As a further embodiment, the power inductor of the present invention... L The other end and the Schottky diode D The PMOS transistor of the cathode and voltage stress value and stress duration control module of 1 QA3 drain and NMOS transistor Q A1 The drains are connected; NMOS transistor Q B0 The source and voltage stress value and stress duration control module of the NMOS transistor Q A1 The source and NMOS transistor Q A2 The source terminals are connected; NMOS transistor Q B0 gate connection V GB0 end.

[0022] Furthermore, the power circuit section of the hard-switching transient and on-resistance testing module of the present invention also includes a PMOS transistor. Q C3 Power resistor R 11 and R 12 Zener diode D 4; among which, NMOS transistor Q C1 The source and NMOS transistor Q C2 The common terminal after the source connection is connected to the NMOS transistor in the current control module. Q B0 The source of the NMOS transistor and the voltage stress value and stress duration control module Q A1 The source and NMOS transistor Q A2 The source terminals are connected; NMOS transistor Q C2 Drain and resistor R 12 One end is connected to the resistor. R 12 The other end is connected to a Zener diode. D 4 Anode and resistance R 11 One end, and with the PMOS transistor Q C3 The gate of the PMOS transistor is connected to the gate. Q C3 The drain of the NMOS transistor Q C1 The common connection terminal of the drain is connected to the Schottky diode of the current control module. D 2 cathodes connected; Zener diode D 4 Cathode and resistor R11 The other end is connected to the PMOS transistor Q C3 The source is connected to the Schottky diode of the current control module. D 1. Cathode, Power Inductor L And the NMOS transistor in the voltage stress value and stress duration control module. Q A1 drain, PMOS transistor Q A3 The common connection terminal of the drain of the NMOS transistor is connected; Q B0 The source and NMOS transistor Q C1 The common connection terminal of the NMOS transistor Q C1 drain, PMOS transistor Q C3 Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two cathodes;

[0023] The logic circuit section of the hard-switching transient and on-resistance test module includes NMOS transistors. Q C4 ,resistance R 5- R 8. Capacitors C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 Among them, NMOS transistors Q C4 gate connection V C0 Terminal, NMOS transistor Q C4 Drain connection resistor R 5 and R One end of 6, resistor R The other end of 5 and V CC Connection; Resistor R The other end of 6 is connected to a capacitor. C 3 and the gate driver chip U C2 The input terminal IN, capacitor C The other end of 3 is connected to an NMOS transistor. Q C4 Source and gate driver chips U C2The ground terminal GND, gate driver chip U C2 The output terminal OUT is V GC2 Terminal; resistor R 7 one end connected V C0 Terminal, resistor R The other end of 7 is connected to a resistor. R One end of the 8, resistor R The other end of 8 is connected to a capacitor. C One end of 4 and the Schottky diode D The anode of 6, and the gate driver chip U C1 Connect the input terminal IN to the Schottky diode. D 6 Cathode connection resistor R 7 and resistance R 8 common connection terminals; capacitor C The other end of 4 is connected to the gate driver chip. U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end.

[0024] The second objective of this invention is to provide a method for testing the reliability of transistors with nanosecond-level delays, implemented using the system provided in the first aspect of this invention, comprising the following steps:

[0025] 1) Determine the duration of the drain voltage stress of the transistor under test, and thereby determine the pulse width of pulse 1;

[0026] 2) Determine the current value of the transistor under test, and thereby determine the pulse width of pulse 2;

[0027] 3) Then determine the turn-on duration of the transistor under test, and thereby determine the pulse width of pulse 3;

[0028] 4) Subsequently, the drain voltage stress value of the transistor under test is determined, and the parameters required for the high-voltage power supply are determined accordingly;

[0029] 5) Set the high-voltage power supply parameters; then input pulse 1, pulse 2, and pulse 3 into the logic circuit;

[0030] 6) The logic circuit will generate 5 pulse signals, and these 5 pulse signals include an adjustable dead time;

[0031] 7) Five pulse signals drive five transistors via a gate drive module;

[0032] 8) Improve test accuracy through clamping circuits;

[0033] 9) Obtain the voltage and current parameters of the transistor under test using an oscilloscope;

[0034] 10) Obtain the transient switching characteristics and conduction characteristics of the transistor under test from the voltage and current parameters;

[0035] 11) Finally, the reliability parameters of the transistor under test under nanosecond delay are obtained.

[0036] The beneficial effects of this invention are:

[0037] 1. This invention can test the switching transients and on-resistance of the transistor under test under arbitrary drain voltage stress value, drain voltage stress duration, and load current, under the premise of measuring delay at the nanosecond level.

[0038] 2. This invention is divided into 3 modules. Each module only needs to input one pulse signal. The test system has built-in logic processing function. It can convert one pulse signal into two pulse signals including dead time through hardware circuit (higher security). The dead time can be flexibly adjusted.

[0039] 3. This transistor reliability testing system proposes two circuit structures. The first structure includes a power module with five NMOS power transistors. Its advantage is that only NMOS technology is involved in integrating this power circuit. Its disadvantage is that the upper NMOS transistor in the half-bridge structure requires an isolated gate driver chip and an isolated power supply for isolated driving. The second structure includes a power module with five NMOS power transistors and two PMOS transistors. Its advantage is that it does not require an isolated gate driver chip and an isolated power supply, allowing for easier integration into a single power chip. Its disadvantage is that it involves two transistor fabrication processes: NMOS and PMOS. Attached Figure Description

[0040] The invention will be better understood from the following description, which relates to a preferred embodiment given by way of non-limiting example and explained with reference to the accompanying schematic diagram, wherein:

[0041] Figure 1 This is a circuit block diagram of the transistor reliability testing system with nanosecond-level delay of the present invention.

[0042] Figure 2 This is a circuit schematic diagram of a transistor reliability testing system with an NMOS structure according to one embodiment of the present invention.

[0043] Figure 3 This is a circuit schematic diagram of a transistor reliability testing system with a CMOS structure according to another embodiment of the present invention.

[0044] Figure 4This is a flowchart of the transistor reliability testing system with nanosecond-level delay according to the present invention.

[0045] Figure 5 This is a circuit embodiment of the transistor reliability testing system with CMOS structure of the present invention.

[0046] Figure 6 This is the present invention. Figure 5 The logic signals of the "voltage stress value and stress duration control module" in the circuit embodiment.

[0047] Figure 7 This is the present invention. Figure 5 The logic signals of the "current control module" in the circuit embodiment.

[0048] Figure 8 This is the present invention. Figure 5 The logic signals of the "hard switching transient and on-resistance test module" in the circuit embodiment.

[0049] Figure 9 This is the present invention. Figure 5 The power signal of the "hard switching transient and on-resistance test module" in the circuit embodiment. Detailed Implementation

[0050] The present invention will now be described in further detail with reference to the accompanying drawings. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0051] This invention relates to a transistor reliability testing system with nanosecond-level delay, which can test the transistor characteristics of the transistor under test under arbitrary drain voltage stress value, drain voltage stress duration, and load current, under the premise of measuring delay at the nanosecond level.

[0052] Figure 1 This is a circuit block diagram of a transistor reliability testing system with nanosecond-level delays. It consists of five parts: experimental setup, external input, logic circuit, power circuit, and external monitoring. First, the experimental setup involves designing the drain voltage stress value, drain voltage stress duration, load current value, and conduction time of the transistor under test (TUT) according to experimental requirements. Next, three pulse signals are designed based on the drain voltage stress duration, load current value, and TUT conduction time. These three pulse signals are then input to the logic circuit, which converts them into five pulse signals with dead time. These five pulse signals are then input to the gate driver chip in the power circuit, which drives the power transistor. A drain clamping module is also added to the power circuit to improve the testing accuracy of the TUT drain voltage. Finally, external monitoring is performed using testing instruments such as an oscilloscope to obtain key information such as the TUT gate drive voltage, drain voltage, and drain-source current.

[0053] Figure 2 This is a circuit schematic diagram of a transistor reliability testing system with an NMOS structure according to one embodiment of the present invention. (See attached diagram.) Figure 2 As shown, the circuit can be divided into three parts: a voltage stress value and stress duration control module, a current control module, and a hard-switching transient and on-resistance testing module. Each module contains two parts: a logic circuit and a power circuit.

[0054] Specifically, in this embodiment, the logic circuit portion of the voltage stress value and stress duration control module includes NMOS transistors. Q A3 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 Among them, NMOS transistors Q A3 gate connection V A0 Terminal, NMOS transistor Q A3 Drain connection resistor R 1 and R 2, one end of the resistor R The other end of 1 and V CC Connection. Resistor. R The other end of 2 is connected to a capacitor. C One end of 1 and the gate driver chip U A1 The input terminal IN, capacitor C The other end of 1 is connected to an NMOS transistor. Q A3 Source and gate driver chips U A1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 Terminal. Resistor R 3 One end connected V A0 Terminal, resistor R The other end of 3 is connected to a resistor. R One end of 4, resistor R The other end of 4 is connected to a capacitor. C One end of 2 and the Schottky diode D 5's anode, and with the gate driver chip UA2 Connect the input terminal IN to the Schottky diode. D 5 Cathode connection resistor R 3 and resistance R 4 common connection terminals; capacitor C The other end of 2 is connected to the gate driver chip. U A2 GND1, the ground terminal, is the gate driver chip. U A2 The output terminal OUT and the ground terminal GND2 are respectively V GA2 End and V SA2 end.

[0055] The power circuit section of the voltage stress value and stress duration control module includes NMOS power transistors. Q A1 and Q A2 Among them, NMOS power transistors Q A2 The source of the NMOS power transistor Q A1 The drain connection forms a common terminal with V SA2 Connection, NMOS power transistor Q A2 drain connection V DD Terminal, its gate is connected V GA2 NMOS power transistor Q A1 Its source is grounded, and its gate is connected to... V GA1 .

[0056] In this embodiment, the logic circuit section of the current control module includes a gate driver chip. U B1 Gate driver chip U B1 IN input terminal connection V B0 The output terminal OUT is V GB0 end.

[0057] The power circuit section of the current control module includes NMOS power transistors. Q B0 Schottky diode D 1 and D 2. Power Inductor L Among them, NMOS transistors QB0 Drain and power inductor L one end and Schottky diode D 1 and D The two anodes are connected to the common terminal, power inductor L The other end and the Schottky diode D The NMOS transistor of the cathode and voltage stress value and stress duration control module of 1 Q A1 drain and NMOS transistor Q A2 The source pole and V SA2 The common connection terminals are connected; NMOS transistors Q B0 The source and voltage stress value and stress duration control module of the NMOS transistor Q A1 The source terminals are connected; NMOS transistor Q B0 gate connection V GB0 end.

[0058] In this embodiment, the logic circuit section of the hard-switching transient and on-resistance testing module includes NMOS transistors. Q C3 ,resistance R 5- R 8. Capacitors C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 Among them, NMOS transistors Q C3 gate connection V C0 Terminal, NMOS transistor Q C3 Drain connection resistor R 5 and R One end of 6, resistor R The other end of 5 and V CC Connection. Resistor. R The other end of 6 is connected to a capacitor. C 3 and the gate driver chip U C2 The input terminal IN, capacitor C The other end of 3 is connected to an NMOS transistor. Q C3 Source and gate driver chips UC2 GND1, the ground terminal, is the gate driver chip. U C2 The output terminal OUT is V GC2 Terminal, gate driver chip U C2 The grounding terminal GND2 is V SC2 Terminal. Resistor R 7 one end connected V C0 Terminal, resistor R The other end of 7 is connected to a resistor. R One end of the 8, resistor R The other end of 8 is connected to a capacitor. C One end of 4 and the Schottky diode D The anode of 6, and the gate driver chip U C1 Connect the input terminal IN to the Schottky diode. D 6 Cathode connection resistor R 7 and resistance R 8 common connection terminals; capacitor C The other end of 4 is connected to the gate driver chip. U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end.

[0059] The power circuit section of the hard-switching transient and on-resistance test module includes NMOS power transistors. Q C1 and Q C2 Among them, NMOS transistors Q C2 The source of the NMOS transistor Q C1 The drain connection forms a common terminal with the Schottky diode of the current control module. D 2 cathodes are connected and with V SC2 Connection; NMOS transistor Q C2 The drain and current control module's Schottky diode D 1. Cathode, Power Inductor L And the NMOS transistor in the voltage stress value and stress duration control module. Q A1 drain of NMOS transistor Q A2 The source pole, VSA2 The common connection terminals are connected. NMOS transistor Q C2 gate connection V GC2 NMOS power transistor Q C1 The NMOS transistor in the source connection current control module Q B0 The source of the NMOS transistor and the voltage stress value and stress duration control module Q A1 The source of the NMOS power transistor Q C1 gate connection V GC1 The NMOS transistor mentioned above Q B0 The source and NMOS transistor Q C1 The source common connection terminal of the NMOS transistor Q C2 The source of the NMOS transistor Q C1 Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two cathodes.

[0060] In this embodiment, the circuit operates by converting the externally input pulse signal into a voltage suitable for driving the power transistor and providing a certain load-carrying (high current output) capability. Simultaneously, the logic circuit can also perform logic conversion to generate a complementary pulse signal with a dead time, which is then input into the power transistor in the power circuit via the gate driver chip.

[0061] Taking the logic circuit in the voltage stress value and stress duration control module as an example, in the initial state there is no pulse signal input, and the test point... V A1 High level, test point V A2 It is at a low level. When the transistor... Q A3 Gate input pulse signal V A0 At that time, transistor Q A3 On, capacitor C 1. Through resistor R 2. Discharge begins. V A1 The voltage gradually decreases; simultaneously, the pulse signal... V A0 After resistor R 3 and resistanceR 4 is a capacitor C 2. Charging, capacitor C Voltage at point 2 V A2 Gradually increasing. When the transistor... Q A3 Gate pulse signal V A0 At the end, transistor Q A3 Turn off the power. V CC After resistor R 1 and resistance R 2 is a capacitor C 1. Charge, V A1 The voltage gradually increases; at the same time, the capacitor... C 2. Through diode D 5 and resistance R 3. Discharge, capacitor C Voltage at point 2 V A2 The voltage gradually decreases. The charging and discharging time constants of the RC circuit mentioned above both satisfy T=R×C. This time constant quantifies the time required for the capacitor to charge or discharge to 63.2% of its final voltage value. (Capacitor) C Voltage at point 1 V A1 and capacitor C Voltage at point 2 V A2 Connect the primary side of the gate driver chip respectively, when the voltage V A1 and voltage V A2 Reaching the gate driver chip respectively U A1 and U A2 When the threshold value is reached, the gate driver chip switches between on and off states. The logic circuits of other modules are analyzed similarly and will not be repeated here.

[0062] The power circuit section of the three modules will be analyzed below.

[0063] For the voltage stress value and stress duration control module, the upper tube of the half-bridge structure... Q A2 and lower pipe Q A1 Alternating conduction. Current pipe Q A1 Upper tube when conducting Q A2 When turned off, the voltage at the midpoint of the bridge arm is... V SA2is 0 V, and there is no high-voltage input to the subsequent circuit. When the lower transistor Q A1 turns off, the upper transistor Q A2 conducts. At this time, the voltage at the midpoint of the bridge arm V SA2 is the supply voltage of the high-voltage power supply V DD , and there is high-voltage input to the subsequent circuit. Controlling the conduction time of the upper transistor Q A2 can control the duration for which the subsequent circuit bears the high voltage V DD .

[0064] For the current control module, when the transistor Q B0 conducts, the potential difference across the power inductor L is V DD , and the current flowing through the power inductor L gradually increases, satisfying the formula L ×di / dt = V DD . When the transistor Q B0 turns off, there is no high-voltage potential difference across the power inductor L . Due to the fact that the inductor current cannot change abruptly, the power inductor L conducts continuous current through the Schottky diode D 1 in parallel with it. Therefore, the Schottky diode D 1 is also called the freewheeling diode. The Schottky diode D 2 is used to connect the low-voltage side port of the power inductor L to the drain of the transistor under test Q C1 . Due to the unidirectional conductivity of the Schottky diode D 2, when the anode potential of the Schottky diode D 2 is relatively low, it is in the cut-off state and will not pull down the potential of the cathode of the Schottky diode D 2 (the drain of the transistor under test Q C1 ), ensuring that during the first charging of the power inductor L , the cathode of the Schottky diode D 2 (the drain of the transistor under test Q C1 ) still bears the voltage stress of the high voltage V DD .

[0065] For the hard-switching transient and on-resistance test module. The power circuit part of it includes two transistors in a half-bridge structure. The upper transistor isQ C2 The lower transistor is the transistor under test. Q C1 Currently in charge Q C1 Top pipe when shut off Q C2 Conduction, enabling the lower tube Q C1 The drain of the upper tube is connected. Q C2 Withstand stable high voltage V DD Currently in charge Q C1 When it is put into operation, the upper pipe Q C2 It will be shut off in advance, allowing the lower pipe to... Q C1 The drain of the Schottky diode is connected to the current control module. D 2. Cathode. Lower tube. Q C1 When turned on, the power inductor L It acts as an inductive load in the circuit. Power inductor. L Potential difference between the two ends V DD Flow through the power inductor L The current gradually increases, satisfying the formula L ×di / dt= V DD When transistors Q C1 When turned off, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change abruptly, the power inductor... L Through a Schottky diode connected in parallel with it D 1. Perform freewheeling. Test the transistor under test. Q C1 From the gate voltage, drain voltage, and drain-source current, we can determine the transistor under test. Q C1 During hard-switching testing, the transient switching characteristics and on-resistance characteristics are examined. Clamping circuitry is used to improve the performance of the transistor under test. Q C1 The accuracy of drain voltage testing will not be discussed further here.

[0066] Figure 3 This is a circuit schematic diagram of a transistor reliability testing system with a CMOS structure according to another embodiment of the present invention. This embodiment is... Figure 2 The circuit shown has been improved, mainly by optimizing the voltage stress value and stress duration control module and the hard-switching transient and on-resistance testing module.

[0067] Specifically, in this embodiment, the power circuit section of the voltage stress value and stress duration control module also includes a PMOS transistor. Q A3 Power resistor R 9 and R 10 Zener diode D 3. Among them, NMOS transistors Q A1 The source of the NMOS transistor Q A2 The common terminal of the NMOS transistor is grounded after the source is connected. Q A2 Drain and resistor R One end of 9 is connected to the resistor. R The other end of 9 is connected to a Zener diode. D 3. Anode and resistor R 10 One end, and with the PMOS transistor Q A3 The gate of the PMOS transistor is connected to the gate. Q A3 The drain of the NMOS transistor Q A1 The drains are connected; Zener diode D 3 Cathode and resistor R 10 The other end is connected to the PMOS transistor Q A3 The source terminals are connected, and connected V DD .

[0068] Furthermore, based on the power circuit of the voltage stress value and stress duration control module described above, the logic circuit portion of the voltage stress value and stress duration control module of this invention includes NMOS transistors. Q A4 ,resistance R 1- R 4. Capacitor C 1- C 2. Schottky diode D 5. Gate driver chip U A1 and U A2 Among them, NMOS transistors Q A4 gate connection V A0 Terminal, NMOS transistor Q A4 Drain connection resistor R 1 and R2, one end of the resistor R The other end of 1 and V CC Connection; Resistor R The other end of 2 is connected to a capacitor. C One end of 1 and the gate driver chip U A1 The input terminal IN, capacitor C The other end of 1 is connected to an NMOS transistor. Q A4 Source and gate driver chips U A1 The ground terminal GND, gate driver chip U A1 The output terminal OUT is V GA1 end.

[0069] resistance R 3 One end connected V A0 Terminal, resistor R The other end of the resistor 3 R One end of 4, resistor R The other end of 4 is connected to a capacitor. C One end of 2 and the Schottky diode D 5's anode, and with the gate driver chip U A2 Connect the input terminal IN to the Schottky diode. D 5 Cathode connection resistor R 3 and resistance R 4 common connection terminals; capacitor C The other end of 2 is connected to the gate driver chip. U A2 The ground terminal GND, gate driver chip U A2 The output terminal OUT is V GA2 end.

[0070] In this embodiment, the logic circuit section of the current control module includes a gate driver chip. U B1 Gate driver chip U B1 IN input terminal connection V B0 The output terminal OUT is V GB0 end.

[0071] The power circuit section of the current control module includes NMOS power transistors. Q B0 Schottky diode D1 and D 2. Power Inductor L Among them, NMOS transistors Q B0 Drain and power inductor L one end and Schottky diode D 1 and D The two anodes are connected to the common terminal, power inductor L The other end and the Schottky diode D The PMOS transistor of the cathode and voltage stress value and stress duration control module of 1 Q A3 drain and NMOS transistor Q A1 The drains are connected; NMOS transistor Q B0 The source and voltage stress value and stress duration control module of the NMOS transistor Q A1 The source and NMOS transistor Q A2 The source terminals are connected; NMOS transistor Q B0 gate connection V GB0 end.

[0072] In this embodiment, the power circuit section of the hard-switching transient and on-resistance testing module also includes a PMOS transistor. Q C3 Power resistor R 11 and R 12 Zener diode D 4. Among them, NMOS transistors Q C1 The source and NMOS transistor Q C2 The common terminal after the source connection is connected to the NMOS transistor in the current control module. Q B0 The source of the NMOS transistor and the voltage stress value and stress duration control module Q A1 The source and NMOS transistor Q A2 The source terminals are connected; NMOS transistor Q C2 Drain and resistor R 12 One end is connected to the resistor. R 12 The other end is connected to a Zener diode. D 4 Anode and resistanceR 11 One end, and with the PMOS transistor Q C3 The gate of the PMOS transistor is connected to the gate. Q C3 The drain of the NMOS transistor Q C1 The common connection terminal of the drain is connected to the Schottky diode of the current control module. D 2 cathodes connected; Zener diode D 4 Cathode and resistor R 11 The other end is connected to the PMOS transistor Q C3 The source is connected to the Schottky diode of the current control module. D 1. Cathode, Power Inductor L And the NMOS transistor in the voltage stress value and stress duration control module. Q A1 drain, PMOS transistor Q A3 The common connection terminal of the drain of the NMOS transistor is connected; Q B0 The source and NMOS transistor Q C1 The common connection terminal of the NMOS transistor Q C1 drain, PMOS transistor Q C3 Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two cathodes.

[0073] Furthermore, based on the power circuit of the above-mentioned hard-switching transient and on-resistance testing module, the logic circuit portion of the hard-switching transient and on-resistance testing module of the present invention includes NMOS transistors. Q C4 ,resistance R 5- R 8. Capacitors C 3- C 4. Schottky diode D 6. Gate driver chip U C1 and U C2 Among them, NMOS transistors Q C4 gate connection V C0 Terminal, NMOS transistor Q C4 Drain connection resistorR 5 and R One end of 6, resistor R The other end of 5 and V CC Connection. Resistor. R The other end of 6 is connected to a capacitor. C 3 and the gate driver chip U C2 The input terminal IN, capacitor C The other end of 3 is connected to an NMOS transistor. Q C4 Source and gate driver chips U C2 The ground terminal GND, gate driver chip U C2 The output terminal OUT is V GC2 end.

[0074] resistance R 7 one end connected V C0 Terminal, resistor R The other end of 7 is connected to a resistor. R One end of the 8, resistor R The other end of 8 is connected to a capacitor. C One end of 4 and the Schottky diode D The anode of 6, and the gate driver chip U C1 Connect the input terminal IN to the Schottky diode. D 6 Cathode connection resistor R 7 and resistance R 8 common connection terminals; capacitor C The other end of 4 is connected to the gate driver chip. U C1 The ground terminal GND, gate driver chip U C1 The output terminal OUT is V GC1 end.

[0075] In this embodiment, the upper transistor in the half-bridge structure is changed from an NMOS transistor to a PMOS transistor. In this case, the source of the PMOS transistor does not change with the turning on or off of the lower transistor, but remains stable at the power supply voltage. V DD Therefore, it eliminates the need for an isolated driver to drive the upper transistor of the half-bridge structure, thus saving the need for an isolation driver chip and an isolation power supply module (isolation power supply modules typically include a transformer composed of inductor coils, and large-value inductors are difficult to integrate inside the chip). This simplifies circuit design, saves chip and PCB area, and facilitates the subsequent integration of the entire circuit into a single chip.

[0076] For the voltage stress value and stress duration control module, the upper tube of the half-bridge structure... Q A3 and lower pipe Q A1 Alternating conduction. Current pipe Q A1 Upper tube when conducting Q A3 When the circuit is turned off, the voltage at the midpoint of the bridge arm is 0 volts, and there is no high-voltage input to the subsequent circuit. When the current transistor is turned off... Q A1 Top pipe when shut off Q A3 When the circuit is turned on, the voltage at the midpoint of the bridge arm is the supply voltage of the high-voltage power supply. V DD The subsequent circuit receives a high-voltage input. This controls the upper transistor. Q A3 The conduction time can control the high voltage that the subsequent circuit can withstand. V DD Duration. This is determined by controlling the transistor. Q A2 The switching on and off of the upper pipe can indirectly control the upper pipe. Q A3 The transistor's on and off states. Q A2 When conducting, the power resistor R 9. Power resistor R 10 Zener diode D 3 form a voltage divider circuit. This is achieved by controlling the power resistor. R 9. Power resistor R 10 Zener diode D 3 values ​​can make PMOS transistors Q A3 The gate-source voltage is exactly its turn-on voltage. When the transistor... Q A2 PMOS transistor when turned off Q A3 The gate-source voltage is 0 volts, at which point the PMOS transistor... Q A3 Turn off.

[0077] For the hard-switching transient and on-resistance testing module, the control principle is similar to that of the voltage stress value and stress duration control module, and will not be elaborated here.

[0078] Figure 4 This is a flowchart of the transistor reliability testing system with nanosecond-level delay according to the present invention.

[0079] In the experimental setup phase, the drain voltage stress duration of the transistor under test is first determined, and the pulse width of pulse 1 is determined accordingly. Then, the current value of the transistor under test is determined, and the pulse width of pulse 2 is determined accordingly. Next, the turn-on duration of the transistor under test is determined, and the pulse width of pulse 3 is determined accordingly. Finally, the drain voltage stress value of the transistor under test is determined, and the parameters required for the high-voltage power supply are determined accordingly.

[0080] The testing phase begins by setting the high-voltage power supply parameters; then pulses 1, 2, and 3 are input into the logic circuit; the logic circuit then generates 5 pulse signals, which include an adjustable dead time; these 5 pulse signals then drive 5 transistors via a gate drive module; the testing system also includes a clamping circuit to improve testing accuracy.

[0081] During the data analysis phase, the voltage and current parameters of the transistor under test can be obtained using an oscilloscope. From the voltage and current parameters, the switching transient characteristics and conduction characteristics (on-resistance) of the transistor under test can be determined. Finally, the reliability parameters of the transistor under test under nanosecond-level delays can be summarized and analyzed.

[0082] Figure 5 This is a circuit embodiment of the transistor reliability testing system with CMOS structure of the present invention. Figure 5 Circuit structure and Figure 3 The circuit structures are consistent. Figure 5 The specific annotation is as follows: Figure 3 The parameters of each component in the circuit shown will not be described in detail here.

[0083] Figure 6 This is the present invention. Figure 5 The logic signals of the "voltage stress value and stress duration control module" in the circuit embodiment. V A0 For external input pulse signals; V A1 for V A0 The inverted pulse signal controls the component parameters of the RC module in the logic circuit to achieve the functions of fast turn-off and slow turn-on; V A2 for V A0 In-phase pulse signals control the component parameters of the RC module in the logic circuit to achieve the functions of rapid turn-off and slow turn-on. V GA1 for V A1 The pulse signal output after passing through the gate driver chip has a threshold voltage for turning on and off. V A1 After reaching the threshold voltage, V GA1 Start level flipping.V GA2 for V A2 The pulse signal output after passing through the gate driver chip has a threshold voltage for turning on and off. V A2 After reaching the threshold voltage, V GA2 Start level flipping. V GSA3 This is the gate-source voltage of the PMOS transistor; the PMOS transistor turns on when the voltage is negative and turns off when it is 0 volts. When the NMOS transistor... Q A2 When turned on, the PMOS transistor Q A3 Synchronous activation; when the NMOS transistor is activated. Q A2 When turned off, the PMOS transistor Q A3 Synchronous shutdown. As shown in the figure, the transistor... Q A1 Turn off ( V GA1 (decline) and transistors Q A2 Open ( V GA2 (The rise) is not at the same time. T 1 and T The time difference between the two points is the dead time, which is determined by... V A2 The rise time determines this. (Transistor) Q A2 Turn off ( V GA2 (decline) and transistors Q A1 Open ( V GA1 (The rise) is not at the same time. T 9 and T 10 The time difference in the middle is called the dead time, which is determined by... V A1 The rising edge time determines this.

[0084] Figure 7 This is the present invention. Figure 5 The logic signals of the "current control module" in the circuit embodiment. V B0 For external input pulse signals; V GB0 for V B0The pulse signal after passing through the gate driver chip can output a larger drive current and has the ability to drive a load, thus better driving the transistors in subsequent stages. The logic circuit of this module does not involve complementary pulse signals or dead time.

[0085] Figure 8 This is the present invention. Figure 5 The logic signals of the "hard switching transient and on-resistance test module" in the circuit embodiment. V C0 For external input pulse signals; V C1 for V C0 In-phase pulse signals control the component parameters of the RC module in the logic circuit to achieve the functions of fast turn-off and slow turn-on; V C2 for V A0 The inverted pulse signal controls the component parameters of the RC module in the logic circuit to achieve the functions of rapid turn-off and slow turn-on. V GC1 for V C1 The pulse signal output after passing through the gate driver chip has a threshold voltage for turning on and off. V C1 After reaching the threshold voltage, V GC1 Start level flipping. V GC2 for V C2 The pulse signal output after passing through the gate driver chip has a threshold voltage for turning on and off. V C2 After reaching the threshold voltage, V GC2 Start level flipping. V GSC3 This is the gate-source voltage of the PMOS transistor. The PMOS transistor turns on when the voltage is negative and turns off when the voltage is 0 volts. T 2 o'clock T The following relationship holds between 9 time points: when the NMOS transistor Q C2 When turned on, the PMOS transistor Q C3 Synchronous activation; when the NMOS transistor is activated. Q C2 When turned off, the PMOS transistor Q C3 Synchronous shutdown. As shown in the figure, the transistor... Q C2 Turn off (V GC2 (decline) and transistors Q C1 Open ( V GC1 (The rise) is not at the same time. T 5 and T The time difference between 6 is the dead time, which is determined by... V C1 The rise time determines this. (Transistor) Q C1 Turn off ( V GC1 (decline) and transistors Q C2 Open ( V GC2 (The rise) is not at the same time. T 7 and T The time difference between 8 is the dead time, which is determined by... V C2 The rising edge time determines this.

[0086] Figure 9 This is the present invention. Figure 5 The power signal of the "hard switching transient and on-resistance test module" in the circuit embodiment. V DA1 Indicates transistor Q A1 The drain voltage; V DC1 Indicates the transistor under test Q C1 The drain voltage; I L Indicates power inductance L The current; R ON This indicates the measured transistor under test. Q C1 The on-resistance. V DA1 exist T 2 o'clock T The transistor is high during time 9, indicating that the transistor is high during this period. Q A1 The drain and subsequent circuit modules are subjected to high voltage stress. V DC1 exist T 2 o'clock T The transistor is high during time 6, indicating that the transistor is high during this period. Q C1 The drain electrode withstands high voltage stress. T 2 o'clock TThe time intervals between the six points can be flexibly adjusted according to experimental needs, ranging from several microseconds to several hours. T 6 o'clock T Transistor under test between 7 time points Q C1 When the transistor under test is turned on, it is in a state of conduction. Q C1 drain voltage V DC1 Low level, value is Q C1 The on-resistance multiplied by the drain-source current. I L Indicates power inductance L The current, as shown in the figure, I L exist T 3 to T Between 4 and T 6 to T The rise between 7 is due to the transistors. Q B0 and transistors Q C1 Conduction enables high voltage electricity V DD Transistor becomes power inductor L Charge. R ON This indicates the measured transistor under test. Q C1 The on-resistance is the resistance of the transistor under test when it is turned on. Q C1 Drain voltage and the transistor under test Q C1 Drain source current ( Q C1 The drain-source current is equal to T 6 to T Current of power inductors between 7 I L The result is obtained by dividing by ).

[0087] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A transistor reliability testing system with nanosecond-level delay, characterized in that, It includes a voltage stress value and stress duration control module, a current control module, and a hard-switching transient and on-resistance testing module. Each of these modules includes a logic circuit and a power circuit. Among them, the voltage stress value and stress duration control module is used to control the drain voltage stress value and drain voltage stress duration of the transistor under test; the current control module is used to control the current magnitude during the hard switching test of the transistor under test; and the hard switching transient and on-resistance test module controls the on-time of the transistor under test after hard switching. The logic circuits of the voltage stress value and stress duration control module and the hard-switching transient and on-resistance test module both include NMOS transistors, resistors, capacitors, Schottky diodes, and gate driver chips. This logic circuit converts an externally input pulse signal into two inverted pulse signals with a dead time through "hardware circuitry," and inputs the two pulse signals into the power circuit. The logic circuit of the current control module includes a gate driver chip. This logic circuit converts an input pulse signal into a pulse signal with "the ability to output large transient current," and inputs the pulse signal into the power circuit.

2. The transistor reliability testing system with nanosecond-level delay according to claim 1, characterized in that, The power circuit of the voltage stress value and stress duration control module includes NMOS power transistors / or PMOS and NMOS power transistors, power resistors, and Zener diodes; the power circuit controls the conduction of the half-bridge circuit of the module based on two pulse signals, thereby controlling the midpoint voltage of the bridge arm.

3. The transistor reliability testing system with nanosecond-level delay according to claim 1, characterized in that, The power circuit section of the current control module includes an NMOS power transistor, a Schottky diode, and a power inductor. The power circuit controls the conduction of the NMOS power transistor based on a pulse signal, thereby controlling the current of the power inductor.

4. The transistor reliability testing system with nanosecond-level delay according to claim 1, characterized in that, The power circuit section of the hard-switching transient and on-resistance test module includes NMOS power transistors / or PMOS and NMOS power transistors, power resistors, and Zener diodes. The power circuit controls the conduction status of the half-bridge circuit of the module based on two pulse signals, thereby controlling whether the transistor under test is turned on and the drain connection position of the transistor under test.

5. The transistor reliability testing system with nanosecond-level delay according to claim 1 or 2, characterized in that, The logic circuit section of the voltage stress value and stress duration control module includes an NMOS transistor Q. A3 Resistors R1-R4, capacitors C1-C2, Schottky diode D5, gate driver chip U A1 and U A2 Among them, the NMOS transistor Q A3 gate connection V A0 Terminal, NMOS transistor Q A3 The drain of the resistor is connected to one end of resistors R1 and R2, and the other end of resistor R1 is connected to V. CC Connection; the other end of resistor R2 is connected to one end of capacitor C1 and the gate driver chip U. A1 The input terminal IN is connected to the NMOS transistor Q. The other end of capacitor C1 is connected to the NMOS transistor Q. A3 The source and gate driver chip U A1 The ground terminal GND, the gate driver chip U A1 The output terminal OUT is V GA1 Terminal; one end of resistor R3 is connected to V. A0 One end of resistor R3 is connected to one end of resistor R4, and the other end of resistor R4 is connected to one end of capacitor C2 and the anode of Schottky diode D5, and is connected to the gate driver chip U. A2 The input terminal IN is connected to the circuit, and the cathode of Schottky diode D5 is connected to the common terminal of resistors R3 and R4; the other end of capacitor C2 is connected to the gate driver chip U. A2 The ground terminal GND1, the gate driver chip U A2 The output terminal OUT and the ground terminal GND2 are respectively V GA2 End and V SA2 end; The power circuit section of the voltage stress value and stress duration control module includes the NMOS power transistor Q. A1 and Q A2 Among them, the NMOS power transistor Q A2 The source of the NMOS power transistor Q A1 The drain connection forms a common terminal with V. SA2 Connection, NMOS power transistor Q A2 Drain connection V DD Terminal, its gate is connected to V GA2 NMOS power transistor Q A1 Its source is grounded, and its gate is connected to V. GA1 .

6. The transistor reliability testing system with nanosecond-level delay according to claim 1 or 3, characterized in that, The logic circuit section of the current control module includes the gate driver chip U B1 Gate driver chip U B1 The input terminal IN is connected to V. B0 The output terminal OUT is V GB0 end; The power circuit section of the current control module includes the NMOS power transistor Q. B0 Schottky diodes D1 and D2, power inductor L; and NMOS transistor Q. B0 The drain of the inductor is connected to one end of the power inductor L and the common connection terminal of the anodes of Schottky diodes D1 and D2. The other end of the power inductor L and the cathode of Schottky diode D1 are connected to the NMOS transistor Q of the voltage stress value and stress duration control module. A1 The drain and NMOS transistor Q A2 The source and V SA2 The common connection terminals are connected; NMOS transistor Q B0 The source and voltage stress value and stress duration control module of the NMOS transistor Q A1 The source terminals are connected; NMOS transistor Q B0 gate connection V GB0 end.

7. The transistor reliability testing system with nanosecond-level delay according to claim 1 or 4, characterized in that, The logic circuit section of the hard-switching transient and on-resistance test module includes an NMOS transistor Q. C3 Resistors R5-R8, capacitors C3-C4, Schottky diode D6, gate driver chip U C1 and U C2 Among them, the NMOS transistor Q C3 gate connection V C0 Terminal, NMOS transistor Q C3 The drain of the resistor is connected to one end of resistors R5 and R6, and the other end of resistor R5 is connected to V. CC Connection; the other end of resistor R6 is connected to one end of capacitor C3 and the gate driver chip U. C2 The input terminal IN is connected to the NMOS transistor Q. The other end of capacitor C3 is connected to the NMOS transistor Q. C3 The source and gate driver chip U C2 The ground terminal GND1, the gate driver chip U C2 The output terminal OUT is V GC2 Terminal, gate driver chip U C2 The grounding terminal GND2 is V SC2 Terminal; one end of resistor R7 is connected to V. C0 One end of resistor R7 is connected to one end of resistor R8, and the other end of resistor R8 is connected to one end of capacitor C4 and the anode of Schottky diode D6, and is connected to the gate driver chip U. C1 The input terminal IN is connected to the circuit, and the cathode of Schottky diode D6 is connected to the common terminal of resistors R7 and R8; the other end of capacitor C4 is connected to the gate driver chip U. C1 The ground terminal GND, the gate driver chip U C1 The output terminal OUT is V GC1 end; The power circuit section of the hard-switching transient and on-resistance test module includes the NMOS power transistor Q. C1 and Q C2 Among them, the NMOS transistor Q C2 The source of the NMOS transistor Q C1 The drain connection forms a common terminal that is connected to the cathode of the Schottky diode D2 in the current control module, and is connected to V. SC2 Connection; NMOS transistor Q C2 The drain and current control module's Schottky diode D1, cathode, power inductor L, and the voltage stress value and stress duration control module's NMOS transistor Q A1 drain of NMOS transistor Q A2 The source, V SA2 The common connection terminals are connected; NMOS transistor Q C2 gate connection V GC2 NMOS power transistor Q C1 The NMOS transistor Q in the source-connected current control module B0 The source of the NMOS transistor Q in the voltage stress value and stress duration control module A1 The source of the NMOS power transistor Q C1 gate connection V GC1 The NMOS transistor Q B0 The source and NMOS transistor Q C1 The source common connection terminal is connected to the NMOS transistor Q. C2 The source of the NMOS transistor Q C1 A clamping circuit is provided between the common connection terminal of the drain of the diode and the cathode of the Schottky diode D2.

8. The transistor reliability testing system with nanosecond-level delay according to claim 1 or 2, characterized in that, The power circuit section of the voltage stress value and stress duration control module also includes a PMOS transistor Q. A3 Power resistors R9 and R 10 Zener diode D3; where NMOS transistor Q A1 The source of the NMOS transistor Q A2 After the source is connected, the common terminal is grounded, and the NMOS transistor Q... A2 The drain of the diode is connected to one end of resistor R9, and the other end of resistor R9 is connected to the anode of Zener diode D3 and resistor R. 10 One end, and connected to the PMOS transistor Q A3 The gate of the PMOS transistor Q is connected to the gate. A3 The drain of the NMOS transistor Q A1 The drain of the Zener diode D3 is connected to the cathode; the cathode of the Zener diode D3 and the resistor R are connected together. 10 The other end is connected to the PMOS transistor Q. A3 The source terminals are connected, and V is connected. DD ; The logic circuit section of the voltage stress value and stress duration control module includes an NMOS transistor Q. A4 Resistors R1-R4, capacitors C1-C2, Schottky diode D5, gate driver chip U A1 and U A2 Among them, the NMOS transistor Q A4 gate connection V A0 Terminal, NMOS transistor Q A4 The drain of the resistor is connected to one end of resistors R1 and R2, and the other end of resistor R1 is connected to V. CC Connection; the other end of resistor R2 is connected to one end of capacitor C1 and the gate driver chip U. A1 The input terminal IN is connected to the NMOS transistor Q. The other end of capacitor C1 is connected to the NMOS transistor Q. A4 The source and gate driver chip U A1 The ground terminal GND, the gate driver chip U A1 The output terminal OUT is V GA1 Terminal; one end of resistor R3 is connected to V. A0 One end of resistor R3 is connected to one end of resistor R4, and the other end of resistor R4 is connected to one end of capacitor C2 and the anode of Schottky diode D5, and is connected to the gate driver chip U. A2 The input terminal IN is connected to the circuit, and the cathode of Schottky diode D5 is connected to the common terminal of resistors R3 and R4; the other end of capacitor C2 is connected to the gate driver chip U. A2 The ground terminal GND, the gate driver chip U A2 The output terminal OUT is V GA2 end.

9. The transistor reliability testing system with nanosecond-level delay according to claim 1 or 4, characterized in that, The power circuit section of the hard-switching transient and on-resistance test module also includes the PMOS transistor Q. C3 Power resistor R 11 and R 12 Zener diode D4; where NMOS transistor Q C1 The source and NMOS transistor Q C2 The common terminal after the source connection is connected to the NMOS transistor Q in the current control module. B0 The source of the NMOS transistor Q in the voltage stress value and stress duration control module A1 The source and NMOS transistor Q A2 The source terminals are connected; NMOS transistor Q C2 Drain and resistor R 12 One end is connected to resistor R 12 The other end is connected to the anode of the Zener diode D4 and the resistor R. 11 One end, and connected to the PMOS transistor Q C3 The gate of the PMOS transistor Q is connected to the gate. C3 The drain of the NMOS transistor Q C1 The common connection terminal, where the drains of the diodes are connected, is connected to the cathode of the Schottky diode D2 in the current control module; the cathode of the Zener diode D4 and the resistor R... 11 The other end is connected to the PMOS transistor Q. C3 The source of the circuit is connected to the cathode of the Schottky diode D1 in the current control module, the power inductor L, and the NMOS transistor Q in the voltage stress value and stress duration control module. A1 The drain of the PMOS transistor Q A3 The common connection terminal of the drain of the NMOS transistor Q is connected; B0 The source and NMOS transistor Q C1 The common connection terminal of the NMOS transistor Q C1 The drain of the PMOS transistor Q C3 A clamping circuit is provided between the common connection terminal of the drain of the diode and the cathode of the Schottky diode D2; The logic circuit section of the hard-switching transient and on-resistance test module includes an NMOS transistor Q. C4 Resistors R5-R8, capacitors C3-C4, Schottky diode D6, gate driver chip U C1 and U C2 Among them, the NMOS transistor Q C4 gate connection V C0 Terminal, NMOS transistor Q C4 The drain of the resistor is connected to one end of resistors R5 and R6, and the other end of resistor R5 is connected to V. CC Connection; the other end of resistor R6 is connected to one end of capacitor C3 and the gate driver chip U. C2 The input terminal IN is connected to the NMOS transistor Q. The other end of capacitor C3 is connected to the NMOS transistor Q. C4 The source and gate driver chip U C2 The ground terminal GND, the gate driver chip U C2 The output terminal OUT is V GC2 Terminal; one end of resistor R7 is connected to V. C0 One end of resistor R7 is connected to one end of resistor R8, and the other end of resistor R8 is connected to one end of capacitor C4 and the anode of Schottky diode D6, and is connected to the gate driver chip U. C1 The input terminal IN is connected to the circuit, and the cathode of Schottky diode D6 is connected to the common terminal of resistors R7 and R8; the other end of capacitor C4 is connected to the gate driver chip U. C1 The ground terminal GND, the gate driver chip U C1 The output terminal OUT is V GC1 end.

10. A method for testing the reliability of transistors with nanosecond-level delays, implemented using the system described in any one of claims 1-9, characterized in that, Includes the following steps: 1) Determine the duration of the drain voltage stress of the transistor under test, and thereby determine the pulse width of pulse 1; 2) Determine the current value of the transistor under test, and thereby determine the pulse width of pulse 2; 3) Then determine the turn-on duration of the transistor under test, and thereby determine the pulse width of pulse 3; 4) Subsequently, the drain voltage stress value of the transistor under test is determined, and the parameters required for the high-voltage power supply are determined accordingly; 5) Set the high-voltage power supply parameters; Then pulse 1, pulse 2, and pulse 3 are input into the logic circuit; 6) The logic circuit will generate 5 pulse signals, and these 5 pulse signals include an adjustable dead time; 7) Five pulse signals drive five transistors via a gate drive module; 8) Improve test accuracy through clamping circuits; 9) Obtain the voltage and current parameters of the transistor under test using an oscilloscope; 10) Obtain the transient switching characteristics and conduction characteristics of the transistor under test from the voltage and current parameters; 11) Finally, the reliability parameters of the transistor under test under nanosecond delay are obtained.

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